| 1 | From 7328ff547389ee0b455cbf98bdfc819731d9f7b9 Mon Sep 17 00:00:00 2001 |
| 2 | From: Gabor Juhos <juhosg@openwrt.org> |
| 3 | Date: Fri, 31 Aug 2012 14:22:35 +0200 |
| 4 | Subject: [PATCH] MIPS: ath79: use correct fractional dividers for |
| 5 | {CPU,DDR}_PLL on AR934x |
| 6 | |
| 7 | The current dividers in the code are wrong and this |
| 8 | leads to broken CPU frequency calculation on boards |
| 9 | where the fractional part is used. |
| 10 | |
| 11 | For example, if the SoC is running from a 40MHz |
| 12 | reference clock, refdiv=1, nint=14, outdiv=0 and |
| 13 | nfrac=31 the real frequency is 579.375MHz but the |
| 14 | current code calculates 569.687MHz instead. |
| 15 | |
| 16 | Because the system time is indirectly related to |
| 17 | the CPU frequency the broken computation causes |
| 18 | drift in the system time. |
| 19 | |
| 20 | The correct divider is 2^6 for the CPU PLL and 2^10 |
| 21 | for the DDR PLL. Use the correct values to fix the |
| 22 | issue. |
| 23 | |
| 24 | Cc: <stable@vger.kernel.org> [3.5+] |
| 25 | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> |
| 26 | --- |
| 27 | arch/mips/ath79/clock.c | 4 ++-- |
| 28 | 1 file changed, 2 insertions(+), 2 deletions(-) |
| 29 | |
| 30 | --- a/arch/mips/ath79/clock.c |
| 31 | +++ b/arch/mips/ath79/clock.c |
| 32 | @@ -189,7 +189,7 @@ static void __init ar934x_clocks_init(vo |
| 33 | AR934X_PLL_CPU_CONFIG_NFRAC_MASK; |
| 34 | |
| 35 | cpu_pll = nint * ath79_ref_clk.rate / ref_div; |
| 36 | - cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 6)); |
| 37 | + cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6)); |
| 38 | cpu_pll /= (1 << out_div); |
| 39 | |
| 40 | pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG); |
| 41 | @@ -203,7 +203,7 @@ static void __init ar934x_clocks_init(vo |
| 42 | AR934X_PLL_DDR_CONFIG_NFRAC_MASK; |
| 43 | |
| 44 | ddr_pll = nint * ath79_ref_clk.rate / ref_div; |
| 45 | - ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 10)); |
| 46 | + ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10)); |
| 47 | ddr_pll /= (1 << out_div); |
| 48 | |
| 49 | clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG); |
| 50 | |
