Root/target/linux/ar71xx/patches-3.3/146-MIPS-ath79-register-platform-devices-for-the-PCI-con.patch

1From 2fdf8dcff3ffaa806e9f9d7f1c1bd876222cff4d Mon Sep 17 00:00:00 2001
2From: Gabor Juhos <juhosg@openwrt.org>
3Date: Mon, 11 Jun 2012 13:39:32 +0200
4Subject: [PATCH 07/34] MIPS: ath79: register platform devices for the PCI controllers
5
6Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
7---
8 arch/mips/ath79/pci.c | 87 +++++++++++++++++++++++++++++++++++++++++++-----
9 1 files changed, 78 insertions(+), 9 deletions(-)
10
11--- a/arch/mips/ath79/pci.c
12+++ b/arch/mips/ath79/pci.c
13@@ -14,6 +14,8 @@
14 
15 #include <linux/init.h>
16 #include <linux/pci.h>
17+#include <linux/resource.h>
18+#include <linux/platform_device.h>
19 #include <asm/mach-ath79/ar71xx_regs.h>
20 #include <asm/mach-ath79/ath79.h>
21 #include <asm/mach-ath79/irq.h>
22@@ -110,21 +112,88 @@ void __init ath79_pci_set_plat_dev_init(
23     ath79_pci_plat_dev_init = func;
24 }
25 
26-int __init ath79_register_pci(void)
27+static struct platform_device *
28+ath79_register_pci_ar71xx(void)
29 {
30- if (soc_is_ar71xx())
31- return ar71xx_pcibios_init();
32+ struct platform_device *pdev;
33+ struct resource res[2];
34+
35+ memset(res, 0, sizeof(res));
36 
37- if (soc_is_ar724x())
38- return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2);
39+ res[0].name = "cfg_base";
40+ res[0].flags = IORESOURCE_MEM;
41+ res[0].start = AR71XX_PCI_CFG_BASE;
42+ res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1;
43+
44+ res[1].flags = IORESOURCE_IRQ;
45+ res[1].start = ATH79_CPU_IRQ_IP2;
46+ res[1].end = ATH79_CPU_IRQ_IP2;
47+
48+ pdev = platform_device_register_simple("ar71xx-pci", -1,
49+ res, ARRAY_SIZE(res));
50+ return pdev;
51+}
52 
53- if (soc_is_ar9342() || soc_is_ar9344()) {
54+static struct platform_device *
55+ath79_register_pci_ar724x(int id,
56+ unsigned long cfg_base,
57+ unsigned long ctrl_base,
58+ int irq)
59+{
60+ struct platform_device *pdev;
61+ struct resource res[3];
62+
63+ memset(res, 0, sizeof(res));
64+
65+ res[0].name = "cfg_base";
66+ res[0].flags = IORESOURCE_MEM;
67+ res[0].start = cfg_base;
68+ res[0].end = cfg_base + AR724X_PCI_CFG_SIZE - 1;
69+
70+ res[1].name = "ctrl_base";
71+ res[1].flags = IORESOURCE_MEM;
72+ res[1].start = ctrl_base;
73+ res[1].end = ctrl_base + AR724X_PCI_CTRL_SIZE - 1;
74+
75+ res[2].flags = IORESOURCE_IRQ;
76+ res[2].start = irq;
77+ res[2].end = irq;
78+
79+ pdev = platform_device_register_simple("ar724x-pci", id,
80+ res, ARRAY_SIZE(res));
81+ return pdev;
82+}
83+
84+int __init ath79_register_pci(void)
85+{
86+ struct platform_device *pdev = NULL;
87+
88+ if (soc_is_ar71xx()) {
89+ pdev = ath79_register_pci_ar71xx();
90+ } else if (soc_is_ar724x()) {
91+ pdev = ath79_register_pci_ar724x(-1,
92+ AR724X_PCI_CFG_BASE,
93+ AR724X_PCI_CTRL_BASE,
94+ ATH79_CPU_IRQ_IP2);
95+ } else if (soc_is_ar9342() ||
96+ soc_is_ar9344()) {
97         u32 bootstrap;
98 
99         bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
100- if (bootstrap & AR934X_BOOTSTRAP_PCIE_RC)
101- return ar724x_pcibios_init(ATH79_IP2_IRQ(0));
102+ if ((bootstrap & AR934X_BOOTSTRAP_PCIE_RC) == 0)
103+ return -ENODEV;
104+
105+ pdev = ath79_register_pci_ar724x(-1,
106+ AR724X_PCI_CFG_BASE,
107+ AR724X_PCI_CTRL_BASE,
108+ ATH79_IP2_IRQ(0));
109+ } else {
110+ /* No PCI support */
111+ return -ENODEV;
112     }
113 
114- return -ENODEV;
115+ if (!pdev)
116+ pr_err("unable to register PCI controller device\n");
117+
118+ return pdev ? 0 : -ENODEV;
119 }
120

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