Root/target/linux/ar71xx/patches-3.3/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch

1From 5d0de52f8e36916485a61b820916b71b5d918e6f Mon Sep 17 00:00:00 2001
2From: Gabor Juhos <juhosg@openwrt.org>
3Date: Sun, 24 Jun 2012 13:44:23 +0200
4Subject: [PATCH 19/34] MIPS: ath79: add IRQ handling code for the QCA955X SoCs
5
6Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
7---
8 arch/mips/ath79/irq.c | 110 ++++++++++++++++++++++--
9 arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 32 +++++++
10 arch/mips/include/asm/mach-ath79/irq.h | 9 ++-
11 3 files changed, 142 insertions(+), 9 deletions(-)
12
13--- a/arch/mips/ath79/irq.c
14+++ b/arch/mips/ath79/irq.c
15@@ -130,7 +130,10 @@ static void __init ath79_misc_irq_init(v
16 
17     if (soc_is_ar71xx() || soc_is_ar913x())
18         ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
19- else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x())
20+ else if (soc_is_ar724x() ||
21+ soc_is_ar933x() ||
22+ soc_is_ar934x() ||
23+ soc_is_qca955x())
24         ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
25     else
26         BUG();
27@@ -177,6 +180,88 @@ static void ar934x_ip2_irq_init(void)
28     irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch);
29 }
30 
31+static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
32+{
33+ u32 status;
34+
35+ disable_irq_nosync(irq);
36+
37+ status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
38+ status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL;
39+
40+ if (status == 0) {
41+ spurious_interrupt();
42+ goto enable;
43+ }
44+
45+ if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
46+ /* TODO: flush DDR? */
47+ generic_handle_irq(ATH79_IP2_IRQ(0));
48+ }
49+
50+ if (status & QCA955X_EXT_INT_WMAC_ALL) {
51+ /* TODO: flsuh DDR? */
52+ generic_handle_irq(ATH79_IP2_IRQ(1));
53+ }
54+
55+enable:
56+ enable_irq(irq);
57+}
58+
59+static void qca955x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc)
60+{
61+ u32 status;
62+
63+ disable_irq_nosync(irq);
64+
65+ status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
66+ status &= QCA955X_EXT_INT_PCIE_RC2_ALL |
67+ QCA955X_EXT_INT_USB1 |
68+ QCA955X_EXT_INT_USB2;
69+
70+ if (status == 0) {
71+ spurious_interrupt();
72+ goto enable;
73+ }
74+
75+ if (status & QCA955X_EXT_INT_USB1) {
76+ /* TODO: flush DDR? */
77+ generic_handle_irq(ATH79_IP3_IRQ(0));
78+ }
79+
80+ if (status & QCA955X_EXT_INT_USB2) {
81+ /* TODO: flsuh DDR? */
82+ generic_handle_irq(ATH79_IP3_IRQ(1));
83+ }
84+
85+ if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) {
86+ /* TODO: flush DDR? */
87+ generic_handle_irq(ATH79_IP3_IRQ(2));
88+ }
89+
90+enable:
91+ enable_irq(irq);
92+}
93+
94+static void qca955x_irq_init(void)
95+{
96+ int i;
97+
98+ for (i = ATH79_IP2_IRQ_BASE;
99+ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
100+ irq_set_chip_and_handler(i, &dummy_irq_chip,
101+ handle_level_irq);
102+
103+ irq_set_chained_handler(ATH79_CPU_IRQ_IP2, qca955x_ip2_irq_dispatch);
104+
105+ for (i = ATH79_IP3_IRQ_BASE;
106+ i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
107+ irq_set_chip_and_handler(i, &dummy_irq_chip,
108+ handle_level_irq);
109+
110+ irq_set_chained_handler(ATH79_CPU_IRQ_IP3, qca955x_ip3_irq_dispatch);
111+}
112+
113 asmlinkage void plat_irq_dispatch(void)
114 {
115     unsigned long pending;
116@@ -212,6 +297,17 @@ asmlinkage void plat_irq_dispatch(void)
117  * Issue a flush in the handlers to ensure that the driver sees
118  * the update.
119  */
120+
121+static void ath79_default_ip2_handler(void)
122+{
123+ do_IRQ(ATH79_CPU_IRQ_IP2);
124+}
125+
126+static void ath79_default_ip3_handler(void)
127+{
128+ do_IRQ(ATH79_CPU_IRQ_USB);
129+}
130+
131 static void ar71xx_ip2_handler(void)
132 {
133     ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI);
134@@ -236,11 +332,6 @@ static void ar933x_ip2_handler(void)
135     do_IRQ(ATH79_CPU_IRQ_IP2);
136 }
137 
138-static void ar934x_ip2_handler(void)
139-{
140- do_IRQ(ATH79_CPU_IRQ_IP2);
141-}
142-
143 static void ar71xx_ip3_handler(void)
144 {
145     ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB);
146@@ -286,8 +377,11 @@ void __init arch_init_irq(void)
147         ath79_ip2_handler = ar933x_ip2_handler;
148         ath79_ip3_handler = ar933x_ip3_handler;
149     } else if (soc_is_ar934x()) {
150- ath79_ip2_handler = ar934x_ip2_handler;
151+ ath79_ip2_handler = ath79_default_ip2_handler;
152         ath79_ip3_handler = ar934x_ip3_handler;
153+ } else if (soc_is_qca955x()) {
154+ ath79_ip2_handler = ath79_default_ip2_handler;
155+ ath79_ip3_handler = ath79_default_ip3_handler;
156     } else {
157         BUG();
158     }
159@@ -298,4 +392,6 @@ void __init arch_init_irq(void)
160 
161     if (soc_is_ar934x())
162         ar934x_ip2_irq_init();
163+ else if (soc_is_qca955x())
164+ qca955x_irq_init();
165 }
166--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
167+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
168@@ -300,6 +300,7 @@
169 #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
170 
171 #define QCA955X_RESET_REG_BOOTSTRAP 0xb0
172+#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
173 
174 #define MISC_INT_ETHSW BIT(12)
175 #define MISC_INT_TIMER4 BIT(10)
176@@ -398,6 +399,37 @@
177      AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
178      AR934X_PCIE_WMAC_INT_PCIE_RC3)
179 
180+#define QCA955X_EXT_INT_WMAC_MISC BIT(0)
181+#define QCA955X_EXT_INT_WMAC_TX BIT(1)
182+#define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
183+#define QCA955X_EXT_INT_WMAC_RXHP BIT(3)
184+#define QCA955X_EXT_INT_PCIE_RC1 BIT(4)
185+#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5)
186+#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6)
187+#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7)
188+#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8)
189+#define QCA955X_EXT_INT_PCIE_RC2 BIT(12)
190+#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13)
191+#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14)
192+#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15)
193+#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16)
194+#define QCA955X_EXT_INT_USB1 BIT(24)
195+#define QCA955X_EXT_INT_USB2 BIT(28)
196+
197+#define QCA955X_EXT_INT_WMAC_ALL \
198+ (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
199+ QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)
200+
201+#define QCA955X_EXT_INT_PCIE_RC1_ALL \
202+ (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \
203+ QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \
204+ QCA955X_EXT_INT_PCIE_RC1_INT3)
205+
206+#define QCA955X_EXT_INT_PCIE_RC2_ALL \
207+ (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \
208+ QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
209+ QCA955X_EXT_INT_PCIE_RC2_INT3)
210+
211 #define REV_ID_MAJOR_MASK 0xfff0
212 #define REV_ID_MAJOR_AR71XX 0x00a0
213 #define REV_ID_MAJOR_AR913X 0x00b0
214--- a/arch/mips/include/asm/mach-ath79/irq.h
215+++ b/arch/mips/include/asm/mach-ath79/irq.h
216@@ -10,7 +10,7 @@
217 #define __ASM_MACH_ATH79_IRQ_H
218 
219 #define MIPS_CPU_IRQ_BASE 0
220-#define NR_IRQS 48
221+#define NR_IRQS 51
222 
223 #define ATH79_MISC_IRQ_BASE 8
224 #define ATH79_MISC_IRQ_COUNT 32
225@@ -23,8 +23,13 @@
226 #define ATH79_IP2_IRQ_COUNT 2
227 #define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x))
228 
229+#define ATH79_IP3_IRQ_BASE (ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT)
230+#define ATH79_IP3_IRQ_COUNT 3
231+#define ATH79_IP3_IRQ(_x) (ATH79_IP3_IRQ_BASE + (_x))
232+
233 #define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2)
234-#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3)
235+#define ATH79_CPU_IRQ_IP3 (MIPS_CPU_IRQ_BASE + 3)
236+#define ATH79_CPU_IRQ_USB ATH79_CPU_IRQ_IP3
237 #define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4)
238 #define ATH79_CPU_IRQ_GE1 (MIPS_CPU_IRQ_BASE + 5)
239 #define ATH79_CPU_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6)
240

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