| 1 | --- a/arch/mips/ath79/common.h |
| 2 | +++ b/arch/mips/ath79/common.h |
| 3 | @@ -26,6 +26,7 @@ void ath79_ddr_wb_flush(unsigned int reg |
| 4 | void ath79_gpio_function_enable(u32 mask); |
| 5 | void ath79_gpio_function_disable(u32 mask); |
| 6 | void ath79_gpio_function_setup(u32 set, u32 clear); |
| 7 | +void ath79_gpio_output_select(unsigned gpio, u8 val); |
| 8 | void ath79_gpio_init(void); |
| 9 | |
| 10 | #endif /* __ATH79_COMMON_H */ |
| 11 | --- a/arch/mips/ath79/gpio.c |
| 12 | +++ b/arch/mips/ath79/gpio.c |
| 13 | @@ -184,6 +184,34 @@ void ath79_gpio_function_setup(u32 set, |
| 14 | spin_unlock_irqrestore(&ath79_gpio_lock, flags); |
| 15 | } |
| 16 | |
| 17 | +void __init ath79_gpio_output_select(unsigned gpio, u8 val) |
| 18 | +{ |
| 19 | + void __iomem *base = ath79_gpio_base; |
| 20 | + unsigned long flags; |
| 21 | + unsigned int reg; |
| 22 | + u32 t, s; |
| 23 | + |
| 24 | + BUG_ON(!soc_is_ar934x()); |
| 25 | + |
| 26 | + if (gpio >= AR934X_GPIO_COUNT) |
| 27 | + return; |
| 28 | + |
| 29 | + reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4); |
| 30 | + s = 8 * (gpio % 4); |
| 31 | + |
| 32 | + spin_lock_irqsave(&ath79_gpio_lock, flags); |
| 33 | + |
| 34 | + t = __raw_readl(base + reg); |
| 35 | + t &= ~(0xff << s); |
| 36 | + t |= val << s; |
| 37 | + __raw_writel(t, base + reg); |
| 38 | + |
| 39 | + /* flush write */ |
| 40 | + (void) __raw_readl(base + reg); |
| 41 | + |
| 42 | + spin_unlock_irqrestore(&ath79_gpio_lock, flags); |
| 43 | +} |
| 44 | + |
| 45 | void __init ath79_gpio_init(void) |
| 46 | { |
| 47 | int err; |
| 48 | |
