| 1 | --- a/arch/mips/ath79/mach-db120.c |
| 2 | +++ b/arch/mips/ath79/mach-db120.c |
| 3 | @@ -2,7 +2,7 @@ |
| 4 | * Atheros DB120 reference board support |
| 5 | * |
| 6 | * Copyright (c) 2011 Qualcomm Atheros |
| 7 | - * Copyright (c) 2011 Gabor Juhos <juhosg@openwrt.org> |
| 8 | + * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org> |
| 9 | * |
| 10 | * Permission to use, copy, modify, and/or distribute this software for any |
| 11 | * purpose with or without fee is hereby granted, provided that the above |
| 12 | @@ -19,16 +19,26 @@ |
| 13 | */ |
| 14 | |
| 15 | #include <linux/pci.h> |
| 16 | +#include <linux/phy.h> |
| 17 | +#include <linux/platform_device.h> |
| 18 | #include <linux/ath9k_platform.h> |
| 19 | +#include <linux/ar8216_platform.h> |
| 20 | |
| 21 | -#include "machtypes.h" |
| 22 | +#include <asm/mach-ath79/ar71xx_regs.h> |
| 23 | + |
| 24 | +#include "common.h" |
| 25 | +#include "dev-ap9x-pci.h" |
| 26 | +#include "dev-eth.h" |
| 27 | #include "dev-gpio-buttons.h" |
| 28 | #include "dev-leds-gpio.h" |
| 29 | +#include "dev-m25p80.h" |
| 30 | +#include "dev-nfc.h" |
| 31 | #include "dev-spi.h" |
| 32 | #include "dev-usb.h" |
| 33 | #include "dev-wmac.h" |
| 34 | -#include "pci.h" |
| 35 | +#include "machtypes.h" |
| 36 | |
| 37 | +#define DB120_GPIO_LED_USB 11 |
| 38 | #define DB120_GPIO_LED_WLAN_5G 12 |
| 39 | #define DB120_GPIO_LED_WLAN_2G 13 |
| 40 | #define DB120_GPIO_LED_STATUS 14 |
| 41 | @@ -39,8 +49,10 @@ |
| 42 | #define DB120_KEYS_POLL_INTERVAL 20 /* msecs */ |
| 43 | #define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL) |
| 44 | |
| 45 | -#define DB120_WMAC_CALDATA_OFFSET 0x1000 |
| 46 | -#define DB120_PCIE_CALDATA_OFFSET 0x5000 |
| 47 | +#define DB120_MAC0_OFFSET 0 |
| 48 | +#define DB120_MAC1_OFFSET 6 |
| 49 | +#define DB120_WMAC_CALDATA_OFFSET 0x1000 |
| 50 | +#define DB120_PCIE_CALDATA_OFFSET 0x5000 |
| 51 | |
| 52 | static struct gpio_led db120_leds_gpio[] __initdata = { |
| 53 | { |
| 54 | @@ -63,6 +75,11 @@ static struct gpio_led db120_leds_gpio[] |
| 55 | .gpio = DB120_GPIO_LED_WLAN_2G, |
| 56 | .active_low = 1, |
| 57 | }, |
| 58 | + { |
| 59 | + .name = "db120:green:usb", |
| 60 | + .gpio = DB120_GPIO_LED_USB, |
| 61 | + .active_low = 1, |
| 62 | + } |
| 63 | }; |
| 64 | |
| 65 | static struct gpio_keys_button db120_gpio_keys[] __initdata = { |
| 66 | @@ -76,66 +93,101 @@ static struct gpio_keys_button db120_gpi |
| 67 | }, |
| 68 | }; |
| 69 | |
| 70 | -static struct ath79_spi_controller_data db120_spi0_data = { |
| 71 | - .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, |
| 72 | - .cs_line = 0, |
| 73 | +static struct ar8327_pad_cfg db120_ar8327_pad0_cfg = { |
| 74 | + .mode = AR8327_PAD_MAC_RGMII, |
| 75 | + .txclk_delay_en = true, |
| 76 | + .rxclk_delay_en = true, |
| 77 | + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, |
| 78 | + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, |
| 79 | }; |
| 80 | |
| 81 | -static struct spi_board_info db120_spi_info[] = { |
| 82 | - { |
| 83 | - .bus_num = 0, |
| 84 | - .chip_select = 0, |
| 85 | - .max_speed_hz = 25000000, |
| 86 | - .modalias = "s25sl064a", |
| 87 | - .controller_data = &db120_spi0_data, |
| 88 | - } |
| 89 | +static struct ar8327_led_cfg db120_ar8327_led_cfg = { |
| 90 | + .led_ctrl0 = 0x00000000, |
| 91 | + .led_ctrl1 = 0xc737c737, |
| 92 | + .led_ctrl2 = 0x00000000, |
| 93 | + .led_ctrl3 = 0x00c30c00, |
| 94 | + .open_drain = true, |
| 95 | }; |
| 96 | |
| 97 | -static struct ath79_spi_platform_data db120_spi_data = { |
| 98 | - .bus_num = 0, |
| 99 | - .num_chipselect = 1, |
| 100 | +static struct ar8327_platform_data db120_ar8327_data = { |
| 101 | + .pad0_cfg = &db120_ar8327_pad0_cfg, |
| 102 | + .cpuport_cfg = { |
| 103 | + .force_link = 1, |
| 104 | + .speed = AR8327_PORT_SPEED_1000, |
| 105 | + .duplex = 1, |
| 106 | + .txpause = 1, |
| 107 | + .rxpause = 1, |
| 108 | + }, |
| 109 | + .led_cfg = &db120_ar8327_led_cfg, |
| 110 | }; |
| 111 | |
| 112 | -#ifdef CONFIG_PCI |
| 113 | -static struct ath9k_platform_data db120_ath9k_data; |
| 114 | +static struct mdio_board_info db120_mdio0_info[] = { |
| 115 | + { |
| 116 | + .bus_id = "ag71xx-mdio.0", |
| 117 | + .phy_addr = 0, |
| 118 | + .platform_data = &db120_ar8327_data, |
| 119 | + }, |
| 120 | +}; |
| 121 | |
| 122 | -static int db120_pci_plat_dev_init(struct pci_dev *dev) |
| 123 | +static void __init db120_gmac_setup(void) |
| 124 | { |
| 125 | - switch (PCI_SLOT(dev->devfn)) { |
| 126 | - case 0: |
| 127 | - dev->dev.platform_data = &db120_ath9k_data; |
| 128 | - break; |
| 129 | - } |
| 130 | + void __iomem *base; |
| 131 | + u32 t; |
| 132 | |
| 133 | - return 0; |
| 134 | -} |
| 135 | + base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE); |
| 136 | |
| 137 | -static void __init db120_pci_init(u8 *eeprom) |
| 138 | -{ |
| 139 | - memcpy(db120_ath9k_data.eeprom_data, eeprom, |
| 140 | - sizeof(db120_ath9k_data.eeprom_data)); |
| 141 | + t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG); |
| 142 | + t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 | |
| 143 | + AR934X_ETH_CFG_GMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE); |
| 144 | + t |= AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE; |
| 145 | + |
| 146 | + __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG); |
| 147 | |
| 148 | - ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init); |
| 149 | - ath79_register_pci(); |
| 150 | + iounmap(base); |
| 151 | } |
| 152 | -#else |
| 153 | -static inline void db120_pci_init(void) {} |
| 154 | -#endif /* CONFIG_PCI */ |
| 155 | |
| 156 | static void __init db120_setup(void) |
| 157 | { |
| 158 | u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); |
| 159 | |
| 160 | + ath79_gpio_output_select(DB120_GPIO_LED_USB, AR934X_GPIO_OUT_GPIO); |
| 161 | + ath79_register_m25p80(NULL); |
| 162 | + |
| 163 | ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio), |
| 164 | db120_leds_gpio); |
| 165 | ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL, |
| 166 | ARRAY_SIZE(db120_gpio_keys), |
| 167 | db120_gpio_keys); |
| 168 | - ath79_register_spi(&db120_spi_data, db120_spi_info, |
| 169 | - ARRAY_SIZE(db120_spi_info)); |
| 170 | ath79_register_usb(); |
| 171 | ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL); |
| 172 | - db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET); |
| 173 | + ap91_pci_init(art + DB120_PCIE_CALDATA_OFFSET, NULL); |
| 174 | + |
| 175 | + db120_gmac_setup(); |
| 176 | + |
| 177 | + ath79_register_mdio(1, 0x0); |
| 178 | + ath79_register_mdio(0, 0x0); |
| 179 | + |
| 180 | + ath79_init_mac(ath79_eth0_data.mac_addr, art + DB120_MAC0_OFFSET, 0); |
| 181 | + |
| 182 | + mdiobus_register_board_info(db120_mdio0_info, |
| 183 | + ARRAY_SIZE(db120_mdio0_info)); |
| 184 | + |
| 185 | + /* GMAC0 is connected to an AR8327 switch */ |
| 186 | + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; |
| 187 | + ath79_eth0_data.phy_mask = BIT(0); |
| 188 | + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; |
| 189 | + ath79_eth0_pll_data.pll_1000 = 0x06000000; |
| 190 | + ath79_register_eth(0); |
| 191 | + |
| 192 | + /* GMAC1 is connected to the internal switch */ |
| 193 | + ath79_init_mac(ath79_eth1_data.mac_addr, art + DB120_MAC1_OFFSET, 0); |
| 194 | + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; |
| 195 | + ath79_eth1_data.speed = SPEED_1000; |
| 196 | + ath79_eth1_data.duplex = DUPLEX_FULL; |
| 197 | + |
| 198 | + ath79_register_eth(1); |
| 199 | + |
| 200 | + ath79_register_nfc(); |
| 201 | } |
| 202 | |
| 203 | MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board", |
| 204 | --- a/arch/mips/ath79/Kconfig |
| 205 | +++ b/arch/mips/ath79/Kconfig |
| 206 | @@ -43,9 +43,12 @@ config ATH79_MACH_AP81 |
| 207 | config ATH79_MACH_DB120 |
| 208 | bool "Atheros DB120 reference board" |
| 209 | select SOC_AR934X |
| 210 | + select ATH79_DEV_AP9X_PCI if PCI |
| 211 | + select ATH79_DEV_ETH |
| 212 | select ATH79_DEV_GPIO_BUTTONS |
| 213 | select ATH79_DEV_LEDS_GPIO |
| 214 | - select ATH79_DEV_SPI |
| 215 | + select ATH79_DEV_M25P80 |
| 216 | + select ATH79_DEV_NFC |
| 217 | select ATH79_DEV_USB |
| 218 | select ATH79_DEV_WMAC |
| 219 | help |
| 220 | |
