Root/target/linux/brcm47xx/patches-3.3/020-bcma-move-parallel-flash-into-a-union.patch

1--- a/arch/mips/bcm47xx/nvram.c
2+++ b/arch/mips/bcm47xx/nvram.c
3@@ -50,6 +50,9 @@ static void early_nvram_init(void)
4 #ifdef CONFIG_BCM47XX_BCMA
5     case BCM47XX_BUS_TYPE_BCMA:
6         bcma_cc = &bcm47xx_bus.bcma.bus.drv_cc;
7+ if (bcma_cc->flash_type != BCMA_PFLASH)
8+ return;
9+
10         base = bcma_cc->pflash.window;
11         lim = bcma_cc->pflash.window_size;
12         break;
13--- a/drivers/bcma/driver_mips.c
14+++ b/drivers/bcma/driver_mips.c
15@@ -189,6 +189,7 @@ static void bcma_core_mips_flash_detect(
16         break;
17     case BCMA_CC_FLASHT_PARA:
18         bcma_info(bus, "found parallel flash.\n");
19+ bus->drv_cc.flash_type = BCMA_PFLASH;
20         bus->drv_cc.pflash.window = 0x1c000000;
21         bus->drv_cc.pflash.window_size = 0x02000000;
22 
23--- a/include/linux/bcma/bcma_driver_chipcommon.h
24+++ b/include/linux/bcma/bcma_driver_chipcommon.h
25@@ -122,10 +122,68 @@
26 #define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */
27 #define BCMA_CC_JCTL_EN 1 /* Enable Jtag master */
28 #define BCMA_CC_FLASHCTL 0x0040
29+
30+/* Start/busy bit in flashcontrol */
31+#define BCMA_CC_FLASHCTL_OPCODE 0x000000ff
32+#define BCMA_CC_FLASHCTL_ACTION 0x00000700
33+#define BCMA_CC_FLASHCTL_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */
34 #define BCMA_CC_FLASHCTL_START 0x80000000
35 #define BCMA_CC_FLASHCTL_BUSY BCMA_CC_FLASHCTL_START
36+
37+/* flashcontrol action+opcodes for ST flashes */
38+#define BCMA_CC_FLASHCTL_ST_WREN 0x0006 /* Write Enable */
39+#define BCMA_CC_FLASHCTL_ST_WRDIS 0x0004 /* Write Disable */
40+#define BCMA_CC_FLASHCTL_ST_RDSR 0x0105 /* Read Status Register */
41+#define BCMA_CC_FLASHCTL_ST_WRSR 0x0101 /* Write Status Register */
42+#define BCMA_CC_FLASHCTL_ST_READ 0x0303 /* Read Data Bytes */
43+#define BCMA_CC_FLASHCTL_ST_PP 0x0302 /* Page Program */
44+#define BCMA_CC_FLASHCTL_ST_SE 0x02d8 /* Sector Erase */
45+#define BCMA_CC_FLASHCTL_ST_BE 0x00c7 /* Bulk Erase */
46+#define BCMA_CC_FLASHCTL_ST_DP 0x00b9 /* Deep Power-down */
47+#define BCMA_CC_FLASHCTL_ST_RES 0x03ab /* Read Electronic Signature */
48+#define BCMA_CC_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
49+#define BCMA_CC_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
50+
51+
52+/* flashcontrol action+opcodes for Atmel flashes */
53+#define BCMA_CC_FLASHCTL_AT_READ 0x07e8
54+#define BCMA_CC_FLASHCTL_AT_PAGE_READ 0x07d2
55+#define BCMA_CC_FLASHCTL_AT_BUF1_READ
56+#define BCMA_CC_FLASHCTL_AT_BUF2_READ
57+#define BCMA_CC_FLASHCTL_AT_STATUS 0x01d7
58+#define BCMA_CC_FLASHCTL_AT_BUF1_WRITE 0x0384
59+#define BCMA_CC_FLASHCTL_AT_BUF2_WRITE 0x0387
60+#define BCMA_CC_FLASHCTL_AT_BUF1_ERASE_PROGRAM 0x0283
61+#define BCMA_CC_FLASHCTL_AT_BUF2_ERASE_PROGRAM 0x0286
62+#define BCMA_CC_FLASHCTL_AT_BUF1_PROGRAM 0x0288
63+#define BCMA_CC_FLASHCTL_AT_BUF2_PROGRAM 0x0289
64+#define BCMA_CC_FLASHCTL_AT_PAGE_ERASE 0x0281
65+#define BCMA_CC_FLASHCTL_AT_BLOCK_ERASE 0x0250
66+#define BCMA_CC_FLASHCTL_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
67+#define BCMA_CC_FLASHCTL_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
68+#define BCMA_CC_FLASHCTL_AT_BUF1_LOAD 0x0253
69+#define BCMA_CC_FLASHCTL_AT_BUF2_LOAD 0x0255
70+#define BCMA_CC_FLASHCTL_AT_BUF1_COMPARE 0x0260
71+#define BCMA_CC_FLASHCTL_AT_BUF2_COMPARE 0x0261
72+#define BCMA_CC_FLASHCTL_AT_BUF1_REPROGRAM 0x0258
73+#define BCMA_CC_FLASHCTL_AT_BUF2_REPROGRAM 0x0259
74+
75 #define BCMA_CC_FLASHADDR 0x0044
76 #define BCMA_CC_FLASHDATA 0x0048
77+
78+/* Status register bits for ST flashes */
79+#define BCMA_CC_FLASHDATA_ST_WIP 0x01 /* Write In Progress */
80+#define BCMA_CC_FLASHDATA_ST_WEL 0x02 /* Write Enable Latch */
81+#define BCMA_CC_FLASHDATA_ST_BP_MASK 0x1c /* Block Protect */
82+#define BCMA_CC_FLASHDATA_ST_BP_SHIFT 2
83+#define BCMA_CC_FLASHDATA_ST_SRWD 0x80 /* Status Register Write Disable */
84+
85+/* Status register bits for Atmel flashes */
86+#define BCMA_CC_FLASHDATA_AT_READY 0x80
87+#define BCMA_CC_FLASHDATA_AT_MISMATCH 0x40
88+#define BCMA_CC_FLASHDATA_AT_ID_MASK 0x38
89+#define BCMA_CC_FLASHDATA_AT_ID_SHIFT 3
90+
91 #define BCMA_CC_BCAST_ADDR 0x0050
92 #define BCMA_CC_BCAST_DATA 0x0054
93 #define BCMA_CC_GPIOPULLUP 0x0058 /* Rev >= 20 only */
94@@ -360,6 +418,12 @@
95 /* 4313 Chip specific ChipControl register bits */
96 #define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
97 
98+#define BCMA_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
99+#define BCMA_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
100+#define BCMA_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
101+#define BCMA_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
102+
103+
104 /* Data for the PMU, if available.
105  * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
106  */
107@@ -369,6 +433,10 @@ struct bcma_chipcommon_pmu {
108 };
109 
110 #ifdef CONFIG_BCMA_DRIVER_MIPS
111+enum bcma_flash_type {
112+ BCMA_PFLASH,
113+};
114+
115 struct bcma_pflash {
116     u8 buswidth;
117     u32 window;
118@@ -394,7 +462,10 @@ struct bcma_drv_cc {
119     u16 fast_pwrup_delay;
120     struct bcma_chipcommon_pmu pmu;
121 #ifdef CONFIG_BCMA_DRIVER_MIPS
122- struct bcma_pflash pflash;
123+ enum bcma_flash_type flash_type;
124+ union {
125+ struct bcma_pflash pflash;
126+ };
127 
128     int nr_serial_ports;
129     struct bcma_serial_port serial_ports[4];
130

Archive Download this file

Branches:
backfire
history
master
release_2010-11-17
release_2010-12-14
release_2011-02-23
release_2011-05-28
release_2011-08-27
release_2011-11-13
release_2012-03-18
release_2012-04-09
release_2012-10-11
uclibc_nptl



interactive