| 1 | From db1cc4ee366bf0528fcb8b4afa65dec915d98889 Mon Sep 17 00:00:00 2001 |
| 2 | From: Florian Fainelli <florian@openwrt.org> |
| 3 | Date: Wed, 25 Jan 2012 17:39:55 +0100 |
| 4 | Subject: [PATCH 04/63] MIPS: BCM63XX: be consistent in clock bits enable naming |
| 5 | |
| 6 | Remove the _CLK suffix from the BCM6368 clock bits definitions to be |
| 7 | consistent with what is already present. |
| 8 | |
| 9 | Signed-off-by: Florian Fainelli <florian@openwrt.org> |
| 10 | --- |
| 11 | arch/mips/bcm63xx/clk.c | 6 ++-- |
| 12 | arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 36 ++++++++++---------- |
| 13 | 2 files changed, 21 insertions(+), 21 deletions(-) |
| 14 | |
| 15 | --- a/arch/mips/bcm63xx/clk.c |
| 16 | +++ b/arch/mips/bcm63xx/clk.c |
| 17 | @@ -120,7 +120,7 @@ static void enetsw_set(struct clk *clk, |
| 18 | { |
| 19 | if (!BCMCPU_IS_6368()) |
| 20 | return; |
| 21 | - bcm_hwclock_set(CKCTL_6368_ROBOSW_CLK_EN | |
| 22 | + bcm_hwclock_set(CKCTL_6368_ROBOSW_EN | |
| 23 | CKCTL_6368_SWPKT_USB_EN | |
| 24 | CKCTL_6368_SWPKT_SAR_EN, enable); |
| 25 | if (enable) { |
| 26 | @@ -163,7 +163,7 @@ static void usbh_set(struct clk *clk, in |
| 27 | if (BCMCPU_IS_6348()) |
| 28 | bcm_hwclock_set(CKCTL_6348_USBH_EN, enable); |
| 29 | else if (BCMCPU_IS_6368()) |
| 30 | - bcm_hwclock_set(CKCTL_6368_USBH_CLK_EN, enable); |
| 31 | + bcm_hwclock_set(CKCTL_6368_USBH_EN, enable); |
| 32 | } |
| 33 | |
| 34 | static struct clk clk_usbh = { |
| 35 | @@ -199,7 +199,7 @@ static void xtm_set(struct clk *clk, int |
| 36 | if (!BCMCPU_IS_6368()) |
| 37 | return; |
| 38 | |
| 39 | - bcm_hwclock_set(CKCTL_6368_SAR_CLK_EN | |
| 40 | + bcm_hwclock_set(CKCTL_6368_SAR_EN | |
| 41 | CKCTL_6368_SWPKT_SAR_EN, enable); |
| 42 | |
| 43 | if (enable) { |
| 44 | --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |
| 45 | +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |
| 46 | @@ -90,29 +90,29 @@ |
| 47 | #define CKCTL_6368_PHYMIPS_EN (1 << 6) |
| 48 | #define CKCTL_6368_SWPKT_USB_EN (1 << 7) |
| 49 | #define CKCTL_6368_SWPKT_SAR_EN (1 << 8) |
| 50 | -#define CKCTL_6368_SPI_CLK_EN (1 << 9) |
| 51 | -#define CKCTL_6368_USBD_CLK_EN (1 << 10) |
| 52 | -#define CKCTL_6368_SAR_CLK_EN (1 << 11) |
| 53 | -#define CKCTL_6368_ROBOSW_CLK_EN (1 << 12) |
| 54 | -#define CKCTL_6368_UTOPIA_CLK_EN (1 << 13) |
| 55 | -#define CKCTL_6368_PCM_CLK_EN (1 << 14) |
| 56 | -#define CKCTL_6368_USBH_CLK_EN (1 << 15) |
| 57 | +#define CKCTL_6368_SPI_EN (1 << 9) |
| 58 | +#define CKCTL_6368_USBD_EN (1 << 10) |
| 59 | +#define CKCTL_6368_SAR_EN (1 << 11) |
| 60 | +#define CKCTL_6368_ROBOSW_EN (1 << 12) |
| 61 | +#define CKCTL_6368_UTOPIA_EN (1 << 13) |
| 62 | +#define CKCTL_6368_PCM_EN (1 << 14) |
| 63 | +#define CKCTL_6368_USBH_EN (1 << 15) |
| 64 | #define CKCTL_6368_DISABLE_GLESS_EN (1 << 16) |
| 65 | -#define CKCTL_6368_NAND_CLK_EN (1 << 17) |
| 66 | -#define CKCTL_6368_IPSEC_CLK_EN (1 << 17) |
| 67 | +#define CKCTL_6368_NAND_EN (1 << 17) |
| 68 | +#define CKCTL_6368_IPSEC_EN (1 << 17) |
| 69 | |
| 70 | #define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \ |
| 71 | CKCTL_6368_SWPKT_SAR_EN | \ |
| 72 | - CKCTL_6368_SPI_CLK_EN | \ |
| 73 | - CKCTL_6368_USBD_CLK_EN | \ |
| 74 | - CKCTL_6368_SAR_CLK_EN | \ |
| 75 | - CKCTL_6368_ROBOSW_CLK_EN | \ |
| 76 | - CKCTL_6368_UTOPIA_CLK_EN | \ |
| 77 | - CKCTL_6368_PCM_CLK_EN | \ |
| 78 | - CKCTL_6368_USBH_CLK_EN | \ |
| 79 | + CKCTL_6368_SPI_EN | \ |
| 80 | + CKCTL_6368_USBD_EN | \ |
| 81 | + CKCTL_6368_SAR_EN | \ |
| 82 | + CKCTL_6368_ROBOSW_EN | \ |
| 83 | + CKCTL_6368_UTOPIA_EN | \ |
| 84 | + CKCTL_6368_PCM_EN | \ |
| 85 | + CKCTL_6368_USBH_EN | \ |
| 86 | CKCTL_6368_DISABLE_GLESS_EN | \ |
| 87 | - CKCTL_6368_NAND_CLK_EN | \ |
| 88 | - CKCTL_6368_IPSEC_CLK_EN) |
| 89 | + CKCTL_6368_NAND_EN | \ |
| 90 | + CKCTL_6368_IPSEC_EN) |
| 91 | |
| 92 | /* System PLL Control register */ |
| 93 | #define PERF_SYS_PLL_CTL_REG 0x8 |
| 94 | |
