| 1 | From 04456614952a9a848192253439b4e361f0321cb5 Mon Sep 17 00:00:00 2001 |
| 2 | From: Florian Fainelli <florian@openwrt.org> |
| 3 | Date: Wed, 25 Jan 2012 17:39:51 +0100 |
| 4 | Subject: [PATCH 05/63] MIPS: BCM63XX: add IRQ_SPI and CPU specific SPI IRQ values |
| 5 | |
| 6 | Signed-off-by: Florian Fainelli <florian@openwrt.org> |
| 7 | --- |
| 8 | arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 7 +++++++ |
| 9 | 1 files changed, 7 insertions(+), 0 deletions(-) |
| 10 | |
| 11 | --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h |
| 12 | +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h |
| 13 | @@ -478,6 +478,7 @@ static inline unsigned long bcm63xx_regs |
| 14 | */ |
| 15 | enum bcm63xx_irq { |
| 16 | IRQ_TIMER = 0, |
| 17 | + IRQ_SPI, |
| 18 | IRQ_UART0, |
| 19 | IRQ_UART1, |
| 20 | IRQ_DSL, |
| 21 | @@ -509,6 +510,7 @@ enum bcm63xx_irq { |
| 22 | * 6338 irqs |
| 23 | */ |
| 24 | #define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) |
| 25 | +#define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1) |
| 26 | #define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2) |
| 27 | #define BCM_6338_UART1_IRQ 0 |
| 28 | #define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5) |
| 29 | @@ -539,6 +541,7 @@ enum bcm63xx_irq { |
| 30 | * 6345 irqs |
| 31 | */ |
| 32 | #define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) |
| 33 | +#define BCM_6345_SPI_IRQ 0 |
| 34 | #define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2) |
| 35 | #define BCM_6345_UART1_IRQ 0 |
| 36 | #define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3) |
| 37 | @@ -569,6 +572,7 @@ enum bcm63xx_irq { |
| 38 | * 6348 irqs |
| 39 | */ |
| 40 | #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) |
| 41 | +#define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1) |
| 42 | #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2) |
| 43 | #define BCM_6348_UART1_IRQ 0 |
| 44 | #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4) |
| 45 | @@ -599,6 +603,7 @@ enum bcm63xx_irq { |
| 46 | * 6358 irqs |
| 47 | */ |
| 48 | #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) |
| 49 | +#define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1) |
| 50 | #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2) |
| 51 | #define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3) |
| 52 | #define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29) |
| 53 | @@ -638,6 +643,7 @@ enum bcm63xx_irq { |
| 54 | #define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) |
| 55 | |
| 56 | #define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) |
| 57 | +#define BCM_6368_SPI_IRQ (IRQ_INTERNAL_BASE + 1) |
| 58 | #define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2) |
| 59 | #define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3) |
| 60 | #define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4) |
| 61 | @@ -677,6 +683,7 @@ extern const int *bcm63xx_irqs; |
| 62 | |
| 63 | #define __GEN_CPU_IRQ_TABLE(__cpu) \ |
| 64 | [IRQ_TIMER] = BCM_## __cpu ##_TIMER_IRQ, \ |
| 65 | + [IRQ_SPI] = BCM_## __cpu ##_SPI_IRQ, \ |
| 66 | [IRQ_UART0] = BCM_## __cpu ##_UART0_IRQ, \ |
| 67 | [IRQ_UART1] = BCM_## __cpu ##_UART1_IRQ, \ |
| 68 | [IRQ_DSL] = BCM_## __cpu ##_DSL_IRQ, \ |
| 69 | |
