| 1 | From 32511e7dfab9b9cabe2772e3f5430559294a8d1c Mon Sep 17 00:00:00 2001 |
| 2 | From: Florian Fainelli <florian@openwrt.org> |
| 3 | Date: Wed, 25 Jan 2012 17:40:01 +0100 |
| 4 | Subject: [PATCH 09/63] MIPS: BCM63XX: remove SPI2 register |
| 5 | |
| 6 | This register was introduced with the support of the BCM6368 CPU in the idea |
| 7 | that its internal layout was different from the other CPUs SPI controller. |
| 8 | The controller is actually the same as the one present on BCM6358 so we can |
| 9 | remove this register and use the usual SPI register instead. |
| 10 | |
| 11 | Signed-off-by: Florian Fainelli <florian@openwrt.org> |
| 12 | --- |
| 13 | arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 10 +--------- |
| 14 | 1 files changed, 1 insertions(+), 9 deletions(-) |
| 15 | |
| 16 | --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h |
| 17 | +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h |
| 18 | @@ -102,7 +102,6 @@ enum bcm63xx_regs_set { |
| 19 | RSET_UART1, |
| 20 | RSET_GPIO, |
| 21 | RSET_SPI, |
| 22 | - RSET_SPI2, |
| 23 | RSET_UDC0, |
| 24 | RSET_OHCI0, |
| 25 | RSET_OHCI_PRIV, |
| 26 | @@ -166,7 +165,6 @@ enum bcm63xx_regs_set { |
| 27 | #define BCM_6338_UART1_BASE (0xdeadbeef) |
| 28 | #define BCM_6338_GPIO_BASE (0xfffe0400) |
| 29 | #define BCM_6338_SPI_BASE (0xfffe0c00) |
| 30 | -#define BCM_6338_SPI2_BASE (0xdeadbeef) |
| 31 | #define BCM_6338_UDC0_BASE (0xdeadbeef) |
| 32 | #define BCM_6338_USBDMA_BASE (0xfffe2400) |
| 33 | #define BCM_6338_OHCI0_BASE (0xdeadbeef) |
| 34 | @@ -210,7 +208,6 @@ enum bcm63xx_regs_set { |
| 35 | #define BCM_6345_UART1_BASE (0xdeadbeef) |
| 36 | #define BCM_6345_GPIO_BASE (0xfffe0400) |
| 37 | #define BCM_6345_SPI_BASE (0xdeadbeef) |
| 38 | -#define BCM_6345_SPI2_BASE (0xdeadbeef) |
| 39 | #define BCM_6345_UDC0_BASE (0xdeadbeef) |
| 40 | #define BCM_6345_USBDMA_BASE (0xfffe2800) |
| 41 | #define BCM_6345_ENET0_BASE (0xfffe1800) |
| 42 | @@ -253,7 +250,6 @@ enum bcm63xx_regs_set { |
| 43 | #define BCM_6348_UART1_BASE (0xdeadbeef) |
| 44 | #define BCM_6348_GPIO_BASE (0xfffe0400) |
| 45 | #define BCM_6348_SPI_BASE (0xfffe0c00) |
| 46 | -#define BCM_6348_SPI2_BASE (0xdeadbeef) |
| 47 | #define BCM_6348_UDC0_BASE (0xfffe1000) |
| 48 | #define BCM_6348_OHCI0_BASE (0xfffe1b00) |
| 49 | #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00) |
| 50 | @@ -294,7 +290,6 @@ enum bcm63xx_regs_set { |
| 51 | #define BCM_6358_UART1_BASE (0xfffe0120) |
| 52 | #define BCM_6358_GPIO_BASE (0xfffe0080) |
| 53 | #define BCM_6358_SPI_BASE (0xfffe0800) |
| 54 | -#define BCM_6358_SPI2_BASE (0xfffe0800) |
| 55 | #define BCM_6358_UDC0_BASE (0xfffe0800) |
| 56 | #define BCM_6358_OHCI0_BASE (0xfffe1400) |
| 57 | #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) |
| 58 | @@ -335,8 +330,7 @@ enum bcm63xx_regs_set { |
| 59 | #define BCM_6368_UART0_BASE (0xb0000100) |
| 60 | #define BCM_6368_UART1_BASE (0xb0000120) |
| 61 | #define BCM_6368_GPIO_BASE (0xb0000080) |
| 62 | -#define BCM_6368_SPI_BASE (0xdeadbeef) |
| 63 | -#define BCM_6368_SPI2_BASE (0xb0000800) |
| 64 | +#define BCM_6368_SPI_BASE (0xb0000800) |
| 65 | #define BCM_6368_UDC0_BASE (0xdeadbeef) |
| 66 | #define BCM_6368_OHCI0_BASE (0xb0001600) |
| 67 | #define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef) |
| 68 | @@ -383,7 +377,6 @@ extern const unsigned long *bcm63xx_regs |
| 69 | __GEN_RSET_BASE(__cpu, UART1) \ |
| 70 | __GEN_RSET_BASE(__cpu, GPIO) \ |
| 71 | __GEN_RSET_BASE(__cpu, SPI) \ |
| 72 | - __GEN_RSET_BASE(__cpu, SPI2) \ |
| 73 | __GEN_RSET_BASE(__cpu, UDC0) \ |
| 74 | __GEN_RSET_BASE(__cpu, OHCI0) \ |
| 75 | __GEN_RSET_BASE(__cpu, OHCI_PRIV) \ |
| 76 | @@ -422,7 +415,6 @@ extern const unsigned long *bcm63xx_regs |
| 77 | [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \ |
| 78 | [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \ |
| 79 | [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \ |
| 80 | - [RSET_SPI2] = BCM_## __cpu ##_SPI2_BASE, \ |
| 81 | [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \ |
| 82 | [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \ |
| 83 | [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \ |
| 84 | |
