| 1 | From a9168d99658bd050e49afc06880d140e2fc2c231 Mon Sep 17 00:00:00 2001 |
| 2 | From: Jonas Gorski <jonas.gorski@gmail.com> |
| 3 | Date: Tue, 12 Jun 2012 10:23:40 +0200 |
| 4 | Subject: [PATCH 3/8] MIPS: BCM63XX: Use the Chip ID register for identifying the SoC |
| 5 | |
| 6 | Newer BCM63XX SoCs use virtually the same CPU ID, differing only in the |
| 7 | revision bits. But since they all have the Chip ID register at the same |
| 8 | location, we can use that to identify the SoC we are running on. |
| 9 | |
| 10 | Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> |
| 11 | Cc: linux-mips@linux-mips.org |
| 12 | Cc: Maxime Bizon <mbizon@freebox.fr> |
| 13 | Cc: Florian Fainelli <florian@openwrt.org> |
| 14 | Cc: Kevin Cernekee <cernekee@gmail.com> |
| 15 | Patchwork: https://patchwork.linux-mips.org/patch/3955/ |
| 16 | Reviewed-by: Florian Fainelli <florian@openwrt.org> |
| 17 | Signed-off-by: Ralf Baechle <ralf@linux-mips.org> |
| 18 | --- |
| 19 | arch/mips/bcm63xx/cpu.c | 20 ++++++++++++-------- |
| 20 | 1 files changed, 12 insertions(+), 8 deletions(-) |
| 21 | |
| 22 | --- a/arch/mips/bcm63xx/cpu.c |
| 23 | +++ b/arch/mips/bcm63xx/cpu.c |
| 24 | @@ -228,17 +228,21 @@ void __init bcm63xx_cpu_init(void) |
| 25 | bcm63xx_irqs = bcm6345_irqs; |
| 26 | break; |
| 27 | case CPU_BMIPS4350: |
| 28 | - switch (read_c0_prid() & 0xf0) { |
| 29 | - case 0x10: |
| 30 | + if ((read_c0_prid() & 0xf0) == 0x10) { |
| 31 | expected_cpu_id = BCM6358_CPU_ID; |
| 32 | bcm63xx_regs_base = bcm6358_regs_base; |
| 33 | bcm63xx_irqs = bcm6358_irqs; |
| 34 | - break; |
| 35 | - case 0x30: |
| 36 | - expected_cpu_id = BCM6368_CPU_ID; |
| 37 | - bcm63xx_regs_base = bcm6368_regs_base; |
| 38 | - bcm63xx_irqs = bcm6368_irqs; |
| 39 | - break; |
| 40 | + } else { |
| 41 | + /* all newer chips have the same chip id location */ |
| 42 | + u16 chip_id = bcm_readw(BCM_6368_PERF_BASE); |
| 43 | + |
| 44 | + switch (chip_id) { |
| 45 | + case BCM6368_CPU_ID: |
| 46 | + expected_cpu_id = BCM6368_CPU_ID; |
| 47 | + bcm63xx_regs_base = bcm6368_regs_base; |
| 48 | + bcm63xx_irqs = bcm6368_irqs; |
| 49 | + break; |
| 50 | + } |
| 51 | } |
| 52 | break; |
| 53 | } |
| 54 | |
