| 1 | From d8237d704fc25eb2fc25ef4403608b78c6a6d4be Mon Sep 17 00:00:00 2001 |
| 2 | From: Jonas Gorski <jonas.gorski@gmail.com> |
| 3 | Date: Sun, 15 Jul 2012 20:08:57 +0200 |
| 4 | Subject: [PATCH 54/81] bcm63xx_enet: enable rgmii clock on external ports |
| 5 | |
| 6 | --- |
| 7 | arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 13 +++++++++++++ |
| 8 | drivers/net/ethernet/broadcom/bcm63xx_enet.c | 12 ++++++++++++ |
| 9 | 2 files changed, 25 insertions(+), 0 deletions(-) |
| 10 | |
| 11 | --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |
| 12 | +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |
| 13 | @@ -838,6 +838,19 @@ |
| 14 | #define ENETSW_PORTOV_FDX_MASK (1 << 1) |
| 15 | #define ENETSW_PORTOV_LINKUP_MASK (1 << 0) |
| 16 | |
| 17 | +/* Port RGMII control register */ |
| 18 | +#define ENETSW_RGMII_CTRL_REG(x) (0x60 + (x)) |
| 19 | +#define ENETSW_RGMII_CTRL_GMII_CLK_EN (1 << 7) |
| 20 | +#define ENETSW_RGMII_CTRL_MII_OVERRIDE_EN (1 << 6) |
| 21 | +#define ENETSW_RGMII_CTRL_MII_MODE_MASK (3 << 4) |
| 22 | +#define ENETSW_RGMII_CTRL_RGMII_MODE (0 << 4) |
| 23 | +#define ENETSW_RGMII_CTRL_MII_MODE (1 << 4) |
| 24 | +#define ENETSW_RGMII_CTRL_RVMII_MODE (2 << 4) |
| 25 | +#define ENETSW_RGMII_CTRL_TIMING_SEL_EN (1 << 0) |
| 26 | + |
| 27 | +/* Port RGMII timing register */ |
| 28 | +#define ENETSW_RGMII_TIMING_REG(x) (0x68 + (x)) |
| 29 | + |
| 30 | /* MDIO control register */ |
| 31 | #define ENETSW_MDIOC_REG (0xb0) |
| 32 | #define ENETSW_MDIOC_EXT_MASK (1 << 16) |
| 33 | --- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c |
| 34 | +++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c |
| 35 | @@ -2222,6 +2222,18 @@ static int bcm_enetsw_open(struct net_de |
| 36 | priv->sw_port_link[i] = 0; |
| 37 | } |
| 38 | |
| 39 | + /* enable external ports */ |
| 40 | + for (i = ENETSW_RGMII_PORT0; i < priv->num_ports; i++) { |
| 41 | + u8 rgmii_ctrl; |
| 42 | + |
| 43 | + if (!priv->used_ports[i].used) |
| 44 | + continue; |
| 45 | + |
| 46 | + rgmii_ctrl = enetsw_readb(priv, ENETSW_RGMII_CTRL_REG(i)); |
| 47 | + rgmii_ctrl |= ENETSW_RGMII_CTRL_GMII_CLK_EN; |
| 48 | + enetsw_writeb(priv, rgmii_ctrl, ENETSW_RGMII_CTRL_REG(i)); |
| 49 | + } |
| 50 | + |
| 51 | /* reset mib */ |
| 52 | val = enetsw_readb(priv, ENETSW_GMCR_REG); |
| 53 | val |= ENETSW_GMCR_RST_MIB_MASK; |
| 54 | |
