| 1 | From f1c1bfa89cdac76a215d0e21161da9f8f8373437 Mon Sep 17 00:00:00 2001 |
| 2 | From: Jonas Gorski <jonas.gorski@gmail.com> |
| 3 | Date: Tue, 14 Jun 2011 21:14:39 +0200 |
| 4 | Subject: [PATCH 40/84] MIPS: BCM63XX: add support for BCM6328 in bcm_enetsw |
| 5 | |
| 6 | Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> |
| 7 | --- |
| 8 | arch/mips/bcm63xx/clk.c | 34 ++++++++++++++----- |
| 9 | arch/mips/bcm63xx/dev-enet.c | 9 +++-- |
| 10 | .../include/asm/mach-bcm63xx/bcm63xx_dev_enet.h | 1 + |
| 11 | 3 files changed, 32 insertions(+), 12 deletions(-) |
| 12 | |
| 13 | --- a/arch/mips/bcm63xx/clk.c |
| 14 | +++ b/arch/mips/bcm63xx/clk.c |
| 15 | @@ -118,21 +118,37 @@ static struct clk clk_ephy = { |
| 16 | */ |
| 17 | static void enetsw_set(struct clk *clk, int enable) |
| 18 | { |
| 19 | - if (!BCMCPU_IS_6368()) |
| 20 | + u32 mask; |
| 21 | + |
| 22 | + if (!BCMCPU_IS_6328() && !BCMCPU_IS_6368()) |
| 23 | return; |
| 24 | - bcm_hwclock_set(CKCTL_6368_ROBOSW_EN | |
| 25 | - CKCTL_6368_SWPKT_USB_EN | |
| 26 | - CKCTL_6368_SWPKT_SAR_EN, enable); |
| 27 | + |
| 28 | + if (BCMCPU_IS_6328()) |
| 29 | + mask = CKCTL_6328_ROBOSW_EN; |
| 30 | + else |
| 31 | + mask = CKCTL_6368_ROBOSW_EN | CKCTL_6368_SWPKT_USB_EN | |
| 32 | + CKCTL_6368_SWPKT_SAR_EN; |
| 33 | + |
| 34 | + bcm_hwclock_set(mask, enable); |
| 35 | if (enable) { |
| 36 | + u32 reg; |
| 37 | u32 val; |
| 38 | |
| 39 | + if (BCMCPU_IS_6328()) { |
| 40 | + reg = PERF_SOFTRESET_6328_REG; |
| 41 | + mask = SOFTRESET_6328_ENETSW_MASK; |
| 42 | + } else { |
| 43 | + reg = PERF_SOFTRESET_6368_REG; |
| 44 | + mask = SOFTRESET_6368_ENETSW_MASK; |
| 45 | + } |
| 46 | + |
| 47 | /* reset switch core afer clock change */ |
| 48 | - val = bcm_perf_readl(PERF_SOFTRESET_6368_REG); |
| 49 | - val &= ~SOFTRESET_6368_ENETSW_MASK; |
| 50 | - bcm_perf_writel(val, PERF_SOFTRESET_6368_REG); |
| 51 | + val = bcm_perf_readl(reg); |
| 52 | + val &= ~mask; |
| 53 | + bcm_perf_writel(val, reg); |
| 54 | msleep(10); |
| 55 | - val |= SOFTRESET_6368_ENETSW_MASK; |
| 56 | - bcm_perf_writel(val, PERF_SOFTRESET_6368_REG); |
| 57 | + val |= mask; |
| 58 | + bcm_perf_writel(val, reg); |
| 59 | msleep(10); |
| 60 | } |
| 61 | } |
| 62 | --- a/arch/mips/bcm63xx/dev-enet.c |
| 63 | +++ b/arch/mips/bcm63xx/dev-enet.c |
| 64 | @@ -141,7 +141,7 @@ static int __init register_shared(void) |
| 65 | shared_res[0].end = shared_res[0].start; |
| 66 | shared_res[0].end += (RSET_ENETDMA_SIZE) - 1; |
| 67 | |
| 68 | - if (BCMCPU_IS_6368()) |
| 69 | + if (BCMCPU_IS_6328() || BCMCPU_IS_6368()) |
| 70 | chan_count = 32; |
| 71 | else |
| 72 | chan_count = 16; |
| 73 | @@ -224,7 +224,7 @@ bcm63xx_enetsw_register(const struct bcm |
| 74 | { |
| 75 | int ret; |
| 76 | |
| 77 | - if (!BCMCPU_IS_6368()) |
| 78 | + if (!BCMCPU_IS_6328() && !BCMCPU_IS_6368()) |
| 79 | return -ENODEV; |
| 80 | |
| 81 | ret = register_shared(); |
| 82 | @@ -241,7 +241,10 @@ bcm63xx_enetsw_register(const struct bcm |
| 83 | |
| 84 | memcpy(bcm63xx_enetsw_device.dev.platform_data, pd, sizeof (*pd)); |
| 85 | |
| 86 | - enetsw_pd.num_ports = ENETSW_PORTS_6368; |
| 87 | + if (BCMCPU_IS_6328()) |
| 88 | + enetsw_pd.num_ports = ENETSW_PORTS_6328; |
| 89 | + else if (BCMCPU_IS_6368()) |
| 90 | + enetsw_pd.num_ports = ENETSW_PORTS_6368; |
| 91 | |
| 92 | ret = platform_device_register(&bcm63xx_enetsw_device); |
| 93 | if (ret) |
| 94 | --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h |
| 95 | +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h |
| 96 | @@ -43,6 +43,7 @@ struct bcm63xx_enet_platform_data { |
| 97 | * on board ethernet switch platform data |
| 98 | */ |
| 99 | #define ENETSW_MAX_PORT 6 |
| 100 | +#define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */ |
| 101 | #define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */ |
| 102 | |
| 103 | #define ENETSW_RGMII_PORT0 4 |
| 104 | |
