Root/target/linux/cns3xxx/patches-3.3/200-dwc_otg.patch

1--- a/drivers/Makefile
2+++ b/drivers/Makefile
3@@ -71,6 +71,7 @@ obj-$(CONFIG_PARIDE) += block/paride/
4 obj-$(CONFIG_TC) += tc/
5 obj-$(CONFIG_UWB) += uwb/
6 obj-$(CONFIG_USB_OTG_UTILS) += usb/
7+obj-$(CONFIG_USB_DWC_OTG) += usb/dwc/
8 obj-$(CONFIG_USB) += usb/
9 obj-$(CONFIG_PCI) += usb/
10 obj-$(CONFIG_USB_GADGET) += usb/
11--- a/drivers/usb/Kconfig
12+++ b/drivers/usb/Kconfig
13@@ -134,6 +134,8 @@ source "drivers/usb/musb/Kconfig"
14 
15 source "drivers/usb/renesas_usbhs/Kconfig"
16 
17+source "drivers/usb/dwc/Kconfig"
18+
19 source "drivers/usb/class/Kconfig"
20 
21 source "drivers/usb/storage/Kconfig"
22--- /dev/null
23+++ b/drivers/usb/dwc/Kconfig
24@@ -0,0 +1,44 @@
25+#
26+# USB Dual Role (OTG-ready) Controller Drivers
27+# for silicon based on Synopsys DesignWare IP
28+#
29+
30+comment "Enable Host or Gadget support for DesignWare OTG controller"
31+depends on !USB && USB_GADGET=n
32+
33+config USB_DWC_OTG
34+ tristate "Synopsys DWC OTG Controller"
35+ depends on USB
36+ help
37+ This driver provides USB Device Controller support for the
38+ Synopsys DesignWare USB OTG Core used on the Cavium CNS34xx SOC.
39+
40+config DWC_DEBUG
41+ bool "Enable DWC Debugging"
42+ depends on USB_DWC_OTG
43+ default n
44+ help
45+ Enable DWC driver debugging
46+
47+choice
48+ prompt "DWC Mode Selection"
49+ depends on USB_DWC_OTG
50+ default DWC_HOST_ONLY
51+ help
52+ Select the DWC Core in OTG, Host only, or Device only mode.
53+
54+config DWC_HOST_ONLY
55+ bool "DWC Host Only Mode"
56+
57+config DWC_OTG_MODE
58+ bool "DWC OTG Mode"
59+ select USB_GADGET
60+ select USB_GADGET_SELECTED
61+
62+config DWC_DEVICE_ONLY
63+ bool "DWC Device Only Mode"
64+ select USB_GADGET
65+ select USB_GADGET_SELECTED
66+
67+endchoice
68+
69--- /dev/null
70+++ b/drivers/usb/dwc/Makefile
71@@ -0,0 +1,26 @@
72+#
73+# Makefile for DWC_otg Highspeed USB controller driver
74+#
75+
76+EXTRA_CFLAGS += -DDWC_HS_ELECT_TST
77+#EXTRA_CFLAGS += -Dlinux -DDWC_HS_ELECT_TST
78+#EXTRA_CFLAGS += -DDWC_EN_ISOC
79+
80+ifneq ($(CONFIG_DWC_HOST_ONLY),)
81+EXTRA_CFLAGS += -DDWC_HOST_ONLY
82+endif
83+
84+ifneq ($(CONFIG_DWC_DEVICE_ONLY),)
85+EXTRA_CFLAGS += -DDWC_DEVICE_ONLY
86+endif
87+
88+ifneq ($(CONFIG_DWC_DEBUG),)
89+EXTRA_CFLAGS += -DDEBUG
90+endif
91+
92+obj-$(CONFIG_USB_DWC_OTG) := dwc_otg.o
93+
94+dwc_otg-objs := otg_driver.o otg_attr.o
95+dwc_otg-objs += otg_cil.o otg_cil_intr.o
96+dwc_otg-objs += otg_pcd.o otg_pcd_intr.o
97+dwc_otg-objs += otg_hcd.o otg_hcd_intr.o otg_hcd_queue.o
98--- /dev/null
99+++ b/drivers/usb/dwc/otg_attr.c
100@@ -0,0 +1,886 @@
101+/* ==========================================================================
102+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.c $
103+ * $Revision: #31 $
104+ * $Date: 2008/07/15 $
105+ * $Change: 1064918 $
106+ *
107+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
108+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
109+ * otherwise expressly agreed to in writing between Synopsys and you.
110+ *
111+ * The Software IS NOT an item of Licensed Software or Licensed Product under
112+ * any End User Software License Agreement or Agreement for Licensed Product
113+ * with Synopsys or any supplement thereto. You are permitted to use and
114+ * redistribute this Software in source and binary forms, with or without
115+ * modification, provided that redistributions of source code must retain this
116+ * notice. You may not view, use, disclose, copy or distribute this file or
117+ * any information contained herein except pursuant to this license grant from
118+ * Synopsys. If you do not agree with this notice, including the disclaimer
119+ * below, then you are not authorized to use the Software.
120+ *
121+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
122+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
123+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
124+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
125+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
126+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
127+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
128+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
129+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
130+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
131+ * DAMAGE.
132+ * ========================================================================== */
133+
134+/** @file
135+ *
136+ * The diagnostic interface will provide access to the controller for
137+ * bringing up the hardware and testing. The Linux driver attributes
138+ * feature will be used to provide the Linux Diagnostic
139+ * Interface. These attributes are accessed through sysfs.
140+ */
141+
142+/** @page "Linux Module Attributes"
143+ *
144+ * The Linux module attributes feature is used to provide the Linux
145+ * Diagnostic Interface. These attributes are accessed through sysfs.
146+ * The diagnostic interface will provide access to the controller for
147+ * bringing up the hardware and testing.
148+
149+
150+ The following table shows the attributes.
151+ <table>
152+ <tr>
153+ <td><b> Name</b></td>
154+ <td><b> Description</b></td>
155+ <td><b> Access</b></td>
156+ </tr>
157+
158+ <tr>
159+ <td> mode </td>
160+ <td> Returns the current mode: 0 for device mode, 1 for host mode</td>
161+ <td> Read</td>
162+ </tr>
163+
164+ <tr>
165+ <td> hnpcapable </td>
166+ <td> Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register.
167+ Read returns the current value.</td>
168+ <td> Read/Write</td>
169+ </tr>
170+
171+ <tr>
172+ <td> srpcapable </td>
173+ <td> Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register.
174+ Read returns the current value.</td>
175+ <td> Read/Write</td>
176+ </tr>
177+
178+ <tr>
179+ <td> hnp </td>
180+ <td> Initiates the Host Negotiation Protocol. Read returns the status.</td>
181+ <td> Read/Write</td>
182+ </tr>
183+
184+ <tr>
185+ <td> srp </td>
186+ <td> Initiates the Session Request Protocol. Read returns the status.</td>
187+ <td> Read/Write</td>
188+ </tr>
189+
190+ <tr>
191+ <td> buspower </td>
192+ <td> Gets or sets the Power State of the bus (0 - Off or 1 - On)</td>
193+ <td> Read/Write</td>
194+ </tr>
195+
196+ <tr>
197+ <td> bussuspend </td>
198+ <td> Suspends the USB bus.</td>
199+ <td> Read/Write</td>
200+ </tr>
201+
202+ <tr>
203+ <td> busconnected </td>
204+ <td> Gets the connection status of the bus</td>
205+ <td> Read</td>
206+ </tr>
207+
208+ <tr>
209+ <td> gotgctl </td>
210+ <td> Gets or sets the Core Control Status Register.</td>
211+ <td> Read/Write</td>
212+ </tr>
213+
214+ <tr>
215+ <td> gusbcfg </td>
216+ <td> Gets or sets the Core USB Configuration Register</td>
217+ <td> Read/Write</td>
218+ </tr>
219+
220+ <tr>
221+ <td> grxfsiz </td>
222+ <td> Gets or sets the Receive FIFO Size Register</td>
223+ <td> Read/Write</td>
224+ </tr>
225+
226+ <tr>
227+ <td> gnptxfsiz </td>
228+ <td> Gets or sets the non-periodic Transmit Size Register</td>
229+ <td> Read/Write</td>
230+ </tr>
231+
232+ <tr>
233+ <td> gpvndctl </td>
234+ <td> Gets or sets the PHY Vendor Control Register</td>
235+ <td> Read/Write</td>
236+ </tr>
237+
238+ <tr>
239+ <td> ggpio </td>
240+ <td> Gets the value in the lower 16-bits of the General Purpose IO Register
241+ or sets the upper 16 bits.</td>
242+ <td> Read/Write</td>
243+ </tr>
244+
245+ <tr>
246+ <td> guid </td>
247+ <td> Gets or sets the value of the User ID Register</td>
248+ <td> Read/Write</td>
249+ </tr>
250+
251+ <tr>
252+ <td> gsnpsid </td>
253+ <td> Gets the value of the Synopsys ID Regester</td>
254+ <td> Read</td>
255+ </tr>
256+
257+ <tr>
258+ <td> devspeed </td>
259+ <td> Gets or sets the device speed setting in the DCFG register</td>
260+ <td> Read/Write</td>
261+ </tr>
262+
263+ <tr>
264+ <td> enumspeed </td>
265+ <td> Gets the device enumeration Speed.</td>
266+ <td> Read</td>
267+ </tr>
268+
269+ <tr>
270+ <td> hptxfsiz </td>
271+ <td> Gets the value of the Host Periodic Transmit FIFO</td>
272+ <td> Read</td>
273+ </tr>
274+
275+ <tr>
276+ <td> hprt0 </td>
277+ <td> Gets or sets the value in the Host Port Control and Status Register</td>
278+ <td> Read/Write</td>
279+ </tr>
280+
281+ <tr>
282+ <td> regoffset </td>
283+ <td> Sets the register offset for the next Register Access</td>
284+ <td> Read/Write</td>
285+ </tr>
286+
287+ <tr>
288+ <td> regvalue </td>
289+ <td> Gets or sets the value of the register at the offset in the regoffset attribute.</td>
290+ <td> Read/Write</td>
291+ </tr>
292+
293+ <tr>
294+ <td> remote_wakeup </td>
295+ <td> On read, shows the status of Remote Wakeup. On write, initiates a remote
296+ wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote
297+ Wakeup signalling bit in the Device Control Register is set for 1
298+ milli-second.</td>
299+ <td> Read/Write</td>
300+ </tr>
301+
302+ <tr>
303+ <td> regdump </td>
304+ <td> Dumps the contents of core registers.</td>
305+ <td> Read</td>
306+ </tr>
307+
308+ <tr>
309+ <td> spramdump </td>
310+ <td> Dumps the contents of core registers.</td>
311+ <td> Read</td>
312+ </tr>
313+
314+ <tr>
315+ <td> hcddump </td>
316+ <td> Dumps the current HCD state.</td>
317+ <td> Read</td>
318+ </tr>
319+
320+ <tr>
321+ <td> hcd_frrem </td>
322+ <td> Shows the average value of the Frame Remaining
323+ field in the Host Frame Number/Frame Remaining register when an SOF interrupt
324+ occurs. This can be used to determine the average interrupt latency. Also
325+ shows the average Frame Remaining value for start_transfer and the "a" and
326+ "b" sample points. The "a" and "b" sample points may be used during debugging
327+ bto determine how long it takes to execute a section of the HCD code.</td>
328+ <td> Read</td>
329+ </tr>
330+
331+ <tr>
332+ <td> rd_reg_test </td>
333+ <td> Displays the time required to read the GNPTXFSIZ register many times
334+ (the output shows the number of times the register is read).
335+ <td> Read</td>
336+ </tr>
337+
338+ <tr>
339+ <td> wr_reg_test </td>
340+ <td> Displays the time required to write the GNPTXFSIZ register many times
341+ (the output shows the number of times the register is written).
342+ <td> Read</td>
343+ </tr>
344+
345+ </table>
346+
347+ Example usage:
348+ To get the current mode:
349+ cat /sys/devices/lm0/mode
350+
351+ To power down the USB:
352+ echo 0 > /sys/devices/lm0/buspower
353+ */
354+
355+#include <linux/kernel.h>
356+#include <linux/module.h>
357+#include <linux/moduleparam.h>
358+#include <linux/init.h>
359+#include <linux/device.h>
360+#include <linux/platform_device.h>
361+#include <linux/errno.h>
362+#include <linux/types.h>
363+#include <linux/stat.h> /* permission constants */
364+#include <linux/version.h>
365+
366+#include <asm/sizes.h>
367+#include <asm/io.h>
368+#include <asm/sizes.h>
369+
370+#include "otg_plat.h"
371+#include "otg_attr.h"
372+#include "otg_driver.h"
373+#include "otg_pcd.h"
374+#include "otg_hcd.h"
375+
376+/*
377+ * MACROs for defining sysfs attribute
378+ */
379+#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
380+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
381+{ \
382+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
383+ dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
384+ uint32_t val; \
385+ val = dwc_read_reg32 (_addr_); \
386+ val = (val & (_mask_)) >> _shift_; \
387+ return sprintf (buf, "%s = 0x%x\n", _string_, val); \
388+}
389+#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
390+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
391+ const char *buf, size_t count) \
392+{ \
393+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
394+ dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
395+ uint32_t set = simple_strtoul(buf, NULL, 16); \
396+ uint32_t clear = set; \
397+ clear = ((~clear) << _shift_) & _mask_; \
398+ set = (set << _shift_) & _mask_; \
399+ dev_dbg(_dev, "Storing Address=0x%08x Set=0x%08x Clear=0x%08x\n", (uint32_t)_addr_, set, clear); \
400+ dwc_modify_reg32(_addr_, clear, set); \
401+ return count; \
402+}
403+
404+/*
405+ * MACROs for defining sysfs attribute for 32-bit registers
406+ */
407+#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
408+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
409+{ \
410+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
411+ dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
412+ uint32_t val; \
413+ val = dwc_read_reg32 (_addr_); \
414+ return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
415+}
416+#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
417+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
418+ const char *buf, size_t count) \
419+{ \
420+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
421+ dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
422+ uint32_t val = simple_strtoul(buf, NULL, 16); \
423+ dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \
424+ dwc_write_reg32(_addr_, val); \
425+ return count; \
426+}
427+
428+#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
429+DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
430+DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
431+DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
432+
433+#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
434+DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
435+DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
436+
437+#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \
438+DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
439+DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
440+DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
441+
442+#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \
443+DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
444+DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
445+
446+
447+/** @name Functions for Show/Store of Attributes */
448+/**@{*/
449+
450+/**
451+ * Show the register offset of the Register Access.
452+ */
453+static ssize_t regoffset_show( struct device *_dev,
454+ struct device_attribute *attr,
455+ char *buf)
456+{
457+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
458+ dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
459+ return snprintf(buf, sizeof("0xFFFFFFFF\n")+1,"0x%08x\n", otg_dev->reg_offset);
460+}
461+
462+/**
463+ * Set the register offset for the next Register Access Read/Write
464+ */
465+static ssize_t regoffset_store( struct device *_dev,
466+ struct device_attribute *attr,
467+ const char *buf,
468+ size_t count )
469+{
470+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
471+ dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
472+ uint32_t offset = simple_strtoul(buf, NULL, 16);
473+ //dev_dbg(_dev, "Offset=0x%08x\n", offset);
474+ if (offset < SZ_256K ) {
475+ otg_dev->reg_offset = offset;
476+ }
477+ else {
478+ dev_err( _dev, "invalid offset\n" );
479+ }
480+
481+ return count;
482+}
483+DEVICE_ATTR(regoffset, S_IRUGO|S_IWUSR, (void *)regoffset_show, regoffset_store);
484+
485+
486+/**
487+ * Show the value of the register at the offset in the reg_offset
488+ * attribute.
489+ */
490+static ssize_t regvalue_show( struct device *_dev,
491+ struct device_attribute *attr,
492+ char *buf)
493+{
494+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
495+ dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
496+ uint32_t val;
497+ volatile uint32_t *addr;
498+
499+ if (otg_dev->reg_offset != 0xFFFFFFFF &&
500+ 0 != otg_dev->base) {
501+ /* Calculate the address */
502+ addr = (uint32_t*)(otg_dev->reg_offset +
503+ (uint8_t*)otg_dev->base);
504+ //dev_dbg(_dev, "@0x%08x\n", (unsigned)addr);
505+ val = dwc_read_reg32( addr );
506+ return snprintf(buf, sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n")+1,
507+ "Reg@0x%06x = 0x%08x\n",
508+ otg_dev->reg_offset, val);
509+ }
510+ else {
511+ dev_err(_dev, "Invalid offset (0x%0x)\n",
512+ otg_dev->reg_offset);
513+ return sprintf(buf, "invalid offset\n" );
514+ }
515+}
516+
517+/**
518+ * Store the value in the register at the offset in the reg_offset
519+ * attribute.
520+ *
521+ */
522+static ssize_t regvalue_store( struct device *_dev,
523+ struct device_attribute *attr,
524+ const char *buf,
525+ size_t count )
526+{
527+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
528+ dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
529+ volatile uint32_t * addr;
530+ uint32_t val = simple_strtoul(buf, NULL, 16);
531+ //dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val);
532+ if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) {
533+ /* Calculate the address */
534+ addr = (uint32_t*)(otg_dev->reg_offset +
535+ (uint8_t*)otg_dev->base);
536+ //dev_dbg(_dev, "@0x%08x\n", (unsigned)addr);
537+ dwc_write_reg32( addr, val );
538+ }
539+ else {
540+ dev_err(_dev, "Invalid Register Offset (0x%08x)\n",
541+ otg_dev->reg_offset);
542+ }
543+ return count;
544+}
545+DEVICE_ATTR(regvalue, S_IRUGO|S_IWUSR, regvalue_show, regvalue_store);
546+
547+/*
548+ * Attributes
549+ */
550+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<20),20,"Mode");
551+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<9),9,"Mode");
552+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<8),8,"Mode");
553+
554+//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
555+//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
556+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected,otg_dev->core_if->host_if->hprt0,0x01,0,"Bus Connected");
557+
558+DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl,&(otg_dev->core_if->core_global_regs->gotgctl),"GOTGCTL");
559+DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,&(otg_dev->core_if->core_global_regs->gusbcfg),"GUSBCFG");
560+DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,&(otg_dev->core_if->core_global_regs->grxfsiz),"GRXFSIZ");
561+DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,&(otg_dev->core_if->core_global_regs->gnptxfsiz),"GNPTXFSIZ");
562+DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,&(otg_dev->core_if->core_global_regs->gpvndctl),"GPVNDCTL");
563+DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,&(otg_dev->core_if->core_global_regs->ggpio),"GGPIO");
564+DWC_OTG_DEVICE_ATTR_REG32_RW(guid,&(otg_dev->core_if->core_global_regs->guid),"GUID");
565+DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,&(otg_dev->core_if->core_global_regs->gsnpsid),"GSNPSID");
566+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dcfg),0x3,0,"Device Speed");
567+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dsts),0x6,1,"Device Enumeration Speed");
568+
569+DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,&(otg_dev->core_if->core_global_regs->hptxfsiz),"HPTXFSIZ");
570+DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0,otg_dev->core_if->host_if->hprt0,"HPRT0");
571+
572+
573+/**
574+ * @todo Add code to initiate the HNP.
575+ */
576+/**
577+ * Show the HNP status bit
578+ */
579+static ssize_t hnp_show( struct device *_dev,
580+ struct device_attribute *attr,
581+ char *buf)
582+{
583+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
584+ dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
585+ gotgctl_data_t val;
586+ val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl));
587+ return sprintf (buf, "HstNegScs = 0x%x\n", val.b.hstnegscs);
588+}
589+
590+/**
591+ * Set the HNP Request bit
592+ */
593+static ssize_t hnp_store( struct device *_dev,
594+ struct device_attribute *attr,
595+ const char *buf,
596+ size_t count )
597+{
598+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
599+ dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
600+ uint32_t in = simple_strtoul(buf, NULL, 16);
601+ uint32_t *addr = (uint32_t *)&(otg_dev->core_if->core_global_regs->gotgctl);
602+ gotgctl_data_t mem;
603+ mem.d32 = dwc_read_reg32(addr);
604+ mem.b.hnpreq = in;
605+ dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
606+ dwc_write_reg32(addr, mem.d32);
607+ return count;
608+}
609+DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store);
610+
611+/**
612+ * @todo Add code to initiate the SRP.
613+ */
614+/**
615+ * Show the SRP status bit
616+ */
617+static ssize_t srp_show( struct device *_dev,
618+ struct device_attribute *attr,
619+ char *buf)
620+{
621+#ifndef DWC_HOST_ONLY
622+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
623+ dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
624+ gotgctl_data_t val;
625+ val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl));
626+ return sprintf (buf, "SesReqScs = 0x%x\n", val.b.sesreqscs);
627+#else
628+ return sprintf(buf, "Host Only Mode!\n");
629+#endif
630+}
631+
632+
633+
634+/**
635+ * Set the SRP Request bit
636+ */
637+static ssize_t srp_store( struct device *_dev,
638+ struct device_attribute *attr,
639+ const char *buf,
640+ size_t count )
641+{
642+#ifndef DWC_HOST_ONLY
643+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
644+ dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
645+ dwc_otg_pcd_initiate_srp(otg_dev->pcd);
646+#endif
647+ return count;
648+}
649+DEVICE_ATTR(srp, 0644, srp_show, srp_store);
650+
651+/**
652+ * @todo Need to do more for power on/off?
653+ */
654+/**
655+ * Show the Bus Power status
656+ */
657+static ssize_t buspower_show( struct device *_dev,
658+ struct device_attribute *attr,
659+ char *buf)
660+{
661+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
662+ dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
663+ hprt0_data_t val;
664+ val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0);
665+ return sprintf (buf, "Bus Power = 0x%x\n", val.b.prtpwr);
666+}
667+
668+
669+/**
670+ * Set the Bus Power status
671+ */
672+static ssize_t buspower_store( struct device *_dev,
673+ struct device_attribute *attr,
674+ const char *buf,
675+ size_t count )
676+{
677+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
678+ dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
679+ uint32_t on = simple_strtoul(buf, NULL, 16);
680+ uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0;
681+ hprt0_data_t mem;
682+
683+ mem.d32 = dwc_read_reg32(addr);
684+ mem.b.prtpwr = on;
685+
686+ //dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
687+ dwc_write_reg32(addr, mem.d32);
688+
689+ return count;
690+}
691+DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store);
692+
693+/**
694+ * @todo Need to do more for suspend?
695+ */
696+/**
697+ * Show the Bus Suspend status
698+ */
699+static ssize_t bussuspend_show( struct device *_dev,
700+ struct device_attribute *attr,
701+ char *buf)
702+{
703+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
704+ dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
705+ hprt0_data_t val;
706+ val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0);
707+ return sprintf (buf, "Bus Suspend = 0x%x\n", val.b.prtsusp);
708+}
709+
710+/**
711+ * Set the Bus Suspend status
712+ */
713+static ssize_t bussuspend_store( struct device *_dev,
714+ struct device_attribute *attr,
715+ const char *buf,
716+ size_t count )
717+{
718+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
719+ dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
720+ uint32_t in = simple_strtoul(buf, NULL, 16);
721+ uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0;
722+ hprt0_data_t mem;
723+ mem.d32 = dwc_read_reg32(addr);
724+ mem.b.prtsusp = in;
725+ dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
726+ dwc_write_reg32(addr, mem.d32);
727+ return count;
728+}
729+DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store);
730+
731+/**
732+ * Show the status of Remote Wakeup.
733+ */
734+static ssize_t remote_wakeup_show( struct device *_dev,
735+ struct device_attribute *attr,
736+ char *buf)
737+{
738+#ifndef DWC_HOST_ONLY
739+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
740+ dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
741+ dctl_data_t val;
742+ val.d32 =
743+ dwc_read_reg32( &otg_dev->core_if->dev_if->dev_global_regs->dctl);
744+ return sprintf( buf, "Remote Wakeup = %d Enabled = %d\n",
745+ val.b.rmtwkupsig, otg_dev->pcd->remote_wakeup_enable);
746+#else
747+ return sprintf(buf, "Host Only Mode!\n");
748+#endif
749+}
750+/**
751+ * Initiate a remote wakeup of the host. The Device control register
752+ * Remote Wakeup Signal bit is written if the PCD Remote wakeup enable
753+ * flag is set.
754+ *
755+ */
756+static ssize_t remote_wakeup_store( struct device *_dev,
757+ struct device_attribute *attr,
758+ const char *buf,
759+ size_t count )
760+{
761+#ifndef DWC_HOST_ONLY
762+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
763+ dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
764+ uint32_t val = simple_strtoul(buf, NULL, 16);
765+ if (val&1) {
766+ dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1);
767+ }
768+ else {
769+ dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0);
770+ }
771+#endif
772+ return count;
773+}
774+DEVICE_ATTR(remote_wakeup, S_IRUGO|S_IWUSR, remote_wakeup_show,
775+ remote_wakeup_store);
776+
777+/**
778+ * Dump global registers and either host or device registers (depending on the
779+ * current mode of the core).
780+ */
781+static ssize_t regdump_show( struct device *_dev,
782+ struct device_attribute *attr,
783+ char *buf)
784+{
785+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
786+ dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
787+ dwc_otg_dump_global_registers( otg_dev->core_if);
788+ if (dwc_otg_is_host_mode(otg_dev->core_if)) {
789+ dwc_otg_dump_host_registers( otg_dev->core_if);
790+ } else {
791+ dwc_otg_dump_dev_registers( otg_dev->core_if);
792+
793+ }
794+ return sprintf( buf, "Register Dump\n" );
795+}
796+
797+DEVICE_ATTR(regdump, S_IRUGO|S_IWUSR, regdump_show, 0);
798+
799+/**
800+ * Dump global registers and either host or device registers (depending on the
801+ * current mode of the core).
802+ */
803+static ssize_t spramdump_show( struct device *_dev,
804+ struct device_attribute *attr,
805+ char *buf)
806+{
807+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
808+ dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
809+ dwc_otg_dump_spram( otg_dev->core_if);
810+
811+ return sprintf( buf, "SPRAM Dump\n" );
812+}
813+
814+DEVICE_ATTR(spramdump, S_IRUGO|S_IWUSR, spramdump_show, 0);
815+
816+/**
817+ * Dump the current hcd state.
818+ */
819+static ssize_t hcddump_show( struct device *_dev,
820+ struct device_attribute *attr,
821+ char *buf)
822+{
823+#ifndef DWC_DEVICE_ONLY
824+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
825+ dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
826+ dwc_otg_hcd_dump_state(otg_dev->hcd);
827+#endif
828+ return sprintf( buf, "HCD Dump\n" );
829+}
830+
831+DEVICE_ATTR(hcddump, S_IRUGO|S_IWUSR, hcddump_show, 0);
832+
833+/**
834+ * Dump the average frame remaining at SOF. This can be used to
835+ * determine average interrupt latency. Frame remaining is also shown for
836+ * start transfer and two additional sample points.
837+ */
838+static ssize_t hcd_frrem_show( struct device *_dev,
839+ struct device_attribute *attr,
840+ char *buf)
841+{
842+#ifndef DWC_DEVICE_ONLY
843+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
844+ dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
845+ dwc_otg_hcd_dump_frrem(otg_dev->hcd);
846+#endif
847+ return sprintf( buf, "HCD Dump Frame Remaining\n" );
848+}
849+
850+DEVICE_ATTR(hcd_frrem, S_IRUGO|S_IWUSR, hcd_frrem_show, 0);
851+
852+/**
853+ * Displays the time required to read the GNPTXFSIZ register many times (the
854+ * output shows the number of times the register is read).
855+ */
856+#define RW_REG_COUNT 10000000
857+#define MSEC_PER_JIFFIE 1000/HZ
858+static ssize_t rd_reg_test_show( struct device *_dev,
859+ struct device_attribute *attr,
860+ char *buf)
861+{
862+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
863+ dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
864+ int i;
865+ int time;
866+ int start_jiffies;
867+
868+ printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
869+ HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
870+ start_jiffies = jiffies;
871+ for (i = 0; i < RW_REG_COUNT; i++) {
872+ dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz);
873+ }
874+ time = jiffies - start_jiffies;
875+ return sprintf( buf, "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
876+ RW_REG_COUNT, time * MSEC_PER_JIFFIE, time );
877+}
878+
879+DEVICE_ATTR(rd_reg_test, S_IRUGO|S_IWUSR, rd_reg_test_show, 0);
880+
881+/**
882+ * Displays the time required to write the GNPTXFSIZ register many times (the
883+ * output shows the number of times the register is written).
884+ */
885+static ssize_t wr_reg_test_show( struct device *_dev,
886+ struct device_attribute *attr,
887+ char *buf)
888+{
889+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev); \
890+ dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev); \
891+ uint32_t reg_val;
892+ int i;
893+ int time;
894+ int start_jiffies;
895+
896+ printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
897+ HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
898+ reg_val = dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz);
899+ start_jiffies = jiffies;
900+ for (i = 0; i < RW_REG_COUNT; i++) {
901+ dwc_write_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz, reg_val);
902+ }
903+ time = jiffies - start_jiffies;
904+ return sprintf( buf, "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
905+ RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
906+}
907+
908+DEVICE_ATTR(wr_reg_test, S_IRUGO|S_IWUSR, wr_reg_test_show, 0);
909+/**@}*/
910+
911+/**
912+ * Create the device files
913+ */
914+void dwc_otg_attr_create (struct platform_device *pdev)
915+{
916+ struct device *dev = &pdev->dev;
917+ int error;
918+
919+ error = device_create_file(dev, &dev_attr_regoffset);
920+ error = device_create_file(dev, &dev_attr_regvalue);
921+ error = device_create_file(dev, &dev_attr_mode);
922+ error = device_create_file(dev, &dev_attr_hnpcapable);
923+ error = device_create_file(dev, &dev_attr_srpcapable);
924+ error = device_create_file(dev, &dev_attr_hnp);
925+ error = device_create_file(dev, &dev_attr_srp);
926+ error = device_create_file(dev, &dev_attr_buspower);
927+ error = device_create_file(dev, &dev_attr_bussuspend);
928+ error = device_create_file(dev, &dev_attr_busconnected);
929+ error = device_create_file(dev, &dev_attr_gotgctl);
930+ error = device_create_file(dev, &dev_attr_gusbcfg);
931+ error = device_create_file(dev, &dev_attr_grxfsiz);
932+ error = device_create_file(dev, &dev_attr_gnptxfsiz);
933+ error = device_create_file(dev, &dev_attr_gpvndctl);
934+ error = device_create_file(dev, &dev_attr_ggpio);
935+ error = device_create_file(dev, &dev_attr_guid);
936+ error = device_create_file(dev, &dev_attr_gsnpsid);
937+ error = device_create_file(dev, &dev_attr_devspeed);
938+ error = device_create_file(dev, &dev_attr_enumspeed);
939+ error = device_create_file(dev, &dev_attr_hptxfsiz);
940+ error = device_create_file(dev, &dev_attr_hprt0);
941+ error = device_create_file(dev, &dev_attr_remote_wakeup);
942+ error = device_create_file(dev, &dev_attr_regdump);
943+ error = device_create_file(dev, &dev_attr_spramdump);
944+ error = device_create_file(dev, &dev_attr_hcddump);
945+ error = device_create_file(dev, &dev_attr_hcd_frrem);
946+ error = device_create_file(dev, &dev_attr_rd_reg_test);
947+ error = device_create_file(dev, &dev_attr_wr_reg_test);
948+}
949+
950+/**
951+ * Remove the device files
952+ */
953+void dwc_otg_attr_remove (struct platform_device *pdev)
954+{
955+ struct device *dev = &pdev->dev;
956+
957+ device_remove_file(dev, &dev_attr_regoffset);
958+ device_remove_file(dev, &dev_attr_regvalue);
959+ device_remove_file(dev, &dev_attr_mode);
960+ device_remove_file(dev, &dev_attr_hnpcapable);
961+ device_remove_file(dev, &dev_attr_srpcapable);
962+ device_remove_file(dev, &dev_attr_hnp);
963+ device_remove_file(dev, &dev_attr_srp);
964+ device_remove_file(dev, &dev_attr_buspower);
965+ device_remove_file(dev, &dev_attr_bussuspend);
966+ device_remove_file(dev, &dev_attr_busconnected);
967+ device_remove_file(dev, &dev_attr_gotgctl);
968+ device_remove_file(dev, &dev_attr_gusbcfg);
969+ device_remove_file(dev, &dev_attr_grxfsiz);
970+ device_remove_file(dev, &dev_attr_gnptxfsiz);
971+ device_remove_file(dev, &dev_attr_gpvndctl);
972+ device_remove_file(dev, &dev_attr_ggpio);
973+ device_remove_file(dev, &dev_attr_guid);
974+ device_remove_file(dev, &dev_attr_gsnpsid);
975+ device_remove_file(dev, &dev_attr_devspeed);
976+ device_remove_file(dev, &dev_attr_enumspeed);
977+ device_remove_file(dev, &dev_attr_hptxfsiz);
978+ device_remove_file(dev, &dev_attr_hprt0);
979+ device_remove_file(dev, &dev_attr_remote_wakeup);
980+ device_remove_file(dev, &dev_attr_regdump);
981+ device_remove_file(dev, &dev_attr_spramdump);
982+ device_remove_file(dev, &dev_attr_hcddump);
983+ device_remove_file(dev, &dev_attr_hcd_frrem);
984+ device_remove_file(dev, &dev_attr_rd_reg_test);
985+ device_remove_file(dev, &dev_attr_wr_reg_test);
986+}
987--- /dev/null
988+++ b/drivers/usb/dwc/otg_attr.h
989@@ -0,0 +1,67 @@
990+/* ==========================================================================
991+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $
992+ * $Revision: #7 $
993+ * $Date: 2005/03/28 $
994+ * $Change: 477051 $
995+ *
996+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
997+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
998+ * otherwise expressly agreed to in writing between Synopsys and you.
999+ *
1000+ * The Software IS NOT an item of Licensed Software or Licensed Product under
1001+ * any End User Software License Agreement or Agreement for Licensed Product
1002+ * with Synopsys or any supplement thereto. You are permitted to use and
1003+ * redistribute this Software in source and binary forms, with or without
1004+ * modification, provided that redistributions of source code must retain this
1005+ * notice. You may not view, use, disclose, copy or distribute this file or
1006+ * any information contained herein except pursuant to this license grant from
1007+ * Synopsys. If you do not agree with this notice, including the disclaimer
1008+ * below, then you are not authorized to use the Software.
1009+ *
1010+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
1011+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1012+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1013+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
1014+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
1015+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
1016+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
1017+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
1018+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
1019+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
1020+ * DAMAGE.
1021+ * ========================================================================== */
1022+
1023+#if !defined(__DWC_OTG_ATTR_H__)
1024+#define __DWC_OTG_ATTR_H__
1025+
1026+/** @file
1027+ * This file contains the interface to the Linux device attributes.
1028+ */
1029+extern struct device_attribute dev_attr_regoffset;
1030+extern struct device_attribute dev_attr_regvalue;
1031+
1032+extern struct device_attribute dev_attr_mode;
1033+extern struct device_attribute dev_attr_hnpcapable;
1034+extern struct device_attribute dev_attr_srpcapable;
1035+extern struct device_attribute dev_attr_hnp;
1036+extern struct device_attribute dev_attr_srp;
1037+extern struct device_attribute dev_attr_buspower;
1038+extern struct device_attribute dev_attr_bussuspend;
1039+extern struct device_attribute dev_attr_busconnected;
1040+extern struct device_attribute dev_attr_gotgctl;
1041+extern struct device_attribute dev_attr_gusbcfg;
1042+extern struct device_attribute dev_attr_grxfsiz;
1043+extern struct device_attribute dev_attr_gnptxfsiz;
1044+extern struct device_attribute dev_attr_gpvndctl;
1045+extern struct device_attribute dev_attr_ggpio;
1046+extern struct device_attribute dev_attr_guid;
1047+extern struct device_attribute dev_attr_gsnpsid;
1048+extern struct device_attribute dev_attr_devspeed;
1049+extern struct device_attribute dev_attr_enumspeed;
1050+extern struct device_attribute dev_attr_hptxfsiz;
1051+extern struct device_attribute dev_attr_hprt0;
1052+
1053+void dwc_otg_attr_create (struct platform_device *pdev);
1054+void dwc_otg_attr_remove (struct platform_device *pdev);
1055+
1056+#endif
1057--- /dev/null
1058+++ b/drivers/usb/dwc/otg_cil.c
1059@@ -0,0 +1,3831 @@
1060+/* ==========================================================================
1061+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $
1062+ * $Revision: #147 $
1063+ * $Date: 2008/10/16 $
1064+ * $Change: 1117667 $
1065+ *
1066+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
1067+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
1068+ * otherwise expressly agreed to in writing between Synopsys and you.
1069+ *
1070+ * The Software IS NOT an item of Licensed Software or Licensed Product under
1071+ * any End User Software License Agreement or Agreement for Licensed Product
1072+ * with Synopsys or any supplement thereto. You are permitted to use and
1073+ * redistribute this Software in source and binary forms, with or without
1074+ * modification, provided that redistributions of source code must retain this
1075+ * notice. You may not view, use, disclose, copy or distribute this file or
1076+ * any information contained herein except pursuant to this license grant from
1077+ * Synopsys. If you do not agree with this notice, including the disclaimer
1078+ * below, then you are not authorized to use the Software.
1079+ *
1080+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
1081+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1082+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1083+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
1084+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
1085+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
1086+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
1087+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
1088+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
1089+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
1090+ * DAMAGE.
1091+ * ========================================================================== */
1092+
1093+/** @file
1094+ *
1095+ * The Core Interface Layer provides basic services for accessing and
1096+ * managing the DWC_otg hardware. These services are used by both the
1097+ * Host Controller Driver and the Peripheral Controller Driver.
1098+ *
1099+ * The CIL manages the memory map for the core so that the HCD and PCD
1100+ * don't have to do this separately. It also handles basic tasks like
1101+ * reading/writing the registers and data FIFOs in the controller.
1102+ * Some of the data access functions provide encapsulation of several
1103+ * operations required to perform a task, such as writing multiple
1104+ * registers to start a transfer. Finally, the CIL performs basic
1105+ * services that are not specific to either the host or device modes
1106+ * of operation. These services include management of the OTG Host
1107+ * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A
1108+ * Diagnostic API is also provided to allow testing of the controller
1109+ * hardware.
1110+ *
1111+ * The Core Interface Layer has the following requirements:
1112+ * - Provides basic controller operations.
1113+ * - Minimal use of OS services.
1114+ * - The OS services used will be abstracted by using inline functions
1115+ * or macros.
1116+ *
1117+ */
1118+#include <asm/unaligned.h>
1119+#include <linux/dma-mapping.h>
1120+#ifdef DEBUG
1121+#include <linux/jiffies.h>
1122+#endif
1123+
1124+#include "otg_plat.h"
1125+#include "otg_regs.h"
1126+#include "otg_cil.h"
1127+#include "otg_pcd.h"
1128+
1129+
1130+/**
1131+ * This function is called to initialize the DWC_otg CSR data
1132+ * structures. The register addresses in the device and host
1133+ * structures are initialized from the base address supplied by the
1134+ * caller. The calling function must make the OS calls to get the
1135+ * base address of the DWC_otg controller registers. The core_params
1136+ * argument holds the parameters that specify how the core should be
1137+ * configured.
1138+ *
1139+ * @param[in] reg_base_addr Base address of DWC_otg core registers
1140+ * @param[in] core_params Pointer to the core configuration parameters
1141+ *
1142+ */
1143+dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *reg_base_addr,
1144+ dwc_otg_core_params_t *core_params)
1145+{
1146+ dwc_otg_core_if_t *core_if = 0;
1147+ dwc_otg_dev_if_t *dev_if = 0;
1148+ dwc_otg_host_if_t *host_if = 0;
1149+ uint8_t *reg_base = (uint8_t *)reg_base_addr;
1150+ int i = 0;
1151+
1152+ DWC_DEBUGPL(DBG_CILV, "%s(%p,%p)\n", __func__, reg_base_addr, core_params);
1153+
1154+ core_if = kmalloc(sizeof(dwc_otg_core_if_t), GFP_KERNEL);
1155+
1156+ if (core_if == 0) {
1157+ DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_core_if_t failed\n");
1158+ return 0;
1159+ }
1160+
1161+ memset(core_if, 0, sizeof(dwc_otg_core_if_t));
1162+
1163+ core_if->core_params = core_params;
1164+ core_if->core_global_regs = (dwc_otg_core_global_regs_t *)reg_base;
1165+
1166+ /*
1167+ * Allocate the Device Mode structures.
1168+ */
1169+ dev_if = kmalloc(sizeof(dwc_otg_dev_if_t), GFP_KERNEL);
1170+
1171+ if (dev_if == 0) {
1172+ DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n");
1173+ kfree(core_if);
1174+ return 0;
1175+ }
1176+
1177+ dev_if->dev_global_regs =
1178+ (dwc_otg_device_global_regs_t *)(reg_base + DWC_DEV_GLOBAL_REG_OFFSET);
1179+
1180+ for (i=0; i<MAX_EPS_CHANNELS; i++)
1181+ {
1182+ dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *)
1183+ (reg_base + DWC_DEV_IN_EP_REG_OFFSET +
1184+ (i * DWC_EP_REG_OFFSET));
1185+
1186+ dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *)
1187+ (reg_base + DWC_DEV_OUT_EP_REG_OFFSET +
1188+ (i * DWC_EP_REG_OFFSET));
1189+ DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n",
1190+ i, &dev_if->in_ep_regs[i]->diepctl);
1191+ DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n",
1192+ i, &dev_if->out_ep_regs[i]->doepctl);
1193+ }
1194+
1195+ dev_if->speed = 0; // unknown
1196+
1197+ core_if->dev_if = dev_if;
1198+
1199+ /*
1200+ * Allocate the Host Mode structures.
1201+ */
1202+ host_if = kmalloc(sizeof(dwc_otg_host_if_t), GFP_KERNEL);
1203+
1204+ if (host_if == 0) {
1205+ DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_host_if_t failed\n");
1206+ kfree(dev_if);
1207+ kfree(core_if);
1208+ return 0;
1209+ }
1210+
1211+ host_if->host_global_regs = (dwc_otg_host_global_regs_t *)
1212+ (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET);
1213+
1214+ host_if->hprt0 = (uint32_t*)(reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET);
1215+
1216+ for (i=0; i<MAX_EPS_CHANNELS; i++)
1217+ {
1218+ host_if->hc_regs[i] = (dwc_otg_hc_regs_t *)
1219+ (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET +
1220+ (i * DWC_OTG_CHAN_REGS_OFFSET));
1221+ DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n",
1222+ i, &host_if->hc_regs[i]->hcchar);
1223+ }
1224+
1225+ host_if->num_host_channels = MAX_EPS_CHANNELS;
1226+ core_if->host_if = host_if;
1227+
1228+ for (i=0; i<MAX_EPS_CHANNELS; i++)
1229+ {
1230+ core_if->data_fifo[i] =
1231+ (uint32_t *)(reg_base + DWC_OTG_DATA_FIFO_OFFSET +
1232+ (i * DWC_OTG_DATA_FIFO_SIZE));
1233+ DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08x\n",
1234+ i, (unsigned)core_if->data_fifo[i]);
1235+ }
1236+
1237+ core_if->pcgcctl = (uint32_t*)(reg_base + DWC_OTG_PCGCCTL_OFFSET);
1238+
1239+ /*
1240+ * Store the contents of the hardware configuration registers here for
1241+ * easy access later.
1242+ */
1243+ core_if->hwcfg1.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg1);
1244+ core_if->hwcfg2.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg2);
1245+ core_if->hwcfg3.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg3);
1246+ core_if->hwcfg4.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg4);
1247+
1248+ DWC_DEBUGPL(DBG_CILV,"hwcfg1=%08x\n",core_if->hwcfg1.d32);
1249+ DWC_DEBUGPL(DBG_CILV,"hwcfg2=%08x\n",core_if->hwcfg2.d32);
1250+ DWC_DEBUGPL(DBG_CILV,"hwcfg3=%08x\n",core_if->hwcfg3.d32);
1251+ DWC_DEBUGPL(DBG_CILV,"hwcfg4=%08x\n",core_if->hwcfg4.d32);
1252+
1253+ core_if->hcfg.d32 = dwc_read_reg32(&core_if->host_if->host_global_regs->hcfg);
1254+ core_if->dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg);
1255+
1256+ DWC_DEBUGPL(DBG_CILV,"hcfg=%08x\n",core_if->hcfg.d32);
1257+ DWC_DEBUGPL(DBG_CILV,"dcfg=%08x\n",core_if->dcfg.d32);
1258+
1259+ DWC_DEBUGPL(DBG_CILV,"op_mode=%0x\n",core_if->hwcfg2.b.op_mode);
1260+ DWC_DEBUGPL(DBG_CILV,"arch=%0x\n",core_if->hwcfg2.b.architecture);
1261+ DWC_DEBUGPL(DBG_CILV,"num_dev_ep=%d\n",core_if->hwcfg2.b.num_dev_ep);
1262+ DWC_DEBUGPL(DBG_CILV,"num_host_chan=%d\n",core_if->hwcfg2.b.num_host_chan);
1263+ DWC_DEBUGPL(DBG_CILV,"nonperio_tx_q_depth=0x%0x\n",core_if->hwcfg2.b.nonperio_tx_q_depth);
1264+ DWC_DEBUGPL(DBG_CILV,"host_perio_tx_q_depth=0x%0x\n",core_if->hwcfg2.b.host_perio_tx_q_depth);
1265+ DWC_DEBUGPL(DBG_CILV,"dev_token_q_depth=0x%0x\n",core_if->hwcfg2.b.dev_token_q_depth);
1266+
1267+ DWC_DEBUGPL(DBG_CILV,"Total FIFO SZ=%d\n", core_if->hwcfg3.b.dfifo_depth);
1268+ DWC_DEBUGPL(DBG_CILV,"xfer_size_cntr_width=%0x\n", core_if->hwcfg3.b.xfer_size_cntr_width);
1269+
1270+ /*
1271+ * Set the SRP sucess bit for FS-I2c
1272+ */
1273+ core_if->srp_success = 0;
1274+ core_if->srp_timer_started = 0;
1275+
1276+
1277+ /*
1278+ * Create new workqueue and init works
1279+ */
1280+ core_if->wq_otg = create_singlethread_workqueue("dwc_otg");
1281+ if(core_if->wq_otg == 0) {
1282+ DWC_DEBUGPL(DBG_CIL, "Creation of wq_otg failed\n");
1283+ kfree(host_if);
1284+ kfree(dev_if);
1285+ kfree(core_if);
1286+ return 0 * HZ;
1287+ }
1288+ INIT_WORK(&core_if->w_conn_id, w_conn_id_status_change);
1289+ INIT_DELAYED_WORK(&core_if->w_wkp, w_wakeup_detected);
1290+
1291+ return core_if;
1292+}
1293+
1294+/**
1295+ * This function frees the structures allocated by dwc_otg_cil_init().
1296+ *
1297+ * @param[in] core_if The core interface pointer returned from
1298+ * dwc_otg_cil_init().
1299+ *
1300+ */
1301+void dwc_otg_cil_remove(dwc_otg_core_if_t *core_if)
1302+{
1303+ /* Disable all interrupts */
1304+ dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, 1, 0);
1305+ dwc_write_reg32(&core_if->core_global_regs->gintmsk, 0);
1306+
1307+ if (core_if->wq_otg) {
1308+ destroy_workqueue(core_if->wq_otg);
1309+ }
1310+ if (core_if->dev_if) {
1311+ kfree(core_if->dev_if);
1312+ }
1313+ if (core_if->host_if) {
1314+ kfree(core_if->host_if);
1315+ }
1316+ kfree(core_if);
1317+}
1318+
1319+/**
1320+ * This function enables the controller's Global Interrupt in the AHB Config
1321+ * register.
1322+ *
1323+ * @param[in] core_if Programming view of DWC_otg controller.
1324+ */
1325+void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t *core_if)
1326+{
1327+ gahbcfg_data_t ahbcfg = { .d32 = 0};
1328+ ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
1329+ dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32);
1330+}
1331+
1332+/**
1333+ * This function disables the controller's Global Interrupt in the AHB Config
1334+ * register.
1335+ *
1336+ * @param[in] core_if Programming view of DWC_otg controller.
1337+ */
1338+void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t *core_if)
1339+{
1340+ gahbcfg_data_t ahbcfg = { .d32 = 0};
1341+ ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
1342+ dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
1343+}
1344+
1345+/**
1346+ * This function initializes the commmon interrupts, used in both
1347+ * device and host modes.
1348+ *
1349+ * @param[in] core_if Programming view of the DWC_otg controller
1350+ *
1351+ */
1352+static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t *core_if)
1353+{
1354+ dwc_otg_core_global_regs_t *global_regs =
1355+ core_if->core_global_regs;
1356+ gintmsk_data_t intr_mask = { .d32 = 0};
1357+
1358+ /* Clear any pending OTG Interrupts */
1359+ dwc_write_reg32(&global_regs->gotgint, 0xFFFFFFFF);
1360+
1361+ /* Clear any pending interrupts */
1362+ dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF);
1363+
1364+ /*
1365+ * Enable the interrupts in the GINTMSK.
1366+ */
1367+ intr_mask.b.modemismatch = 1;
1368+ intr_mask.b.otgintr = 1;
1369+
1370+ if (!core_if->dma_enable) {
1371+ intr_mask.b.rxstsqlvl = 1;
1372+ }
1373+
1374+ intr_mask.b.conidstschng = 1;
1375+ intr_mask.b.wkupintr = 1;
1376+ intr_mask.b.disconnect = 1;
1377+ intr_mask.b.usbsuspend = 1;
1378+ intr_mask.b.sessreqintr = 1;
1379+ dwc_write_reg32(&global_regs->gintmsk, intr_mask.d32);
1380+}
1381+
1382+/**
1383+ * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY
1384+ * type.
1385+ */
1386+static void init_fslspclksel(dwc_otg_core_if_t *core_if)
1387+{
1388+ uint32_t val;
1389+ hcfg_data_t hcfg;
1390+
1391+ if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
1392+ (core_if->hwcfg2.b.fs_phy_type == 1) &&
1393+ (core_if->core_params->ulpi_fs_ls)) ||
1394+ (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
1395+ /* Full speed PHY */
1396+ val = DWC_HCFG_48_MHZ;
1397+ }
1398+ else {
1399+ /* High speed PHY running at full speed or high speed */
1400+ val = DWC_HCFG_30_60_MHZ;
1401+ }
1402+
1403+ DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val);
1404+ hcfg.d32 = dwc_read_reg32(&core_if->host_if->host_global_regs->hcfg);
1405+ hcfg.b.fslspclksel = val;
1406+ dwc_write_reg32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
1407+}
1408+
1409+/**
1410+ * Initializes the DevSpd field of the DCFG register depending on the PHY type
1411+ * and the enumeration speed of the device.
1412+ */
1413+static void init_devspd(dwc_otg_core_if_t *core_if)
1414+{
1415+ uint32_t val;
1416+ dcfg_data_t dcfg;
1417+
1418+ if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
1419+ (core_if->hwcfg2.b.fs_phy_type == 1) &&
1420+ (core_if->core_params->ulpi_fs_ls)) ||
1421+ (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
1422+ /* Full speed PHY */
1423+ val = 0x3;
1424+ }
1425+ else if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
1426+ /* High speed PHY running at full speed */
1427+ val = 0x1;
1428+ }
1429+ else {
1430+ /* High speed PHY running at high speed */
1431+ val = 0x0;
1432+ }
1433+
1434+ DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
1435+
1436+ dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg);
1437+ dcfg.b.devspd = val;
1438+ dwc_write_reg32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
1439+}
1440+
1441+/**
1442+ * This function calculates the number of IN EPS
1443+ * using GHWCFG1 and GHWCFG2 registers values
1444+ *
1445+ * @param core_if Programming view of the DWC_otg controller
1446+ */
1447+static uint32_t calc_num_in_eps(dwc_otg_core_if_t *core_if)
1448+{
1449+ uint32_t num_in_eps = 0;
1450+ uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
1451+ uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 3;
1452+ uint32_t num_tx_fifos = core_if->hwcfg4.b.num_in_eps;
1453+ int i;
1454+
1455+
1456+ for(i = 0; i < num_eps; ++i)
1457+ {
1458+ if(!(hwcfg1 & 0x1))
1459+ num_in_eps++;
1460+
1461+ hwcfg1 >>= 2;
1462+ }
1463+
1464+ if(core_if->hwcfg4.b.ded_fifo_en) {
1465+ num_in_eps = (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps;
1466+ }
1467+
1468+ return num_in_eps;
1469+}
1470+
1471+
1472+/**
1473+ * This function calculates the number of OUT EPS
1474+ * using GHWCFG1 and GHWCFG2 registers values
1475+ *
1476+ * @param core_if Programming view of the DWC_otg controller
1477+ */
1478+static uint32_t calc_num_out_eps(dwc_otg_core_if_t *core_if)
1479+{
1480+ uint32_t num_out_eps = 0;
1481+ uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
1482+ uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2;
1483+ int i;
1484+
1485+ for(i = 0; i < num_eps; ++i)
1486+ {
1487+ if(!(hwcfg1 & 0x2))
1488+ num_out_eps++;
1489+
1490+ hwcfg1 >>= 2;
1491+ }
1492+ return num_out_eps;
1493+}
1494+/**
1495+ * This function initializes the DWC_otg controller registers and
1496+ * prepares the core for device mode or host mode operation.
1497+ *
1498+ * @param core_if Programming view of the DWC_otg controller
1499+ *
1500+ */
1501+void dwc_otg_core_init(dwc_otg_core_if_t *core_if)
1502+{
1503+ int i = 0;
1504+ dwc_otg_core_global_regs_t *global_regs =
1505+ core_if->core_global_regs;
1506+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
1507+ gahbcfg_data_t ahbcfg = { .d32 = 0 };
1508+ gusbcfg_data_t usbcfg = { .d32 = 0 };
1509+ gi2cctl_data_t i2cctl = { .d32 = 0 };
1510+
1511+ DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p)\n", core_if);
1512+
1513+ /* Common Initialization */
1514+
1515+ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
1516+
1517+// usbcfg.b.tx_end_delay = 1;
1518+ /* Program the ULPI External VBUS bit if needed */
1519+ usbcfg.b.ulpi_ext_vbus_drv =
1520+ (core_if->core_params->phy_ulpi_ext_vbus == DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0;
1521+
1522+ /* Set external TS Dline pulsing */
1523+ usbcfg.b.term_sel_dl_pulse = (core_if->core_params->ts_dline == 1) ? 1 : 0;
1524+ dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32);
1525+
1526+
1527+ /* Reset the Controller */
1528+ dwc_otg_core_reset(core_if);
1529+
1530+ /* Initialize parameters from Hardware configuration registers. */
1531+ dev_if->num_in_eps = calc_num_in_eps(core_if);
1532+ dev_if->num_out_eps = calc_num_out_eps(core_if);
1533+
1534+
1535+ DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n", core_if->hwcfg4.b.num_dev_perio_in_ep);
1536+
1537+ for (i=0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
1538+ {
1539+ dev_if->perio_tx_fifo_size[i] =
1540+ dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16;
1541+ DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n",
1542+ i, dev_if->perio_tx_fifo_size[i]);
1543+ }
1544+
1545+ for (i=0; i < core_if->hwcfg4.b.num_in_eps; i++)
1546+ {
1547+ dev_if->tx_fifo_size[i] =
1548+ dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16;
1549+ DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n",
1550+ i, dev_if->perio_tx_fifo_size[i]);
1551+ }
1552+
1553+ core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth;
1554+ core_if->rx_fifo_size =
1555+ dwc_read_reg32(&global_regs->grxfsiz);
1556+ core_if->nperio_tx_fifo_size =
1557+ dwc_read_reg32(&global_regs->gnptxfsiz) >> 16;
1558+
1559+ DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size);
1560+ DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size);
1561+ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n", core_if->nperio_tx_fifo_size);
1562+
1563+ /* This programming sequence needs to happen in FS mode before any other
1564+ * programming occurs */
1565+ if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) &&
1566+ (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
1567+ /* If FS mode with FS PHY */
1568+
1569+ /* core_init() is now called on every switch so only call the
1570+ * following for the first time through. */
1571+ if (!core_if->phy_init_done) {
1572+ core_if->phy_init_done = 1;
1573+ DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n");
1574+ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
1575+ usbcfg.b.physel = 1;
1576+ dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32);
1577+
1578+ /* Reset after a PHY select */
1579+ dwc_otg_core_reset(core_if);
1580+ }
1581+
1582+ /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
1583+ * do this on HNP Dev/Host mode switches (done in dev_init and
1584+ * host_init). */
1585+ if (dwc_otg_is_host_mode(core_if)) {
1586+ init_fslspclksel(core_if);
1587+ }
1588+ else {
1589+ init_devspd(core_if);
1590+ }
1591+
1592+ if (core_if->core_params->i2c_enable) {
1593+ DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
1594+ /* Program GUSBCFG.OtgUtmifsSel to I2C */
1595+ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
1596+ usbcfg.b.otgutmifssel = 1;
1597+ dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32);
1598+
1599+ /* Program GI2CCTL.I2CEn */
1600+ i2cctl.d32 = dwc_read_reg32(&global_regs->gi2cctl);
1601+ i2cctl.b.i2cdevaddr = 1;
1602+ i2cctl.b.i2cen = 0;
1603+ dwc_write_reg32 (&global_regs->gi2cctl, i2cctl.d32);
1604+ i2cctl.b.i2cen = 1;
1605+ dwc_write_reg32 (&global_regs->gi2cctl, i2cctl.d32);
1606+ }
1607+
1608+ } /* endif speed == DWC_SPEED_PARAM_FULL */
1609+
1610+ else {
1611+ /* High speed PHY. */
1612+ if (!core_if->phy_init_done) {
1613+ core_if->phy_init_done = 1;
1614+ /* HS PHY parameters. These parameters are preserved
1615+ * during soft reset so only program the first time. Do
1616+ * a soft reset immediately after setting phyif. */
1617+ usbcfg.b.ulpi_utmi_sel = core_if->core_params->phy_type;
1618+ if (usbcfg.b.ulpi_utmi_sel == 1) {
1619+ /* ULPI interface */
1620+ usbcfg.b.phyif = 0;
1621+ usbcfg.b.ddrsel = core_if->core_params->phy_ulpi_ddr;
1622+ }
1623+ else {
1624+ /* UTMI+ interface */
1625+ if (core_if->core_params->phy_utmi_width == 16) {
1626+ usbcfg.b.phyif = 1;
1627+ }
1628+ else {
1629+ usbcfg.b.phyif = 0;
1630+ }
1631+ }
1632+
1633+ dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
1634+
1635+ /* Reset after setting the PHY parameters */
1636+ dwc_otg_core_reset(core_if);
1637+ }
1638+ }
1639+
1640+ if ((core_if->hwcfg2.b.hs_phy_type == 2) &&
1641+ (core_if->hwcfg2.b.fs_phy_type == 1) &&
1642+ (core_if->core_params->ulpi_fs_ls)) {
1643+ DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n");
1644+ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
1645+ usbcfg.b.ulpi_fsls = 1;
1646+ usbcfg.b.ulpi_clk_sus_m = 1;
1647+ dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
1648+ }
1649+ else {
1650+ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
1651+ usbcfg.b.ulpi_fsls = 0;
1652+ usbcfg.b.ulpi_clk_sus_m = 0;
1653+ dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
1654+ }
1655+
1656+ /* Program the GAHBCFG Register.*/
1657+ switch (core_if->hwcfg2.b.architecture) {
1658+
1659+ case DWC_SLAVE_ONLY_ARCH:
1660+ DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n");
1661+ ahbcfg.b.nptxfemplvl_txfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
1662+ ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
1663+ core_if->dma_enable = 0;
1664+ core_if->dma_desc_enable = 0;
1665+ break;
1666+
1667+ case DWC_EXT_DMA_ARCH:
1668+ DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n");
1669+ ahbcfg.b.hburstlen = core_if->core_params->dma_burst_size;
1670+ core_if->dma_enable = (core_if->core_params->dma_enable != 0);
1671+ core_if->dma_desc_enable = (core_if->core_params->dma_desc_enable != 0);
1672+ break;
1673+
1674+ case DWC_INT_DMA_ARCH:
1675+ DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
1676+ ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR;
1677+ core_if->dma_enable = (core_if->core_params->dma_enable != 0);
1678+ core_if->dma_desc_enable = (core_if->core_params->dma_desc_enable != 0);
1679+ break;
1680+
1681+ }
1682+ ahbcfg.b.dmaenable = core_if->dma_enable;
1683+ dwc_write_reg32(&global_regs->gahbcfg, ahbcfg.d32);
1684+
1685+ core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en;
1686+
1687+ core_if->pti_enh_enable = core_if->core_params->pti_enable != 0;
1688+ core_if->multiproc_int_enable = core_if->core_params->mpi_enable;
1689+ DWC_PRINT("Periodic Transfer Interrupt Enhancement - %s\n", ((core_if->pti_enh_enable) ? "enabled": "disabled"));
1690+ DWC_PRINT("Multiprocessor Interrupt Enhancement - %s\n", ((core_if->multiproc_int_enable) ? "enabled": "disabled"));
1691+
1692+ /*
1693+ * Program the GUSBCFG register.
1694+ */
1695+ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
1696+
1697+ switch (core_if->hwcfg2.b.op_mode) {
1698+ case DWC_MODE_HNP_SRP_CAPABLE:
1699+ usbcfg.b.hnpcap = (core_if->core_params->otg_cap ==
1700+ DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
1701+ usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1702+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1703+ break;
1704+
1705+ case DWC_MODE_SRP_ONLY_CAPABLE:
1706+ usbcfg.b.hnpcap = 0;
1707+ usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1708+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1709+ break;
1710+
1711+ case DWC_MODE_NO_HNP_SRP_CAPABLE:
1712+ usbcfg.b.hnpcap = 0;
1713+ usbcfg.b.srpcap = 0;
1714+ break;
1715+
1716+ case DWC_MODE_SRP_CAPABLE_DEVICE:
1717+ usbcfg.b.hnpcap = 0;
1718+ usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1719+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1720+ break;
1721+
1722+ case DWC_MODE_NO_SRP_CAPABLE_DEVICE:
1723+ usbcfg.b.hnpcap = 0;
1724+ usbcfg.b.srpcap = 0;
1725+ break;
1726+
1727+ case DWC_MODE_SRP_CAPABLE_HOST:
1728+ usbcfg.b.hnpcap = 0;
1729+ usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1730+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1731+ break;
1732+
1733+ case DWC_MODE_NO_SRP_CAPABLE_HOST:
1734+ usbcfg.b.hnpcap = 0;
1735+ usbcfg.b.srpcap = 0;
1736+ break;
1737+ }
1738+
1739+ dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
1740+
1741+ /* Enable common interrupts */
1742+ dwc_otg_enable_common_interrupts(core_if);
1743+
1744+ /* Do device or host intialization based on mode during PCD
1745+ * and HCD initialization */
1746+ if (dwc_otg_is_host_mode(core_if)) {
1747+ DWC_DEBUGPL(DBG_ANY, "Host Mode\n");
1748+ core_if->op_state = A_HOST;
1749+ }
1750+ else {
1751+ DWC_DEBUGPL(DBG_ANY, "Device Mode\n");
1752+ core_if->op_state = B_PERIPHERAL;
1753+#ifdef DWC_DEVICE_ONLY
1754+ dwc_otg_core_dev_init(core_if);
1755+#endif
1756+ }
1757+}
1758+
1759+
1760+/**
1761+ * This function enables the Device mode interrupts.
1762+ *
1763+ * @param core_if Programming view of DWC_otg controller
1764+ */
1765+void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *core_if)
1766+{
1767+ gintmsk_data_t intr_mask = { .d32 = 0};
1768+ dwc_otg_core_global_regs_t *global_regs =
1769+ core_if->core_global_regs;
1770+
1771+ DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
1772+
1773+ /* Disable all interrupts. */
1774+ dwc_write_reg32(&global_regs->gintmsk, 0);
1775+
1776+ /* Clear any pending interrupts */
1777+ dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF);
1778+
1779+ /* Enable the common interrupts */
1780+ dwc_otg_enable_common_interrupts(core_if);
1781+
1782+ /* Enable interrupts */
1783+ intr_mask.b.usbreset = 1;
1784+ intr_mask.b.enumdone = 1;
1785+
1786+ if(!core_if->multiproc_int_enable) {
1787+ intr_mask.b.inepintr = 1;
1788+ intr_mask.b.outepintr = 1;
1789+ }
1790+
1791+ intr_mask.b.erlysuspend = 1;
1792+
1793+ if(core_if->en_multiple_tx_fifo == 0) {
1794+ intr_mask.b.epmismatch = 1;
1795+ }
1796+
1797+
1798+#ifdef DWC_EN_ISOC
1799+ if(core_if->dma_enable) {
1800+ if(core_if->dma_desc_enable == 0) {
1801+ if(core_if->pti_enh_enable) {
1802+ dctl_data_t dctl = { .d32 = 0 };
1803+ dctl.b.ifrmnum = 1;
1804+ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
1805+ } else {
1806+ intr_mask.b.incomplisoin = 1;
1807+ intr_mask.b.incomplisoout = 1;
1808+ }
1809+ }
1810+ } else {
1811+ intr_mask.b.incomplisoin = 1;
1812+ intr_mask.b.incomplisoout = 1;
1813+ }
1814+#endif // DWC_EN_ISOC
1815+
1816+/** @todo NGS: Should this be a module parameter? */
1817+#ifdef USE_PERIODIC_EP
1818+ intr_mask.b.isooutdrop = 1;
1819+ intr_mask.b.eopframe = 1;
1820+ intr_mask.b.incomplisoin = 1;
1821+ intr_mask.b.incomplisoout = 1;
1822+#endif
1823+
1824+ dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
1825+
1826+ DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__,
1827+ dwc_read_reg32(&global_regs->gintmsk));
1828+}
1829+
1830+/**
1831+ * This function initializes the DWC_otg controller registers for
1832+ * device mode.
1833+ *
1834+ * @param core_if Programming view of DWC_otg controller
1835+ *
1836+ */
1837+void dwc_otg_core_dev_init(dwc_otg_core_if_t *core_if)
1838+{
1839+ int i,size;
1840+ u_int32_t *default_value_array;
1841+
1842+ dwc_otg_core_global_regs_t *global_regs =
1843+ core_if->core_global_regs;
1844+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
1845+ dwc_otg_core_params_t *params = core_if->core_params;
1846+ dcfg_data_t dcfg = { .d32 = 0};
1847+ grstctl_t resetctl = { .d32 = 0 };
1848+ uint32_t rx_fifo_size;
1849+ fifosize_data_t nptxfifosize;
1850+ fifosize_data_t txfifosize;
1851+ dthrctl_data_t dthrctl;
1852+
1853+ /* Restart the Phy Clock */
1854+ dwc_write_reg32(core_if->pcgcctl, 0);
1855+
1856+ /* Device configuration register */
1857+ init_devspd(core_if);
1858+ dcfg.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dcfg);
1859+ dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0;
1860+ dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80;
1861+
1862+ dwc_write_reg32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
1863+
1864+ /* Configure data FIFO sizes */
1865+ if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
1866+ DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n", core_if->total_fifo_size);
1867+ DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n", params->dev_rx_fifo_size);
1868+ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n", params->dev_nperio_tx_fifo_size);
1869+
1870+ /* Rx FIFO */
1871+ DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
1872+ dwc_read_reg32(&global_regs->grxfsiz));
1873+
1874+ rx_fifo_size = params->dev_rx_fifo_size;
1875+ dwc_write_reg32(&global_regs->grxfsiz, rx_fifo_size);
1876+
1877+ DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
1878+ dwc_read_reg32(&global_regs->grxfsiz));
1879+
1880+ /** Set Periodic Tx FIFO Mask all bits 0 */
1881+ core_if->p_tx_msk = 0;
1882+
1883+ /** Set Tx FIFO Mask all bits 0 */
1884+ core_if->tx_msk = 0;
1885+
1886+ /* Non-periodic Tx FIFO */
1887+ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
1888+ dwc_read_reg32(&global_regs->gnptxfsiz));
1889+
1890+ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
1891+ nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
1892+
1893+ dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32);
1894+
1895+ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
1896+ dwc_read_reg32(&global_regs->gnptxfsiz));
1897+
1898+ txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
1899+ if(core_if->en_multiple_tx_fifo == 0) {
1900+ //core_if->hwcfg4.b.ded_fifo_en==0
1901+
1902+ /**@todo NGS: Fix Periodic FIFO Sizing! */
1903+ /*
1904+ * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15.
1905+ * Indexes of the FIFO size module parameters in the
1906+ * dev_perio_tx_fifo_size array and the FIFO size registers in
1907+ * the dptxfsiz array run from 0 to 14.
1908+ */
1909+ /** @todo Finish debug of this */
1910+ size=core_if->hwcfg4.b.num_dev_perio_in_ep;
1911+ default_value_array=params->dev_perio_tx_fifo_size;
1912+
1913+ }
1914+ else {
1915+ //core_if->hwcfg4.b.ded_fifo_en==1
1916+ /*
1917+ * Tx FIFOs These FIFOs are numbered from 1 to 15.
1918+ * Indexes of the FIFO size module parameters in the
1919+ * dev_tx_fifo_size array and the FIFO size registers in
1920+ * the dptxfsiz_dieptxf array run from 0 to 14.
1921+ */
1922+
1923+ size=core_if->hwcfg4.b.num_in_eps;
1924+ default_value_array=params->dev_tx_fifo_size;
1925+
1926+ }
1927+ for (i=0; i < size; i++)
1928+ {
1929+
1930+ txfifosize.b.depth = default_value_array[i];
1931+ DWC_DEBUGPL(DBG_CIL, "initial dptxfsiz_dieptxf[%d]=%08x\n", i,
1932+ dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]));
1933+ dwc_write_reg32(&global_regs->dptxfsiz_dieptxf[i],
1934+ txfifosize.d32);
1935+ DWC_DEBUGPL(DBG_CIL, "new dptxfsiz_dieptxf[%d]=%08x\n", i,
1936+ dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]));
1937+ txfifosize.b.startaddr += txfifosize.b.depth;
1938+ }
1939+ }
1940+ /* Flush the FIFOs */
1941+ dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */
1942+ dwc_otg_flush_rx_fifo(core_if);
1943+
1944+ /* Flush the Learning Queue. */
1945+ resetctl.b.intknqflsh = 1;
1946+ dwc_write_reg32(&core_if->core_global_regs->grstctl, resetctl.d32);
1947+
1948+ /* Clear all pending Device Interrupts */
1949+
1950+ if(core_if->multiproc_int_enable) {
1951+ }
1952+
1953+ /** @todo - if the condition needed to be checked
1954+ * or in any case all pending interrutps should be cleared?
1955+ */
1956+ if(core_if->multiproc_int_enable) {
1957+ for(i = 0; i < core_if->dev_if->num_in_eps; ++i) {
1958+ dwc_write_reg32(&dev_if->dev_global_regs->diepeachintmsk[i], 0);
1959+ }
1960+
1961+ for(i = 0; i < core_if->dev_if->num_out_eps; ++i) {
1962+ dwc_write_reg32(&dev_if->dev_global_regs->doepeachintmsk[i], 0);
1963+ }
1964+
1965+ dwc_write_reg32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF);
1966+ dwc_write_reg32(&dev_if->dev_global_regs->deachintmsk, 0);
1967+ } else {
1968+ dwc_write_reg32(&dev_if->dev_global_regs->diepmsk, 0);
1969+ dwc_write_reg32(&dev_if->dev_global_regs->doepmsk, 0);
1970+ dwc_write_reg32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF);
1971+ dwc_write_reg32(&dev_if->dev_global_regs->daintmsk, 0);
1972+ }
1973+
1974+ for (i=0; i <= dev_if->num_in_eps; i++)
1975+ {
1976+ depctl_data_t depctl;
1977+ depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl);
1978+ if (depctl.b.epena) {
1979+ depctl.d32 = 0;
1980+ depctl.b.epdis = 1;
1981+ depctl.b.snak = 1;
1982+ }
1983+ else {
1984+ depctl.d32 = 0;
1985+ }
1986+
1987+ dwc_write_reg32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
1988+
1989+
1990+ dwc_write_reg32(&dev_if->in_ep_regs[i]->dieptsiz, 0);
1991+ dwc_write_reg32(&dev_if->in_ep_regs[i]->diepdma, 0);
1992+ dwc_write_reg32(&dev_if->in_ep_regs[i]->diepint, 0xFF);
1993+ }
1994+
1995+ for (i=0; i <= dev_if->num_out_eps; i++)
1996+ {
1997+ depctl_data_t depctl;
1998+ depctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl);
1999+ if (depctl.b.epena) {
2000+ depctl.d32 = 0;
2001+ depctl.b.epdis = 1;
2002+ depctl.b.snak = 1;
2003+ }
2004+ else {
2005+ depctl.d32 = 0;
2006+ }
2007+
2008+ dwc_write_reg32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32);
2009+
2010+ dwc_write_reg32(&dev_if->out_ep_regs[i]->doeptsiz, 0);
2011+ dwc_write_reg32(&dev_if->out_ep_regs[i]->doepdma, 0);
2012+ dwc_write_reg32(&dev_if->out_ep_regs[i]->doepint, 0xFF);
2013+ }
2014+
2015+ if(core_if->en_multiple_tx_fifo && core_if->dma_enable) {
2016+ dev_if->non_iso_tx_thr_en = params->thr_ctl & 0x1;
2017+ dev_if->iso_tx_thr_en = (params->thr_ctl >> 1) & 0x1;
2018+ dev_if->rx_thr_en = (params->thr_ctl >> 2) & 0x1;
2019+
2020+ dev_if->rx_thr_length = params->rx_thr_length;
2021+ dev_if->tx_thr_length = params->tx_thr_length;
2022+
2023+ dev_if->setup_desc_index = 0;
2024+
2025+ dthrctl.d32 = 0;
2026+ dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en;
2027+ dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en;
2028+ dthrctl.b.tx_thr_len = dev_if->tx_thr_length;
2029+ dthrctl.b.rx_thr_en = dev_if->rx_thr_en;
2030+ dthrctl.b.rx_thr_len = dev_if->rx_thr_length;
2031+
2032+ dwc_write_reg32(&dev_if->dev_global_regs->dtknqr3_dthrctl, dthrctl.d32);
2033+
2034+ DWC_DEBUGPL(DBG_CIL, "Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n",
2035+ dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en, dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len, dthrctl.b.rx_thr_len);
2036+
2037+ }
2038+
2039+ dwc_otg_enable_device_interrupts(core_if);
2040+
2041+ {
2042+ diepmsk_data_t msk = { .d32 = 0 };
2043+ msk.b.txfifoundrn = 1;
2044+ if(core_if->multiproc_int_enable) {
2045+ dwc_modify_reg32(&dev_if->dev_global_regs->diepeachintmsk[0], msk.d32, msk.d32);
2046+ } else {
2047+ dwc_modify_reg32(&dev_if->dev_global_regs->diepmsk, msk.d32, msk.d32);
2048+ }
2049+ }
2050+
2051+
2052+ if(core_if->multiproc_int_enable) {
2053+ /* Set NAK on Babble */
2054+ dctl_data_t dctl = { .d32 = 0};
2055+ dctl.b.nakonbble = 1;
2056+ dwc_modify_reg32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
2057+ }
2058+}
2059+
2060+/**
2061+ * This function enables the Host mode interrupts.
2062+ *
2063+ * @param core_if Programming view of DWC_otg controller
2064+ */
2065+void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *core_if)
2066+{
2067+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
2068+ gintmsk_data_t intr_mask = { .d32 = 0 };
2069+
2070+ DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
2071+
2072+ /* Disable all interrupts. */
2073+ dwc_write_reg32(&global_regs->gintmsk, 0);
2074+
2075+ /* Clear any pending interrupts. */
2076+ dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF);
2077+
2078+ /* Enable the common interrupts */
2079+ dwc_otg_enable_common_interrupts(core_if);
2080+
2081+ /*
2082+ * Enable host mode interrupts without disturbing common
2083+ * interrupts.
2084+ */
2085+ intr_mask.b.sofintr = 1;
2086+ intr_mask.b.portintr = 1;
2087+ intr_mask.b.hcintr = 1;
2088+
2089+ dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
2090+}
2091+
2092+/**
2093+ * This function disables the Host Mode interrupts.
2094+ *
2095+ * @param core_if Programming view of DWC_otg controller
2096+ */
2097+void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *core_if)
2098+{
2099+ dwc_otg_core_global_regs_t *global_regs =
2100+ core_if->core_global_regs;
2101+ gintmsk_data_t intr_mask = { .d32 = 0 };
2102+
2103+ DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__);
2104+
2105+ /*
2106+ * Disable host mode interrupts without disturbing common
2107+ * interrupts.
2108+ */
2109+ intr_mask.b.sofintr = 1;
2110+ intr_mask.b.portintr = 1;
2111+ intr_mask.b.hcintr = 1;
2112+ intr_mask.b.ptxfempty = 1;
2113+ intr_mask.b.nptxfempty = 1;
2114+
2115+ dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
2116+}
2117+
2118+/**
2119+ * This function initializes the DWC_otg controller registers for
2120+ * host mode.
2121+ *
2122+ * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
2123+ * request queues. Host channels are reset to ensure that they are ready for
2124+ * performing transfers.
2125+ *
2126+ * @param core_if Programming view of DWC_otg controller
2127+ *
2128+ */
2129+void dwc_otg_core_host_init(dwc_otg_core_if_t *core_if)
2130+{
2131+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
2132+ dwc_otg_host_if_t *host_if = core_if->host_if;
2133+ dwc_otg_core_params_t *params = core_if->core_params;
2134+ hprt0_data_t hprt0 = { .d32 = 0 };
2135+ fifosize_data_t nptxfifosize;
2136+ fifosize_data_t ptxfifosize;
2137+ int i;
2138+ hcchar_data_t hcchar;
2139+ hcfg_data_t hcfg;
2140+ dwc_otg_hc_regs_t *hc_regs;
2141+ int num_channels;
2142+ gotgctl_data_t gotgctl = { .d32 = 0 };
2143+
2144+ DWC_DEBUGPL(DBG_CILV,"%s(%p)\n", __func__, core_if);
2145+
2146+ /* Restart the Phy Clock */
2147+ dwc_write_reg32(core_if->pcgcctl, 0);
2148+
2149+ /* Initialize Host Configuration Register */
2150+ init_fslspclksel(core_if);
2151+ if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL)
2152+ {
2153+ hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg);
2154+ hcfg.b.fslssupp = 1;
2155+ dwc_write_reg32(&host_if->host_global_regs->hcfg, hcfg.d32);
2156+ }
2157+
2158+ /* Configure data FIFO sizes */
2159+ if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
2160+ DWC_DEBUGPL(DBG_CIL,"Total FIFO Size=%d\n", core_if->total_fifo_size);
2161+ DWC_DEBUGPL(DBG_CIL,"Rx FIFO Size=%d\n", params->host_rx_fifo_size);
2162+ DWC_DEBUGPL(DBG_CIL,"NP Tx FIFO Size=%d\n", params->host_nperio_tx_fifo_size);
2163+ DWC_DEBUGPL(DBG_CIL,"P Tx FIFO Size=%d\n", params->host_perio_tx_fifo_size);
2164+
2165+ /* Rx FIFO */
2166+ DWC_DEBUGPL(DBG_CIL,"initial grxfsiz=%08x\n", dwc_read_reg32(&global_regs->grxfsiz));
2167+ dwc_write_reg32(&global_regs->grxfsiz, params->host_rx_fifo_size);
2168+ DWC_DEBUGPL(DBG_CIL,"new grxfsiz=%08x\n", dwc_read_reg32(&global_regs->grxfsiz));
2169+
2170+ /* Non-periodic Tx FIFO */
2171+ DWC_DEBUGPL(DBG_CIL,"initial gnptxfsiz=%08x\n", dwc_read_reg32(&global_regs->gnptxfsiz));
2172+ nptxfifosize.b.depth = params->host_nperio_tx_fifo_size;
2173+ nptxfifosize.b.startaddr = params->host_rx_fifo_size;
2174+ dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32);
2175+ DWC_DEBUGPL(DBG_CIL,"new gnptxfsiz=%08x\n", dwc_read_reg32(&global_regs->gnptxfsiz));
2176+
2177+ /* Periodic Tx FIFO */
2178+ DWC_DEBUGPL(DBG_CIL,"initial hptxfsiz=%08x\n", dwc_read_reg32(&global_regs->hptxfsiz));
2179+ ptxfifosize.b.depth = params->host_perio_tx_fifo_size;
2180+ ptxfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
2181+ dwc_write_reg32(&global_regs->hptxfsiz, ptxfifosize.d32);
2182+ DWC_DEBUGPL(DBG_CIL,"new hptxfsiz=%08x\n", dwc_read_reg32(&global_regs->hptxfsiz));
2183+ }
2184+
2185+ /* Clear Host Set HNP Enable in the OTG Control Register */
2186+ gotgctl.b.hstsethnpen = 1;
2187+ dwc_modify_reg32(&global_regs->gotgctl, gotgctl.d32, 0);
2188+
2189+ /* Make sure the FIFOs are flushed. */
2190+ dwc_otg_flush_tx_fifo(core_if, 0x10 /* all Tx FIFOs */);
2191+ dwc_otg_flush_rx_fifo(core_if);
2192+
2193+ /* Flush out any leftover queued requests. */
2194+ num_channels = core_if->core_params->host_channels;
2195+ for (i = 0; i < num_channels; i++)
2196+ {
2197+ hc_regs = core_if->host_if->hc_regs[i];
2198+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2199+ hcchar.b.chen = 0;
2200+ hcchar.b.chdis = 1;
2201+ hcchar.b.epdir = 0;
2202+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2203+ }
2204+
2205+ /* Halt all channels to put them into a known state. */
2206+ for (i = 0; i < num_channels; i++)
2207+ {
2208+ int count = 0;
2209+ hc_regs = core_if->host_if->hc_regs[i];
2210+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2211+ hcchar.b.chen = 1;
2212+ hcchar.b.chdis = 1;
2213+ hcchar.b.epdir = 0;
2214+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2215+ DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__, i);
2216+ do {
2217+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2218+ if (++count > 1000)
2219+ {
2220+ DWC_ERROR("%s: Unable to clear halt on channel %d\n",
2221+ __func__, i);
2222+ break;
2223+ }
2224+ }
2225+ while (hcchar.b.chen);
2226+ }
2227+
2228+ /* Turn on the vbus power. */
2229+ DWC_PRINT("Init: Port Power? op_state=%d\n", core_if->op_state);
2230+ if (core_if->op_state == A_HOST) {
2231+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
2232+ DWC_PRINT("Init: Power Port (%d)\n", hprt0.b.prtpwr);
2233+ if (hprt0.b.prtpwr == 0) {
2234+ hprt0.b.prtpwr = 1;
2235+ dwc_write_reg32(host_if->hprt0, hprt0.d32);
2236+ }
2237+ }
2238+
2239+ dwc_otg_enable_host_interrupts(core_if);
2240+}
2241+
2242+/**
2243+ * Prepares a host channel for transferring packets to/from a specific
2244+ * endpoint. The HCCHARn register is set up with the characteristics specified
2245+ * in _hc. Host channel interrupts that may need to be serviced while this
2246+ * transfer is in progress are enabled.
2247+ *
2248+ * @param core_if Programming view of DWC_otg controller
2249+ * @param hc Information needed to initialize the host channel
2250+ */
2251+void dwc_otg_hc_init(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
2252+{
2253+ uint32_t intr_enable;
2254+ hcintmsk_data_t hc_intr_mask;
2255+ gintmsk_data_t gintmsk = { .d32 = 0 };
2256+ hcchar_data_t hcchar;
2257+ hcsplt_data_t hcsplt;
2258+
2259+ uint8_t hc_num = hc->hc_num;
2260+ dwc_otg_host_if_t *host_if = core_if->host_if;
2261+ dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num];
2262+
2263+ /* Clear old interrupt conditions for this host channel. */
2264+ hc_intr_mask.d32 = 0xFFFFFFFF;
2265+ hc_intr_mask.b.reserved = 0;
2266+ dwc_write_reg32(&hc_regs->hcint, hc_intr_mask.d32);
2267+
2268+ /* Enable channel interrupts required for this transfer. */
2269+ hc_intr_mask.d32 = 0;
2270+ hc_intr_mask.b.chhltd = 1;
2271+ if (core_if->dma_enable) {
2272+ hc_intr_mask.b.ahberr = 1;
2273+ if (hc->error_state && !hc->do_split &&
2274+ hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
2275+ hc_intr_mask.b.ack = 1;
2276+ if (hc->ep_is_in) {
2277+ hc_intr_mask.b.datatglerr = 1;
2278+ if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
2279+ hc_intr_mask.b.nak = 1;
2280+ }
2281+ }
2282+ }
2283+ }
2284+ else {
2285+ switch (hc->ep_type) {
2286+ case DWC_OTG_EP_TYPE_CONTROL:
2287+ case DWC_OTG_EP_TYPE_BULK:
2288+ hc_intr_mask.b.xfercompl = 1;
2289+ hc_intr_mask.b.stall = 1;
2290+ hc_intr_mask.b.xacterr = 1;
2291+ hc_intr_mask.b.datatglerr = 1;
2292+ if (hc->ep_is_in) {
2293+ hc_intr_mask.b.bblerr = 1;
2294+ }
2295+ else {
2296+ hc_intr_mask.b.nak = 1;
2297+ hc_intr_mask.b.nyet = 1;
2298+ if (hc->do_ping) {
2299+ hc_intr_mask.b.ack = 1;
2300+ }
2301+ }
2302+
2303+ if (hc->do_split) {
2304+ hc_intr_mask.b.nak = 1;
2305+ if (hc->complete_split) {
2306+ hc_intr_mask.b.nyet = 1;
2307+ }
2308+ else {
2309+ hc_intr_mask.b.ack = 1;
2310+ }
2311+ }
2312+
2313+ if (hc->error_state) {
2314+ hc_intr_mask.b.ack = 1;
2315+ }
2316+ break;
2317+ case DWC_OTG_EP_TYPE_INTR:
2318+ hc_intr_mask.b.xfercompl = 1;
2319+ hc_intr_mask.b.nak = 1;
2320+ hc_intr_mask.b.stall = 1;
2321+ hc_intr_mask.b.xacterr = 1;
2322+ hc_intr_mask.b.datatglerr = 1;
2323+ hc_intr_mask.b.frmovrun = 1;
2324+
2325+ if (hc->ep_is_in) {
2326+ hc_intr_mask.b.bblerr = 1;
2327+ }
2328+ if (hc->error_state) {
2329+ hc_intr_mask.b.ack = 1;
2330+ }
2331+ if (hc->do_split) {
2332+ if (hc->complete_split) {
2333+ hc_intr_mask.b.nyet = 1;
2334+ }
2335+ else {
2336+ hc_intr_mask.b.ack = 1;
2337+ }
2338+ }
2339+ break;
2340+ case DWC_OTG_EP_TYPE_ISOC:
2341+ hc_intr_mask.b.xfercompl = 1;
2342+ hc_intr_mask.b.frmovrun = 1;
2343+ hc_intr_mask.b.ack = 1;
2344+
2345+ if (hc->ep_is_in) {
2346+ hc_intr_mask.b.xacterr = 1;
2347+ hc_intr_mask.b.bblerr = 1;
2348+ }
2349+ break;
2350+ }
2351+ }
2352+ dwc_write_reg32(&hc_regs->hcintmsk, hc_intr_mask.d32);
2353+
2354+// if(hc->ep_type == DWC_OTG_EP_TYPE_BULK && !hc->ep_is_in)
2355+// hc->max_packet = 512;
2356+ /* Enable the top level host channel interrupt. */
2357+ intr_enable = (1 << hc_num);
2358+ dwc_modify_reg32(&host_if->host_global_regs->haintmsk, 0, intr_enable);
2359+
2360+ /* Make sure host channel interrupts are enabled. */
2361+ gintmsk.b.hcintr = 1;
2362+ dwc_modify_reg32(&core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
2363+
2364+ /*
2365+ * Program the HCCHARn register with the endpoint characteristics for
2366+ * the current transfer.
2367+ */
2368+ hcchar.d32 = 0;
2369+ hcchar.b.devaddr = hc->dev_addr;
2370+ hcchar.b.epnum = hc->ep_num;
2371+ hcchar.b.epdir = hc->ep_is_in;
2372+ hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
2373+ hcchar.b.eptype = hc->ep_type;
2374+ hcchar.b.mps = hc->max_packet;
2375+
2376+ dwc_write_reg32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32);
2377+
2378+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
2379+ DWC_DEBUGPL(DBG_HCDV, " Dev Addr: %d\n", hcchar.b.devaddr);
2380+ DWC_DEBUGPL(DBG_HCDV, " Ep Num: %d\n", hcchar.b.epnum);
2381+ DWC_DEBUGPL(DBG_HCDV, " Is In: %d\n", hcchar.b.epdir);
2382+ DWC_DEBUGPL(DBG_HCDV, " Is Low Speed: %d\n", hcchar.b.lspddev);
2383+ DWC_DEBUGPL(DBG_HCDV, " Ep Type: %d\n", hcchar.b.eptype);
2384+ DWC_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n", hcchar.b.mps);
2385+ DWC_DEBUGPL(DBG_HCDV, " Multi Cnt: %d\n", hcchar.b.multicnt);
2386+
2387+ /*
2388+ * Program the HCSPLIT register for SPLITs
2389+ */
2390+ hcsplt.d32 = 0;
2391+ if (hc->do_split) {
2392+ DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n", hc->hc_num,
2393+ hc->complete_split ? "CSPLIT" : "SSPLIT");
2394+ hcsplt.b.compsplt = hc->complete_split;
2395+ hcsplt.b.xactpos = hc->xact_pos;
2396+ hcsplt.b.hubaddr = hc->hub_addr;
2397+ hcsplt.b.prtaddr = hc->port_addr;
2398+ DWC_DEBUGPL(DBG_HCDV, " comp split %d\n", hc->complete_split);
2399+ DWC_DEBUGPL(DBG_HCDV, " xact pos %d\n", hc->xact_pos);
2400+ DWC_DEBUGPL(DBG_HCDV, " hub addr %d\n", hc->hub_addr);
2401+ DWC_DEBUGPL(DBG_HCDV, " port addr %d\n", hc->port_addr);
2402+ DWC_DEBUGPL(DBG_HCDV, " is_in %d\n", hc->ep_is_in);
2403+ DWC_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n", hcchar.b.mps);
2404+ DWC_DEBUGPL(DBG_HCDV, " xferlen: %d\n", hc->xfer_len);
2405+ }
2406+ dwc_write_reg32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32);
2407+
2408+}
2409+
2410+/**
2411+ * Attempts to halt a host channel. This function should only be called in
2412+ * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under
2413+ * normal circumstances in DMA mode, the controller halts the channel when the
2414+ * transfer is complete or a condition occurs that requires application
2415+ * intervention.
2416+ *
2417+ * In slave mode, checks for a free request queue entry, then sets the Channel
2418+ * Enable and Channel Disable bits of the Host Channel Characteristics
2419+ * register of the specified channel to intiate the halt. If there is no free
2420+ * request queue entry, sets only the Channel Disable bit of the HCCHARn
2421+ * register to flush requests for this channel. In the latter case, sets a
2422+ * flag to indicate that the host channel needs to be halted when a request
2423+ * queue slot is open.
2424+ *
2425+ * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
2426+ * HCCHARn register. The controller ensures there is space in the request
2427+ * queue before submitting the halt request.
2428+ *
2429+ * Some time may elapse before the core flushes any posted requests for this
2430+ * host channel and halts. The Channel Halted interrupt handler completes the
2431+ * deactivation of the host channel.
2432+ *
2433+ * @param core_if Controller register interface.
2434+ * @param hc Host channel to halt.
2435+ * @param halt_status Reason for halting the channel.
2436+ */
2437+void dwc_otg_hc_halt(dwc_otg_core_if_t *core_if,
2438+ dwc_hc_t *hc,
2439+ dwc_otg_halt_status_e halt_status)
2440+{
2441+ gnptxsts_data_t nptxsts;
2442+ hptxsts_data_t hptxsts;
2443+ hcchar_data_t hcchar;
2444+ dwc_otg_hc_regs_t *hc_regs;
2445+ dwc_otg_core_global_regs_t *global_regs;
2446+ dwc_otg_host_global_regs_t *host_global_regs;
2447+
2448+ hc_regs = core_if->host_if->hc_regs[hc->hc_num];
2449+ global_regs = core_if->core_global_regs;
2450+ host_global_regs = core_if->host_if->host_global_regs;
2451+
2452+ WARN_ON(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS);
2453+
2454+ if (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
2455+ halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
2456+ /*
2457+ * Disable all channel interrupts except Ch Halted. The QTD
2458+ * and QH state associated with this transfer has been cleared
2459+ * (in the case of URB_DEQUEUE), so the channel needs to be
2460+ * shut down carefully to prevent crashes.
2461+ */
2462+ hcintmsk_data_t hcintmsk;
2463+ hcintmsk.d32 = 0;
2464+ hcintmsk.b.chhltd = 1;
2465+ dwc_write_reg32(&hc_regs->hcintmsk, hcintmsk.d32);
2466+
2467+ /*
2468+ * Make sure no other interrupts besides halt are currently
2469+ * pending. Handling another interrupt could cause a crash due
2470+ * to the QTD and QH state.
2471+ */
2472+ dwc_write_reg32(&hc_regs->hcint, ~hcintmsk.d32);
2473+
2474+ /*
2475+ * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
2476+ * even if the channel was already halted for some other
2477+ * reason.
2478+ */
2479+ hc->halt_status = halt_status;
2480+
2481+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2482+ if (hcchar.b.chen == 0) {
2483+ /*
2484+ * The channel is either already halted or it hasn't
2485+ * started yet. In DMA mode, the transfer may halt if
2486+ * it finishes normally or a condition occurs that
2487+ * requires driver intervention. Don't want to halt
2488+ * the channel again. In either Slave or DMA mode,
2489+ * it's possible that the transfer has been assigned
2490+ * to a channel, but not started yet when an URB is
2491+ * dequeued. Don't want to halt a channel that hasn't
2492+ * started yet.
2493+ */
2494+ return;
2495+ }
2496+ }
2497+
2498+ if (hc->halt_pending) {
2499+ /*
2500+ * A halt has already been issued for this channel. This might
2501+ * happen when a transfer is aborted by a higher level in
2502+ * the stack.
2503+ */
2504+#ifdef DEBUG
2505+ DWC_PRINT("*** %s: Channel %d, _hc->halt_pending already set ***\n",
2506+ __func__, hc->hc_num);
2507+
2508+/* dwc_otg_dump_global_registers(core_if); */
2509+/* dwc_otg_dump_host_registers(core_if); */
2510+#endif
2511+ return;
2512+ }
2513+
2514+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2515+ hcchar.b.chen = 1;
2516+ hcchar.b.chdis = 1;
2517+
2518+ if (!core_if->dma_enable) {
2519+ /* Check for space in the request queue to issue the halt. */
2520+ if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
2521+ hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
2522+ nptxsts.d32 = dwc_read_reg32(&global_regs->gnptxsts);
2523+ if (nptxsts.b.nptxqspcavail == 0) {
2524+ hcchar.b.chen = 0;
2525+ }
2526+ }
2527+ else {
2528+ hptxsts.d32 = dwc_read_reg32(&host_global_regs->hptxsts);
2529+ if ((hptxsts.b.ptxqspcavail == 0) || (core_if->queuing_high_bandwidth)) {
2530+ hcchar.b.chen = 0;
2531+ }
2532+ }
2533+ }
2534+
2535+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2536+
2537+ hc->halt_status = halt_status;
2538+
2539+ if (hcchar.b.chen) {
2540+ hc->halt_pending = 1;
2541+ hc->halt_on_queue = 0;
2542+ }
2543+ else {
2544+ hc->halt_on_queue = 1;
2545+ }
2546+
2547+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
2548+ DWC_DEBUGPL(DBG_HCDV, " hcchar: 0x%08x\n", hcchar.d32);
2549+ DWC_DEBUGPL(DBG_HCDV, " halt_pending: %d\n", hc->halt_pending);
2550+ DWC_DEBUGPL(DBG_HCDV, " halt_on_queue: %d\n", hc->halt_on_queue);
2551+ DWC_DEBUGPL(DBG_HCDV, " halt_status: %d\n", hc->halt_status);
2552+
2553+ return;
2554+}
2555+
2556+/**
2557+ * Clears the transfer state for a host channel. This function is normally
2558+ * called after a transfer is done and the host channel is being released.
2559+ *
2560+ * @param core_if Programming view of DWC_otg controller.
2561+ * @param hc Identifies the host channel to clean up.
2562+ */
2563+void dwc_otg_hc_cleanup(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
2564+{
2565+ dwc_otg_hc_regs_t *hc_regs;
2566+
2567+ hc->xfer_started = 0;
2568+
2569+ /*
2570+ * Clear channel interrupt enables and any unhandled channel interrupt
2571+ * conditions.
2572+ */
2573+ hc_regs = core_if->host_if->hc_regs[hc->hc_num];
2574+ dwc_write_reg32(&hc_regs->hcintmsk, 0);
2575+ dwc_write_reg32(&hc_regs->hcint, 0xFFFFFFFF);
2576+
2577+#ifdef DEBUG
2578+ del_timer(&core_if->hc_xfer_timer[hc->hc_num]);
2579+ {
2580+ hcchar_data_t hcchar;
2581+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2582+ if (hcchar.b.chdis) {
2583+ DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
2584+ __func__, hc->hc_num, hcchar.d32);
2585+ }
2586+ }
2587+#endif
2588+}
2589+
2590+/**
2591+ * Sets the channel property that indicates in which frame a periodic transfer
2592+ * should occur. This is always set to the _next_ frame. This function has no
2593+ * effect on non-periodic transfers.
2594+ *
2595+ * @param core_if Programming view of DWC_otg controller.
2596+ * @param hc Identifies the host channel to set up and its properties.
2597+ * @param hcchar Current value of the HCCHAR register for the specified host
2598+ * channel.
2599+ */
2600+static inline void hc_set_even_odd_frame(dwc_otg_core_if_t *core_if,
2601+ dwc_hc_t *hc,
2602+ hcchar_data_t *hcchar)
2603+{
2604+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2605+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2606+ hfnum_data_t hfnum;
2607+ hfnum.d32 = dwc_read_reg32(&core_if->host_if->host_global_regs->hfnum);
2608+
2609+ /* 1 if _next_ frame is odd, 0 if it's even */
2610+ hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
2611+#ifdef DEBUG
2612+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR && hc->do_split && !hc->complete_split) {
2613+ switch (hfnum.b.frnum & 0x7) {
2614+ case 7:
2615+ core_if->hfnum_7_samples++;
2616+ core_if->hfnum_7_frrem_accum += hfnum.b.frrem;
2617+ break;
2618+ case 0:
2619+ core_if->hfnum_0_samples++;
2620+ core_if->hfnum_0_frrem_accum += hfnum.b.frrem;
2621+ break;
2622+ default:
2623+ core_if->hfnum_other_samples++;
2624+ core_if->hfnum_other_frrem_accum += hfnum.b.frrem;
2625+ break;
2626+ }
2627+ }
2628+#endif
2629+ }
2630+}
2631+
2632+#ifdef DEBUG
2633+static void hc_xfer_timeout(unsigned long ptr)
2634+{
2635+ hc_xfer_info_t *xfer_info = (hc_xfer_info_t *)ptr;
2636+ int hc_num = xfer_info->hc->hc_num;
2637+ DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num);
2638+ DWC_WARN(" start_hcchar_val 0x%08x\n", xfer_info->core_if->start_hcchar_val[hc_num]);
2639+}
2640+#endif
2641+
2642+/*
2643+ * This function does the setup for a data transfer for a host channel and
2644+ * starts the transfer. May be called in either Slave mode or DMA mode. In
2645+ * Slave mode, the caller must ensure that there is sufficient space in the
2646+ * request queue and Tx Data FIFO.
2647+ *
2648+ * For an OUT transfer in Slave mode, it loads a data packet into the
2649+ * appropriate FIFO. If necessary, additional data packets will be loaded in
2650+ * the Host ISR.
2651+ *
2652+ * For an IN transfer in Slave mode, a data packet is requested. The data
2653+ * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
2654+ * additional data packets are requested in the Host ISR.
2655+ *
2656+ * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
2657+ * register along with a packet count of 1 and the channel is enabled. This
2658+ * causes a single PING transaction to occur. Other fields in HCTSIZ are
2659+ * simply set to 0 since no data transfer occurs in this case.
2660+ *
2661+ * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
2662+ * all the information required to perform the subsequent data transfer. In
2663+ * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
2664+ * controller performs the entire PING protocol, then starts the data
2665+ * transfer.
2666+ *
2667+ * @param core_if Programming view of DWC_otg controller.
2668+ * @param hc Information needed to initialize the host channel. The xfer_len
2669+ * value may be reduced to accommodate the max widths of the XferSize and
2670+ * PktCnt fields in the HCTSIZn register. The multi_count value may be changed
2671+ * to reflect the final xfer_len value.
2672+ */
2673+void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
2674+{
2675+ hcchar_data_t hcchar;
2676+ hctsiz_data_t hctsiz;
2677+ uint16_t num_packets;
2678+ uint32_t max_hc_xfer_size = core_if->core_params->max_transfer_size;
2679+ uint16_t max_hc_pkt_count = core_if->core_params->max_packet_count;
2680+ dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
2681+
2682+ hctsiz.d32 = 0;
2683+
2684+ if (hc->do_ping) {
2685+ if (!core_if->dma_enable) {
2686+ dwc_otg_hc_do_ping(core_if, hc);
2687+ hc->xfer_started = 1;
2688+ return;
2689+ }
2690+ else {
2691+ hctsiz.b.dopng = 1;
2692+ }
2693+ }
2694+
2695+ if (hc->do_split) {
2696+ num_packets = 1;
2697+
2698+ if (hc->complete_split && !hc->ep_is_in) {
2699+ /* For CSPLIT OUT Transfer, set the size to 0 so the
2700+ * core doesn't expect any data written to the FIFO */
2701+ hc->xfer_len = 0;
2702+ }
2703+ else if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {
2704+ hc->xfer_len = hc->max_packet;
2705+ }
2706+ else if (!hc->ep_is_in && (hc->xfer_len > 188)) {
2707+ hc->xfer_len = 188;
2708+ }
2709+
2710+ hctsiz.b.xfersize = hc->xfer_len;
2711+ }
2712+ else {
2713+ /*
2714+ * Ensure that the transfer length and packet count will fit
2715+ * in the widths allocated for them in the HCTSIZn register.
2716+ */
2717+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2718+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2719+ /*
2720+ * Make sure the transfer size is no larger than one
2721+ * (micro)frame's worth of data. (A check was done
2722+ * when the periodic transfer was accepted to ensure
2723+ * that a (micro)frame's worth of data can be
2724+ * programmed into a channel.)
2725+ */
2726+ uint32_t max_periodic_len = hc->multi_count * hc->max_packet;
2727+ if (hc->xfer_len > max_periodic_len) {
2728+ hc->xfer_len = max_periodic_len;
2729+ }
2730+ else {
2731+ }
2732+ }
2733+ else if (hc->xfer_len > max_hc_xfer_size) {
2734+ /* Make sure that xfer_len is a multiple of max packet size. */
2735+ hc->xfer_len = max_hc_xfer_size - hc->max_packet + 1;
2736+ }
2737+
2738+ if (hc->xfer_len > 0) {
2739+ num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet;
2740+ if (num_packets > max_hc_pkt_count) {
2741+ num_packets = max_hc_pkt_count;
2742+ hc->xfer_len = num_packets * hc->max_packet;
2743+ }
2744+ }
2745+ else {
2746+ /* Need 1 packet for transfer length of 0. */
2747+ num_packets = 1;
2748+ }
2749+
2750+#if 0
2751+//host testusb item 10, would do series of Control transfer
2752+//with URB_SHORT_NOT_OK set in transfer_flags ,
2753+//changing the xfer_len would cause the test fail
2754+ if (hc->ep_is_in) {
2755+ /* Always program an integral # of max packets for IN transfers. */
2756+ hc->xfer_len = num_packets * hc->max_packet;
2757+ }
2758+#endif
2759+
2760+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2761+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2762+ /*
2763+ * Make sure that the multi_count field matches the
2764+ * actual transfer length.
2765+ */
2766+ hc->multi_count = num_packets;
2767+ }
2768+
2769+ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2770+ /* Set up the initial PID for the transfer. */
2771+ if (hc->speed == DWC_OTG_EP_SPEED_HIGH) {
2772+ if (hc->ep_is_in) {
2773+ if (hc->multi_count == 1) {
2774+ hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
2775+ }
2776+ else if (hc->multi_count == 2) {
2777+ hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
2778+ }
2779+ else {
2780+ hc->data_pid_start = DWC_OTG_HC_PID_DATA2;
2781+ }
2782+ }
2783+ else {
2784+ if (hc->multi_count == 1) {
2785+ hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
2786+ }
2787+ else {
2788+ hc->data_pid_start = DWC_OTG_HC_PID_MDATA;
2789+ }
2790+ }
2791+ }
2792+ else {
2793+ hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
2794+ }
2795+ }
2796+
2797+ hctsiz.b.xfersize = hc->xfer_len;
2798+ }
2799+
2800+ hc->start_pkt_count = num_packets;
2801+ hctsiz.b.pktcnt = num_packets;
2802+ hctsiz.b.pid = hc->data_pid_start;
2803+ dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
2804+
2805+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
2806+ DWC_DEBUGPL(DBG_HCDV, " Xfer Size: %d\n", hctsiz.b.xfersize);
2807+ DWC_DEBUGPL(DBG_HCDV, " Num Pkts: %d\n", hctsiz.b.pktcnt);
2808+ DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid);
2809+
2810+ if (core_if->dma_enable) {
2811+ dwc_write_reg32(&hc_regs->hcdma, (uint32_t)hc->xfer_buff);
2812+ }
2813+
2814+ /* Start the split */
2815+ if (hc->do_split) {
2816+ hcsplt_data_t hcsplt;
2817+ hcsplt.d32 = dwc_read_reg32 (&hc_regs->hcsplt);
2818+ hcsplt.b.spltena = 1;
2819+ dwc_write_reg32(&hc_regs->hcsplt, hcsplt.d32);
2820+ }
2821+
2822+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2823+ hcchar.b.multicnt = hc->multi_count;
2824+ hc_set_even_odd_frame(core_if, hc, &hcchar);
2825+#ifdef DEBUG
2826+ core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
2827+ if (hcchar.b.chdis) {
2828+ DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
2829+ __func__, hc->hc_num, hcchar.d32);
2830+ }
2831+#endif
2832+
2833+ /* Set host channel enable after all other setup is complete. */
2834+ hcchar.b.chen = 1;
2835+ hcchar.b.chdis = 0;
2836+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2837+
2838+ hc->xfer_started = 1;
2839+ hc->requests++;
2840+
2841+ if (!core_if->dma_enable &&
2842+ !hc->ep_is_in && hc->xfer_len > 0) {
2843+ /* Load OUT packet into the appropriate Tx FIFO. */
2844+ dwc_otg_hc_write_packet(core_if, hc);
2845+ }
2846+
2847+#ifdef DEBUG
2848+ /* Start a timer for this transfer. */
2849+ core_if->hc_xfer_timer[hc->hc_num].function = hc_xfer_timeout;
2850+ core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
2851+ core_if->hc_xfer_info[hc->hc_num].hc = hc;
2852+ core_if->hc_xfer_timer[hc->hc_num].data = (unsigned long)(&core_if->hc_xfer_info[hc->hc_num]);
2853+ core_if->hc_xfer_timer[hc->hc_num].expires = jiffies + (HZ*10);
2854+ add_timer(&core_if->hc_xfer_timer[hc->hc_num]);
2855+#endif
2856+}
2857+
2858+/**
2859+ * This function continues a data transfer that was started by previous call
2860+ * to <code>dwc_otg_hc_start_transfer</code>. The caller must ensure there is
2861+ * sufficient space in the request queue and Tx Data FIFO. This function
2862+ * should only be called in Slave mode. In DMA mode, the controller acts
2863+ * autonomously to complete transfers programmed to a host channel.
2864+ *
2865+ * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
2866+ * if there is any data remaining to be queued. For an IN transfer, another
2867+ * data packet is always requested. For the SETUP phase of a control transfer,
2868+ * this function does nothing.
2869+ *
2870+ * @return 1 if a new request is queued, 0 if no more requests are required
2871+ * for this transfer.
2872+ */
2873+int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
2874+{
2875+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
2876+
2877+ if (hc->do_split) {
2878+ /* SPLITs always queue just once per channel */
2879+ return 0;
2880+ }
2881+ else if (hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
2882+ /* SETUPs are queued only once since they can't be NAKed. */
2883+ return 0;
2884+ }
2885+ else if (hc->ep_is_in) {
2886+ /*
2887+ * Always queue another request for other IN transfers. If
2888+ * back-to-back INs are issued and NAKs are received for both,
2889+ * the driver may still be processing the first NAK when the
2890+ * second NAK is received. When the interrupt handler clears
2891+ * the NAK interrupt for the first NAK, the second NAK will
2892+ * not be seen. So we can't depend on the NAK interrupt
2893+ * handler to requeue a NAKed request. Instead, IN requests
2894+ * are issued each time this function is called. When the
2895+ * transfer completes, the extra requests for the channel will
2896+ * be flushed.
2897+ */
2898+ hcchar_data_t hcchar;
2899+ dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
2900+
2901+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2902+ hc_set_even_odd_frame(core_if, hc, &hcchar);
2903+ hcchar.b.chen = 1;
2904+ hcchar.b.chdis = 0;
2905+ DWC_DEBUGPL(DBG_HCDV, " IN xfer: hcchar = 0x%08x\n", hcchar.d32);
2906+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2907+ hc->requests++;
2908+ return 1;
2909+ }
2910+ else {
2911+ /* OUT transfers. */
2912+ if (hc->xfer_count < hc->xfer_len) {
2913+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2914+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2915+ hcchar_data_t hcchar;
2916+ dwc_otg_hc_regs_t *hc_regs;
2917+ hc_regs = core_if->host_if->hc_regs[hc->hc_num];
2918+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2919+ hc_set_even_odd_frame(core_if, hc, &hcchar);
2920+ }
2921+
2922+ /* Load OUT packet into the appropriate Tx FIFO. */
2923+ dwc_otg_hc_write_packet(core_if, hc);
2924+ hc->requests++;
2925+ return 1;
2926+ }
2927+ else {
2928+ return 0;
2929+ }
2930+ }
2931+}
2932+
2933+/**
2934+ * Starts a PING transfer. This function should only be called in Slave mode.
2935+ * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled.
2936+ */
2937+void dwc_otg_hc_do_ping(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
2938+{
2939+ hcchar_data_t hcchar;
2940+ hctsiz_data_t hctsiz;
2941+ dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
2942+
2943+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
2944+
2945+ hctsiz.d32 = 0;
2946+ hctsiz.b.dopng = 1;
2947+ hctsiz.b.pktcnt = 1;
2948+ dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
2949+
2950+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2951+ hcchar.b.chen = 1;
2952+ hcchar.b.chdis = 0;
2953+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2954+}
2955+
2956+/*
2957+ * This function writes a packet into the Tx FIFO associated with the Host
2958+ * Channel. For a channel associated with a non-periodic EP, the non-periodic
2959+ * Tx FIFO is written. For a channel associated with a periodic EP, the
2960+ * periodic Tx FIFO is written. This function should only be called in Slave
2961+ * mode.
2962+ *
2963+ * Upon return the xfer_buff and xfer_count fields in _hc are incremented by
2964+ * then number of bytes written to the Tx FIFO.
2965+ */
2966+void dwc_otg_hc_write_packet(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
2967+{
2968+ uint32_t i;
2969+ uint32_t remaining_count;
2970+ uint32_t byte_count;
2971+ uint32_t dword_count;
2972+
2973+ uint32_t *data_buff = (uint32_t *)(hc->xfer_buff);
2974+ uint32_t *data_fifo = core_if->data_fifo[hc->hc_num];
2975+
2976+ remaining_count = hc->xfer_len - hc->xfer_count;
2977+ if (remaining_count > hc->max_packet) {
2978+ byte_count = hc->max_packet;
2979+ }
2980+ else {
2981+ byte_count = remaining_count;
2982+ }
2983+
2984+ dword_count = (byte_count + 3) / 4;
2985+
2986+ if ((((unsigned long)data_buff) & 0x3) == 0) {
2987+ /* xfer_buff is DWORD aligned. */
2988+ for (i = 0; i < dword_count; i++, data_buff++)
2989+ {
2990+ dwc_write_reg32(data_fifo, *data_buff);
2991+ }
2992+ }
2993+ else {
2994+ /* xfer_buff is not DWORD aligned. */
2995+ for (i = 0; i < dword_count; i++, data_buff++)
2996+ {
2997+ dwc_write_reg32(data_fifo, get_unaligned(data_buff));
2998+ }
2999+ }
3000+
3001+ hc->xfer_count += byte_count;
3002+ hc->xfer_buff += byte_count;
3003+}
3004+
3005+/**
3006+ * Gets the current USB frame number. This is the frame number from the last
3007+ * SOF packet.
3008+ */
3009+uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *core_if)
3010+{
3011+ dsts_data_t dsts;
3012+ dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
3013+
3014+ /* read current frame/microframe number from DSTS register */
3015+ return dsts.b.soffn;
3016+}
3017+
3018+/**
3019+ * This function reads a setup packet from the Rx FIFO into the destination
3020+ * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl)
3021+ * Interrupt routine when a SETUP packet has been received in Slave mode.
3022+ *
3023+ * @param core_if Programming view of DWC_otg controller.
3024+ * @param dest Destination buffer for packet data.
3025+ */
3026+void dwc_otg_read_setup_packet(dwc_otg_core_if_t *core_if, uint32_t *dest)
3027+{
3028+ /* Get the 8 bytes of a setup transaction data */
3029+
3030+ /* Pop 2 DWORDS off the receive data FIFO into memory */
3031+ dest[0] = dwc_read_reg32(core_if->data_fifo[0]);
3032+ dest[1] = dwc_read_reg32(core_if->data_fifo[0]);
3033+}
3034+
3035+
3036+/**
3037+ * This function enables EP0 OUT to receive SETUP packets and configures EP0
3038+ * IN for transmitting packets. It is normally called when the
3039+ * "Enumeration Done" interrupt occurs.
3040+ *
3041+ * @param core_if Programming view of DWC_otg controller.
3042+ * @param ep The EP0 data.
3043+ */
3044+void dwc_otg_ep0_activate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
3045+{
3046+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
3047+ dsts_data_t dsts;
3048+ depctl_data_t diepctl;
3049+ depctl_data_t doepctl;
3050+ dctl_data_t dctl = { .d32 = 0 };
3051+
3052+ /* Read the Device Status and Endpoint 0 Control registers */
3053+ dsts.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dsts);
3054+ diepctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl);
3055+ doepctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl);
3056+
3057+ /* Set the MPS of the IN EP based on the enumeration speed */
3058+ switch (dsts.b.enumspd) {
3059+ case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
3060+ case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
3061+ case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
3062+ diepctl.b.mps = DWC_DEP0CTL_MPS_64;
3063+ break;
3064+ case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
3065+ diepctl.b.mps = DWC_DEP0CTL_MPS_8;
3066+ break;
3067+ }
3068+
3069+ dwc_write_reg32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
3070+
3071+ /* Enable OUT EP for receive */
3072+ doepctl.b.epena = 1;
3073+ dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
3074+
3075+#ifdef VERBOSE
3076+ DWC_DEBUGPL(DBG_PCDV,"doepctl0=%0x\n",
3077+ dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl));
3078+ DWC_DEBUGPL(DBG_PCDV,"diepctl0=%0x\n",
3079+ dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl));
3080+#endif
3081+ dctl.b.cgnpinnak = 1;
3082+
3083+ dwc_modify_reg32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
3084+ DWC_DEBUGPL(DBG_PCDV,"dctl=%0x\n",
3085+ dwc_read_reg32(&dev_if->dev_global_regs->dctl));
3086+}
3087+
3088+/**
3089+ * This function activates an EP. The Device EP control register for
3090+ * the EP is configured as defined in the ep structure. Note: This
3091+ * function is not used for EP0.
3092+ *
3093+ * @param core_if Programming view of DWC_otg controller.
3094+ * @param ep The EP to activate.
3095+ */
3096+void dwc_otg_ep_activate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
3097+{
3098+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
3099+ depctl_data_t depctl;
3100+ volatile uint32_t *addr;
3101+ daint_data_t daintmsk = { .d32 = 0 };
3102+
3103+ DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, ep->num,
3104+ (ep->is_in?"IN":"OUT"));
3105+
3106+ /* Read DEPCTLn register */
3107+ if (ep->is_in == 1) {
3108+ addr = &dev_if->in_ep_regs[ep->num]->diepctl;
3109+ daintmsk.ep.in = 1<<ep->num;
3110+ }
3111+ else {
3112+ addr = &dev_if->out_ep_regs[ep->num]->doepctl;
3113+ daintmsk.ep.out = 1<<ep->num;
3114+ }
3115+
3116+ /* If the EP is already active don't change the EP Control
3117+ * register. */
3118+ depctl.d32 = dwc_read_reg32(addr);
3119+ if (!depctl.b.usbactep) {
3120+ depctl.b.mps = ep->maxpacket;
3121+ depctl.b.eptype = ep->type;
3122+ depctl.b.txfnum = ep->tx_fifo_num;
3123+
3124+ if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
3125+ depctl.b.setd0pid = 1; // ???
3126+ }
3127+ else {
3128+ depctl.b.setd0pid = 1;
3129+ }
3130+ depctl.b.usbactep = 1;
3131+
3132+ dwc_write_reg32(addr, depctl.d32);
3133+ DWC_DEBUGPL(DBG_PCDV,"DEPCTL(%.8x)=%08x\n",(u32)addr, dwc_read_reg32(addr));
3134+ }
3135+
3136+ /* Enable the Interrupt for this EP */
3137+ if(core_if->multiproc_int_enable) {
3138+ if (ep->is_in == 1) {
3139+ diepmsk_data_t diepmsk = { .d32 = 0};
3140+ diepmsk.b.xfercompl = 1;
3141+ diepmsk.b.timeout = 1;
3142+ diepmsk.b.epdisabled = 1;
3143+ diepmsk.b.ahberr = 1;
3144+ diepmsk.b.intknepmis = 1;
3145+ diepmsk.b.txfifoundrn = 1; //?????
3146+
3147+
3148+ if(core_if->dma_desc_enable) {
3149+ diepmsk.b.bna = 1;
3150+ }
3151+/*
3152+ if(core_if->dma_enable) {
3153+ doepmsk.b.nak = 1;
3154+ }
3155+*/
3156+ dwc_write_reg32(&dev_if->dev_global_regs->diepeachintmsk[ep->num], diepmsk.d32);
3157+
3158+ } else {
3159+ doepmsk_data_t doepmsk = { .d32 = 0};
3160+ doepmsk.b.xfercompl = 1;
3161+ doepmsk.b.ahberr = 1;
3162+ doepmsk.b.epdisabled = 1;
3163+
3164+
3165+ if(core_if->dma_desc_enable) {
3166+ doepmsk.b.bna = 1;
3167+ }
3168+/*
3169+ doepmsk.b.babble = 1;
3170+ doepmsk.b.nyet = 1;
3171+ doepmsk.b.nak = 1;
3172+*/
3173+ dwc_write_reg32(&dev_if->dev_global_regs->doepeachintmsk[ep->num], doepmsk.d32);
3174+ }
3175+ dwc_modify_reg32(&dev_if->dev_global_regs->deachintmsk,
3176+ 0, daintmsk.d32);
3177+ } else {
3178+ dwc_modify_reg32(&dev_if->dev_global_regs->daintmsk,
3179+ 0, daintmsk.d32);
3180+ }
3181+
3182+ DWC_DEBUGPL(DBG_PCDV,"DAINTMSK=%0x\n",
3183+ dwc_read_reg32(&dev_if->dev_global_regs->daintmsk));
3184+
3185+ ep->stall_clear_flag = 0;
3186+ return;
3187+}
3188+
3189+/**
3190+ * This function deactivates an EP. This is done by clearing the USB Active
3191+ * EP bit in the Device EP control register. Note: This function is not used
3192+ * for EP0. EP0 cannot be deactivated.
3193+ *
3194+ * @param core_if Programming view of DWC_otg controller.
3195+ * @param ep The EP to deactivate.
3196+ */
3197+void dwc_otg_ep_deactivate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
3198+{
3199+ depctl_data_t depctl = { .d32 = 0 };
3200+ volatile uint32_t *addr;
3201+ daint_data_t daintmsk = { .d32 = 0};
3202+
3203+ /* Read DEPCTLn register */
3204+ if (ep->is_in == 1) {
3205+ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
3206+ daintmsk.ep.in = 1<<ep->num;
3207+ }
3208+ else {
3209+ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
3210+ daintmsk.ep.out = 1<<ep->num;
3211+ }
3212+
3213+ //disabled ep only when ep is enabled
3214+ //or got halt in the loop in test in cv9
3215+ depctl.d32=dwc_read_reg32(addr);
3216+ if(depctl.b.epena){
3217+ if (ep->is_in == 1) {
3218+ diepint_data_t diepint;
3219+ dwc_otg_dev_in_ep_regs_t *in_reg=core_if->dev_if->in_ep_regs[ep->num];
3220+
3221+ //Set ep nak
3222+ depctl.d32=dwc_read_reg32(&in_reg->diepctl);
3223+ depctl.b.snak=1;
3224+ dwc_write_reg32(&in_reg->diepctl,depctl.d32);
3225+
3226+ //wait for diepint.b.inepnakeff
3227+ diepint.d32=dwc_read_reg32(&in_reg->diepint);
3228+ while(!diepint.b.inepnakeff){
3229+ udelay(1);
3230+ diepint.d32=dwc_read_reg32(&in_reg->diepint);
3231+ }
3232+ diepint.d32=0;
3233+ diepint.b.inepnakeff=1;
3234+ dwc_write_reg32(&in_reg->diepint,diepint.d32);
3235+
3236+ //set ep disable and snak
3237+ depctl.d32=dwc_read_reg32(&in_reg->diepctl);
3238+ depctl.b.snak=1;
3239+ depctl.b.epdis=1;
3240+ dwc_write_reg32(&in_reg->diepctl,depctl.d32);
3241+
3242+ //wait for diepint.b.epdisabled
3243+ diepint.d32=dwc_read_reg32(&in_reg->diepint);
3244+ while(!diepint.b.epdisabled){
3245+ udelay(1);
3246+ diepint.d32=dwc_read_reg32(&in_reg->diepint);
3247+ }
3248+ diepint.d32=0;
3249+ diepint.b.epdisabled=1;
3250+ dwc_write_reg32(&in_reg->diepint,diepint.d32);
3251+
3252+ //clear ep enable and disable bit
3253+ depctl.d32=dwc_read_reg32(&in_reg->diepctl);
3254+ depctl.b.epena=0;
3255+ depctl.b.epdis=0;
3256+ dwc_write_reg32(&in_reg->diepctl,depctl.d32);
3257+
3258+ }
3259+#if 0
3260+//following DWC OTG DataBook v2.72a, 6.4.2.1.3 Disabling an OUT Endpoint,
3261+//but this doesn't work, the old code do.
3262+ else {
3263+ doepint_data_t doepint;
3264+ dwc_otg_dev_out_ep_regs_t *out_reg=core_if->dev_if->out_ep_regs[ep->num];
3265+ dctl_data_t dctl;
3266+ gintsts_data_t gintsts;
3267+
3268+ //set dctl global out nak
3269+ dctl.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dctl);
3270+ dctl.b.sgoutnak=1;
3271+ dwc_write_reg32(&core_if->dev_if->dev_global_regs->dctl,dctl.d32);
3272+
3273+ //wait for gintsts.goutnakeff
3274+ gintsts.d32=dwc_read_reg32(&core_if->core_global_regs->gintsts);
3275+ while(!gintsts.b.goutnakeff){
3276+ udelay(1);
3277+ gintsts.d32=dwc_read_reg32(&core_if->core_global_regs->gintsts);
3278+ }
3279+ gintsts.d32=0;
3280+ gintsts.b.goutnakeff=1;
3281+ dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
3282+
3283+ //set ep disable and snak
3284+ depctl.d32=dwc_read_reg32(&out_reg->doepctl);
3285+ depctl.b.snak=1;
3286+ depctl.b.epdis=1;
3287+ dwc_write_reg32(&out_reg->doepctl,depctl.d32);
3288+
3289+ //wait for diepint.b.epdisabled
3290+ doepint.d32=dwc_read_reg32(&out_reg->doepint);
3291+ while(!doepint.b.epdisabled){
3292+ udelay(1);
3293+ doepint.d32=dwc_read_reg32(&out_reg->doepint);
3294+ }
3295+ doepint.d32=0;
3296+ doepint.b.epdisabled=1;
3297+ dwc_write_reg32(&out_reg->doepint,doepint.d32);
3298+
3299+ //clear ep enable and disable bit
3300+ depctl.d32=dwc_read_reg32(&out_reg->doepctl);
3301+ depctl.b.epena=0;
3302+ depctl.b.epdis=0;
3303+ dwc_write_reg32(&out_reg->doepctl,depctl.d32);
3304+ }
3305+#endif
3306+
3307+ depctl.d32=0;
3308+ depctl.b.usbactep = 0;
3309+
3310+ if (ep->is_in == 0) {
3311+ if(core_if->dma_enable||core_if->dma_desc_enable)
3312+ depctl.b.epdis = 1;
3313+ }
3314+
3315+ dwc_write_reg32(addr, depctl.d32);
3316+ }
3317+
3318+ /* Disable the Interrupt for this EP */
3319+ if(core_if->multiproc_int_enable) {
3320+ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->deachintmsk,
3321+ daintmsk.d32, 0);
3322+
3323+ if (ep->is_in == 1) {
3324+ dwc_write_reg32(&core_if->dev_if->dev_global_regs->diepeachintmsk[ep->num], 0);
3325+ } else {
3326+ dwc_write_reg32(&core_if->dev_if->dev_global_regs->doepeachintmsk[ep->num], 0);
3327+ }
3328+ } else {
3329+ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->daintmsk,
3330+ daintmsk.d32, 0);
3331+ }
3332+
3333+ if (ep->is_in == 1) {
3334+ DWC_DEBUGPL(DBG_PCD, "DIEPCTL(%.8x)=%08x DIEPTSIZ=%08x, DIEPINT=%.8x, DIEPDMA=%.8x, DTXFSTS=%.8x\n",
3335+ (u32)&core_if->dev_if->in_ep_regs[ep->num]->diepctl,
3336+ dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->diepctl),
3337+ dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz),
3338+ dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->diepint),
3339+ dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->diepdma),
3340+ dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts));
3341+ DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
3342+ dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk),
3343+ dwc_read_reg32(&core_if->core_global_regs->gintmsk));
3344+ }
3345+ else {
3346+ DWC_DEBUGPL(DBG_PCD, "DOEPCTL(%.8x)=%08x DOEPTSIZ=%08x, DOEPINT=%.8x, DOEPDMA=%.8x\n",
3347+ (u32)&core_if->dev_if->out_ep_regs[ep->num]->doepctl,
3348+ dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doepctl),
3349+ dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doeptsiz),
3350+ dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doepint),
3351+ dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doepdma));
3352+
3353+ DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
3354+ dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk),
3355+ dwc_read_reg32(&core_if->core_global_regs->gintmsk));
3356+ }
3357+
3358+}
3359+
3360+/**
3361+ * This function does the setup for a data transfer for an EP and
3362+ * starts the transfer. For an IN transfer, the packets will be
3363+ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
3364+ * the packets are unloaded from the Rx FIFO in the ISR. the ISR.
3365+ *
3366+ * @param core_if Programming view of DWC_otg controller.
3367+ * @param ep The EP to start the transfer on.
3368+ */
3369+static void init_dma_desc_chain(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
3370+{
3371+ dwc_otg_dma_desc_t* dma_desc;
3372+ uint32_t offset;
3373+ uint32_t xfer_est;
3374+ int i;
3375+
3376+ ep->desc_cnt = ( ep->total_len / ep->maxxfer) +
3377+ ((ep->total_len % ep->maxxfer) ? 1 : 0);
3378+ if(!ep->desc_cnt)
3379+ ep->desc_cnt = 1;
3380+
3381+ dma_desc = ep->desc_addr;
3382+ xfer_est = ep->total_len;
3383+ offset = 0;
3384+ for( i = 0; i < ep->desc_cnt; ++i) {
3385+ /** DMA Descriptor Setup */
3386+ if(xfer_est > ep->maxxfer) {
3387+ dma_desc->status.b.bs = BS_HOST_BUSY;
3388+ dma_desc->status.b.l = 0;
3389+ dma_desc->status.b.ioc = 0;
3390+ dma_desc->status.b.sp = 0;
3391+ dma_desc->status.b.bytes = ep->maxxfer;
3392+ dma_desc->buf = ep->dma_addr + offset;
3393+ dma_desc->status.b.bs = BS_HOST_READY;
3394+
3395+ xfer_est -= ep->maxxfer;
3396+ offset += ep->maxxfer;
3397+ } else {
3398+ dma_desc->status.b.bs = BS_HOST_BUSY;
3399+ dma_desc->status.b.l = 1;
3400+ dma_desc->status.b.ioc = 1;
3401+ if(ep->is_in) {
3402+ dma_desc->status.b.sp = (xfer_est % ep->maxpacket) ?
3403+ 1 : ((ep->sent_zlp) ? 1 : 0);
3404+ dma_desc->status.b.bytes = xfer_est;
3405+ } else {
3406+ dma_desc->status.b.bytes = xfer_est + ((4 - (xfer_est & 0x3)) & 0x3) ;
3407+ }
3408+
3409+ dma_desc->buf = ep->dma_addr + offset;
3410+ dma_desc->status.b.bs = BS_HOST_READY;
3411+ }
3412+ dma_desc ++;
3413+ }
3414+}
3415+
3416+/**
3417+ * This function does the setup for a data transfer for an EP and
3418+ * starts the transfer. For an IN transfer, the packets will be
3419+ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
3420+ * the packets are unloaded from the Rx FIFO in the ISR. the ISR.
3421+ *
3422+ * @param core_if Programming view of DWC_otg controller.
3423+ * @param ep The EP to start the transfer on.
3424+ */
3425+
3426+void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
3427+{
3428+ depctl_data_t depctl;
3429+ deptsiz_data_t deptsiz;
3430+ gintmsk_data_t intr_mask = { .d32 = 0};
3431+
3432+ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
3433+
3434+ DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
3435+ "xfer_buff=%p start_xfer_buff=%p\n",
3436+ ep->num, (ep->is_in?"IN":"OUT"), ep->xfer_len,
3437+ ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff);
3438+
3439+ /* IN endpoint */
3440+ if (ep->is_in == 1) {
3441+ dwc_otg_dev_in_ep_regs_t *in_regs =
3442+ core_if->dev_if->in_ep_regs[ep->num];
3443+
3444+ gnptxsts_data_t gtxstatus;
3445+
3446+ gtxstatus.d32 =
3447+ dwc_read_reg32(&core_if->core_global_regs->gnptxsts);
3448+
3449+ if(core_if->en_multiple_tx_fifo == 0 && gtxstatus.b.nptxqspcavail == 0) {
3450+#ifdef DEBUG
3451+ DWC_PRINT("TX Queue Full (0x%0x)\n", gtxstatus.d32);
3452+#endif
3453+ return;
3454+ }
3455+
3456+ depctl.d32 = dwc_read_reg32(&(in_regs->diepctl));
3457+ deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz));
3458+
3459+ ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
3460+ ep->maxxfer : (ep->total_len - ep->xfer_len);
3461+
3462+ /* Zero Length Packet? */
3463+ if ((ep->xfer_len - ep->xfer_count) == 0) {
3464+ deptsiz.b.xfersize = 0;
3465+ deptsiz.b.pktcnt = 1;
3466+ }
3467+ else {
3468+ /* Program the transfer size and packet count
3469+ * as follows: xfersize = N * maxpacket +
3470+ * short_packet pktcnt = N + (short_packet
3471+ * exist ? 1 : 0)
3472+ */
3473+ deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
3474+ deptsiz.b.pktcnt =
3475+ (ep->xfer_len - ep->xfer_count - 1 + ep->maxpacket) /
3476+ ep->maxpacket;
3477+ }
3478+
3479+
3480+ /* Write the DMA register */
3481+ if (core_if->dma_enable) {
3482+ if (/*(core_if->dma_enable)&&*/(ep->dma_addr==DMA_ADDR_INVALID)) {
3483+ ep->dma_addr=dma_map_single(NULL,(void *)(ep->xfer_buff),(ep->xfer_len),DMA_TO_DEVICE);
3484+ }
3485+ DWC_DEBUGPL(DBG_PCDV, "ep%d dma_addr=%.8x\n", ep->num, ep->dma_addr);
3486+
3487+ if (core_if->dma_desc_enable == 0) {
3488+ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
3489+
3490+ VERIFY_PCD_DMA_ADDR(ep->dma_addr);
3491+ dwc_write_reg32 (&(in_regs->diepdma),
3492+ (uint32_t)ep->dma_addr);
3493+ }
3494+ else {
3495+ init_dma_desc_chain(core_if, ep);
3496+ /** DIEPDMAn Register write */
3497+
3498+ VERIFY_PCD_DMA_ADDR(ep->dma_desc_addr);
3499+ dwc_write_reg32(&in_regs->diepdma, ep->dma_desc_addr);
3500+ }
3501+ }
3502+ else
3503+ {
3504+ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
3505+ if(ep->type != DWC_OTG_EP_TYPE_ISOC) {
3506+ /**
3507+ * Enable the Non-Periodic Tx FIFO empty interrupt,
3508+ * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
3509+ * the data will be written into the fifo by the ISR.
3510+ */
3511+ if(core_if->en_multiple_tx_fifo == 0) {
3512+ intr_mask.b.nptxfempty = 1;
3513+ dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
3514+ intr_mask.d32, intr_mask.d32);
3515+ }
3516+ else {
3517+ /* Enable the Tx FIFO Empty Interrupt for this EP */
3518+ if(ep->xfer_len > 0) {
3519+ uint32_t fifoemptymsk = 0;
3520+ fifoemptymsk = 1 << ep->num;
3521+ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
3522+ 0, fifoemptymsk);
3523+
3524+ }
3525+ }
3526+ }
3527+ }
3528+
3529+ /* EP enable, IN data in FIFO */
3530+ depctl.b.cnak = 1;
3531+ depctl.b.epena = 1;
3532+ dwc_write_reg32(&in_regs->diepctl, depctl.d32);
3533+
3534+ depctl.d32 = dwc_read_reg32 (&core_if->dev_if->in_ep_regs[0]->diepctl);
3535+ depctl.b.nextep = ep->num;
3536+ dwc_write_reg32 (&core_if->dev_if->in_ep_regs[0]->diepctl, depctl.d32);
3537+
3538+ DWC_DEBUGPL(DBG_PCD, "DIEPCTL(%.8x)=%08x DIEPTSIZ=%08x, DIEPINT=%.8x, DIEPDMA=%.8x, DTXFSTS=%.8x\n",
3539+ (u32)&in_regs->diepctl,
3540+ dwc_read_reg32(&in_regs->diepctl),
3541+ dwc_read_reg32(&in_regs->dieptsiz),
3542+ dwc_read_reg32(&in_regs->diepint),
3543+ dwc_read_reg32(&in_regs->diepdma),
3544+ dwc_read_reg32(&in_regs->dtxfsts));
3545+ DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
3546+ dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk),
3547+ dwc_read_reg32(&core_if->core_global_regs->gintmsk));
3548+
3549+ }
3550+ else {
3551+ /* OUT endpoint */
3552+ dwc_otg_dev_out_ep_regs_t *out_regs =
3553+ core_if->dev_if->out_ep_regs[ep->num];
3554+
3555+ depctl.d32 = dwc_read_reg32(&(out_regs->doepctl));
3556+ deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz));
3557+
3558+ ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
3559+ ep->maxxfer : (ep->total_len - ep->xfer_len);
3560+
3561+ /* Program the transfer size and packet count as follows:
3562+ *
3563+ * pktcnt = N
3564+ * xfersize = N * maxpacket
3565+ */
3566+ if ((ep->xfer_len - ep->xfer_count) == 0) {
3567+ /* Zero Length Packet */
3568+ deptsiz.b.xfersize = ep->maxpacket;
3569+ deptsiz.b.pktcnt = 1;
3570+ }
3571+ else {
3572+ deptsiz.b.pktcnt =
3573+ (ep->xfer_len - ep->xfer_count + (ep->maxpacket - 1)) /
3574+ ep->maxpacket;
3575+ ep->xfer_len = deptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count;
3576+ deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
3577+ }
3578+
3579+ DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n",
3580+ ep->num,
3581+ deptsiz.b.xfersize, deptsiz.b.pktcnt);
3582+
3583+ if (core_if->dma_enable) {
3584+ if (/*(core_if->dma_enable)&&*/(ep->dma_addr==DMA_ADDR_INVALID)) {
3585+ ep->dma_addr=dma_map_single(NULL,(void *)(ep->xfer_buff),(ep->xfer_len),DMA_TO_DEVICE);
3586+ }
3587+ DWC_DEBUGPL(DBG_PCDV, "ep%d dma_addr=%.8x\n",
3588+ ep->num,
3589+ ep->dma_addr);
3590+ if (!core_if->dma_desc_enable) {
3591+ dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
3592+
3593+ VERIFY_PCD_DMA_ADDR(ep->dma_addr);
3594+ dwc_write_reg32 (&(out_regs->doepdma),
3595+ (uint32_t)ep->dma_addr);
3596+ }
3597+ else {
3598+ init_dma_desc_chain(core_if, ep);
3599+
3600+ /** DOEPDMAn Register write */
3601+
3602+ VERIFY_PCD_DMA_ADDR(ep->dma_desc_addr);
3603+ dwc_write_reg32(&out_regs->doepdma, ep->dma_desc_addr);
3604+ }
3605+ }
3606+ else {
3607+ dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
3608+ }
3609+
3610+ /* EP enable */
3611+ depctl.b.cnak = 1;
3612+ depctl.b.epena = 1;
3613+
3614+ dwc_write_reg32(&out_regs->doepctl, depctl.d32);
3615+
3616+ DWC_DEBUGPL(DBG_PCD, "DOEPCTL(%.8x)=%08x DOEPTSIZ=%08x, DOEPINT=%.8x, DOEPDMA=%.8x\n",
3617+ (u32)&out_regs->doepctl,
3618+ dwc_read_reg32(&out_regs->doepctl),
3619+ dwc_read_reg32(&out_regs->doeptsiz),
3620+ dwc_read_reg32(&out_regs->doepint),
3621+ dwc_read_reg32(&out_regs->doepdma));
3622+
3623+ DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
3624+ dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk),
3625+ dwc_read_reg32(&core_if->core_global_regs->gintmsk));
3626+ }
3627+}
3628+
3629+/**
3630+ * This function setup a zero length transfer in Buffer DMA and
3631+ * Slave modes for usb requests with zero field set
3632+ *
3633+ * @param core_if Programming view of DWC_otg controller.
3634+ * @param ep The EP to start the transfer on.
3635+ *
3636+ */
3637+void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
3638+{
3639+
3640+ depctl_data_t depctl;
3641+ deptsiz_data_t deptsiz;
3642+ gintmsk_data_t intr_mask = { .d32 = 0};
3643+
3644+ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
3645+
3646+ /* IN endpoint */
3647+ if (ep->is_in == 1) {
3648+ dwc_otg_dev_in_ep_regs_t *in_regs =
3649+ core_if->dev_if->in_ep_regs[ep->num];
3650+
3651+ depctl.d32 = dwc_read_reg32(&(in_regs->diepctl));
3652+ deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz));
3653+
3654+ deptsiz.b.xfersize = 0;
3655+ deptsiz.b.pktcnt = 1;
3656+
3657+
3658+ /* Write the DMA register */
3659+ if (core_if->dma_enable) {
3660+ if (/*(core_if->dma_enable)&&*/(ep->dma_addr==DMA_ADDR_INVALID)) {
3661+ ep->dma_addr=dma_map_single(NULL,(void *)(ep->xfer_buff),(ep->xfer_len),DMA_TO_DEVICE);
3662+ }
3663+ if (core_if->dma_desc_enable == 0) {
3664+ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
3665+
3666+ VERIFY_PCD_DMA_ADDR(ep->dma_addr);
3667+ dwc_write_reg32 (&(in_regs->diepdma),
3668+ (uint32_t)ep->dma_addr);
3669+ }
3670+ }
3671+ else {
3672+ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
3673+ /**
3674+ * Enable the Non-Periodic Tx FIFO empty interrupt,
3675+ * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
3676+ * the data will be written into the fifo by the ISR.
3677+ */
3678+ if(core_if->en_multiple_tx_fifo == 0) {
3679+ intr_mask.b.nptxfempty = 1;
3680+ dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
3681+ intr_mask.d32, intr_mask.d32);
3682+ }
3683+ else {
3684+ /* Enable the Tx FIFO Empty Interrupt for this EP */
3685+ if(ep->xfer_len > 0) {
3686+ uint32_t fifoemptymsk = 0;
3687+ fifoemptymsk = 1 << ep->num;
3688+ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
3689+ 0, fifoemptymsk);
3690+ }
3691+ }
3692+ }
3693+
3694+ /* EP enable, IN data in FIFO */
3695+ depctl.b.cnak = 1;
3696+ depctl.b.epena = 1;
3697+ dwc_write_reg32(&in_regs->diepctl, depctl.d32);
3698+
3699+ depctl.d32 = dwc_read_reg32 (&core_if->dev_if->in_ep_regs[0]->diepctl);
3700+ depctl.b.nextep = ep->num;
3701+ dwc_write_reg32 (&core_if->dev_if->in_ep_regs[0]->diepctl, depctl.d32);
3702+
3703+ }
3704+ else {
3705+ /* OUT endpoint */
3706+ dwc_otg_dev_out_ep_regs_t *out_regs =
3707+ core_if->dev_if->out_ep_regs[ep->num];
3708+
3709+ depctl.d32 = dwc_read_reg32(&(out_regs->doepctl));
3710+ deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz));
3711+
3712+ /* Zero Length Packet */
3713+ deptsiz.b.xfersize = ep->maxpacket;
3714+ deptsiz.b.pktcnt = 1;
3715+
3716+ if (core_if->dma_enable) {
3717+ if (/*(core_if->dma_enable)&&*/(ep->dma_addr==DMA_ADDR_INVALID)) {
3718+ ep->dma_addr=dma_map_single(NULL,(void *)(ep->xfer_buff),(ep->xfer_len),DMA_TO_DEVICE);
3719+ }
3720+ if (!core_if->dma_desc_enable) {
3721+ dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
3722+
3723+
3724+ VERIFY_PCD_DMA_ADDR(ep->dma_addr);
3725+ dwc_write_reg32 (&(out_regs->doepdma),
3726+ (uint32_t)ep->dma_addr);
3727+ }
3728+ }
3729+ else {
3730+ dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
3731+ }
3732+
3733+ /* EP enable */
3734+ depctl.b.cnak = 1;
3735+ depctl.b.epena = 1;
3736+
3737+ dwc_write_reg32(&out_regs->doepctl, depctl.d32);
3738+
3739+ }
3740+}
3741+
3742+/**
3743+ * This function does the setup for a data transfer for EP0 and starts
3744+ * the transfer. For an IN transfer, the packets will be loaded into
3745+ * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are
3746+ * unloaded from the Rx FIFO in the ISR.
3747+ *
3748+ * @param core_if Programming view of DWC_otg controller.
3749+ * @param ep The EP0 data.
3750+ */
3751+void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
3752+{
3753+ depctl_data_t depctl;
3754+ deptsiz0_data_t deptsiz;
3755+ gintmsk_data_t intr_mask = { .d32 = 0};
3756+ dwc_otg_dma_desc_t* dma_desc;
3757+
3758+ DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
3759+ "xfer_buff=%p start_xfer_buff=%p, dma_addr=%.8x\n",
3760+ ep->num, (ep->is_in?"IN":"OUT"), ep->xfer_len,
3761+ ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff,ep->dma_addr);
3762+
3763+ ep->total_len = ep->xfer_len;
3764+
3765+ /* IN endpoint */
3766+ if (ep->is_in == 1) {
3767+ dwc_otg_dev_in_ep_regs_t *in_regs =
3768+ core_if->dev_if->in_ep_regs[0];
3769+
3770+ gnptxsts_data_t gtxstatus;
3771+
3772+ gtxstatus.d32 =
3773+ dwc_read_reg32(&core_if->core_global_regs->gnptxsts);
3774+
3775+ if(core_if->en_multiple_tx_fifo == 0 && gtxstatus.b.nptxqspcavail == 0) {
3776+#ifdef DEBUG
3777+ deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
3778+ DWC_DEBUGPL(DBG_PCD,"DIEPCTL0=%0x\n",
3779+ dwc_read_reg32(&in_regs->diepctl));
3780+ DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n",
3781+ deptsiz.d32,
3782+ deptsiz.b.xfersize, deptsiz.b.pktcnt);
3783+ DWC_PRINT("TX Queue or FIFO Full (0x%0x)\n",
3784+ gtxstatus.d32);
3785+#endif
3786+ return;
3787+ }
3788+
3789+
3790+ depctl.d32 = dwc_read_reg32(&in_regs->diepctl);
3791+ deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
3792+
3793+ /* Zero Length Packet? */
3794+ if (ep->xfer_len == 0) {
3795+ deptsiz.b.xfersize = 0;
3796+ deptsiz.b.pktcnt = 1;
3797+ }
3798+ else {
3799+ /* Program the transfer size and packet count
3800+ * as follows: xfersize = N * maxpacket +
3801+ * short_packet pktcnt = N + (short_packet
3802+ * exist ? 1 : 0)
3803+ */
3804+ if (ep->xfer_len > ep->maxpacket) {
3805+ ep->xfer_len = ep->maxpacket;
3806+ deptsiz.b.xfersize = ep->maxpacket;
3807+ }
3808+ else {
3809+ deptsiz.b.xfersize = ep->xfer_len;
3810+ }
3811+ deptsiz.b.pktcnt = 1;
3812+
3813+ }
3814+ DWC_DEBUGPL(DBG_PCDV, "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
3815+ ep->xfer_len,
3816+ deptsiz.b.xfersize, deptsiz.b.pktcnt, deptsiz.d32);
3817+ /* Write the DMA register */
3818+ if (core_if->dma_enable) {
3819+ if (/*(core_if->dma_enable)&&*/(ep->dma_addr==DMA_ADDR_INVALID)) {
3820+ ep->dma_addr=dma_map_single(NULL,(void *)(ep->xfer_buff),(ep->xfer_len),DMA_TO_DEVICE);
3821+ }
3822+ if(core_if->dma_desc_enable == 0) {
3823+ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
3824+
3825+ VERIFY_PCD_DMA_ADDR(ep->dma_addr);
3826+ dwc_write_reg32 (&(in_regs->diepdma),
3827+ (uint32_t)ep->dma_addr);
3828+ }
3829+ else {
3830+ dma_desc = core_if->dev_if->in_desc_addr;
3831+
3832+ /** DMA Descriptor Setup */
3833+ dma_desc->status.b.bs = BS_HOST_BUSY;
3834+ dma_desc->status.b.l = 1;
3835+ dma_desc->status.b.ioc = 1;
3836+ dma_desc->status.b.sp = (ep->xfer_len == ep->maxpacket) ? 0 : 1;
3837+ dma_desc->status.b.bytes = ep->xfer_len;
3838+ dma_desc->buf = ep->dma_addr;
3839+ dma_desc->status.b.bs = BS_HOST_READY;
3840+
3841+ /** DIEPDMA0 Register write */
3842+
3843+ VERIFY_PCD_DMA_ADDR(core_if->dev_if->dma_in_desc_addr);
3844+ dwc_write_reg32(&in_regs->diepdma, core_if->dev_if->dma_in_desc_addr);
3845+ }
3846+ }
3847+ else {
3848+ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
3849+ }
3850+
3851+ /* EP enable, IN data in FIFO */
3852+ depctl.b.cnak = 1;
3853+ depctl.b.epena = 1;
3854+ dwc_write_reg32(&in_regs->diepctl, depctl.d32);
3855+
3856+ /**
3857+ * Enable the Non-Periodic Tx FIFO empty interrupt, the
3858+ * data will be written into the fifo by the ISR.
3859+ */
3860+ if (!core_if->dma_enable) {
3861+ if(core_if->en_multiple_tx_fifo == 0) {
3862+ intr_mask.b.nptxfempty = 1;
3863+ dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
3864+ intr_mask.d32, intr_mask.d32);
3865+ }
3866+ else {
3867+ /* Enable the Tx FIFO Empty Interrupt for this EP */
3868+ if(ep->xfer_len > 0) {
3869+ uint32_t fifoemptymsk = 0;
3870+ fifoemptymsk |= 1 << ep->num;
3871+ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
3872+ 0, fifoemptymsk);
3873+ }
3874+ }
3875+ }
3876+ }
3877+ else {
3878+ /* OUT endpoint */
3879+ dwc_otg_dev_out_ep_regs_t *out_regs =
3880+ core_if->dev_if->out_ep_regs[0];
3881+
3882+ depctl.d32 = dwc_read_reg32(&out_regs->doepctl);
3883+ deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz);
3884+
3885+ /* Program the transfer size and packet count as follows:
3886+ * xfersize = N * (maxpacket + 4 - (maxpacket % 4))
3887+ * pktcnt = N */
3888+ /* Zero Length Packet */
3889+ deptsiz.b.xfersize = ep->maxpacket;
3890+ deptsiz.b.pktcnt = 1;
3891+
3892+ DWC_DEBUGPL(DBG_PCDV, "len=%d xfersize=%d pktcnt=%d\n",
3893+ ep->xfer_len,
3894+ deptsiz.b.xfersize, deptsiz.b.pktcnt);
3895+
3896+ if (core_if->dma_enable) {
3897+ if (/*(core_if->dma_enable)&&*/(ep->dma_addr==DMA_ADDR_INVALID)) {
3898+ ep->dma_addr=dma_map_single(NULL,(void *)(ep->xfer_buff),(ep->xfer_len),DMA_TO_DEVICE);
3899+ }
3900+ if(!core_if->dma_desc_enable) {
3901+ dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
3902+
3903+
3904+ VERIFY_PCD_DMA_ADDR(ep->dma_addr);
3905+ dwc_write_reg32 (&(out_regs->doepdma),
3906+ (uint32_t)ep->dma_addr);
3907+ }
3908+ else {
3909+ dma_desc = core_if->dev_if->out_desc_addr;
3910+
3911+ /** DMA Descriptor Setup */
3912+ dma_desc->status.b.bs = BS_HOST_BUSY;
3913+ dma_desc->status.b.l = 1;
3914+ dma_desc->status.b.ioc = 1;
3915+ dma_desc->status.b.bytes = ep->maxpacket;
3916+ dma_desc->buf = ep->dma_addr;
3917+ dma_desc->status.b.bs = BS_HOST_READY;
3918+
3919+ /** DOEPDMA0 Register write */
3920+ VERIFY_PCD_DMA_ADDR(core_if->dev_if->dma_out_desc_addr);
3921+ dwc_write_reg32(&out_regs->doepdma, core_if->dev_if->dma_out_desc_addr);
3922+ }
3923+ }
3924+ else {
3925+ dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
3926+ }
3927+
3928+ /* EP enable */
3929+ depctl.b.cnak = 1;
3930+ depctl.b.epena = 1;
3931+ dwc_write_reg32 (&(out_regs->doepctl), depctl.d32);
3932+ }
3933+}
3934+
3935+/**
3936+ * This function continues control IN transfers started by
3937+ * dwc_otg_ep0_start_transfer, when the transfer does not fit in a
3938+ * single packet. NOTE: The DIEPCTL0/DOEPCTL0 registers only have one
3939+ * bit for the packet count.
3940+ *
3941+ * @param core_if Programming view of DWC_otg controller.
3942+ * @param ep The EP0 data.
3943+ */
3944+void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
3945+{
3946+ depctl_data_t depctl;
3947+ deptsiz0_data_t deptsiz;
3948+ gintmsk_data_t intr_mask = { .d32 = 0};
3949+ dwc_otg_dma_desc_t* dma_desc;
3950+
3951+ if (ep->is_in == 1) {
3952+ dwc_otg_dev_in_ep_regs_t *in_regs =
3953+ core_if->dev_if->in_ep_regs[0];
3954+ gnptxsts_data_t tx_status = { .d32 = 0 };
3955+
3956+ tx_status.d32 = dwc_read_reg32(&core_if->core_global_regs->gnptxsts);
3957+ /** @todo Should there be check for room in the Tx
3958+ * Status Queue. If not remove the code above this comment. */
3959+
3960+ depctl.d32 = dwc_read_reg32(&in_regs->diepctl);
3961+ deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
3962+
3963+ /* Program the transfer size and packet count
3964+ * as follows: xfersize = N * maxpacket +
3965+ * short_packet pktcnt = N + (short_packet
3966+ * exist ? 1 : 0)
3967+ */
3968+
3969+
3970+ if(core_if->dma_desc_enable == 0) {
3971+ deptsiz.b.xfersize = (ep->total_len - ep->xfer_count) > ep->maxpacket ? ep->maxpacket :
3972+ (ep->total_len - ep->xfer_count);
3973+ deptsiz.b.pktcnt = 1;
3974+ if(core_if->dma_enable == 0) {
3975+ ep->xfer_len += deptsiz.b.xfersize;
3976+ } else {
3977+ ep->xfer_len = deptsiz.b.xfersize;
3978+ }
3979+ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
3980+ }
3981+ else {
3982+ ep->xfer_len = (ep->total_len - ep->xfer_count) > ep->maxpacket ? ep->maxpacket :
3983+ (ep->total_len - ep->xfer_count);
3984+
3985+ dma_desc = core_if->dev_if->in_desc_addr;
3986+
3987+ /** DMA Descriptor Setup */
3988+ dma_desc->status.b.bs = BS_HOST_BUSY;
3989+ dma_desc->status.b.l = 1;
3990+ dma_desc->status.b.ioc = 1;
3991+ dma_desc->status.b.sp = (ep->xfer_len == ep->maxpacket) ? 0 : 1;
3992+ dma_desc->status.b.bytes = ep->xfer_len;
3993+ dma_desc->buf = ep->dma_addr;
3994+ dma_desc->status.b.bs = BS_HOST_READY;
3995+
3996+
3997+ /** DIEPDMA0 Register write */
3998+ VERIFY_PCD_DMA_ADDR(core_if->dev_if->dma_in_desc_addr);
3999+ dwc_write_reg32(&in_regs->diepdma, core_if->dev_if->dma_in_desc_addr);
4000+ }
4001+
4002+
4003+ DWC_DEBUGPL(DBG_PCDV, "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
4004+ ep->xfer_len,
4005+ deptsiz.b.xfersize, deptsiz.b.pktcnt, deptsiz.d32);
4006+
4007+ /* Write the DMA register */
4008+ if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
4009+ if(core_if->dma_desc_enable == 0){
4010+
4011+ VERIFY_PCD_DMA_ADDR(ep->dma_addr);
4012+ dwc_write_reg32 (&(in_regs->diepdma), (uint32_t)ep->dma_addr);
4013+ }
4014+ }
4015+
4016+ /* EP enable, IN data in FIFO */
4017+ depctl.b.cnak = 1;
4018+ depctl.b.epena = 1;
4019+ dwc_write_reg32(&in_regs->diepctl, depctl.d32);
4020+
4021+ /**
4022+ * Enable the Non-Periodic Tx FIFO empty interrupt, the
4023+ * data will be written into the fifo by the ISR.
4024+ */
4025+ if (!core_if->dma_enable) {
4026+ if(core_if->en_multiple_tx_fifo == 0) {
4027+ /* First clear it from GINTSTS */
4028+ intr_mask.b.nptxfempty = 1;
4029+ dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
4030+ intr_mask.d32, intr_mask.d32);
4031+
4032+ }
4033+ else {
4034+ /* Enable the Tx FIFO Empty Interrupt for this EP */
4035+ if(ep->xfer_len > 0) {
4036+ uint32_t fifoemptymsk = 0;
4037+ fifoemptymsk |= 1 << ep->num;
4038+ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
4039+ 0, fifoemptymsk);
4040+ }
4041+ }
4042+ }
4043+ }
4044+ else {
4045+ dwc_otg_dev_out_ep_regs_t *out_regs =
4046+ core_if->dev_if->out_ep_regs[0];
4047+
4048+
4049+ depctl.d32 = dwc_read_reg32(&out_regs->doepctl);
4050+ deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz);
4051+
4052+ /* Program the transfer size and packet count
4053+ * as follows: xfersize = N * maxpacket +
4054+ * short_packet pktcnt = N + (short_packet
4055+ * exist ? 1 : 0)
4056+ */
4057+ deptsiz.b.xfersize = ep->maxpacket;
4058+ deptsiz.b.pktcnt = 1;
4059+
4060+
4061+ if(core_if->dma_desc_enable == 0) {
4062+ dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
4063+ }
4064+ else {
4065+ dma_desc = core_if->dev_if->out_desc_addr;
4066+
4067+ /** DMA Descriptor Setup */
4068+ dma_desc->status.b.bs = BS_HOST_BUSY;
4069+ dma_desc->status.b.l = 1;
4070+ dma_desc->status.b.ioc = 1;
4071+ dma_desc->status.b.bytes = ep->maxpacket;
4072+ dma_desc->buf = ep->dma_addr;
4073+ dma_desc->status.b.bs = BS_HOST_READY;
4074+
4075+ /** DOEPDMA0 Register write */
4076+ VERIFY_PCD_DMA_ADDR(core_if->dev_if->dma_out_desc_addr);
4077+ dwc_write_reg32(&out_regs->doepdma, core_if->dev_if->dma_out_desc_addr);
4078+ }
4079+
4080+
4081+ DWC_DEBUGPL(DBG_PCDV, "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
4082+ ep->xfer_len,
4083+ deptsiz.b.xfersize, deptsiz.b.pktcnt, deptsiz.d32);
4084+
4085+ /* Write the DMA register */
4086+ if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
4087+ if(core_if->dma_desc_enable == 0){
4088+
4089+ VERIFY_PCD_DMA_ADDR(ep->dma_addr);
4090+ dwc_write_reg32 (&(out_regs->doepdma), (uint32_t)ep->dma_addr);
4091+ }
4092+ }
4093+
4094+ /* EP enable, IN data in FIFO */
4095+ depctl.b.cnak = 1;
4096+ depctl.b.epena = 1;
4097+ dwc_write_reg32(&out_regs->doepctl, depctl.d32);
4098+
4099+ }
4100+}
4101+
4102+#ifdef DEBUG
4103+void dump_msg(const u8 *buf, unsigned int length)
4104+{
4105+ unsigned int start, num, i;
4106+ char line[52], *p;
4107+
4108+ if (length >= 512)
4109+ return;
4110+ start = 0;
4111+ while (length > 0) {
4112+ num = min(length, 16u);
4113+ p = line;
4114+ for (i = 0; i < num; ++i)
4115+ {
4116+ if (i == 8)
4117+ *p++ = ' ';
4118+ sprintf(p, " %02x", buf[i]);
4119+ p += 3;
4120+ }
4121+ *p = 0;
4122+ DWC_PRINT("%6x: %s\n", start, line);
4123+ buf += num;
4124+ start += num;
4125+ length -= num;
4126+ }
4127+}
4128+#else
4129+static inline void dump_msg(const u8 *buf, unsigned int length)
4130+{
4131+}
4132+#endif
4133+
4134+/**
4135+ * This function writes a packet into the Tx FIFO associated with the
4136+ * EP. For non-periodic EPs the non-periodic Tx FIFO is written. For
4137+ * periodic EPs the periodic Tx FIFO associated with the EP is written
4138+ * with all packets for the next micro-frame.
4139+ *
4140+ * @param core_if Programming view of DWC_otg controller.
4141+ * @param ep The EP to write packet for.
4142+ * @param dma Indicates if DMA is being used.
4143+ */
4144+void dwc_otg_ep_write_packet(dwc_otg_core_if_t *core_if, dwc_ep_t *ep, int dma)
4145+{
4146+ /**
4147+ * The buffer is padded to DWORD on a per packet basis in
4148+ * slave/dma mode if the MPS is not DWORD aligned. The last
4149+ * packet, if short, is also padded to a multiple of DWORD.
4150+ *
4151+ * ep->xfer_buff always starts DWORD aligned in memory and is a
4152+ * multiple of DWORD in length
4153+ *
4154+ * ep->xfer_len can be any number of bytes
4155+ *
4156+ * ep->xfer_count is a multiple of ep->maxpacket until the last
4157+ * packet
4158+ *
4159+ * FIFO access is DWORD */
4160+
4161+ uint32_t i;
4162+ uint32_t byte_count;
4163+ uint32_t dword_count;
4164+ uint32_t *fifo;
4165+ uint32_t *data_buff = (uint32_t *)ep->xfer_buff;
4166+
4167+ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, core_if, ep);
4168+ if (ep->xfer_count >= ep->xfer_len) {
4169+ DWC_WARN("%s() No data for EP%d!!!\n", __func__, ep->num);
4170+ return;
4171+ }
4172+
4173+ /* Find the byte length of the packet either short packet or MPS */
4174+ if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket) {
4175+ byte_count = ep->xfer_len - ep->xfer_count;
4176+ }
4177+ else {
4178+ byte_count = ep->maxpacket;
4179+ }
4180+
4181+ /* Find the DWORD length, padded by extra bytes as neccessary if MPS
4182+ * is not a multiple of DWORD */
4183+ dword_count = (byte_count + 3) / 4;
4184+
4185+#ifdef VERBOSE
4186+ dump_msg(ep->xfer_buff, byte_count);
4187+#endif
4188+
4189+ /**@todo NGS Where are the Periodic Tx FIFO addresses
4190+ * intialized? What should this be? */
4191+
4192+ fifo = core_if->data_fifo[ep->num];
4193+
4194+
4195+ DWC_DEBUGPL((DBG_PCDV|DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n", fifo, data_buff, *data_buff, byte_count);
4196+
4197+ if (!dma) {
4198+ for (i=0; i<dword_count; i++, data_buff++) {
4199+ dwc_write_reg32(fifo, *data_buff);
4200+ }
4201+ }
4202+
4203+ ep->xfer_count += byte_count;
4204+ ep->xfer_buff += byte_count;
4205+ ep->dma_addr += byte_count;
4206+}
4207+
4208+/**
4209+ * Set the EP STALL.
4210+ *
4211+ * @param core_if Programming view of DWC_otg controller.
4212+ * @param ep The EP to set the stall on.
4213+ */
4214+void dwc_otg_ep_set_stall(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
4215+{
4216+ depctl_data_t depctl;
4217+ volatile uint32_t *depctl_addr;
4218+
4219+ DWC_DEBUGPL(DBG_PCDV, "%s ep%d-%s1\n", __func__, ep->num,
4220+ (ep->is_in?"IN":"OUT"));
4221+
4222+ DWC_PRINT("%s ep%d-%s\n", __func__, ep->num,
4223+ (ep->is_in?"in":"out"));
4224+
4225+ if (ep->is_in == 1) {
4226+ depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
4227+ depctl.d32 = dwc_read_reg32(depctl_addr);
4228+
4229+ /* set the disable and stall bits */
4230+#if 0
4231+//epdis is set here but not cleared at latter dwc_otg_ep_clear_stall,
4232+//which cause the testusb item 13 failed(Host:pc, device: otg device)
4233+ if (depctl.b.epena) {
4234+ depctl.b.epdis = 1;
4235+ }
4236+#endif
4237+ depctl.b.stall = 1;
4238+ dwc_write_reg32(depctl_addr, depctl.d32);
4239+ }
4240+ else {
4241+ depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
4242+ depctl.d32 = dwc_read_reg32(depctl_addr);
4243+
4244+ /* set the stall bit */
4245+ depctl.b.stall = 1;
4246+ dwc_write_reg32(depctl_addr, depctl.d32);
4247+ }
4248+
4249+ DWC_DEBUGPL(DBG_PCDV,"%s: DEPCTL(%.8x)=%0x\n",__func__,(u32)depctl_addr,dwc_read_reg32(depctl_addr));
4250+
4251+ return;
4252+}
4253+
4254+/**
4255+ * Clear the EP STALL.
4256+ *
4257+ * @param core_if Programming view of DWC_otg controller.
4258+ * @param ep The EP to clear stall from.
4259+ */
4260+void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
4261+{
4262+ depctl_data_t depctl;
4263+ volatile uint32_t *depctl_addr;
4264+
4265+ DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
4266+ (ep->is_in?"IN":"OUT"));
4267+
4268+ if (ep->is_in == 1) {
4269+ depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
4270+ }
4271+ else {
4272+ depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
4273+ }
4274+
4275+ depctl.d32 = dwc_read_reg32(depctl_addr);
4276+
4277+ /* clear the stall bits */
4278+ depctl.b.stall = 0;
4279+
4280+ /*
4281+ * USB Spec 9.4.5: For endpoints using data toggle, regardless
4282+ * of whether an endpoint has the Halt feature set, a
4283+ * ClearFeature(ENDPOINT_HALT) request always results in the
4284+ * data toggle being reinitialized to DATA0.
4285+ */
4286+ if (ep->type == DWC_OTG_EP_TYPE_INTR ||
4287+ ep->type == DWC_OTG_EP_TYPE_BULK) {
4288+ depctl.b.setd0pid = 1; /* DATA0 */
4289+ }
4290+
4291+ dwc_write_reg32(depctl_addr, depctl.d32);
4292+ DWC_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",dwc_read_reg32(depctl_addr));
4293+ return;
4294+}
4295+
4296+/**
4297+ * This function reads a packet from the Rx FIFO into the destination
4298+ * buffer. To read SETUP data use dwc_otg_read_setup_packet.
4299+ *
4300+ * @param core_if Programming view of DWC_otg controller.
4301+ * @param dest Destination buffer for the packet.
4302+ * @param bytes Number of bytes to copy to the destination.
4303+ */
4304+void dwc_otg_read_packet(dwc_otg_core_if_t *core_if,
4305+ uint8_t *dest,
4306+ uint16_t bytes)
4307+{
4308+ int i;
4309+ int word_count = (bytes + 3) / 4;
4310+
4311+ volatile uint32_t *fifo = core_if->data_fifo[0];
4312+ uint32_t *data_buff = (uint32_t *)dest;
4313+
4314+ /**
4315+ * @todo Account for the case where _dest is not dword aligned. This
4316+ * requires reading data from the FIFO into a uint32_t temp buffer,
4317+ * then moving it into the data buffer.
4318+ */
4319+
4320+ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__,
4321+ core_if, dest, bytes);
4322+
4323+ for (i=0; i<word_count; i++, data_buff++)
4324+ {
4325+ *data_buff = dwc_read_reg32(fifo);
4326+ }
4327+
4328+ return;
4329+}
4330+
4331+
4332+
4333+/**
4334+ * This functions reads the device registers and prints them
4335+ *
4336+ * @param core_if Programming view of DWC_otg controller.
4337+ */
4338+void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *core_if)
4339+{
4340+ int i;
4341+ volatile uint32_t *addr;
4342+
4343+ DWC_PRINT("Device Global Registers\n");
4344+ addr=&core_if->dev_if->dev_global_regs->dcfg;
4345+ DWC_PRINT("DCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4346+ addr=&core_if->dev_if->dev_global_regs->dctl;
4347+ DWC_PRINT("DCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4348+ addr=&core_if->dev_if->dev_global_regs->dsts;
4349+ DWC_PRINT("DSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4350+ addr=&core_if->dev_if->dev_global_regs->diepmsk;
4351+ DWC_PRINT("DIEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4352+ addr=&core_if->dev_if->dev_global_regs->doepmsk;
4353+ DWC_PRINT("DOEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4354+ addr=&core_if->dev_if->dev_global_regs->daint;
4355+ DWC_PRINT("DAINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4356+ addr=&core_if->dev_if->dev_global_regs->daintmsk;
4357+ DWC_PRINT("DAINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4358+ addr=&core_if->dev_if->dev_global_regs->dtknqr1;
4359+ DWC_PRINT("DTKNQR1 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4360+ if (core_if->hwcfg2.b.dev_token_q_depth > 6) {
4361+ addr=&core_if->dev_if->dev_global_regs->dtknqr2;
4362+ DWC_PRINT("DTKNQR2 @0x%08X : 0x%08X\n",
4363+ (uint32_t)addr,dwc_read_reg32(addr));
4364+ }
4365+
4366+ addr=&core_if->dev_if->dev_global_regs->dvbusdis;
4367+ DWC_PRINT("DVBUSID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4368+
4369+ addr=&core_if->dev_if->dev_global_regs->dvbuspulse;
4370+ DWC_PRINT("DVBUSPULSE @0x%08X : 0x%08X\n",
4371+ (uint32_t)addr,dwc_read_reg32(addr));
4372+
4373+ if (core_if->hwcfg2.b.dev_token_q_depth > 14) {
4374+ addr=&core_if->dev_if->dev_global_regs->dtknqr3_dthrctl;
4375+ DWC_PRINT("DTKNQR3_DTHRCTL @0x%08X : 0x%08X\n",
4376+ (uint32_t)addr, dwc_read_reg32(addr));
4377+ }
4378+/*
4379+ if (core_if->hwcfg2.b.dev_token_q_depth > 22) {
4380+ addr=&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
4381+ DWC_PRINT("DTKNQR4 @0x%08X : 0x%08X\n",
4382+ (uint32_t)addr, dwc_read_reg32(addr));
4383+ }
4384+*/
4385+ addr=&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
4386+ DWC_PRINT("FIFOEMPMSK @0x%08X : 0x%08X\n", (uint32_t)addr, dwc_read_reg32(addr));
4387+
4388+ addr=&core_if->dev_if->dev_global_regs->deachint;
4389+ DWC_PRINT("DEACHINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4390+ addr=&core_if->dev_if->dev_global_regs->deachintmsk;
4391+ DWC_PRINT("DEACHINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4392+
4393+ for (i=0; i<= core_if->dev_if->num_in_eps; i++) {
4394+ addr=&core_if->dev_if->dev_global_regs->diepeachintmsk[i];
4395+ DWC_PRINT("DIEPEACHINTMSK[%d] @0x%08X : 0x%08X\n", i, (uint32_t)addr, dwc_read_reg32(addr));
4396+ }
4397+
4398+
4399+ for (i=0; i<= core_if->dev_if->num_out_eps; i++) {
4400+ addr=&core_if->dev_if->dev_global_regs->doepeachintmsk[i];
4401+ DWC_PRINT("DOEPEACHINTMSK[%d] @0x%08X : 0x%08X\n", i, (uint32_t)addr, dwc_read_reg32(addr));
4402+ }
4403+
4404+ for (i=0; i<= core_if->dev_if->num_in_eps; i++) {
4405+ DWC_PRINT("Device IN EP %d Registers\n", i);
4406+ addr=&core_if->dev_if->in_ep_regs[i]->diepctl;
4407+ DWC_PRINT("DIEPCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4408+ addr=&core_if->dev_if->in_ep_regs[i]->diepint;
4409+ DWC_PRINT("DIEPINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4410+ addr=&core_if->dev_if->in_ep_regs[i]->dieptsiz;
4411+ DWC_PRINT("DIETSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4412+ addr=&core_if->dev_if->in_ep_regs[i]->diepdma;
4413+ DWC_PRINT("DIEPDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4414+ addr=&core_if->dev_if->in_ep_regs[i]->dtxfsts;
4415+ DWC_PRINT("DTXFSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4416+ //reading depdmab in non desc dma mode would halt the ahb bus...
4417+ if(core_if->dma_desc_enable){
4418+ addr=&core_if->dev_if->in_ep_regs[i]->diepdmab;
4419+ DWC_PRINT("DIEPDMAB @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4420+ }
4421+ }
4422+
4423+
4424+ for (i=0; i<= core_if->dev_if->num_out_eps; i++) {
4425+ DWC_PRINT("Device OUT EP %d Registers\n", i);
4426+ addr=&core_if->dev_if->out_ep_regs[i]->doepctl;
4427+ DWC_PRINT("DOEPCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4428+ addr=&core_if->dev_if->out_ep_regs[i]->doepfn;
4429+ DWC_PRINT("DOEPFN @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4430+ addr=&core_if->dev_if->out_ep_regs[i]->doepint;
4431+ DWC_PRINT("DOEPINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4432+ addr=&core_if->dev_if->out_ep_regs[i]->doeptsiz;
4433+ DWC_PRINT("DOETSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4434+ addr=&core_if->dev_if->out_ep_regs[i]->doepdma;
4435+ DWC_PRINT("DOEPDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4436+
4437+ //reading depdmab in non desc dma mode would halt the ahb bus...
4438+ if(core_if->dma_desc_enable){
4439+ addr=&core_if->dev_if->out_ep_regs[i]->doepdmab;
4440+ DWC_PRINT("DOEPDMAB @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4441+ }
4442+
4443+ }
4444+
4445+
4446+
4447+ return;
4448+}
4449+
4450+/**
4451+ * This functions reads the SPRAM and prints its content
4452+ *
4453+ * @param core_if Programming view of DWC_otg controller.
4454+ */
4455+void dwc_otg_dump_spram(dwc_otg_core_if_t *core_if)
4456+{
4457+ volatile uint8_t *addr, *start_addr, *end_addr;
4458+
4459+ DWC_PRINT("SPRAM Data:\n");
4460+ start_addr = (void*)core_if->core_global_regs;
4461+ DWC_PRINT("Base Address: 0x%8X\n", (uint32_t)start_addr);
4462+ start_addr += 0x00028000;
4463+ end_addr=(void*)core_if->core_global_regs;
4464+ end_addr += 0x000280e0;
4465+
4466+ for(addr = start_addr; addr < end_addr; addr+=16)
4467+ {
4468+ DWC_PRINT("0x%8X:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n", (uint32_t)addr,
4469+ addr[0],
4470+ addr[1],
4471+ addr[2],
4472+ addr[3],
4473+ addr[4],
4474+ addr[5],
4475+ addr[6],
4476+ addr[7],
4477+ addr[8],
4478+ addr[9],
4479+ addr[10],
4480+ addr[11],
4481+ addr[12],
4482+ addr[13],
4483+ addr[14],
4484+ addr[15]
4485+ );
4486+ }
4487+
4488+ return;
4489+}
4490+/**
4491+ * This function reads the host registers and prints them
4492+ *
4493+ * @param core_if Programming view of DWC_otg controller.
4494+ */
4495+void dwc_otg_dump_host_registers(dwc_otg_core_if_t *core_if)
4496+{
4497+ int i;
4498+ volatile uint32_t *addr;
4499+
4500+ DWC_PRINT("Host Global Registers\n");
4501+ addr=&core_if->host_if->host_global_regs->hcfg;
4502+ DWC_PRINT("HCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4503+ addr=&core_if->host_if->host_global_regs->hfir;
4504+ DWC_PRINT("HFIR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4505+ addr=&core_if->host_if->host_global_regs->hfnum;
4506+ DWC_PRINT("HFNUM @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4507+ addr=&core_if->host_if->host_global_regs->hptxsts;
4508+ DWC_PRINT("HPTXSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4509+ addr=&core_if->host_if->host_global_regs->haint;
4510+ DWC_PRINT("HAINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4511+ addr=&core_if->host_if->host_global_regs->haintmsk;
4512+ DWC_PRINT("HAINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4513+ addr=core_if->host_if->hprt0;
4514+ DWC_PRINT("HPRT0 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4515+
4516+ for (i=0; i<core_if->core_params->host_channels; i++)
4517+ {
4518+ DWC_PRINT("Host Channel %d Specific Registers\n", i);
4519+ addr=&core_if->host_if->hc_regs[i]->hcchar;
4520+ DWC_PRINT("HCCHAR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4521+ addr=&core_if->host_if->hc_regs[i]->hcsplt;
4522+ DWC_PRINT("HCSPLT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4523+ addr=&core_if->host_if->hc_regs[i]->hcint;
4524+ DWC_PRINT("HCINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4525+ addr=&core_if->host_if->hc_regs[i]->hcintmsk;
4526+ DWC_PRINT("HCINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4527+ addr=&core_if->host_if->hc_regs[i]->hctsiz;
4528+ DWC_PRINT("HCTSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4529+ addr=&core_if->host_if->hc_regs[i]->hcdma;
4530+ DWC_PRINT("HCDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4531+ }
4532+ return;
4533+}
4534+
4535+/**
4536+ * This function reads the core global registers and prints them
4537+ *
4538+ * @param core_if Programming view of DWC_otg controller.
4539+ */
4540+void dwc_otg_dump_global_registers(dwc_otg_core_if_t *core_if)
4541+{
4542+ int i,size;
4543+ char* str;
4544+ volatile uint32_t *addr;
4545+
4546+ DWC_PRINT("Core Global Registers\n");
4547+ addr=&core_if->core_global_regs->gotgctl;
4548+ DWC_PRINT("GOTGCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4549+ addr=&core_if->core_global_regs->gotgint;
4550+ DWC_PRINT("GOTGINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4551+ addr=&core_if->core_global_regs->gahbcfg;
4552+ DWC_PRINT("GAHBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4553+ addr=&core_if->core_global_regs->gusbcfg;
4554+ DWC_PRINT("GUSBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4555+ addr=&core_if->core_global_regs->grstctl;
4556+ DWC_PRINT("GRSTCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4557+ addr=&core_if->core_global_regs->gintsts;
4558+ DWC_PRINT("GINTSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4559+ addr=&core_if->core_global_regs->gintmsk;
4560+ DWC_PRINT("GINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4561+ addr=&core_if->core_global_regs->grxstsr;
4562+ DWC_PRINT("GRXSTSR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4563+ //addr=&core_if->core_global_regs->grxstsp;
4564+ //DWC_PRINT("GRXSTSP @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4565+ addr=&core_if->core_global_regs->grxfsiz;
4566+ DWC_PRINT("GRXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4567+ addr=&core_if->core_global_regs->gnptxfsiz;
4568+ DWC_PRINT("GNPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4569+ addr=&core_if->core_global_regs->gnptxsts;
4570+ DWC_PRINT("GNPTXSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4571+ addr=&core_if->core_global_regs->gi2cctl;
4572+ DWC_PRINT("GI2CCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4573+ addr=&core_if->core_global_regs->gpvndctl;
4574+ DWC_PRINT("GPVNDCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4575+ addr=&core_if->core_global_regs->ggpio;
4576+ DWC_PRINT("GGPIO @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4577+ addr=&core_if->core_global_regs->guid;
4578+ DWC_PRINT("GUID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4579+ addr=&core_if->core_global_regs->gsnpsid;
4580+ DWC_PRINT("GSNPSID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4581+ addr=&core_if->core_global_regs->ghwcfg1;
4582+ DWC_PRINT("GHWCFG1 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4583+ addr=&core_if->core_global_regs->ghwcfg2;
4584+ DWC_PRINT("GHWCFG2 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4585+ addr=&core_if->core_global_regs->ghwcfg3;
4586+ DWC_PRINT("GHWCFG3 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4587+ addr=&core_if->core_global_regs->ghwcfg4;
4588+ DWC_PRINT("GHWCFG4 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4589+ addr=&core_if->core_global_regs->hptxfsiz;
4590+ DWC_PRINT("HPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
4591+
4592+ size=(core_if->hwcfg4.b.ded_fifo_en)?
4593+ core_if->hwcfg4.b.num_in_eps:core_if->hwcfg4.b.num_dev_perio_in_ep;
4594+ str=(core_if->hwcfg4.b.ded_fifo_en)?"DIEPTXF":"DPTXFSIZ";
4595+ for (i=0; i<size; i++)
4596+ {
4597+ addr=&core_if->core_global_regs->dptxfsiz_dieptxf[i];
4598+ DWC_PRINT("%s[%d] @0x%08X : 0x%08X\n",str,i,(uint32_t)addr,dwc_read_reg32(addr));
4599+ }
4600+}
4601+
4602+/**
4603+ * Flush a Tx FIFO.
4604+ *
4605+ * @param core_if Programming view of DWC_otg controller.
4606+ * @param num Tx FIFO to flush.
4607+ */
4608+void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t *core_if,
4609+ const int num)
4610+{
4611+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
4612+ volatile grstctl_t greset = { .d32 = 0};
4613+ int count = 0;
4614+
4615+ DWC_DEBUGPL((DBG_CIL|DBG_PCDV), "Flush Tx FIFO %d\n", num);
4616+
4617+ greset.b.txfflsh = 1;
4618+ greset.b.txfnum = num;
4619+ dwc_write_reg32(&global_regs->grstctl, greset.d32);
4620+
4621+ do {
4622+ greset.d32 = dwc_read_reg32(&global_regs->grstctl);
4623+ if (++count > 10000) {
4624+ DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
4625+ __func__, greset.d32,
4626+ dwc_read_reg32(&global_regs->gnptxsts));
4627+ break;
4628+ }
4629+ }
4630+ while (greset.b.txfflsh == 1);
4631+
4632+ /* Wait for 3 PHY Clocks*/
4633+ UDELAY(1);
4634+}
4635+
4636+/**
4637+ * Flush Rx FIFO.
4638+ *
4639+ * @param core_if Programming view of DWC_otg controller.
4640+ */
4641+void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t *core_if)
4642+{
4643+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
4644+ volatile grstctl_t greset = { .d32 = 0};
4645+ int count = 0;
4646+
4647+ DWC_DEBUGPL((DBG_CIL|DBG_PCDV), "%s\n", __func__);
4648+ /*
4649+ *
4650+ */
4651+ greset.b.rxfflsh = 1;
4652+ dwc_write_reg32(&global_regs->grstctl, greset.d32);
4653+
4654+ do {
4655+ greset.d32 = dwc_read_reg32(&global_regs->grstctl);
4656+ if (++count > 10000) {
4657+ DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__,
4658+ greset.d32);
4659+ break;
4660+ }
4661+ }
4662+ while (greset.b.rxfflsh == 1);
4663+
4664+ /* Wait for 3 PHY Clocks*/
4665+ UDELAY(1);
4666+}
4667+
4668+/**
4669+ * Do core a soft reset of the core. Be careful with this because it
4670+ * resets all the internal state machines of the core.
4671+ */
4672+void dwc_otg_core_reset(dwc_otg_core_if_t *core_if)
4673+{
4674+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
4675+ volatile grstctl_t greset = { .d32 = 0};
4676+ int count = 0;
4677+
4678+ DWC_DEBUGPL(DBG_CILV, "%s\n", __func__);
4679+ /* Wait for AHB master IDLE state. */
4680+ do {
4681+ UDELAY(10);
4682+ greset.d32 = dwc_read_reg32(&global_regs->grstctl);
4683+ if (++count > 100000) {
4684+ DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__,
4685+ greset.d32);
4686+ return;
4687+ }
4688+ }
4689+ while (greset.b.ahbidle == 0);
4690+
4691+ /* Core Soft Reset */
4692+ count = 0;
4693+ greset.b.csftrst = 1;
4694+ dwc_write_reg32(&global_regs->grstctl, greset.d32);
4695+ do {
4696+ greset.d32 = dwc_read_reg32(&global_regs->grstctl);
4697+ if (++count > 10000) {
4698+ DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n", __func__,
4699+ greset.d32);
4700+ break;
4701+ }
4702+ }
4703+ while (greset.b.csftrst == 1);
4704+
4705+ /* Wait for 3 PHY Clocks*/
4706+ MDELAY(100);
4707+
4708+ DWC_DEBUGPL(DBG_CILV, "GINTSTS=%.8x\n", dwc_read_reg32(&global_regs->gintsts));
4709+ DWC_DEBUGPL(DBG_CILV, "GINTSTS=%.8x\n", dwc_read_reg32(&global_regs->gintsts));
4710+ DWC_DEBUGPL(DBG_CILV, "GINTSTS=%.8x\n", dwc_read_reg32(&global_regs->gintsts));
4711+
4712+}
4713+
4714+
4715+
4716+/**
4717+ * Register HCD callbacks. The callbacks are used to start and stop
4718+ * the HCD for interrupt processing.
4719+ *
4720+ * @param core_if Programming view of DWC_otg controller.
4721+ * @param cb the HCD callback structure.
4722+ * @param p pointer to be passed to callback function (usb_hcd*).
4723+ */
4724+void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t *core_if,
4725+ dwc_otg_cil_callbacks_t *cb,
4726+ void *p)
4727+{
4728+ core_if->hcd_cb = cb;
4729+ cb->p = p;
4730+}
4731+
4732+/**
4733+ * Register PCD callbacks. The callbacks are used to start and stop
4734+ * the PCD for interrupt processing.
4735+ *
4736+ * @param core_if Programming view of DWC_otg controller.
4737+ * @param cb the PCD callback structure.
4738+ * @param p pointer to be passed to callback function (pcd*).
4739+ */
4740+void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t *core_if,
4741+ dwc_otg_cil_callbacks_t *cb,
4742+ void *p)
4743+{
4744+ core_if->pcd_cb = cb;
4745+ cb->p = p;
4746+}
4747+
4748+#ifdef DWC_EN_ISOC
4749+
4750+/**
4751+ * This function writes isoc data per 1 (micro)frame into tx fifo
4752+ *
4753+ * @param core_if Programming view of DWC_otg controller.
4754+ * @param ep The EP to start the transfer on.
4755+ *
4756+ */
4757+void write_isoc_frame_data(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
4758+{
4759+ dwc_otg_dev_in_ep_regs_t *ep_regs;
4760+ dtxfsts_data_t txstatus = {.d32 = 0};
4761+ uint32_t len = 0;
4762+ uint32_t dwords;
4763+
4764+ ep->xfer_len = ep->data_per_frame;
4765+ ep->xfer_count = 0;
4766+
4767+ ep_regs = core_if->dev_if->in_ep_regs[ep->num];
4768+
4769+ len = ep->xfer_len - ep->xfer_count;
4770+
4771+ if (len > ep->maxpacket) {
4772+ len = ep->maxpacket;
4773+ }
4774+
4775+ dwords = (len + 3)/4;
4776+
4777+ /* While there is space in the queue and space in the FIFO and
4778+ * More data to tranfer, Write packets to the Tx FIFO */
4779+ txstatus.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts);
4780+ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n",ep->num,txstatus.d32);
4781+
4782+ while (txstatus.b.txfspcavail > dwords &&
4783+ ep->xfer_count < ep->xfer_len &&
4784+ ep->xfer_len != 0) {
4785+ /* Write the FIFO */
4786+ dwc_otg_ep_write_packet(core_if, ep, 0);
4787+
4788+ len = ep->xfer_len - ep->xfer_count;
4789+ if (len > ep->maxpacket) {
4790+ len = ep->maxpacket;
4791+ }
4792+
4793+ dwords = (len + 3)/4;
4794+ txstatus.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts);
4795+ DWC_DEBUGPL(DBG_PCDV,"dtxfsts[%d]=0x%08x\n", ep->num, txstatus.d32);
4796+ }
4797+}
4798+
4799+
4800+/**
4801+ * This function initializes a descriptor chain for Isochronous transfer
4802+ *
4803+ * @param core_if Programming view of DWC_otg controller.
4804+ * @param ep The EP to start the transfer on.
4805+ *
4806+ */
4807+void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
4808+{
4809+ deptsiz_data_t deptsiz = { .d32 = 0 };
4810+ depctl_data_t depctl = { .d32 = 0 };
4811+ dsts_data_t dsts = { .d32 = 0 };
4812+ volatile uint32_t *addr;
4813+
4814+ if(ep->is_in) {
4815+ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
4816+ } else {
4817+ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
4818+ }
4819+
4820+ ep->xfer_len = ep->data_per_frame;
4821+ ep->xfer_count = 0;
4822+ ep->xfer_buff = ep->cur_pkt_addr;
4823+ ep->dma_addr = ep->cur_pkt_dma_addr;
4824+
4825+ if(ep->is_in) {
4826+ /* Program the transfer size and packet count
4827+ * as follows: xfersize = N * maxpacket +
4828+ * short_packet pktcnt = N + (short_packet
4829+ * exist ? 1 : 0)
4830+ */
4831+ deptsiz.b.xfersize = ep->xfer_len;
4832+ deptsiz.b.pktcnt =
4833+ (ep->xfer_len - 1 + ep->maxpacket) /
4834+ ep->maxpacket;
4835+ deptsiz.b.mc = deptsiz.b.pktcnt;
4836+ dwc_write_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz, deptsiz.d32);
4837+
4838+ /* Write the DMA register */
4839+ if (core_if->dma_enable) {
4840+ dwc_write_reg32 (&(core_if->dev_if->in_ep_regs[ep->num]->diepdma), (uint32_t)ep->dma_addr);
4841+ }
4842+ } else {
4843+ deptsiz.b.pktcnt =
4844+ (ep->xfer_len + (ep->maxpacket - 1)) /
4845+ ep->maxpacket;
4846+ deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
4847+
4848+ dwc_write_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doeptsiz, deptsiz.d32);
4849+
4850+ if (core_if->dma_enable) {
4851+ dwc_write_reg32 (&(core_if->dev_if->out_ep_regs[ep->num]->doepdma),
4852+ (uint32_t)ep->dma_addr);
4853+ }
4854+ }
4855+
4856+
4857+ /** Enable endpoint, clear nak */
4858+
4859+ depctl.d32 = 0;
4860+ if(ep->bInterval == 1) {
4861+ dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
4862+ ep->next_frame = dsts.b.soffn + ep->bInterval;
4863+
4864+ if(ep->next_frame & 0x1) {
4865+ depctl.b.setd1pid = 1;
4866+ } else {
4867+ depctl.b.setd0pid = 1;
4868+ }
4869+ } else {
4870+ ep->next_frame += ep->bInterval;
4871+
4872+ if(ep->next_frame & 0x1) {
4873+ depctl.b.setd1pid = 1;
4874+ } else {
4875+ depctl.b.setd0pid = 1;
4876+ }
4877+ }
4878+ depctl.b.epena = 1;
4879+ depctl.b.cnak = 1;
4880+
4881+ dwc_modify_reg32(addr, 0, depctl.d32);
4882+ depctl.d32 = dwc_read_reg32(addr);
4883+
4884+ if(ep->is_in && core_if->dma_enable == 0) {
4885+ write_isoc_frame_data(core_if, ep);
4886+ }
4887+
4888+}
4889+
4890+#endif //DWC_EN_ISOC
4891--- /dev/null
4892+++ b/drivers/usb/dwc/otg_cil.h
4893@@ -0,0 +1,1106 @@
4894+/* ==========================================================================
4895+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $
4896+ * $Revision: #91 $
4897+ * $Date: 2008/09/19 $
4898+ * $Change: 1099526 $
4899+ *
4900+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
4901+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
4902+ * otherwise expressly agreed to in writing between Synopsys and you.
4903+ *
4904+ * The Software IS NOT an item of Licensed Software or Licensed Product under
4905+ * any End User Software License Agreement or Agreement for Licensed Product
4906+ * with Synopsys or any supplement thereto. You are permitted to use and
4907+ * redistribute this Software in source and binary forms, with or without
4908+ * modification, provided that redistributions of source code must retain this
4909+ * notice. You may not view, use, disclose, copy or distribute this file or
4910+ * any information contained herein except pursuant to this license grant from
4911+ * Synopsys. If you do not agree with this notice, including the disclaimer
4912+ * below, then you are not authorized to use the Software.
4913+ *
4914+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
4915+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
4916+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4917+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
4918+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
4919+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
4920+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
4921+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
4922+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
4923+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
4924+ * DAMAGE.
4925+ * ========================================================================== */
4926+
4927+#if !defined(__DWC_CIL_H__)
4928+#define __DWC_CIL_H__
4929+
4930+#include <linux/workqueue.h>
4931+#include <linux/version.h>
4932+#include <asm/param.h>
4933+//#include <asm/arch/regs-irq.h>
4934+
4935+#include "otg_plat.h"
4936+#include "otg_regs.h"
4937+#ifdef DEBUG
4938+#include "linux/timer.h"
4939+#endif
4940+
4941+/**
4942+ * @file
4943+ * This file contains the interface to the Core Interface Layer.
4944+ */
4945+
4946+
4947+/** Macros defined for DWC OTG HW Release verison */
4948+#define OTG_CORE_REV_2_00 0x4F542000
4949+#define OTG_CORE_REV_2_60a 0x4F54260A
4950+#define OTG_CORE_REV_2_71a 0x4F54271A
4951+#define OTG_CORE_REV_2_72a 0x4F54272A
4952+
4953+/**
4954+*/
4955+typedef struct iso_pkt_info
4956+{
4957+ uint32_t offset;
4958+ uint32_t length;
4959+ int32_t status;
4960+} iso_pkt_info_t;
4961+/**
4962+ * The <code>dwc_ep</code> structure represents the state of a single
4963+ * endpoint when acting in device mode. It contains the data items
4964+ * needed for an endpoint to be activated and transfer packets.
4965+ */
4966+typedef struct dwc_ep
4967+{
4968+ /** EP number used for register address lookup */
4969+ uint8_t num;
4970+ /** EP direction 0 = OUT */
4971+ unsigned is_in : 1;
4972+ /** EP active. */
4973+ unsigned active : 1;
4974+
4975+ /** Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO
4976+ If dedicated Tx FIFOs are enabled for all IN Eps - Tx FIFO # FOR IN EPs*/
4977+ unsigned tx_fifo_num : 4;
4978+ /** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */
4979+ unsigned type : 2;
4980+#define DWC_OTG_EP_TYPE_CONTROL 0
4981+#define DWC_OTG_EP_TYPE_ISOC 1
4982+#define DWC_OTG_EP_TYPE_BULK 2
4983+#define DWC_OTG_EP_TYPE_INTR 3
4984+
4985+ /** DATA start PID for INTR and BULK EP */
4986+ unsigned data_pid_start : 1;
4987+ /** Frame (even/odd) for ISOC EP */
4988+ unsigned even_odd_frame : 1;
4989+ /** Max Packet bytes */
4990+ unsigned maxpacket : 11;
4991+
4992+ /** Max Transfer size */
4993+ unsigned maxxfer : 16;
4994+
4995+ /** @name Transfer state */
4996+ /** @{ */
4997+
4998+ /**
4999+ * Pointer to the beginning of the transfer buffer -- do not modify
5000+ * during transfer.
5001+ */
5002+
5003+ uint32_t dma_addr;
5004+
5005+ uint32_t dma_desc_addr;
5006+ dwc_otg_dma_desc_t* desc_addr;
5007+
5008+
5009+ uint8_t *start_xfer_buff;
5010+ /** pointer to the transfer buffer */
5011+ uint8_t *xfer_buff;
5012+ /** Number of bytes to transfer */
5013+ unsigned xfer_len : 19;
5014+ /** Number of bytes transferred. */
5015+ unsigned xfer_count : 19;
5016+ /** Sent ZLP */
5017+ unsigned sent_zlp : 1;
5018+ /** Total len for control transfer */
5019+ unsigned total_len : 19;
5020+
5021+ /** stall clear flag */
5022+ unsigned stall_clear_flag : 1;
5023+
5024+ /** Allocated DMA Desc count */
5025+ uint32_t desc_cnt;
5026+
5027+ uint32_t aligned_dma_addr;
5028+ uint32_t aligned_buf_size;
5029+ uint8_t *aligned_buf;
5030+
5031+
5032+#ifdef DWC_EN_ISOC
5033+ /**
5034+ * Variables specific for ISOC EPs
5035+ *
5036+ */
5037+ /** DMA addresses of ISOC buffers */
5038+ uint32_t dma_addr0;
5039+ uint32_t dma_addr1;
5040+
5041+ uint32_t iso_dma_desc_addr;
5042+ dwc_otg_dma_desc_t* iso_desc_addr;
5043+
5044+ /** pointer to the transfer buffers */
5045+ uint8_t *xfer_buff0;
5046+ uint8_t *xfer_buff1;
5047+
5048+ /** number of ISOC Buffer is processing */
5049+ uint32_t proc_buf_num;
5050+ /** Interval of ISOC Buffer processing */
5051+ uint32_t buf_proc_intrvl;
5052+ /** Data size for regular frame */
5053+ uint32_t data_per_frame;
5054+
5055+ /* todo - pattern data support is to be implemented in the future */
5056+ /** Data size for pattern frame */
5057+ uint32_t data_pattern_frame;
5058+ /** Frame number of pattern data */
5059+ uint32_t sync_frame;
5060+
5061+ /** bInterval */
5062+ uint32_t bInterval;
5063+ /** ISO Packet number per frame */
5064+ uint32_t pkt_per_frm;
5065+ /** Next frame num for which will be setup DMA Desc */
5066+ uint32_t next_frame;
5067+ /** Number of packets per buffer processing */
5068+ uint32_t pkt_cnt;
5069+ /** Info for all isoc packets */
5070+ iso_pkt_info_t *pkt_info;
5071+ /** current pkt number */
5072+ uint32_t cur_pkt;
5073+ /** current pkt number */
5074+ uint8_t *cur_pkt_addr;
5075+ /** current pkt number */
5076+ uint32_t cur_pkt_dma_addr;
5077+#endif //DWC_EN_ISOC
5078+/** @} */
5079+} dwc_ep_t;
5080+
5081+/*
5082+ * Reasons for halting a host channel.
5083+ */
5084+typedef enum dwc_otg_halt_status
5085+{
5086+ DWC_OTG_HC_XFER_NO_HALT_STATUS,
5087+ DWC_OTG_HC_XFER_COMPLETE,
5088+ DWC_OTG_HC_XFER_URB_COMPLETE,
5089+ DWC_OTG_HC_XFER_ACK,
5090+ DWC_OTG_HC_XFER_NAK,
5091+ DWC_OTG_HC_XFER_NYET,
5092+ DWC_OTG_HC_XFER_STALL,
5093+ DWC_OTG_HC_XFER_XACT_ERR,
5094+ DWC_OTG_HC_XFER_FRAME_OVERRUN,
5095+ DWC_OTG_HC_XFER_BABBLE_ERR,
5096+ DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
5097+ DWC_OTG_HC_XFER_AHB_ERR,
5098+ DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
5099+ DWC_OTG_HC_XFER_URB_DEQUEUE
5100+} dwc_otg_halt_status_e;
5101+
5102+/**
5103+ * Host channel descriptor. This structure represents the state of a single
5104+ * host channel when acting in host mode. It contains the data items needed to
5105+ * transfer packets to an endpoint via a host channel.
5106+ */
5107+typedef struct dwc_hc
5108+{
5109+ /** Host channel number used for register address lookup */
5110+ uint8_t hc_num;
5111+
5112+ /** Device to access */
5113+ unsigned dev_addr : 7;
5114+
5115+ /** EP to access */
5116+ unsigned ep_num : 4;
5117+
5118+ /** EP direction. 0: OUT, 1: IN */
5119+ unsigned ep_is_in : 1;
5120+
5121+ /**
5122+ * EP speed.
5123+ * One of the following values:
5124+ * - DWC_OTG_EP_SPEED_LOW
5125+ * - DWC_OTG_EP_SPEED_FULL
5126+ * - DWC_OTG_EP_SPEED_HIGH
5127+ */
5128+ unsigned speed : 2;
5129+#define DWC_OTG_EP_SPEED_LOW 0
5130+#define DWC_OTG_EP_SPEED_FULL 1
5131+#define DWC_OTG_EP_SPEED_HIGH 2
5132+
5133+ /**
5134+ * Endpoint type.
5135+ * One of the following values:
5136+ * - DWC_OTG_EP_TYPE_CONTROL: 0
5137+ * - DWC_OTG_EP_TYPE_ISOC: 1
5138+ * - DWC_OTG_EP_TYPE_BULK: 2
5139+ * - DWC_OTG_EP_TYPE_INTR: 3
5140+ */
5141+ unsigned ep_type : 2;
5142+
5143+ /** Max packet size in bytes */
5144+ unsigned max_packet : 11;
5145+
5146+ /**
5147+ * PID for initial transaction.
5148+ * 0: DATA0,<br>
5149+ * 1: DATA2,<br>
5150+ * 2: DATA1,<br>
5151+ * 3: MDATA (non-Control EP),
5152+ * SETUP (Control EP)
5153+ */
5154+ unsigned data_pid_start : 2;
5155+#define DWC_OTG_HC_PID_DATA0 0
5156+#define DWC_OTG_HC_PID_DATA2 1
5157+#define DWC_OTG_HC_PID_DATA1 2
5158+#define DWC_OTG_HC_PID_MDATA 3
5159+#define DWC_OTG_HC_PID_SETUP 3
5160+
5161+ /** Number of periodic transactions per (micro)frame */
5162+ unsigned multi_count: 2;
5163+
5164+ /** @name Transfer State */
5165+ /** @{ */
5166+
5167+ /** Pointer to the current transfer buffer position. */
5168+ uint8_t *xfer_buff;
5169+ /** Total number of bytes to transfer. */
5170+ uint32_t xfer_len;
5171+ /** Number of bytes transferred so far. */
5172+ uint32_t xfer_count;
5173+ /** Packet count at start of transfer.*/
5174+ uint16_t start_pkt_count;
5175+
5176+ /**
5177+ * Flag to indicate whether the transfer has been started. Set to 1 if
5178+ * it has been started, 0 otherwise.
5179+ */
5180+ uint8_t xfer_started;
5181+
5182+ /**
5183+ * Set to 1 to indicate that a PING request should be issued on this
5184+ * channel. If 0, process normally.
5185+ */
5186+ uint8_t do_ping;
5187+
5188+ /**
5189+ * Set to 1 to indicate that the error count for this transaction is
5190+ * non-zero. Set to 0 if the error count is 0.
5191+ */
5192+ uint8_t error_state;
5193+
5194+ /**
5195+ * Set to 1 to indicate that this channel should be halted the next
5196+ * time a request is queued for the channel. This is necessary in
5197+ * slave mode if no request queue space is available when an attempt
5198+ * is made to halt the channel.
5199+ */
5200+ uint8_t halt_on_queue;
5201+
5202+ /**
5203+ * Set to 1 if the host channel has been halted, but the core is not
5204+ * finished flushing queued requests. Otherwise 0.
5205+ */
5206+ uint8_t halt_pending;
5207+
5208+ /**
5209+ * Reason for halting the host channel.
5210+ */
5211+ dwc_otg_halt_status_e halt_status;
5212+
5213+ /*
5214+ * Split settings for the host channel
5215+ */
5216+ uint8_t do_split; /**< Enable split for the channel */
5217+ uint8_t complete_split; /**< Enable complete split */
5218+ uint8_t hub_addr; /**< Address of high speed hub */
5219+
5220+ uint8_t port_addr; /**< Port of the low/full speed device */
5221+ /** Split transaction position
5222+ * One of the following values:
5223+ * - DWC_HCSPLIT_XACTPOS_MID
5224+ * - DWC_HCSPLIT_XACTPOS_BEGIN
5225+ * - DWC_HCSPLIT_XACTPOS_END
5226+ * - DWC_HCSPLIT_XACTPOS_ALL */
5227+ uint8_t xact_pos;
5228+
5229+ /** Set when the host channel does a short read. */
5230+ uint8_t short_read;
5231+
5232+ /**
5233+ * Number of requests issued for this channel since it was assigned to
5234+ * the current transfer (not counting PINGs).
5235+ */
5236+ uint8_t requests;
5237+
5238+ /**
5239+ * Queue Head for the transfer being processed by this channel.
5240+ */
5241+ struct dwc_otg_qh *qh;
5242+
5243+ /** @} */
5244+
5245+ /** Entry in list of host channels. */
5246+ struct list_head hc_list_entry;
5247+} dwc_hc_t;
5248+
5249+/**
5250+ * The following parameters may be specified when starting the module. These
5251+ * parameters define how the DWC_otg controller should be configured.
5252+ * Parameter values are passed to the CIL initialization function
5253+ * dwc_otg_cil_init.
5254+ */
5255+typedef struct dwc_otg_core_params
5256+{
5257+ int32_t opt;
5258+#define dwc_param_opt_default 1
5259+
5260+ /**
5261+ * Specifies the OTG capabilities. The driver will automatically
5262+ * detect the value for this parameter if none is specified.
5263+ * 0 - HNP and SRP capable (default)
5264+ * 1 - SRP Only capable
5265+ * 2 - No HNP/SRP capable
5266+ */
5267+ int32_t otg_cap;
5268+#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
5269+#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
5270+#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
5271+//#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
5272+#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE
5273+
5274+ /**
5275+ * Specifies whether to use slave or DMA mode for accessing the data
5276+ * FIFOs. The driver will automatically detect the value for this
5277+ * parameter if none is specified.
5278+ * 0 - Slave
5279+ * 1 - DMA (default, if available)
5280+ */
5281+ int32_t dma_enable;
5282+#define dwc_param_dma_enable_default 1
5283+
5284+ /**
5285+ * When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data
5286+ * FIFOs in device mode. The driver will automatically detect the value for this
5287+ * parameter if none is specified.
5288+ * 0 - address DMA
5289+ * 1 - DMA Descriptor(default, if available)
5290+ */
5291+ int32_t dma_desc_enable;
5292+#define dwc_param_dma_desc_enable_default 0
5293+ /** The DMA Burst size (applicable only for External DMA
5294+ * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
5295+ */
5296+ int32_t dma_burst_size; /* Translate this to GAHBCFG values */
5297+//#define dwc_param_dma_burst_size_default 32
5298+#define dwc_param_dma_burst_size_default 1
5299+
5300+ /**
5301+ * Specifies the maximum speed of operation in host and device mode.
5302+ * The actual speed depends on the speed of the attached device and
5303+ * the value of phy_type. The actual speed depends on the speed of the
5304+ * attached device.
5305+ * 0 - High Speed (default)
5306+ * 1 - Full Speed
5307+ */
5308+ int32_t speed;
5309+#define dwc_param_speed_default 0
5310+#define DWC_SPEED_PARAM_HIGH 0
5311+#define DWC_SPEED_PARAM_FULL 1
5312+
5313+ /** Specifies whether low power mode is supported when attached
5314+ * to a Full Speed or Low Speed device in host mode.
5315+ * 0 - Don't support low power mode (default)
5316+ * 1 - Support low power mode
5317+ */
5318+ int32_t host_support_fs_ls_low_power;
5319+#define dwc_param_host_support_fs_ls_low_power_default 0
5320+
5321+ /** Specifies the PHY clock rate in low power mode when connected to a
5322+ * Low Speed device in host mode. This parameter is applicable only if
5323+ * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
5324+ * then defaults to 6 MHZ otherwise 48 MHZ.
5325+ *
5326+ * 0 - 48 MHz
5327+ * 1 - 6 MHz
5328+ */
5329+ int32_t host_ls_low_power_phy_clk;
5330+#define dwc_param_host_ls_low_power_phy_clk_default 0
5331+#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
5332+#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
5333+
5334+ /**
5335+ * 0 - Use cC FIFO size parameters
5336+ * 1 - Allow dynamic FIFO sizing (default)
5337+ */
5338+ int32_t enable_dynamic_fifo;
5339+#define dwc_param_enable_dynamic_fifo_default 1
5340+
5341+ /** Total number of 4-byte words in the data FIFO memory. This
5342+ * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
5343+ * Tx FIFOs.
5344+ * 32 to 32768 (default 8192)
5345+ * Note: The total FIFO memory depth in the FPGA configuration is 8192.
5346+ */
5347+ int32_t data_fifo_size;
5348+#define dwc_param_data_fifo_size_default 8192
5349+
5350+ /** Number of 4-byte words in the Rx FIFO in device mode when dynamic
5351+ * FIFO sizing is enabled.
5352+ * 16 to 32768 (default 1064)
5353+ */
5354+ int32_t dev_rx_fifo_size;
5355+//#define dwc_param_dev_rx_fifo_size_default 1064
5356+#define dwc_param_dev_rx_fifo_size_default 0x100
5357+
5358+ /**
5359+ * Specifies whether dedicated transmit FIFOs are
5360+ * enabled for non periodic IN endpoints in device mode
5361+ * 0 - No
5362+ * 1 - Yes
5363+ */
5364+ int32_t en_multiple_tx_fifo;
5365+#define dwc_param_en_multiple_tx_fifo_default 1
5366+
5367+ /** Number of 4-byte words in each of the Tx FIFOs in device
5368+ * mode when dynamic FIFO sizing is enabled.
5369+ * 4 to 768 (default 256)
5370+ */
5371+ uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
5372+//#define dwc_param_dev_tx_fifo_size_default 256
5373+#define dwc_param_dev_tx_fifo_size_default 0x80
5374+
5375+ /** Number of 4-byte words in the non-periodic Tx FIFO in device mode
5376+ * when dynamic FIFO sizing is enabled.
5377+ * 16 to 32768 (default 1024)
5378+ */
5379+ int32_t dev_nperio_tx_fifo_size;
5380+//#define dwc_param_dev_nperio_tx_fifo_size_default 1024
5381+#define dwc_param_dev_nperio_tx_fifo_size_default 0x80
5382+
5383+ /** Number of 4-byte words in each of the periodic Tx FIFOs in device
5384+ * mode when dynamic FIFO sizing is enabled.
5385+ * 4 to 768 (default 256)
5386+ */
5387+ uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
5388+//#define dwc_param_dev_perio_tx_fifo_size_default 256
5389+#define dwc_param_dev_perio_tx_fifo_size_default 0x80
5390+
5391+ /** Number of 4-byte words in the Rx FIFO in host mode when dynamic
5392+ * FIFO sizing is enabled.
5393+ * 16 to 32768 (default 1024)
5394+ */
5395+ int32_t host_rx_fifo_size;
5396+//#define dwc_param_host_rx_fifo_size_default 1024
5397+#define dwc_param_host_rx_fifo_size_default 0x292
5398+
5399+ /** Number of 4-byte words in the non-periodic Tx FIFO in host mode
5400+ * when Dynamic FIFO sizing is enabled in the core.
5401+ * 16 to 32768 (default 1024)
5402+ */
5403+ int32_t host_nperio_tx_fifo_size;
5404+//#define dwc_param_host_nperio_tx_fifo_size_default 1024
5405+//#define dwc_param_host_nperio_tx_fifo_size_default 0x292
5406+#define dwc_param_host_nperio_tx_fifo_size_default 0x80
5407+
5408+ /** Number of 4-byte words in the host periodic Tx FIFO when dynamic
5409+ * FIFO sizing is enabled.
5410+ * 16 to 32768 (default 1024)
5411+ */
5412+ int32_t host_perio_tx_fifo_size;
5413+//#define dwc_param_host_perio_tx_fifo_size_default 1024
5414+#define dwc_param_host_perio_tx_fifo_size_default 0x292
5415+
5416+ /** The maximum transfer size supported in bytes.
5417+ * 2047 to 65,535 (default 65,535)
5418+ */
5419+ int32_t max_transfer_size;
5420+#define dwc_param_max_transfer_size_default 65535
5421+
5422+ /** The maximum number of packets in a transfer.
5423+ * 15 to 511 (default 511)
5424+ */
5425+ int32_t max_packet_count;
5426+#define dwc_param_max_packet_count_default 511
5427+
5428+ /** The number of host channel registers to use.
5429+ * 1 to 16 (default 12)
5430+ * Note: The FPGA configuration supports a maximum of 12 host channels.
5431+ */
5432+ int32_t host_channels;
5433+//#define dwc_param_host_channels_default 12
5434+#define dwc_param_host_channels_default 16
5435+
5436+ /** The number of endpoints in addition to EP0 available for device
5437+ * mode operations.
5438+ * 1 to 15 (default 6 IN and OUT)
5439+ * Note: The FPGA configuration supports a maximum of 6 IN and OUT
5440+ * endpoints in addition to EP0.
5441+ */
5442+ int32_t dev_endpoints;
5443+//#define dwc_param_dev_endpoints_default 6
5444+#define dwc_param_dev_endpoints_default 8
5445+
5446+ /**
5447+ * Specifies the type of PHY interface to use. By default, the driver
5448+ * will automatically detect the phy_type.
5449+ *
5450+ * 0 - Full Speed PHY
5451+ * 1 - UTMI+ (default)
5452+ * 2 - ULPI
5453+ */
5454+ int32_t phy_type;
5455+#define DWC_PHY_TYPE_PARAM_FS 0
5456+#define DWC_PHY_TYPE_PARAM_UTMI 1
5457+#define DWC_PHY_TYPE_PARAM_ULPI 2
5458+#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
5459+
5460+ /**
5461+ * Specifies the UTMI+ Data Width. This parameter is
5462+ * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
5463+ * PHY_TYPE, this parameter indicates the data width between
5464+ * the MAC and the ULPI Wrapper.) Also, this parameter is
5465+ * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
5466+ * to "8 and 16 bits", meaning that the core has been
5467+ * configured to work at either data path width.
5468+ *
5469+ * 8 or 16 bits (default 16)
5470+ */
5471+ int32_t phy_utmi_width;
5472+#define dwc_param_phy_utmi_width_default 16
5473+
5474+ /**
5475+ * Specifies whether the ULPI operates at double or single
5476+ * data rate. This parameter is only applicable if PHY_TYPE is
5477+ * ULPI.
5478+ *
5479+ * 0 - single data rate ULPI interface with 8 bit wide data
5480+ * bus (default)
5481+ * 1 - double data rate ULPI interface with 4 bit wide data
5482+ * bus
5483+ */
5484+ int32_t phy_ulpi_ddr;
5485+#define dwc_param_phy_ulpi_ddr_default 0
5486+
5487+ /**
5488+ * Specifies whether to use the internal or external supply to
5489+ * drive the vbus with a ULPI phy.
5490+ */
5491+ int32_t phy_ulpi_ext_vbus;
5492+#define DWC_PHY_ULPI_INTERNAL_VBUS 0
5493+#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
5494+#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
5495+
5496+ /**
5497+ * Specifies whether to use the I2Cinterface for full speed PHY. This
5498+ * parameter is only applicable if PHY_TYPE is FS.
5499+ * 0 - No (default)
5500+ * 1 - Yes
5501+ */
5502+ int32_t i2c_enable;
5503+#define dwc_param_i2c_enable_default 0
5504+
5505+ int32_t ulpi_fs_ls;
5506+#define dwc_param_ulpi_fs_ls_default 0
5507+
5508+ int32_t ts_dline;
5509+#define dwc_param_ts_dline_default 0
5510+
5511+ /** Thresholding enable flag-
5512+ * bit 0 - enable non-ISO Tx thresholding
5513+ * bit 1 - enable ISO Tx thresholding
5514+ * bit 2 - enable Rx thresholding
5515+ */
5516+ uint32_t thr_ctl;
5517+#define dwc_param_thr_ctl_default 0
5518+
5519+ /** Thresholding length for Tx
5520+ * FIFOs in 32 bit DWORDs
5521+ */
5522+ uint32_t tx_thr_length;
5523+#define dwc_param_tx_thr_length_default 64
5524+
5525+ /** Thresholding length for Rx
5526+ * FIFOs in 32 bit DWORDs
5527+ */
5528+ uint32_t rx_thr_length;
5529+#define dwc_param_rx_thr_length_default 64
5530+
5531+ /** Per Transfer Interrupt
5532+ * mode enable flag
5533+ * 1 - Enabled
5534+ * 0 - Disabled
5535+ */
5536+ uint32_t pti_enable;
5537+#define dwc_param_pti_enable_default 0
5538+
5539+ /** Molti Processor Interrupt
5540+ * mode enable flag
5541+ * 1 - Enabled
5542+ * 0 - Disabled
5543+ */
5544+ uint32_t mpi_enable;
5545+#define dwc_param_mpi_enable_default 0
5546+
5547+} dwc_otg_core_params_t;
5548+
5549+#ifdef DEBUG
5550+struct dwc_otg_core_if;
5551+typedef struct hc_xfer_info
5552+{
5553+ struct dwc_otg_core_if *core_if;
5554+ dwc_hc_t *hc;
5555+} hc_xfer_info_t;
5556+#endif
5557+
5558+/**
5559+ * The <code>dwc_otg_core_if</code> structure contains information needed to manage
5560+ * the DWC_otg controller acting in either host or device mode. It
5561+ * represents the programming view of the controller as a whole.
5562+ */
5563+typedef struct dwc_otg_core_if
5564+{
5565+ /** Parameters that define how the core should be configured.*/
5566+ dwc_otg_core_params_t *core_params;
5567+
5568+ /** Core Global registers starting at offset 000h. */
5569+ dwc_otg_core_global_regs_t *core_global_regs;
5570+
5571+ /** Device-specific information */
5572+ dwc_otg_dev_if_t *dev_if;
5573+ /** Host-specific information */
5574+ dwc_otg_host_if_t *host_if;
5575+
5576+ /** Value from SNPSID register */
5577+ uint32_t snpsid;
5578+
5579+ /*
5580+ * Set to 1 if the core PHY interface bits in USBCFG have been
5581+ * initialized.
5582+ */
5583+ uint8_t phy_init_done;
5584+
5585+ /*
5586+ * SRP Success flag, set by srp success interrupt in FS I2C mode
5587+ */
5588+ uint8_t srp_success;
5589+ uint8_t srp_timer_started;
5590+
5591+ /* Common configuration information */
5592+ /** Power and Clock Gating Control Register */
5593+ volatile uint32_t *pcgcctl;
5594+#define DWC_OTG_PCGCCTL_OFFSET 0xE00
5595+
5596+ /** Push/pop addresses for endpoints or host channels.*/
5597+ uint32_t *data_fifo[MAX_EPS_CHANNELS];
5598+#define DWC_OTG_DATA_FIFO_OFFSET 0x1000
5599+#define DWC_OTG_DATA_FIFO_SIZE 0x1000
5600+
5601+ /** Total RAM for FIFOs (Bytes) */
5602+ uint16_t total_fifo_size;
5603+ /** Size of Rx FIFO (Bytes) */
5604+ uint16_t rx_fifo_size;
5605+ /** Size of Non-periodic Tx FIFO (Bytes) */
5606+ uint16_t nperio_tx_fifo_size;
5607+
5608+
5609+ /** 1 if DMA is enabled, 0 otherwise. */
5610+ uint8_t dma_enable;
5611+
5612+ /** 1 if Descriptor DMA mode is enabled, 0 otherwise. */
5613+ uint8_t dma_desc_enable;
5614+
5615+ /** 1 if PTI Enhancement mode is enabled, 0 otherwise. */
5616+ uint8_t pti_enh_enable;
5617+
5618+ /** 1 if MPI Enhancement mode is enabled, 0 otherwise. */
5619+ uint8_t multiproc_int_enable;
5620+
5621+ /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */
5622+ uint8_t en_multiple_tx_fifo;
5623+
5624+ /** Set to 1 if multiple packets of a high-bandwidth transfer is in
5625+ * process of being queued */
5626+ uint8_t queuing_high_bandwidth;
5627+
5628+ /** Hardware Configuration -- stored here for convenience.*/
5629+ hwcfg1_data_t hwcfg1;
5630+ hwcfg2_data_t hwcfg2;
5631+ hwcfg3_data_t hwcfg3;
5632+ hwcfg4_data_t hwcfg4;
5633+
5634+ /** Host and Device Configuration -- stored here for convenience.*/
5635+ hcfg_data_t hcfg;
5636+ dcfg_data_t dcfg;
5637+
5638+ /** The operational State, during transations
5639+ * (a_host>>a_peripherial and b_device=>b_host) this may not
5640+ * match the core but allows the software to determine
5641+ * transitions.
5642+ */
5643+ uint8_t op_state;
5644+
5645+ /**
5646+ * Set to 1 if the HCD needs to be restarted on a session request
5647+ * interrupt. This is required if no connector ID status change has
5648+ * occurred since the HCD was last disconnected.
5649+ */
5650+ uint8_t restart_hcd_on_session_req;
5651+
5652+ /** HCD callbacks */
5653+ /** A-Device is a_host */
5654+#define A_HOST (1)
5655+ /** A-Device is a_suspend */
5656+#define A_SUSPEND (2)
5657+ /** A-Device is a_peripherial */
5658+#define A_PERIPHERAL (3)
5659+ /** B-Device is operating as a Peripheral. */
5660+#define B_PERIPHERAL (4)
5661+ /** B-Device is operating as a Host. */
5662+#define B_HOST (5)
5663+
5664+ /** HCD callbacks */
5665+ struct dwc_otg_cil_callbacks *hcd_cb;
5666+ /** PCD callbacks */
5667+ struct dwc_otg_cil_callbacks *pcd_cb;
5668+
5669+ /** Device mode Periodic Tx FIFO Mask */
5670+ uint32_t p_tx_msk;
5671+ /** Device mode Periodic Tx FIFO Mask */
5672+ uint32_t tx_msk;
5673+
5674+ /** Workqueue object used for handling several interrupts */
5675+ struct workqueue_struct *wq_otg;
5676+
5677+ /** Work object used for handling "Connector ID Status Change" Interrupt */
5678+ struct work_struct w_conn_id;
5679+
5680+ /** Work object used for handling "Wakeup Detected" Interrupt */
5681+ struct delayed_work w_wkp;
5682+
5683+#ifdef DEBUG
5684+ uint32_t start_hcchar_val[MAX_EPS_CHANNELS];
5685+
5686+ hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS];
5687+ struct timer_list hc_xfer_timer[MAX_EPS_CHANNELS];
5688+
5689+ uint32_t hfnum_7_samples;
5690+ uint64_t hfnum_7_frrem_accum;
5691+ uint32_t hfnum_0_samples;
5692+ uint64_t hfnum_0_frrem_accum;
5693+ uint32_t hfnum_other_samples;
5694+ uint64_t hfnum_other_frrem_accum;
5695+#endif
5696+
5697+
5698+} dwc_otg_core_if_t;
5699+
5700+/*We must clear S3C24XX_EINTPEND external interrupt register
5701+ * because after clearing in this register trigerred IRQ from
5702+ * H/W core in kernel interrupt can be occured again before OTG
5703+ * handlers clear all IRQ sources of Core registers because of
5704+ * timing latencies and Low Level IRQ Type.
5705+ */
5706+
5707+#ifdef CONFIG_MACH_IPMATE
5708+#define S3C2410X_CLEAR_EINTPEND() \
5709+do { \
5710+ if (!dwc_otg_read_core_intr(core_if)) { \
5711+ __raw_writel(1UL << 11,S3C24XX_EINTPEND); \
5712+ } \
5713+} while (0)
5714+#else
5715+#define S3C2410X_CLEAR_EINTPEND() do { } while (0)
5716+#endif
5717+
5718+/*
5719+ * The following functions are functions for works
5720+ * using during handling some interrupts
5721+ */
5722+extern void w_conn_id_status_change(struct work_struct *p);
5723+extern void w_wakeup_detected(struct work_struct *p);
5724+
5725+
5726+/*
5727+ * The following functions support initialization of the CIL driver component
5728+ * and the DWC_otg controller.
5729+ */
5730+extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *_reg_base_addr,
5731+ dwc_otg_core_params_t *_core_params);
5732+extern void dwc_otg_cil_remove(dwc_otg_core_if_t *_core_if);
5733+extern void dwc_otg_core_init(dwc_otg_core_if_t *_core_if);
5734+extern void dwc_otg_core_host_init(dwc_otg_core_if_t *_core_if);
5735+extern void dwc_otg_core_dev_init(dwc_otg_core_if_t *_core_if);
5736+extern void dwc_otg_enable_global_interrupts( dwc_otg_core_if_t *_core_if );
5737+extern void dwc_otg_disable_global_interrupts( dwc_otg_core_if_t *_core_if );
5738+
5739+/** @name Device CIL Functions
5740+ * The following functions support managing the DWC_otg controller in device
5741+ * mode.
5742+ */
5743+/**@{*/
5744+extern void dwc_otg_wakeup(dwc_otg_core_if_t *_core_if);
5745+extern void dwc_otg_read_setup_packet (dwc_otg_core_if_t *_core_if, uint32_t *_dest);
5746+extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *_core_if);
5747+extern void dwc_otg_ep0_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
5748+extern void dwc_otg_ep_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
5749+extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
5750+extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
5751+extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
5752+extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
5753+extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
5754+extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma);
5755+extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
5756+extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
5757+extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *_core_if);
5758+extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *_core_if);
5759+extern void dwc_otg_dump_spram(dwc_otg_core_if_t *_core_if);
5760+#ifdef DWC_EN_ISOC
5761+extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep);
5762+extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep);
5763+#endif //DWC_EN_ISOC
5764+/**@}*/
5765+
5766+/** @name Host CIL Functions
5767+ * The following functions support managing the DWC_otg controller in host
5768+ * mode.
5769+ */
5770+/**@{*/
5771+extern void dwc_otg_hc_init(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
5772+extern void dwc_otg_hc_halt(dwc_otg_core_if_t *_core_if,
5773+ dwc_hc_t *_hc,
5774+ dwc_otg_halt_status_e _halt_status);
5775+extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
5776+extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
5777+extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
5778+extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
5779+extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
5780+extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *_core_if);
5781+extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *_core_if);
5782+
5783+/**
5784+ * This function Reads HPRT0 in preparation to modify. It keeps the
5785+ * WC bits 0 so that if they are read as 1, they won't clear when you
5786+ * write it back
5787+ */
5788+static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t *_core_if)
5789+{
5790+ hprt0_data_t hprt0;
5791+ hprt0.d32 = dwc_read_reg32(_core_if->host_if->hprt0);
5792+ hprt0.b.prtena = 0;
5793+ hprt0.b.prtconndet = 0;
5794+ hprt0.b.prtenchng = 0;
5795+ hprt0.b.prtovrcurrchng = 0;
5796+ return hprt0.d32;
5797+}
5798+
5799+extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t *_core_if);
5800+/**@}*/
5801+
5802+/** @name Common CIL Functions
5803+ * The following functions support managing the DWC_otg controller in either
5804+ * device or host mode.
5805+ */
5806+/**@{*/
5807+
5808+extern void dwc_otg_read_packet(dwc_otg_core_if_t *core_if,
5809+ uint8_t *dest,
5810+ uint16_t bytes);
5811+
5812+extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t *_core_if);
5813+
5814+extern void dwc_otg_flush_tx_fifo( dwc_otg_core_if_t *_core_if,
5815+ const int _num );
5816+extern void dwc_otg_flush_rx_fifo( dwc_otg_core_if_t *_core_if );
5817+extern void dwc_otg_core_reset( dwc_otg_core_if_t *_core_if );
5818+
5819+extern dwc_otg_dma_desc_t* dwc_otg_ep_alloc_desc_chain(uint32_t * dma_desc_addr, uint32_t count);
5820+extern void dwc_otg_ep_free_desc_chain(dwc_otg_dma_desc_t* desc_addr, uint32_t dma_desc_addr, uint32_t count);
5821+
5822+/**
5823+ * This function returns the Core Interrupt register.
5824+ */
5825+static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t *_core_if)
5826+{
5827+ return (dwc_read_reg32(&_core_if->core_global_regs->gintsts) &
5828+ dwc_read_reg32(&_core_if->core_global_regs->gintmsk));
5829+}
5830+
5831+/**
5832+ * This function returns the OTG Interrupt register.
5833+ */
5834+static inline uint32_t dwc_otg_read_otg_intr (dwc_otg_core_if_t *_core_if)
5835+{
5836+ return (dwc_read_reg32 (&_core_if->core_global_regs->gotgint));
5837+}
5838+
5839+/**
5840+ * This function reads the Device All Endpoints Interrupt register and
5841+ * returns the IN endpoint interrupt bits.
5842+ */
5843+static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *core_if)
5844+{
5845+ uint32_t v;
5846+
5847+ if(core_if->multiproc_int_enable) {
5848+ v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachint) &
5849+ dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachintmsk);
5850+ } else {
5851+ v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) &
5852+ dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk);
5853+ }
5854+ return (v & 0xffff);
5855+
5856+}
5857+
5858+/**
5859+ * This function reads the Device All Endpoints Interrupt register and
5860+ * returns the OUT endpoint interrupt bits.
5861+ */
5862+static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *core_if)
5863+{
5864+ uint32_t v;
5865+
5866+ if(core_if->multiproc_int_enable) {
5867+ v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachint) &
5868+ dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachintmsk);
5869+ } else {
5870+ v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) &
5871+ dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk);
5872+ }
5873+
5874+ return ((v & 0xffff0000) >> 16);
5875+}
5876+
5877+/**
5878+ * This function returns the Device IN EP Interrupt register
5879+ */
5880+static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t *core_if,
5881+ dwc_ep_t *ep)
5882+{
5883+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
5884+ uint32_t v, msk, emp;
5885+
5886+ if(core_if->multiproc_int_enable) {
5887+ msk = dwc_read_reg32(&dev_if->dev_global_regs->diepeachintmsk[ep->num]);
5888+ emp = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk);
5889+ msk |= ((emp >> ep->num) & 0x1) << 7;
5890+ v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
5891+ } else {
5892+ msk = dwc_read_reg32(&dev_if->dev_global_regs->diepmsk);
5893+ emp = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk);
5894+ msk |= ((emp >> ep->num) & 0x1) << 7;
5895+ v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
5896+ }
5897+
5898+
5899+ return v;
5900+}
5901+/**
5902+ * This function returns the Device OUT EP Interrupt register
5903+ */
5904+static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *_core_if,
5905+ dwc_ep_t *_ep)
5906+{
5907+ dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
5908+ uint32_t v;
5909+ doepmsk_data_t msk = { .d32 = 0 };
5910+
5911+ if(_core_if->multiproc_int_enable) {
5912+ msk.d32 = dwc_read_reg32(&dev_if->dev_global_regs->doepeachintmsk[_ep->num]);
5913+ if(_core_if->pti_enh_enable) {
5914+ msk.b.pktdrpsts = 1;
5915+ }
5916+ v = dwc_read_reg32( &dev_if->out_ep_regs[_ep->num]->doepint) & msk.d32;
5917+ } else {
5918+ msk.d32 = dwc_read_reg32(&dev_if->dev_global_regs->doepmsk);
5919+ if(_core_if->pti_enh_enable) {
5920+ msk.b.pktdrpsts = 1;
5921+ }
5922+ v = dwc_read_reg32( &dev_if->out_ep_regs[_ep->num]->doepint) & msk.d32;
5923+ }
5924+ return v;
5925+}
5926+
5927+/**
5928+ * This function returns the Host All Channel Interrupt register
5929+ */
5930+static inline uint32_t dwc_otg_read_host_all_channels_intr (dwc_otg_core_if_t *_core_if)
5931+{
5932+ return (dwc_read_reg32 (&_core_if->host_if->host_global_regs->haint));
5933+}
5934+
5935+static inline uint32_t dwc_otg_read_host_channel_intr (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
5936+{
5937+ return (dwc_read_reg32 (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint));
5938+}
5939+
5940+
5941+/**
5942+ * This function returns the mode of the operation, host or device.
5943+ *
5944+ * @return 0 - Device Mode, 1 - Host Mode
5945+ */
5946+static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t *_core_if)
5947+{
5948+ return (dwc_read_reg32( &_core_if->core_global_regs->gintsts ) & 0x1);
5949+}
5950+
5951+static inline uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t *_core_if)
5952+{
5953+ return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
5954+}
5955+static inline uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t *_core_if)
5956+{
5957+ return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
5958+}
5959+
5960+extern int32_t dwc_otg_handle_common_intr( dwc_otg_core_if_t *_core_if );
5961+
5962+
5963+/**@}*/
5964+
5965+/**
5966+ * DWC_otg CIL callback structure. This structure allows the HCD and
5967+ * PCD to register functions used for starting and stopping the PCD
5968+ * and HCD for role change on for a DRD.
5969+ */
5970+typedef struct dwc_otg_cil_callbacks
5971+{
5972+ /** Start function for role change */
5973+ int (*start) (void *_p);
5974+ /** Stop Function for role change */
5975+ int (*stop) (void *_p);
5976+ /** Disconnect Function for role change */
5977+ int (*disconnect) (void *_p);
5978+ /** Resume/Remote wakeup Function */
5979+ int (*resume_wakeup) (void *_p);
5980+ /** Suspend function */
5981+ int (*suspend) (void *_p);
5982+ /** Session Start (SRP) */
5983+ int (*session_start) (void *_p);
5984+ /** Pointer passed to start() and stop() */
5985+ void *p;
5986+} dwc_otg_cil_callbacks_t;
5987+
5988+extern void dwc_otg_cil_register_pcd_callbacks( dwc_otg_core_if_t *_core_if,
5989+ dwc_otg_cil_callbacks_t *_cb,
5990+ void *_p);
5991+extern void dwc_otg_cil_register_hcd_callbacks( dwc_otg_core_if_t *_core_if,
5992+ dwc_otg_cil_callbacks_t *_cb,
5993+ void *_p);
5994+#ifndef warn
5995+#define warn printk
5996+#endif
5997+
5998+#endif
5999+
6000--- /dev/null
6001+++ b/drivers/usb/dwc/otg_cil_intr.c
6002@@ -0,0 +1,852 @@
6003+/* ==========================================================================
6004+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $
6005+ * $Revision: #10 $
6006+ * $Date: 2008/07/16 $
6007+ * $Change: 1065567 $
6008+ *
6009+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
6010+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
6011+ * otherwise expressly agreed to in writing between Synopsys and you.
6012+ *
6013+ * The Software IS NOT an item of Licensed Software or Licensed Product under
6014+ * any End User Software License Agreement or Agreement for Licensed Product
6015+ * with Synopsys or any supplement thereto. You are permitted to use and
6016+ * redistribute this Software in source and binary forms, with or without
6017+ * modification, provided that redistributions of source code must retain this
6018+ * notice. You may not view, use, disclose, copy or distribute this file or
6019+ * any information contained herein except pursuant to this license grant from
6020+ * Synopsys. If you do not agree with this notice, including the disclaimer
6021+ * below, then you are not authorized to use the Software.
6022+ *
6023+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
6024+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
6025+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
6026+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
6027+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
6028+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
6029+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
6030+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
6031+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
6032+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
6033+ * DAMAGE.
6034+ * ========================================================================== */
6035+
6036+/** @file
6037+ *
6038+ * The Core Interface Layer provides basic services for accessing and
6039+ * managing the DWC_otg hardware. These services are used by both the
6040+ * Host Controller Driver and the Peripheral Controller Driver.
6041+ *
6042+ * This file contains the Common Interrupt handlers.
6043+ */
6044+#include "otg_plat.h"
6045+#include "otg_regs.h"
6046+#include "otg_cil.h"
6047+#include "otg_pcd.h"
6048+
6049+#ifdef DEBUG
6050+inline const char *op_state_str(dwc_otg_core_if_t *core_if)
6051+{
6052+ return (core_if->op_state==A_HOST?"a_host":
6053+ (core_if->op_state==A_SUSPEND?"a_suspend":
6054+ (core_if->op_state==A_PERIPHERAL?"a_peripheral":
6055+ (core_if->op_state==B_PERIPHERAL?"b_peripheral":
6056+ (core_if->op_state==B_HOST?"b_host":
6057+ "unknown")))));
6058+}
6059+#endif
6060+
6061+/** This function will log a debug message
6062+ *
6063+ * @param core_if Programming view of DWC_otg controller.
6064+ */
6065+int32_t dwc_otg_handle_mode_mismatch_intr (dwc_otg_core_if_t *core_if)
6066+{
6067+ gintsts_data_t gintsts;
6068+ DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n",
6069+ dwc_otg_mode(core_if) ? "Host" : "Device");
6070+
6071+ /* Clear interrupt */
6072+ gintsts.d32 = 0;
6073+ gintsts.b.modemismatch = 1;
6074+ dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
6075+ return 1;
6076+}
6077+
6078+/** Start the HCD. Helper function for using the HCD callbacks.
6079+ *
6080+ * @param core_if Programming view of DWC_otg controller.
6081+ */
6082+static inline void hcd_start(dwc_otg_core_if_t *core_if)
6083+{
6084+ if (core_if->hcd_cb && core_if->hcd_cb->start) {
6085+ core_if->hcd_cb->start(core_if->hcd_cb->p);
6086+ }
6087+}
6088+/** Stop the HCD. Helper function for using the HCD callbacks.
6089+ *
6090+ * @param core_if Programming view of DWC_otg controller.
6091+ */
6092+static inline void hcd_stop(dwc_otg_core_if_t *core_if)
6093+{
6094+ if (core_if->hcd_cb && core_if->hcd_cb->stop) {
6095+ core_if->hcd_cb->stop(core_if->hcd_cb->p);
6096+ }
6097+}
6098+/** Disconnect the HCD. Helper function for using the HCD callbacks.
6099+ *
6100+ * @param core_if Programming view of DWC_otg controller.
6101+ */
6102+static inline void hcd_disconnect(dwc_otg_core_if_t *core_if)
6103+{
6104+ if (core_if->hcd_cb && core_if->hcd_cb->disconnect) {
6105+ core_if->hcd_cb->disconnect(core_if->hcd_cb->p);
6106+ }
6107+}
6108+/** Inform the HCD the a New Session has begun. Helper function for
6109+ * using the HCD callbacks.
6110+ *
6111+ * @param core_if Programming view of DWC_otg controller.
6112+ */
6113+static inline void hcd_session_start(dwc_otg_core_if_t *core_if)
6114+{
6115+ if (core_if->hcd_cb && core_if->hcd_cb->session_start) {
6116+ core_if->hcd_cb->session_start(core_if->hcd_cb->p);
6117+ }
6118+}
6119+
6120+/** Start the PCD. Helper function for using the PCD callbacks.
6121+ *
6122+ * @param core_if Programming view of DWC_otg controller.
6123+ */
6124+static inline void pcd_start(dwc_otg_core_if_t *core_if)
6125+{
6126+ if (core_if->pcd_cb && core_if->pcd_cb->start) {
6127+ core_if->pcd_cb->start(core_if->pcd_cb->p);
6128+ }
6129+}
6130+/** Stop the PCD. Helper function for using the PCD callbacks.
6131+ *
6132+ * @param core_if Programming view of DWC_otg controller.
6133+ */
6134+static inline void pcd_stop(dwc_otg_core_if_t *core_if)
6135+{
6136+ if (core_if->pcd_cb && core_if->pcd_cb->stop) {
6137+ core_if->pcd_cb->stop(core_if->pcd_cb->p);
6138+ }
6139+}
6140+/** Suspend the PCD. Helper function for using the PCD callbacks.
6141+ *
6142+ * @param core_if Programming view of DWC_otg controller.
6143+ */
6144+static inline void pcd_suspend(dwc_otg_core_if_t *core_if)
6145+{
6146+ if (core_if->pcd_cb && core_if->pcd_cb->suspend) {
6147+ core_if->pcd_cb->suspend(core_if->pcd_cb->p);
6148+ }
6149+}
6150+/** Resume the PCD. Helper function for using the PCD callbacks.
6151+ *
6152+ * @param core_if Programming view of DWC_otg controller.
6153+ */
6154+static inline void pcd_resume(dwc_otg_core_if_t *core_if)
6155+{
6156+ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
6157+ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
6158+ }
6159+}
6160+
6161+/**
6162+ * This function handles the OTG Interrupts. It reads the OTG
6163+ * Interrupt Register (GOTGINT) to determine what interrupt has
6164+ * occurred.
6165+ *
6166+ * @param core_if Programming view of DWC_otg controller.
6167+ */
6168+int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t *core_if)
6169+{
6170+ dwc_otg_core_global_regs_t *global_regs =
6171+ core_if->core_global_regs;
6172+ gotgint_data_t gotgint;
6173+ gotgctl_data_t gotgctl;
6174+ gintmsk_data_t gintmsk;
6175+ gotgint.d32 = dwc_read_reg32(&global_regs->gotgint);
6176+ gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
6177+ DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32,
6178+ op_state_str(core_if));
6179+ //DWC_DEBUGPL(DBG_CIL, "gotgctl=%08x\n", gotgctl.d32);
6180+
6181+ if (gotgint.b.sesenddet) {
6182+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
6183+ "Session End Detected++ (%s)\n",
6184+ op_state_str(core_if));
6185+ gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
6186+
6187+ if (core_if->op_state == B_HOST) {
6188+
6189+ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)core_if->pcd_cb->p;
6190+ if(unlikely(!pcd)) {
6191+ DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
6192+ BUG();
6193+ }
6194+ SPIN_LOCK(&pcd->lock);
6195+
6196+ pcd_start(core_if);
6197+
6198+ SPIN_UNLOCK(&pcd->lock);
6199+ core_if->op_state = B_PERIPHERAL;
6200+ } else {
6201+ dwc_otg_pcd_t *pcd;
6202+
6203+ /* If not B_HOST and Device HNP still set. HNP
6204+ * Did not succeed!*/
6205+ if (gotgctl.b.devhnpen) {
6206+ DWC_DEBUGPL(DBG_ANY, "Session End Detected\n");
6207+ DWC_ERROR("Device Not Connected/Responding!\n");
6208+ }
6209+
6210+ /* If Session End Detected the B-Cable has
6211+ * been disconnected. */
6212+ /* Reset PCD and Gadget driver to a
6213+ * clean state. */
6214+
6215+ pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
6216+ if(unlikely(!pcd)) {
6217+ DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
6218+ BUG();
6219+ }
6220+ SPIN_LOCK(&pcd->lock);
6221+
6222+ pcd_stop(core_if);
6223+
6224+ SPIN_UNLOCK(&pcd->lock);
6225+ }
6226+ gotgctl.d32 = 0;
6227+ gotgctl.b.devhnpen = 1;
6228+ dwc_modify_reg32(&global_regs->gotgctl,
6229+ gotgctl.d32, 0);
6230+ }
6231+ if (gotgint.b.sesreqsucstschng) {
6232+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
6233+ "Session Reqeust Success Status Change++\n");
6234+ gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
6235+ if (gotgctl.b.sesreqscs) {
6236+ if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
6237+ (core_if->core_params->i2c_enable)) {
6238+ core_if->srp_success = 1;
6239+ }
6240+ else {
6241+ dwc_otg_pcd_t *pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
6242+ if(unlikely(!pcd)) {
6243+ DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
6244+ BUG();
6245+ }
6246+ SPIN_LOCK(&pcd->lock);
6247+
6248+ pcd_resume(core_if);
6249+
6250+ SPIN_UNLOCK(&pcd->lock);
6251+ /* Clear Session Request */
6252+ gotgctl.d32 = 0;
6253+ gotgctl.b.sesreq = 1;
6254+ dwc_modify_reg32(&global_regs->gotgctl,
6255+ gotgctl.d32, 0);
6256+ }
6257+ }
6258+ }
6259+ if (gotgint.b.hstnegsucstschng) {
6260+ /* Print statements during the HNP interrupt handling
6261+ * can cause it to fail.*/
6262+ gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
6263+ if (gotgctl.b.hstnegscs) {
6264+ if (dwc_otg_is_host_mode(core_if)) {
6265+ dwc_otg_pcd_t *pcd;
6266+
6267+ core_if->op_state = B_HOST;
6268+ /*
6269+ * Need to disable SOF interrupt immediately.
6270+ * When switching from device to host, the PCD
6271+ * interrupt handler won't handle the
6272+ * interrupt if host mode is already set. The
6273+ * HCD interrupt handler won't get called if
6274+ * the HCD state is HALT. This means that the
6275+ * interrupt does not get handled and Linux
6276+ * complains loudly.
6277+ */
6278+ gintmsk.d32 = 0;
6279+ gintmsk.b.sofintr = 1;
6280+ dwc_modify_reg32(&global_regs->gintmsk,
6281+ gintmsk.d32, 0);
6282+
6283+ pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
6284+ if(unlikely(!pcd)) {
6285+ DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
6286+ BUG();
6287+ }
6288+ SPIN_LOCK(&pcd->lock);
6289+
6290+ pcd_stop(core_if);
6291+
6292+ SPIN_UNLOCK(&pcd->lock);
6293+ /*
6294+ * Initialize the Core for Host mode.
6295+ */
6296+ hcd_start(core_if);
6297+ core_if->op_state = B_HOST;
6298+ }
6299+ } else {
6300+ gotgctl.d32 = 0;
6301+ gotgctl.b.hnpreq = 1;
6302+ gotgctl.b.devhnpen = 1;
6303+ dwc_modify_reg32(&global_regs->gotgctl,
6304+ gotgctl.d32, 0);
6305+ DWC_DEBUGPL(DBG_ANY, "HNP Failed\n");
6306+ DWC_ERROR("Device Not Connected/Responding\n");
6307+ }
6308+ }
6309+ if (gotgint.b.hstnegdet) {
6310+ /* The disconnect interrupt is set at the same time as
6311+ * Host Negotiation Detected. During the mode
6312+ * switch all interrupts are cleared so the disconnect
6313+ * interrupt handler will not get executed.
6314+ */
6315+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
6316+ "Host Negotiation Detected++ (%s)\n",
6317+ (dwc_otg_is_host_mode(core_if)?"Host":"Device"));
6318+ if (dwc_otg_is_device_mode(core_if)){
6319+ dwc_otg_pcd_t *pcd;
6320+
6321+ DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n", core_if->op_state);
6322+ hcd_disconnect(core_if);
6323+
6324+ pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
6325+ if(unlikely(!pcd)) {
6326+ DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
6327+ BUG();
6328+ }
6329+ SPIN_LOCK(&pcd->lock);
6330+
6331+ pcd_start(core_if);
6332+
6333+ SPIN_UNLOCK(&pcd->lock);
6334+ core_if->op_state = A_PERIPHERAL;
6335+ } else {
6336+ dwc_otg_pcd_t *pcd;
6337+
6338+ /*
6339+ * Need to disable SOF interrupt immediately. When
6340+ * switching from device to host, the PCD interrupt
6341+ * handler won't handle the interrupt if host mode is
6342+ * already set. The HCD interrupt handler won't get
6343+ * called if the HCD state is HALT. This means that
6344+ * the interrupt does not get handled and Linux
6345+ * complains loudly.
6346+ */
6347+ gintmsk.d32 = 0;
6348+ gintmsk.b.sofintr = 1;
6349+ dwc_modify_reg32(&global_regs->gintmsk,
6350+ gintmsk.d32, 0);
6351+
6352+ pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
6353+ if(unlikely(!pcd)) {
6354+ DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
6355+ BUG();
6356+ }
6357+ SPIN_LOCK(&pcd->lock);
6358+
6359+ pcd_stop(core_if);
6360+
6361+ SPIN_UNLOCK(&pcd->lock);
6362+ hcd_start(core_if);
6363+ core_if->op_state = A_HOST;
6364+ }
6365+ }
6366+ if (gotgint.b.adevtoutchng) {
6367+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
6368+ "A-Device Timeout Change++\n");
6369+ }
6370+ if (gotgint.b.debdone) {
6371+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
6372+ "Debounce Done++\n");
6373+ }
6374+
6375+ /* Clear GOTGINT */
6376+ dwc_write_reg32 (&core_if->core_global_regs->gotgint, gotgint.d32);
6377+
6378+ return 1;
6379+}
6380+
6381+
6382+void w_conn_id_status_change(struct work_struct *p)
6383+{
6384+ dwc_otg_core_if_t *core_if = container_of(p, dwc_otg_core_if_t, w_conn_id);
6385+
6386+ uint32_t count = 0;
6387+ gotgctl_data_t gotgctl = { .d32 = 0 };
6388+
6389+ gotgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
6390+ DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
6391+ DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
6392+
6393+ /* B-Device connector (Device Mode) */
6394+ if (gotgctl.b.conidsts) {
6395+ dwc_otg_pcd_t *pcd;
6396+
6397+ /* Wait for switch to device mode. */
6398+ while (!dwc_otg_is_device_mode(core_if)){
6399+ DWC_PRINT("Waiting for Peripheral Mode, Mode=%s\n",
6400+ (dwc_otg_is_host_mode(core_if)?"Host":"Peripheral"));
6401+ MDELAY(100);
6402+ if (++count > 10000) *(uint32_t*)NULL=0;
6403+ }
6404+ core_if->op_state = B_PERIPHERAL;
6405+ dwc_otg_core_init(core_if);
6406+ dwc_otg_enable_global_interrupts(core_if);
6407+
6408+ pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
6409+ if(unlikely(!pcd)) {
6410+ DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
6411+ BUG();
6412+ }
6413+ SPIN_LOCK(&pcd->lock);
6414+
6415+ pcd_start(core_if);
6416+
6417+ SPIN_UNLOCK(&pcd->lock);
6418+ } else {
6419+ /* A-Device connector (Host Mode) */
6420+ while (!dwc_otg_is_host_mode(core_if)) {
6421+ DWC_PRINT("Waiting for Host Mode, Mode=%s\n",
6422+ (dwc_otg_is_host_mode(core_if)?"Host":"Peripheral"));
6423+ MDELAY(100);
6424+ if (++count > 10000) *(uint32_t*)NULL=0;
6425+ }
6426+ core_if->op_state = A_HOST;
6427+ /*
6428+ * Initialize the Core for Host mode.
6429+ */
6430+ dwc_otg_core_init(core_if);
6431+ dwc_otg_enable_global_interrupts(core_if);
6432+ hcd_start(core_if);
6433+ }
6434+}
6435+
6436+
6437+/**
6438+ * This function handles the Connector ID Status Change Interrupt. It
6439+ * reads the OTG Interrupt Register (GOTCTL) to determine whether this
6440+ * is a Device to Host Mode transition or a Host Mode to Device
6441+ * Transition.
6442+ *
6443+ * This only occurs when the cable is connected/removed from the PHY
6444+ * connector.
6445+ *
6446+ * @param core_if Programming view of DWC_otg controller.
6447+ */
6448+int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t *core_if)
6449+{
6450+
6451+ /*
6452+ * Need to disable SOF interrupt immediately. If switching from device
6453+ * to host, the PCD interrupt handler won't handle the interrupt if
6454+ * host mode is already set. The HCD interrupt handler won't get
6455+ * called if the HCD state is HALT. This means that the interrupt does
6456+ * not get handled and Linux complains loudly.
6457+ */
6458+ gintmsk_data_t gintmsk = { .d32 = 0 };
6459+ gintsts_data_t gintsts = { .d32 = 0 };
6460+
6461+ gintmsk.b.sofintr = 1;
6462+ dwc_modify_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
6463+
6464+ DWC_DEBUGPL(DBG_CIL, " ++Connector ID Status Change Interrupt++ (%s)\n",
6465+ (dwc_otg_is_host_mode(core_if)?"Host":"Device"));
6466+
6467+ /*
6468+ * Need to schedule a work, as there are possible DELAY function calls
6469+ */
6470+ queue_work(core_if->wq_otg, &core_if->w_conn_id);
6471+
6472+ /* Set flag and clear interrupt */
6473+ gintsts.b.conidstschng = 1;
6474+ dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
6475+
6476+ return 1;
6477+}
6478+
6479+/**
6480+ * This interrupt indicates that a device is initiating the Session
6481+ * Request Protocol to request the host to turn on bus power so a new
6482+ * session can begin. The handler responds by turning on bus power. If
6483+ * the DWC_otg controller is in low power mode, the handler brings the
6484+ * controller out of low power mode before turning on bus power.
6485+ *
6486+ * @param core_if Programming view of DWC_otg controller.
6487+ */
6488+int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t *core_if)
6489+{
6490+ hprt0_data_t hprt0;
6491+ gintsts_data_t gintsts;
6492+
6493+#ifndef DWC_HOST_ONLY
6494+ DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
6495+
6496+ if (dwc_otg_is_device_mode(core_if)) {
6497+ DWC_PRINT("SRP: Device mode\n");
6498+ } else {
6499+ DWC_PRINT("SRP: Host mode\n");
6500+
6501+ /* Turn on the port power bit. */
6502+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
6503+ hprt0.b.prtpwr = 1;
6504+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
6505+
6506+ /* Start the Connection timer. So a message can be displayed
6507+ * if connect does not occur within 10 seconds. */
6508+ hcd_session_start(core_if);
6509+ }
6510+#endif
6511+
6512+ /* Clear interrupt */
6513+ gintsts.d32 = 0;
6514+ gintsts.b.sessreqintr = 1;
6515+ dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
6516+
6517+ return 1;
6518+}
6519+
6520+
6521+void w_wakeup_detected(struct work_struct *p)
6522+{
6523+ struct delayed_work *dw = container_of(p, struct delayed_work, work);
6524+ dwc_otg_core_if_t *core_if = container_of(dw, dwc_otg_core_if_t, w_wkp);
6525+
6526+ /*
6527+ * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
6528+ * so that OPT tests pass with all PHYs).
6529+ */
6530+ hprt0_data_t hprt0 = {.d32=0};
6531+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
6532+ DWC_DEBUGPL(DBG_ANY,"Resume: HPRT0=%0x\n", hprt0.d32);
6533+// MDELAY(70);
6534+ hprt0.b.prtres = 0; /* Resume */
6535+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
6536+ DWC_DEBUGPL(DBG_ANY,"Clear Resume: HPRT0=%0x\n", dwc_read_reg32(core_if->host_if->hprt0));
6537+}
6538+/**
6539+ * This interrupt indicates that the DWC_otg controller has detected a
6540+ * resume or remote wakeup sequence. If the DWC_otg controller is in
6541+ * low power mode, the handler must brings the controller out of low
6542+ * power mode. The controller automatically begins resume
6543+ * signaling. The handler schedules a time to stop resume signaling.
6544+ */
6545+int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t *core_if)
6546+{
6547+ gintsts_data_t gintsts;
6548+
6549+ DWC_DEBUGPL(DBG_ANY, "++Resume and Remote Wakeup Detected Interrupt++\n");
6550+
6551+ if (dwc_otg_is_device_mode(core_if)) {
6552+ dctl_data_t dctl = {.d32=0};
6553+ DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
6554+ dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts));
6555+#ifdef PARTIAL_POWER_DOWN
6556+ if (core_if->hwcfg4.b.power_optimiz) {
6557+ pcgcctl_data_t power = {.d32=0};
6558+
6559+ power.d32 = dwc_read_reg32(core_if->pcgcctl);
6560+ DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n", power.d32);
6561+
6562+ power.b.stoppclk = 0;
6563+ dwc_write_reg32(core_if->pcgcctl, power.d32);
6564+
6565+ power.b.pwrclmp = 0;
6566+ dwc_write_reg32(core_if->pcgcctl, power.d32);
6567+
6568+ power.b.rstpdwnmodule = 0;
6569+ dwc_write_reg32(core_if->pcgcctl, power.d32);
6570+ }
6571+#endif
6572+ /* Clear the Remote Wakeup Signalling */
6573+ dctl.b.rmtwkupsig = 1;
6574+ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl,
6575+ dctl.d32, 0);
6576+
6577+ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
6578+ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
6579+ }
6580+
6581+ } else {
6582+ pcgcctl_data_t pcgcctl = {.d32=0};
6583+
6584+ /* Restart the Phy Clock */
6585+ pcgcctl.b.stoppclk = 1;
6586+ dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0);
6587+
6588+ queue_delayed_work(core_if->wq_otg, &core_if->w_wkp, ((70 * HZ / 1000) + 1));
6589+ }
6590+
6591+ /* Clear interrupt */
6592+ gintsts.d32 = 0;
6593+ gintsts.b.wkupintr = 1;
6594+ dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
6595+
6596+ return 1;
6597+}
6598+
6599+/**
6600+ * This interrupt indicates that a device has been disconnected from
6601+ * the root port.
6602+ */
6603+int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t *core_if)
6604+{
6605+ gintsts_data_t gintsts;
6606+
6607+ DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n",
6608+ (dwc_otg_is_host_mode(core_if)?"Host":"Device"),
6609+ op_state_str(core_if));
6610+
6611+/** @todo Consolidate this if statement. */
6612+#ifndef DWC_HOST_ONLY
6613+ if (core_if->op_state == B_HOST) {
6614+ dwc_otg_pcd_t *pcd;
6615+
6616+ /* If in device mode Disconnect and stop the HCD, then
6617+ * start the PCD. */
6618+ hcd_disconnect(core_if);
6619+
6620+ pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
6621+ if(unlikely(!pcd)) {
6622+ DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
6623+ BUG();
6624+ }
6625+ SPIN_LOCK(&pcd->lock);
6626+
6627+ pcd_start(core_if);
6628+
6629+ SPIN_UNLOCK(&pcd->lock);
6630+ core_if->op_state = B_PERIPHERAL;
6631+ } else if (dwc_otg_is_device_mode(core_if)) {
6632+ gotgctl_data_t gotgctl = { .d32 = 0 };
6633+ gotgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
6634+ if (gotgctl.b.hstsethnpen==1) {
6635+ /* Do nothing, if HNP in process the OTG
6636+ * interrupt "Host Negotiation Detected"
6637+ * interrupt will do the mode switch.
6638+ */
6639+ } else if (gotgctl.b.devhnpen == 0) {
6640+ dwc_otg_pcd_t *pcd;
6641+
6642+ /* If in device mode Disconnect and stop the HCD, then
6643+ * start the PCD. */
6644+ hcd_disconnect(core_if);
6645+
6646+ pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
6647+ if(unlikely(!pcd)) {
6648+ DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
6649+ BUG();
6650+ }
6651+ SPIN_LOCK(&pcd->lock);
6652+
6653+ pcd_start(core_if);
6654+
6655+ SPIN_UNLOCK(&pcd->lock);
6656+
6657+ core_if->op_state = B_PERIPHERAL;
6658+ } else {
6659+ DWC_DEBUGPL(DBG_ANY,"!a_peripheral && !devhnpen\n");
6660+ }
6661+ } else {
6662+ if (core_if->op_state == A_HOST) {
6663+ /* A-Cable still connected but device disconnected. */
6664+ hcd_disconnect(core_if);
6665+ }
6666+ }
6667+#endif
6668+
6669+ gintsts.d32 = 0;
6670+ gintsts.b.disconnect = 1;
6671+ dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
6672+ return 1;
6673+}
6674+/**
6675+ * This interrupt indicates that SUSPEND state has been detected on
6676+ * the USB.
6677+ *
6678+ * For HNP the USB Suspend interrupt signals the change from
6679+ * "a_peripheral" to "a_host".
6680+ *
6681+ * When power management is enabled the core will be put in low power
6682+ * mode.
6683+ */
6684+int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t *core_if)
6685+{
6686+ dsts_data_t dsts;
6687+ gintsts_data_t gintsts;
6688+
6689+ DWC_DEBUGPL(DBG_ANY,"USB SUSPEND\n");
6690+
6691+ if (dwc_otg_is_device_mode(core_if)) {
6692+ dwc_otg_pcd_t *pcd;
6693+
6694+ /* Check the Device status register to determine if the Suspend
6695+ * state is active. */
6696+ dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
6697+ DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32);
6698+ DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d "
6699+ "HWCFG4.power Optimize=%d\n",
6700+ dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz);
6701+
6702+
6703+#ifdef PARTIAL_POWER_DOWN
6704+/** @todo Add a module parameter for power management. */
6705+ if (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) {
6706+ pcgcctl_data_t power = {.d32=0};
6707+ DWC_DEBUGPL(DBG_CIL, "suspend\n");
6708+
6709+ power.b.pwrclmp = 1;
6710+ dwc_write_reg32(core_if->pcgcctl, power.d32);
6711+
6712+ power.b.rstpdwnmodule = 1;
6713+ dwc_modify_reg32(core_if->pcgcctl, 0, power.d32);
6714+
6715+ power.b.stoppclk = 1;
6716+ dwc_modify_reg32(core_if->pcgcctl, 0, power.d32);
6717+ } else {
6718+ DWC_DEBUGPL(DBG_ANY,"disconnect?\n");
6719+ }
6720+#endif
6721+ /* PCD callback for suspend. */
6722+ pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
6723+ if(unlikely(!pcd)) {
6724+ DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
6725+ BUG();
6726+ }
6727+ SPIN_LOCK(&pcd->lock);
6728+
6729+ pcd_suspend(core_if);
6730+
6731+ SPIN_UNLOCK(&pcd->lock);
6732+ } else {
6733+ if (core_if->op_state == A_PERIPHERAL) {
6734+ dwc_otg_pcd_t *pcd;
6735+
6736+ DWC_DEBUGPL(DBG_ANY,"a_peripheral->a_host\n");
6737+ /* Clear the a_peripheral flag, back to a_host. */
6738+
6739+ pcd=(dwc_otg_pcd_t *)core_if->pcd_cb->p;
6740+ if(unlikely(!pcd)) {
6741+ DWC_ERROR("%s: data structure not initialized properly, core_if->pcd_cb->p = NULL!!!",__func__);
6742+ BUG();
6743+ }
6744+ SPIN_LOCK(&pcd->lock);
6745+
6746+ pcd_stop(core_if);
6747+
6748+ SPIN_UNLOCK(&pcd->lock);
6749+
6750+ hcd_start(core_if);
6751+ core_if->op_state = A_HOST;
6752+ }
6753+ }
6754+
6755+ /* Clear interrupt */
6756+ gintsts.d32 = 0;
6757+ gintsts.b.usbsuspend = 1;
6758+ dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
6759+
6760+ return 1;
6761+}
6762+
6763+
6764+/**
6765+ * This function returns the Core Interrupt register.
6766+ */
6767+static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t *core_if)
6768+{
6769+ gintsts_data_t gintsts;
6770+ gintmsk_data_t gintmsk;
6771+ gintmsk_data_t gintmsk_common = {.d32=0};
6772+ gintmsk_common.b.wkupintr = 1;
6773+ gintmsk_common.b.sessreqintr = 1;
6774+ gintmsk_common.b.conidstschng = 1;
6775+ gintmsk_common.b.otgintr = 1;
6776+ gintmsk_common.b.modemismatch = 1;
6777+ gintmsk_common.b.disconnect = 1;
6778+ gintmsk_common.b.usbsuspend = 1;
6779+ /** @todo: The port interrupt occurs while in device
6780+ * mode. Added code to CIL to clear the interrupt for now!
6781+ */
6782+ gintmsk_common.b.portintr = 1;
6783+
6784+ gintsts.d32 = dwc_read_reg32(&core_if->core_global_regs->gintsts);
6785+ gintmsk.d32 = dwc_read_reg32(&core_if->core_global_regs->gintmsk);
6786+#ifdef DEBUG
6787+ /* if any common interrupts set */
6788+ if (gintsts.d32 & gintmsk_common.d32) {
6789+ DWC_DEBUGPL(DBG_ANY, "gintsts=%08x gintmsk=%08x\n",
6790+ gintsts.d32, gintmsk.d32);
6791+ }
6792+#endif
6793+
6794+ return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
6795+
6796+}
6797+
6798+/**
6799+ * Common interrupt handler.
6800+ *
6801+ * The common interrupts are those that occur in both Host and Device mode.
6802+ * This handler handles the following interrupts:
6803+ * - Mode Mismatch Interrupt
6804+ * - Disconnect Interrupt
6805+ * - OTG Interrupt
6806+ * - Connector ID Status Change Interrupt
6807+ * - Session Request Interrupt.
6808+ * - Resume / Remote Wakeup Detected Interrupt.
6809+ *
6810+ */
6811+int32_t dwc_otg_handle_common_intr(dwc_otg_core_if_t *core_if)
6812+{
6813+ int retval = 0;
6814+ gintsts_data_t gintsts;
6815+
6816+ gintsts.d32 = dwc_otg_read_common_intr(core_if);
6817+
6818+ if (gintsts.b.modemismatch) {
6819+ retval |= dwc_otg_handle_mode_mismatch_intr(core_if);
6820+ }
6821+ if (gintsts.b.otgintr) {
6822+ retval |= dwc_otg_handle_otg_intr(core_if);
6823+ }
6824+ if (gintsts.b.conidstschng) {
6825+ retval |= dwc_otg_handle_conn_id_status_change_intr(core_if);
6826+ }
6827+ if (gintsts.b.disconnect) {
6828+ retval |= dwc_otg_handle_disconnect_intr(core_if);
6829+ }
6830+ if (gintsts.b.sessreqintr) {
6831+ retval |= dwc_otg_handle_session_req_intr(core_if);
6832+ }
6833+ if (gintsts.b.wkupintr) {
6834+ retval |= dwc_otg_handle_wakeup_detected_intr(core_if);
6835+ }
6836+ if (gintsts.b.usbsuspend) {
6837+ retval |= dwc_otg_handle_usb_suspend_intr(core_if);
6838+ }
6839+ if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) {
6840+ /* The port interrupt occurs while in device mode with HPRT0
6841+ * Port Enable/Disable.
6842+ */
6843+ gintsts.d32 = 0;
6844+ gintsts.b.portintr = 1;
6845+ dwc_write_reg32(&core_if->core_global_regs->gintsts,
6846+ gintsts.d32);
6847+ retval |= 1;
6848+
6849+ }
6850+
6851+ S3C2410X_CLEAR_EINTPEND();
6852+
6853+ return retval;
6854+}
6855--- /dev/null
6856+++ b/drivers/usb/dwc/otg_driver.c
6857@@ -0,0 +1,965 @@
6858+/* ==========================================================================
6859+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
6860+ * $Revision: #63 $
6861+ * $Date: 2008/09/24 $
6862+ * $Change: 1101777 $
6863+ *
6864+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
6865+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
6866+ * otherwise expressly agreed to in writing between Synopsys and you.
6867+ *
6868+ * The Software IS NOT an item of Licensed Software or Licensed Product under
6869+ * any End User Software License Agreement or Agreement for Licensed Product
6870+ * with Synopsys or any supplement thereto. You are permitted to use and
6871+ * redistribute this Software in source and binary forms, with or without
6872+ * modification, provided that redistributions of source code must retain this
6873+ * notice. You may not view, use, disclose, copy or distribute this file or
6874+ * any information contained herein except pursuant to this license grant from
6875+ * Synopsys. If you do not agree with this notice, including the disclaimer
6876+ * below, then you are not authorized to use the Software.
6877+ *
6878+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
6879+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
6880+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
6881+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
6882+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
6883+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
6884+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
6885+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
6886+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
6887+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
6888+ * DAMAGE.
6889+ * ========================================================================== */
6890+
6891+/** @file
6892+ * The dwc_otg_driver module provides the initialization and cleanup entry
6893+ * points for the DWC_otg driver. This module will be dynamically installed
6894+ * after Linux is booted using the insmod command. When the module is
6895+ * installed, the dwc_otg_driver_init function is called. When the module is
6896+ * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
6897+ *
6898+ * This module also defines a data structure for the dwc_otg_driver, which is
6899+ * used in conjunction with the standard ARM lm_device structure. These
6900+ * structures allow the OTG driver to comply with the standard Linux driver
6901+ * model in which devices and drivers are registered with a bus driver. This
6902+ * has the benefit that Linux can expose attributes of the driver and device
6903+ * in its special sysfs file system. Users can then read or write files in
6904+ * this file system to perform diagnostics on the driver components or the
6905+ * device.
6906+ */
6907+
6908+#include <linux/kernel.h>
6909+#include <linux/module.h>
6910+#include <linux/moduleparam.h>
6911+#include <linux/init.h>
6912+#include <linux/device.h>
6913+#include <linux/errno.h>
6914+#include <linux/types.h>
6915+#include <linux/stat.h> /* permission constants */
6916+#include <linux/version.h>
6917+#include <linux/platform_device.h>
6918+#include <linux/io.h>
6919+#include <linux/irq.h>
6920+#include <asm/io.h>
6921+
6922+#include <asm/sizes.h>
6923+#include <mach/pm.h>
6924+
6925+#include "otg_plat.h"
6926+#include "otg_attr.h"
6927+#include "otg_driver.h"
6928+#include "otg_cil.h"
6929+#include "otg_pcd.h"
6930+#include "otg_hcd.h"
6931+
6932+#define DWC_DRIVER_VERSION "2.72a 24-JUN-2008"
6933+#define DWC_DRIVER_DESC "HS OTG USB Controller driver"
6934+
6935+static const char dwc_driver_name[] = "dwc_otg";
6936+
6937+/*-------------------------------------------------------------------------*/
6938+/* Encapsulate the module parameter settings */
6939+
6940+static dwc_otg_core_params_t dwc_otg_module_params = {
6941+ .opt = -1,
6942+ .otg_cap = -1,
6943+ .dma_enable = -1,
6944+ .dma_desc_enable = -1,
6945+ .dma_burst_size = -1,
6946+ .speed = -1,
6947+ .host_support_fs_ls_low_power = -1,
6948+ .host_ls_low_power_phy_clk = -1,
6949+ .enable_dynamic_fifo = -1,
6950+ .data_fifo_size = -1,
6951+ .dev_rx_fifo_size = -1,
6952+ .dev_nperio_tx_fifo_size = -1,
6953+ .dev_perio_tx_fifo_size = {
6954+ /* dev_perio_tx_fifo_size_1 */
6955+ -1,
6956+ -1,
6957+ -1,
6958+ -1,
6959+ -1,
6960+ -1,
6961+ -1,
6962+ -1,
6963+ -1,
6964+ -1,
6965+ -1,
6966+ -1,
6967+ -1,
6968+ -1,
6969+ -1
6970+ /* 15 */
6971+ },
6972+ .host_rx_fifo_size = -1,
6973+ .host_nperio_tx_fifo_size = -1,
6974+ .host_perio_tx_fifo_size = -1,
6975+ .max_transfer_size = -1,
6976+ .max_packet_count = -1,
6977+ .host_channels = -1,
6978+ .dev_endpoints = -1,
6979+ .phy_type = -1,
6980+ .phy_utmi_width = -1,
6981+ .phy_ulpi_ddr = -1,
6982+ .phy_ulpi_ext_vbus = -1,
6983+ .i2c_enable = -1,
6984+ .ulpi_fs_ls = -1,
6985+ .ts_dline = -1,
6986+ .en_multiple_tx_fifo = -1,
6987+ .dev_tx_fifo_size = {
6988+ /* dev_tx_fifo_size */
6989+ -1,
6990+ -1,
6991+ -1,
6992+ -1,
6993+ -1,
6994+ -1,
6995+ -1,
6996+ -1,
6997+ -1,
6998+ -1,
6999+ -1,
7000+ -1,
7001+ -1,
7002+ -1,
7003+ -1
7004+ /* 15 */
7005+ },
7006+ .thr_ctl = -1,
7007+ .tx_thr_length = -1,
7008+ .rx_thr_length = -1,
7009+ .pti_enable = -1,
7010+ .mpi_enable = -1,
7011+};
7012+
7013+/**
7014+ * Global Debug Level Mask.
7015+ */
7016+uint32_t g_dbg_lvl = 0; /* OFF */
7017+
7018+/**
7019+ * This function is called during module intialization to verify that
7020+ * the module parameters are in a valid state.
7021+ */
7022+static int check_parameters(dwc_otg_core_if_t *core_if)
7023+{
7024+ int i;
7025+ int retval = 0;
7026+
7027+/* Checks if the parameter is outside of its valid range of values */
7028+#define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \
7029+ ((dwc_otg_module_params._param_ < (_low_)) || \
7030+ (dwc_otg_module_params._param_ > (_high_)))
7031+
7032+/* If the parameter has been set by the user, check that the parameter value is
7033+ * within the value range of values. If not, report a module error. */
7034+#define DWC_OTG_PARAM_ERR(_param_, _low_, _high_, _string_) \
7035+ do { \
7036+ if (dwc_otg_module_params._param_ != -1) { \
7037+ if (DWC_OTG_PARAM_TEST(_param_, (_low_), (_high_))) { \
7038+ DWC_ERROR("`%d' invalid for parameter `%s'\n", \
7039+ dwc_otg_module_params._param_, _string_); \
7040+ dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \
7041+ retval++; \
7042+ } \
7043+ } \
7044+ } while (0)
7045+
7046+ DWC_OTG_PARAM_ERR(opt,0,1,"opt");
7047+ DWC_OTG_PARAM_ERR(otg_cap,0,2,"otg_cap");
7048+ DWC_OTG_PARAM_ERR(dma_enable,0,1,"dma_enable");
7049+ DWC_OTG_PARAM_ERR(dma_desc_enable,0,1,"dma_desc_enable");
7050+ DWC_OTG_PARAM_ERR(speed,0,1,"speed");
7051+ DWC_OTG_PARAM_ERR(host_support_fs_ls_low_power,0,1,"host_support_fs_ls_low_power");
7052+ DWC_OTG_PARAM_ERR(host_ls_low_power_phy_clk,0,1,"host_ls_low_power_phy_clk");
7053+ DWC_OTG_PARAM_ERR(enable_dynamic_fifo,0,1,"enable_dynamic_fifo");
7054+ DWC_OTG_PARAM_ERR(data_fifo_size,32,32768,"data_fifo_size");
7055+ DWC_OTG_PARAM_ERR(dev_rx_fifo_size,16,32768,"dev_rx_fifo_size");
7056+ DWC_OTG_PARAM_ERR(dev_nperio_tx_fifo_size,16,32768,"dev_nperio_tx_fifo_size");
7057+ DWC_OTG_PARAM_ERR(host_rx_fifo_size,16,32768,"host_rx_fifo_size");
7058+ DWC_OTG_PARAM_ERR(host_nperio_tx_fifo_size,16,32768,"host_nperio_tx_fifo_size");
7059+ DWC_OTG_PARAM_ERR(host_perio_tx_fifo_size,16,32768,"host_perio_tx_fifo_size");
7060+ DWC_OTG_PARAM_ERR(max_transfer_size,2047,524288,"max_transfer_size");
7061+ DWC_OTG_PARAM_ERR(max_packet_count,15,511,"max_packet_count");
7062+ DWC_OTG_PARAM_ERR(host_channels,1,16,"host_channels");
7063+ DWC_OTG_PARAM_ERR(dev_endpoints,1,15,"dev_endpoints");
7064+ DWC_OTG_PARAM_ERR(phy_type,0,2,"phy_type");
7065+ DWC_OTG_PARAM_ERR(phy_ulpi_ddr,0,1,"phy_ulpi_ddr");
7066+ DWC_OTG_PARAM_ERR(phy_ulpi_ext_vbus,0,1,"phy_ulpi_ext_vbus");
7067+ DWC_OTG_PARAM_ERR(i2c_enable,0,1,"i2c_enable");
7068+ DWC_OTG_PARAM_ERR(ulpi_fs_ls,0,1,"ulpi_fs_ls");
7069+ DWC_OTG_PARAM_ERR(ts_dline,0,1,"ts_dline");
7070+
7071+ if (dwc_otg_module_params.dma_burst_size != -1) {
7072+ if (DWC_OTG_PARAM_TEST(dma_burst_size,1,1) &&
7073+ DWC_OTG_PARAM_TEST(dma_burst_size,4,4) &&
7074+ DWC_OTG_PARAM_TEST(dma_burst_size,8,8) &&
7075+ DWC_OTG_PARAM_TEST(dma_burst_size,16,16) &&
7076+ DWC_OTG_PARAM_TEST(dma_burst_size,32,32) &&
7077+ DWC_OTG_PARAM_TEST(dma_burst_size,64,64) &&
7078+ DWC_OTG_PARAM_TEST(dma_burst_size,128,128) &&
7079+ DWC_OTG_PARAM_TEST(dma_burst_size,256,256)) {
7080+ DWC_ERROR("`%d' invalid for parameter `dma_burst_size'\n",
7081+ dwc_otg_module_params.dma_burst_size);
7082+ dwc_otg_module_params.dma_burst_size = 32;
7083+ retval++;
7084+ }
7085+
7086+ {
7087+ uint8_t brst_sz = 0;
7088+ while(dwc_otg_module_params.dma_burst_size > 1) {
7089+ brst_sz ++;
7090+ dwc_otg_module_params.dma_burst_size >>= 1;
7091+ }
7092+ dwc_otg_module_params.dma_burst_size = brst_sz;
7093+ }
7094+ }
7095+
7096+ if (dwc_otg_module_params.phy_utmi_width != -1) {
7097+ if (DWC_OTG_PARAM_TEST(phy_utmi_width, 8, 8) &&
7098+ DWC_OTG_PARAM_TEST(phy_utmi_width, 16, 16)) {
7099+ DWC_ERROR("`%d' invalid for parameter `phy_utmi_width'\n",
7100+ dwc_otg_module_params.phy_utmi_width);
7101+ dwc_otg_module_params.phy_utmi_width = 16;
7102+ retval++;
7103+ }
7104+ }
7105+
7106+ for (i = 0; i < 15; i++) {
7107+ /** @todo should be like above */
7108+ //DWC_OTG_PARAM_ERR(dev_perio_tx_fifo_size[i], 4, 768, "dev_perio_tx_fifo_size");
7109+ if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
7110+ if (DWC_OTG_PARAM_TEST(dev_perio_tx_fifo_size[i], 4, 768)) {
7111+ DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
7112+ dwc_otg_module_params.dev_perio_tx_fifo_size[i], "dev_perio_tx_fifo_size", i);
7113+ dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
7114+ retval++;
7115+ }
7116+ }
7117+ }
7118+
7119+ DWC_OTG_PARAM_ERR(en_multiple_tx_fifo, 0, 1, "en_multiple_tx_fifo");
7120+
7121+ for (i = 0; i < 15; i++) {
7122+ /** @todo should be like above */
7123+ //DWC_OTG_PARAM_ERR(dev_tx_fifo_size[i], 4, 768, "dev_tx_fifo_size");
7124+ if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
7125+ if (DWC_OTG_PARAM_TEST(dev_tx_fifo_size[i], 4, 768)) {
7126+ DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
7127+ dwc_otg_module_params.dev_tx_fifo_size[i], "dev_tx_fifo_size", i);
7128+ dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_param_dev_tx_fifo_size_default;
7129+ retval++;
7130+ }
7131+ }
7132+ }
7133+
7134+ DWC_OTG_PARAM_ERR(thr_ctl, 0, 7, "thr_ctl");
7135+ DWC_OTG_PARAM_ERR(tx_thr_length, 8, 128, "tx_thr_length");
7136+ DWC_OTG_PARAM_ERR(rx_thr_length, 8, 128, "rx_thr_length");
7137+
7138+ DWC_OTG_PARAM_ERR(pti_enable,0,1,"pti_enable");
7139+ DWC_OTG_PARAM_ERR(mpi_enable,0,1,"mpi_enable");
7140+
7141+ /* At this point, all module parameters that have been set by the user
7142+ * are valid, and those that have not are left unset. Now set their
7143+ * default values and/or check the parameters against the hardware
7144+ * configurations of the OTG core. */
7145+
7146+/* This sets the parameter to the default value if it has not been set by the
7147+ * user */
7148+#define DWC_OTG_PARAM_SET_DEFAULT(_param_) \
7149+ ({ \
7150+ int changed = 1; \
7151+ if (dwc_otg_module_params._param_ == -1) { \
7152+ changed = 0; \
7153+ dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \
7154+ } \
7155+ changed; \
7156+ })
7157+
7158+/* This checks the macro agains the hardware configuration to see if it is
7159+ * valid. It is possible that the default value could be invalid. In this
7160+ * case, it will report a module error if the user touched the parameter.
7161+ * Otherwise it will adjust the value without any error. */
7162+#define DWC_OTG_PARAM_CHECK_VALID(_param_, _str_, _is_valid_, _set_valid_) \
7163+ ({ \
7164+ int changed = DWC_OTG_PARAM_SET_DEFAULT(_param_); \
7165+ int error = 0; \
7166+ if (!(_is_valid_)) { \
7167+ if (changed) { \
7168+ DWC_ERROR("`%d' invalid for parameter `%s'. Check HW configuration.\n", dwc_otg_module_params._param_, _str_); \
7169+ error = 1; \
7170+ } \
7171+ dwc_otg_module_params._param_ = (_set_valid_); \
7172+ } \
7173+ error; \
7174+ })
7175+
7176+ /* OTG Cap */
7177+ retval += DWC_OTG_PARAM_CHECK_VALID(otg_cap, "otg_cap",
7178+ ({
7179+ int valid;
7180+ valid = 1;
7181+ switch (dwc_otg_module_params.otg_cap) {
7182+ case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
7183+ if (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
7184+ valid = 0;
7185+ break;
7186+ case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
7187+ if ((core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) &&
7188+ (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) &&
7189+ (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) &&
7190+ (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
7191+ valid = 0;
7192+ }
7193+ break;
7194+ case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
7195+ /* always valid */
7196+ break;
7197+ }
7198+ valid;
7199+ }),
7200+ (((core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ||
7201+ (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) ||
7202+ (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
7203+ (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
7204+ DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
7205+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE));
7206+
7207+ retval += DWC_OTG_PARAM_CHECK_VALID(dma_enable, "dma_enable",
7208+ ((dwc_otg_module_params.dma_enable == 1) && (core_if->hwcfg2.b.architecture == 0)) ? 0 : 1,
7209+ 0);
7210+
7211+ retval += DWC_OTG_PARAM_CHECK_VALID(dma_desc_enable, "dma_desc_enable",
7212+ ((dwc_otg_module_params.dma_desc_enable == 1) &&
7213+ ((dwc_otg_module_params.dma_enable == 0) || (core_if->hwcfg4.b.desc_dma == 0))) ? 0 : 1,
7214+ 0);
7215+
7216+ retval += DWC_OTG_PARAM_CHECK_VALID(opt, "opt", 1, 0);
7217+
7218+ DWC_OTG_PARAM_SET_DEFAULT(dma_burst_size);
7219+
7220+ retval += DWC_OTG_PARAM_CHECK_VALID(host_support_fs_ls_low_power,
7221+ "host_support_fs_ls_low_power",
7222+ 1, 0);
7223+
7224+ retval += DWC_OTG_PARAM_CHECK_VALID(enable_dynamic_fifo,
7225+ "enable_dynamic_fifo",
7226+ ((dwc_otg_module_params.enable_dynamic_fifo == 0) ||
7227+ (core_if->hwcfg2.b.dynamic_fifo == 1)), 0);
7228+
7229+ retval += DWC_OTG_PARAM_CHECK_VALID(data_fifo_size,
7230+ "data_fifo_size",
7231+ (dwc_otg_module_params.data_fifo_size <= core_if->hwcfg3.b.dfifo_depth),
7232+ core_if->hwcfg3.b.dfifo_depth);
7233+
7234+ retval += DWC_OTG_PARAM_CHECK_VALID(dev_rx_fifo_size,
7235+ "dev_rx_fifo_size",
7236+ (dwc_otg_module_params.dev_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
7237+ dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
7238+
7239+ retval += DWC_OTG_PARAM_CHECK_VALID(dev_nperio_tx_fifo_size,
7240+ "dev_nperio_tx_fifo_size",
7241+ (dwc_otg_module_params.dev_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
7242+ (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
7243+
7244+ retval += DWC_OTG_PARAM_CHECK_VALID(host_rx_fifo_size,
7245+ "host_rx_fifo_size",
7246+ (dwc_otg_module_params.host_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
7247+ dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
7248+
7249+ retval += DWC_OTG_PARAM_CHECK_VALID(host_nperio_tx_fifo_size,
7250+ "host_nperio_tx_fifo_size",
7251+ (dwc_otg_module_params.host_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
7252+ (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
7253+
7254+ retval += DWC_OTG_PARAM_CHECK_VALID(host_perio_tx_fifo_size,
7255+ "host_perio_tx_fifo_size",
7256+ (dwc_otg_module_params.host_perio_tx_fifo_size <= ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))),
7257+ ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16)));
7258+
7259+ retval += DWC_OTG_PARAM_CHECK_VALID(max_transfer_size,
7260+ "max_transfer_size",
7261+ (dwc_otg_module_params.max_transfer_size < (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))),
7262+ ((1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1));
7263+
7264+ retval += DWC_OTG_PARAM_CHECK_VALID(max_packet_count,
7265+ "max_packet_count",
7266+ (dwc_otg_module_params.max_packet_count < (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))),
7267+ ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1));
7268+
7269+ retval += DWC_OTG_PARAM_CHECK_VALID(host_channels,
7270+ "host_channels",
7271+ (dwc_otg_module_params.host_channels <= (core_if->hwcfg2.b.num_host_chan + 1)),
7272+ (core_if->hwcfg2.b.num_host_chan + 1));
7273+
7274+ retval += DWC_OTG_PARAM_CHECK_VALID(dev_endpoints,
7275+ "dev_endpoints",
7276+ (dwc_otg_module_params.dev_endpoints <= (core_if->hwcfg2.b.num_dev_ep)),
7277+ core_if->hwcfg2.b.num_dev_ep);
7278+
7279+/*
7280+ * Define the following to disable the FS PHY Hardware checking. This is for
7281+ * internal testing only.
7282+ *
7283+ * #define NO_FS_PHY_HW_CHECKS
7284+ */
7285+
7286+#ifdef NO_FS_PHY_HW_CHECKS
7287+ retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
7288+ "phy_type", 1, 0);
7289+#else
7290+ retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
7291+ "phy_type",
7292+ ({
7293+ int valid = 0;
7294+ if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_UTMI) &&
7295+ ((core_if->hwcfg2.b.hs_phy_type == 1) ||
7296+ (core_if->hwcfg2.b.hs_phy_type == 3))) {
7297+ valid = 1;
7298+ }
7299+ else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_ULPI) &&
7300+ ((core_if->hwcfg2.b.hs_phy_type == 2) ||
7301+ (core_if->hwcfg2.b.hs_phy_type == 3))) {
7302+ valid = 1;
7303+ }
7304+ else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) &&
7305+ (core_if->hwcfg2.b.fs_phy_type == 1)) {
7306+ valid = 1;
7307+ }
7308+ valid;
7309+ }),
7310+ ({
7311+ int set = DWC_PHY_TYPE_PARAM_FS;
7312+ if (core_if->hwcfg2.b.hs_phy_type) {
7313+ if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
7314+ (core_if->hwcfg2.b.hs_phy_type == 1)) {
7315+ set = DWC_PHY_TYPE_PARAM_UTMI;
7316+ }
7317+ else {
7318+ set = DWC_PHY_TYPE_PARAM_ULPI;
7319+ }
7320+ }
7321+ set;
7322+ }));
7323+#endif
7324+
7325+ retval += DWC_OTG_PARAM_CHECK_VALID(speed, "speed",
7326+ (dwc_otg_module_params.speed == 0) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1,
7327+ dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
7328+
7329+ retval += DWC_OTG_PARAM_CHECK_VALID(host_ls_low_power_phy_clk,
7330+ "host_ls_low_power_phy_clk",
7331+ ((dwc_otg_module_params.host_ls_low_power_phy_clk == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1),
7332+ ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ : DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ));
7333+
7334+ DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ddr);
7335+ DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ext_vbus);
7336+ DWC_OTG_PARAM_SET_DEFAULT(phy_utmi_width);
7337+ DWC_OTG_PARAM_SET_DEFAULT(ulpi_fs_ls);
7338+ DWC_OTG_PARAM_SET_DEFAULT(ts_dline);
7339+
7340+#ifdef NO_FS_PHY_HW_CHECKS
7341+ retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable, "i2c_enable", 1, 0);
7342+#else
7343+ retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable,
7344+ "i2c_enable",
7345+ (dwc_otg_module_params.i2c_enable == 1) && (core_if->hwcfg3.b.i2c == 0) ? 0 : 1,
7346+ 0);
7347+#endif
7348+
7349+ for (i = 0; i < 15; i++) {
7350+ int changed = 1;
7351+ int error = 0;
7352+
7353+ if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] == -1) {
7354+ changed = 0;
7355+ dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
7356+ }
7357+ if (!(dwc_otg_module_params.dev_perio_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) {
7358+ if (changed) {
7359+ DWC_ERROR("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params.dev_perio_tx_fifo_size[i], i);
7360+ error = 1;
7361+ }
7362+ dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
7363+ }
7364+ retval += error;
7365+ }
7366+
7367+ retval += DWC_OTG_PARAM_CHECK_VALID(en_multiple_tx_fifo, "en_multiple_tx_fifo",
7368+ ((dwc_otg_module_params.en_multiple_tx_fifo == 1) && (core_if->hwcfg4.b.ded_fifo_en == 0)) ? 0 : 1,
7369+ 0);
7370+
7371+ for (i = 0; i < 15; i++) {
7372+ int changed = 1;
7373+ int error = 0;
7374+
7375+ if (dwc_otg_module_params.dev_tx_fifo_size[i] == -1) {
7376+ changed = 0;
7377+ dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_param_dev_tx_fifo_size_default;
7378+ }
7379+ if (!(dwc_otg_module_params.dev_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) {
7380+ if (changed) {
7381+ DWC_ERROR("%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params.dev_tx_fifo_size[i], i);
7382+ error = 1;
7383+ }
7384+ dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
7385+ }
7386+ retval += error;
7387+ }
7388+
7389+ retval += DWC_OTG_PARAM_CHECK_VALID(thr_ctl, "thr_ctl",
7390+ ((dwc_otg_module_params.thr_ctl != 0) && ((dwc_otg_module_params.dma_enable == 0) || (core_if->hwcfg4.b.ded_fifo_en == 0))) ? 0 : 1,
7391+ 0);
7392+
7393+ DWC_OTG_PARAM_SET_DEFAULT(tx_thr_length);
7394+ DWC_OTG_PARAM_SET_DEFAULT(rx_thr_length);
7395+
7396+ retval += DWC_OTG_PARAM_CHECK_VALID(pti_enable, "pti_enable",
7397+ ((dwc_otg_module_params.pti_enable == 0) || ((dwc_otg_module_params.pti_enable == 1) && (core_if->snpsid >= 0x4F54272A))) ? 1 : 0,
7398+ 0);
7399+
7400+ retval += DWC_OTG_PARAM_CHECK_VALID(mpi_enable, "mpi_enable",
7401+ ((dwc_otg_module_params.mpi_enable == 0) || ((dwc_otg_module_params.mpi_enable == 1) && (core_if->hwcfg2.b.multi_proc_int == 1))) ? 1 : 0,
7402+ 0);
7403+ return retval;
7404+}
7405+
7406+/**
7407+ * This function is the top level interrupt handler for the Common
7408+ * (Device and host modes) interrupts.
7409+ */
7410+static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
7411+{
7412+ dwc_otg_device_t *otg_dev = dev;
7413+ int32_t retval = IRQ_NONE;
7414+
7415+ retval = dwc_otg_handle_common_intr(otg_dev->core_if);
7416+ return IRQ_RETVAL(retval);
7417+}
7418+
7419+/**
7420+ * This function is called when a lm_device is unregistered with the
7421+ * dwc_otg_driver. This happens, for example, when the rmmod command is
7422+ * executed. The device may or may not be electrically present. If it is
7423+ * present, the driver stops device processing. Any resources used on behalf
7424+ * of this device are freed.
7425+ *
7426+ * @param[in] lmdev
7427+ */
7428+static int dwc_otg_driver_cleanup(struct platform_device *pdev)
7429+{
7430+ dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev);
7431+ DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, pdev);
7432+
7433+ if (!otg_dev) {
7434+ /* Memory allocation for the dwc_otg_device failed. */
7435+ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
7436+ return 0;
7437+ }
7438+
7439+ /*
7440+ * Free the IRQ
7441+ */
7442+ if (otg_dev->common_irq_installed) {
7443+ free_irq(otg_dev->irq, otg_dev);
7444+ }
7445+
7446+#ifndef DWC_DEVICE_ONLY
7447+ if (otg_dev->hcd) {
7448+ dwc_otg_hcd_remove(pdev);
7449+ } else {
7450+ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
7451+ return 0;
7452+ }
7453+#endif
7454+
7455+#ifndef DWC_HOST_ONLY
7456+ if (otg_dev->pcd) {
7457+ dwc_otg_pcd_remove(pdev);
7458+ }
7459+#endif
7460+ if (otg_dev->core_if) {
7461+ dwc_otg_cil_remove(otg_dev->core_if);
7462+ }
7463+
7464+ /*
7465+ * Remove the device attributes
7466+ */
7467+ dwc_otg_attr_remove(pdev);
7468+
7469+ /*
7470+ * Return the memory.
7471+ */
7472+ if (otg_dev->base) {
7473+ iounmap(otg_dev->base);
7474+ }
7475+ kfree(otg_dev);
7476+
7477+ /*
7478+ * Clear the drvdata pointer.
7479+ */
7480+ platform_set_drvdata(pdev, 0);
7481+
7482+ return 0;
7483+}
7484+
7485+/**
7486+ * This function is called when an lm_device is bound to a
7487+ * dwc_otg_driver. It creates the driver components required to
7488+ * control the device (CIL, HCD, and PCD) and it initializes the
7489+ * device. The driver components are stored in a dwc_otg_device
7490+ * structure. A reference to the dwc_otg_device is saved in the
7491+ * lm_device. This allows the driver to access the dwc_otg_device
7492+ * structure on subsequent calls to driver methods for this device.
7493+ *
7494+ * @param[in] lmdev lm_device definition
7495+ */
7496+static int __devinit dwc_otg_driver_probe(struct platform_device *pdev)
7497+{
7498+ struct device *dev = &pdev->dev;
7499+ int retval = 0;
7500+ uint32_t snpsid;
7501+ dwc_otg_device_t *dwc_otg_device;
7502+ struct resource *res;
7503+
7504+ dev_dbg(dev, "dwc_otg_driver_probe(%p)\n", pdev);
7505+
7506+ dwc_otg_device = kmalloc(sizeof(dwc_otg_device_t), GFP_KERNEL);
7507+
7508+ if (!dwc_otg_device) {
7509+ dev_err(dev, "kmalloc of dwc_otg_device failed\n");
7510+ retval = -ENOMEM;
7511+ goto fail;
7512+ }
7513+
7514+ memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
7515+ dwc_otg_device->reg_offset = 0xFFFFFFFF;
7516+
7517+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7518+ if (!res) {
7519+ dev_err(dev, "Found OTG with no register addr.\n");
7520+ retval = -ENODEV;
7521+ goto fail;
7522+ }
7523+ dwc_otg_device->rsrc_start = res->start;
7524+ dwc_otg_device->rsrc_len = res->end - res->start + 1;
7525+
7526+ dwc_otg_device->base = ioremap(dwc_otg_device->rsrc_start, dwc_otg_device->rsrc_len);
7527+
7528+ if (!dwc_otg_device->base) {
7529+ dev_err(dev, "ioremap() failed\n");
7530+ retval = -ENOMEM;
7531+ goto fail;
7532+ }
7533+ dev_dbg(dev, "base=0x%08x\n", (unsigned)dwc_otg_device->base);
7534+
7535+ /*
7536+ * Attempt to ensure this device is really a DWC_otg Controller.
7537+ * Read and verify the SNPSID register contents. The value should be
7538+ * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX".
7539+ */
7540+ snpsid = dwc_read_reg32((uint32_t *)((uint8_t *)dwc_otg_device->base + 0x40));
7541+
7542+ if ((snpsid & 0xFFFFF000) != OTG_CORE_REV_2_00) {
7543+ dev_err(dev, "Bad value for SNPSID: 0x%08x\n", snpsid);
7544+ retval = -EINVAL;
7545+ goto fail;
7546+ }
7547+
7548+ DWC_PRINT("Core Release: %x.%x%x%x\n",
7549+ (snpsid >> 12 & 0xF),
7550+ (snpsid >> 8 & 0xF),
7551+ (snpsid >> 4 & 0xF),
7552+ (snpsid & 0xF));
7553+
7554+ /*
7555+ * Initialize driver data to point to the global DWC_otg
7556+ * Device structure.
7557+ */
7558+ platform_set_drvdata(pdev, dwc_otg_device);
7559+
7560+ dev_dbg(dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
7561+
7562+ dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->base,
7563+ &dwc_otg_module_params);
7564+
7565+ dwc_otg_device->core_if->snpsid = snpsid;
7566+
7567+ if (!dwc_otg_device->core_if) {
7568+ dev_err(dev, "CIL initialization failed!\n");
7569+ retval = -ENOMEM;
7570+ goto fail;
7571+ }
7572+
7573+ /*
7574+ * Validate parameter values.
7575+ */
7576+ if (check_parameters(dwc_otg_device->core_if)) {
7577+ retval = -EINVAL;
7578+ goto fail;
7579+ }
7580+
7581+ /*
7582+ * Create Device Attributes in sysfs
7583+ */
7584+ dwc_otg_attr_create(pdev);
7585+
7586+ /*
7587+ * Disable the global interrupt until all the interrupt
7588+ * handlers are installed.
7589+ */
7590+ dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
7591+
7592+ /*
7593+ * Install the interrupt handler for the common interrupts before
7594+ * enabling common interrupts in core_init below.
7595+ */
7596+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
7597+ if (!res) {
7598+ dev_err(dev, "Fount OTG with to IRQ.\n");
7599+ retval = -ENODEV;
7600+ goto fail;
7601+ }
7602+ dwc_otg_device->irq = res->start;
7603+
7604+ retval = request_irq(res->start, dwc_otg_common_irq,
7605+ IRQF_SHARED, "dwc_otg", dwc_otg_device);
7606+ if (retval) {
7607+ DWC_ERROR("request of irq%d failed\n", res->start);
7608+ retval = -EBUSY;
7609+ goto fail;
7610+ } else {
7611+ dwc_otg_device->common_irq_installed = 1;
7612+ }
7613+
7614+ /*
7615+ * Initialize the DWC_otg core.
7616+ */
7617+ dwc_otg_core_init(dwc_otg_device->core_if);
7618+
7619+#ifndef DWC_HOST_ONLY
7620+ /*
7621+ * Initialize the PCD
7622+ */
7623+ retval = dwc_otg_pcd_init(pdev);
7624+ if (retval != 0) {
7625+ DWC_ERROR("dwc_otg_pcd_init failed\n");
7626+ dwc_otg_device->pcd = NULL;
7627+ goto fail;
7628+ }
7629+#endif
7630+#ifndef DWC_DEVICE_ONLY
7631+ /*
7632+ * Initialize the HCD
7633+ */
7634+ retval = dwc_otg_hcd_init(pdev);
7635+ if (retval != 0) {
7636+ DWC_ERROR("dwc_otg_hcd_init failed\n");
7637+ dwc_otg_device->hcd = NULL;
7638+ goto fail;
7639+ }
7640+#endif
7641+
7642+ /*
7643+ * Enable the global interrupt after all the interrupt
7644+ * handlers are installed.
7645+ */
7646+ dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
7647+
7648+ return 0;
7649+
7650+ fail:
7651+ dwc_otg_driver_cleanup(pdev);
7652+ return retval;
7653+}
7654+
7655+static int __devexit dwc_otg_driver_remove(struct platform_device *pdev)
7656+{
7657+ return dwc_otg_driver_cleanup(pdev);
7658+}
7659+
7660+static struct platform_driver dwc_otg_platform_driver = {
7661+ .driver.name = "dwc_otg",
7662+ .probe = dwc_otg_driver_probe,
7663+ .remove = __devexit_p(dwc_otg_driver_remove),
7664+};
7665+
7666+static int __init dwc_otg_init_module(void)
7667+{
7668+ return platform_driver_register(&dwc_otg_platform_driver);
7669+}
7670+
7671+static void __exit dwc_otg_cleanup_module(void)
7672+{
7673+ platform_driver_unregister(&dwc_otg_platform_driver);
7674+}
7675+
7676+module_init(dwc_otg_init_module);
7677+module_exit(dwc_otg_cleanup_module);
7678+
7679+/**
7680+ * This function is called when the driver is removed from the kernel
7681+ * with the rmmod command. The driver unregisters itself with its bus
7682+ * driver.
7683+ *
7684+ */
7685+
7686+MODULE_DESCRIPTION(DWC_DRIVER_DESC);
7687+MODULE_AUTHOR("Synopsys Inc.");
7688+MODULE_LICENSE("GPL");
7689+
7690+module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
7691+MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
7692+module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
7693+MODULE_PARM_DESC(opt, "OPT Mode");
7694+module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
7695+MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
7696+
7697+module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int, 0444);
7698+MODULE_PARM_DESC(dma_desc_enable, "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
7699+
7700+module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int, 0444);
7701+MODULE_PARM_DESC(dma_burst_size, "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
7702+module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
7703+MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
7704+module_param_named(host_support_fs_ls_low_power, dwc_otg_module_params.host_support_fs_ls_low_power, int, 0444);
7705+MODULE_PARM_DESC(host_support_fs_ls_low_power, "Support Low Power w/FS or LS 0=Support 1=Don't Support");
7706+module_param_named(host_ls_low_power_phy_clk, dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
7707+MODULE_PARM_DESC(host_ls_low_power_phy_clk, "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
7708+module_param_named(enable_dynamic_fifo, dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
7709+MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
7710+module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int, 0444);
7711+MODULE_PARM_DESC(data_fifo_size, "Total number of words in the data FIFO memory 32-32768");
7712+module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, int, 0444);
7713+MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
7714+module_param_named(dev_nperio_tx_fifo_size, dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
7715+MODULE_PARM_DESC(dev_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
7716+module_param_named(dev_perio_tx_fifo_size_1, dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
7717+MODULE_PARM_DESC(dev_perio_tx_fifo_size_1, "Number of words in the periodic Tx FIFO 4-768");
7718+module_param_named(dev_perio_tx_fifo_size_2, dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
7719+MODULE_PARM_DESC(dev_perio_tx_fifo_size_2, "Number of words in the periodic Tx FIFO 4-768");
7720+module_param_named(dev_perio_tx_fifo_size_3, dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
7721+MODULE_PARM_DESC(dev_perio_tx_fifo_size_3, "Number of words in the periodic Tx FIFO 4-768");
7722+module_param_named(dev_perio_tx_fifo_size_4, dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
7723+MODULE_PARM_DESC(dev_perio_tx_fifo_size_4, "Number of words in the periodic Tx FIFO 4-768");
7724+module_param_named(dev_perio_tx_fifo_size_5, dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
7725+MODULE_PARM_DESC(dev_perio_tx_fifo_size_5, "Number of words in the periodic Tx FIFO 4-768");
7726+module_param_named(dev_perio_tx_fifo_size_6, dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
7727+MODULE_PARM_DESC(dev_perio_tx_fifo_size_6, "Number of words in the periodic Tx FIFO 4-768");
7728+module_param_named(dev_perio_tx_fifo_size_7, dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
7729+MODULE_PARM_DESC(dev_perio_tx_fifo_size_7, "Number of words in the periodic Tx FIFO 4-768");
7730+module_param_named(dev_perio_tx_fifo_size_8, dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
7731+MODULE_PARM_DESC(dev_perio_tx_fifo_size_8, "Number of words in the periodic Tx FIFO 4-768");
7732+module_param_named(dev_perio_tx_fifo_size_9, dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
7733+MODULE_PARM_DESC(dev_perio_tx_fifo_size_9, "Number of words in the periodic Tx FIFO 4-768");
7734+module_param_named(dev_perio_tx_fifo_size_10, dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
7735+MODULE_PARM_DESC(dev_perio_tx_fifo_size_10, "Number of words in the periodic Tx FIFO 4-768");
7736+module_param_named(dev_perio_tx_fifo_size_11, dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
7737+MODULE_PARM_DESC(dev_perio_tx_fifo_size_11, "Number of words in the periodic Tx FIFO 4-768");
7738+module_param_named(dev_perio_tx_fifo_size_12, dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
7739+MODULE_PARM_DESC(dev_perio_tx_fifo_size_12, "Number of words in the periodic Tx FIFO 4-768");
7740+module_param_named(dev_perio_tx_fifo_size_13, dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
7741+MODULE_PARM_DESC(dev_perio_tx_fifo_size_13, "Number of words in the periodic Tx FIFO 4-768");
7742+module_param_named(dev_perio_tx_fifo_size_14, dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
7743+MODULE_PARM_DESC(dev_perio_tx_fifo_size_14, "Number of words in the periodic Tx FIFO 4-768");
7744+module_param_named(dev_perio_tx_fifo_size_15, dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
7745+MODULE_PARM_DESC(dev_perio_tx_fifo_size_15, "Number of words in the periodic Tx FIFO 4-768");
7746+module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size, int, 0444);
7747+MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
7748+module_param_named(host_nperio_tx_fifo_size, dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
7749+MODULE_PARM_DESC(host_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
7750+module_param_named(host_perio_tx_fifo_size, dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
7751+MODULE_PARM_DESC(host_perio_tx_fifo_size, "Number of words in the host periodic Tx FIFO 16-32768");
7752+module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size, int, 0444);
7753+/** @todo Set the max to 512K, modify checks */
7754+MODULE_PARM_DESC(max_transfer_size, "The maximum transfer size supported in bytes 2047-65535");
7755+module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count, int, 0444);
7756+MODULE_PARM_DESC(max_packet_count, "The maximum number of packets in a transfer 15-511");
7757+module_param_named(host_channels, dwc_otg_module_params.host_channels, int, 0444);
7758+MODULE_PARM_DESC(host_channels, "The number of host channel registers to use 1-16");
7759+module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int, 0444);
7760+MODULE_PARM_DESC(dev_endpoints, "The number of endpoints in addition to EP0 available for device mode 1-15");
7761+module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
7762+MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
7763+module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int, 0444);
7764+MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
7765+module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
7766+MODULE_PARM_DESC(phy_ulpi_ddr, "ULPI at double or single data rate 0=Single 1=Double");
7767+module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus, int, 0444);
7768+MODULE_PARM_DESC(phy_ulpi_ext_vbus, "ULPI PHY using internal or external vbus 0=Internal");
7769+module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
7770+MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
7771+module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
7772+MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
7773+module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
7774+MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
7775+module_param_named(debug, g_dbg_lvl, int, 0444);
7776+MODULE_PARM_DESC(debug, "");
7777+
7778+module_param_named(en_multiple_tx_fifo, dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
7779+MODULE_PARM_DESC(en_multiple_tx_fifo, "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
7780+module_param_named(dev_tx_fifo_size_1, dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
7781+MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
7782+module_param_named(dev_tx_fifo_size_2, dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
7783+MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
7784+module_param_named(dev_tx_fifo_size_3, dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
7785+MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
7786+module_param_named(dev_tx_fifo_size_4, dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
7787+MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
7788+module_param_named(dev_tx_fifo_size_5, dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
7789+MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
7790+module_param_named(dev_tx_fifo_size_6, dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
7791+MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
7792+module_param_named(dev_tx_fifo_size_7, dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
7793+MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
7794+module_param_named(dev_tx_fifo_size_8, dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
7795+MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
7796+module_param_named(dev_tx_fifo_size_9, dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
7797+MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
7798+module_param_named(dev_tx_fifo_size_10, dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
7799+MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
7800+module_param_named(dev_tx_fifo_size_11, dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
7801+MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
7802+module_param_named(dev_tx_fifo_size_12, dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
7803+MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
7804+module_param_named(dev_tx_fifo_size_13, dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
7805+MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
7806+module_param_named(dev_tx_fifo_size_14, dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
7807+MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
7808+module_param_named(dev_tx_fifo_size_15, dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
7809+MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
7810+
7811+module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
7812+MODULE_PARM_DESC(thr_ctl, "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
7813+module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int, 0444);
7814+MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
7815+module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int, 0444);
7816+MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
7817+
7818+module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
7819+MODULE_PARM_DESC(pti_enable, "Per Transfer Interrupt mode 0=disabled 1=enabled");
7820+
7821+module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
7822+MODULE_PARM_DESC(mpi_enable, "Multiprocessor Interrupt mode 0=disabled 1=enabled");
7823--- /dev/null
7824+++ b/drivers/usb/dwc/otg_driver.h
7825@@ -0,0 +1,62 @@
7826+/* ==========================================================================
7827+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $
7828+ * $Revision: #12 $
7829+ * $Date: 2008/07/15 $
7830+ * $Change: 1064918 $
7831+ *
7832+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
7833+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
7834+ * otherwise expressly agreed to in writing between Synopsys and you.
7835+ *
7836+ * The Software IS NOT an item of Licensed Software or Licensed Product under
7837+ * any End User Software License Agreement or Agreement for Licensed Product
7838+ * with Synopsys or any supplement thereto. You are permitted to use and
7839+ * redistribute this Software in source and binary forms, with or without
7840+ * modification, provided that redistributions of source code must retain this
7841+ * notice. You may not view, use, disclose, copy or distribute this file or
7842+ * any information contained herein except pursuant to this license grant from
7843+ * Synopsys. If you do not agree with this notice, including the disclaimer
7844+ * below, then you are not authorized to use the Software.
7845+ *
7846+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
7847+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
7848+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
7849+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
7850+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
7851+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
7852+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
7853+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
7854+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
7855+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
7856+ * DAMAGE.
7857+ * ========================================================================== */
7858+
7859+#ifndef __DWC_OTG_DRIVER_H__
7860+#define __DWC_OTG_DRIVER_H__
7861+
7862+/** @file
7863+ * This file contains the interface to the Linux driver.
7864+ */
7865+#include "otg_cil.h"
7866+
7867+/* Type declarations */
7868+struct dwc_otg_pcd;
7869+struct dwc_otg_hcd;
7870+
7871+/**
7872+ * This structure is a wrapper that encapsulates the driver components used to
7873+ * manage a single DWC_otg controller.
7874+ */
7875+typedef struct dwc_otg_device {
7876+ void *base;
7877+ dwc_otg_core_if_t *core_if;
7878+ uint32_t reg_offset;
7879+ struct dwc_otg_pcd *pcd;
7880+ struct dwc_otg_hcd *hcd;
7881+ uint8_t common_irq_installed;
7882+ int irq;
7883+ uint32_t rsrc_start;
7884+ uint32_t rsrc_len;
7885+} dwc_otg_device_t;
7886+
7887+#endif
7888--- /dev/null
7889+++ b/drivers/usb/dwc/otg_hcd.c
7890@@ -0,0 +1,2752 @@
7891+/* ==========================================================================
7892+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
7893+ * $Revision: #75 $
7894+ * $Date: 2008/07/15 $
7895+ * $Change: 1064940 $
7896+ *
7897+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
7898+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
7899+ * otherwise expressly agreed to in writing between Synopsys and you.
7900+ *
7901+ * The Software IS NOT an item of Licensed Software or Licensed Product under
7902+ * any End User Software License Agreement or Agreement for Licensed Product
7903+ * with Synopsys or any supplement thereto. You are permitted to use and
7904+ * redistribute this Software in source and binary forms, with or without
7905+ * modification, provided that redistributions of source code must retain this
7906+ * notice. You may not view, use, disclose, copy or distribute this file or
7907+ * any information contained herein except pursuant to this license grant from
7908+ * Synopsys. If you do not agree with this notice, including the disclaimer
7909+ * below, then you are not authorized to use the Software.
7910+ *
7911+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
7912+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
7913+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
7914+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
7915+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
7916+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
7917+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
7918+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
7919+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
7920+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
7921+ * DAMAGE.
7922+ * ========================================================================== */
7923+#ifndef DWC_DEVICE_ONLY
7924+
7925+/**
7926+ * @file
7927+ *
7928+ * This file contains the implementation of the HCD. In Linux, the HCD
7929+ * implements the hc_driver API.
7930+ */
7931+#include <linux/kernel.h>
7932+#include <linux/module.h>
7933+#include <linux/moduleparam.h>
7934+#include <linux/init.h>
7935+#include <linux/device.h>
7936+#include <linux/platform_device.h>
7937+#include <linux/errno.h>
7938+#include <linux/list.h>
7939+#include <linux/interrupt.h>
7940+#include <linux/string.h>
7941+#include <linux/dma-mapping.h>
7942+#include <linux/version.h>
7943+
7944+#include <mach/irqs.h>
7945+
7946+#include "otg_driver.h"
7947+#include "otg_hcd.h"
7948+#include "otg_regs.h"
7949+
7950+static const char dwc_otg_hcd_name[] = "dwc_otg_hcd";
7951+
7952+static const struct hc_driver dwc_otg_hc_driver = {
7953+
7954+ .description = dwc_otg_hcd_name,
7955+ .product_desc = "DWC OTG Controller",
7956+ .hcd_priv_size = sizeof(dwc_otg_hcd_t),
7957+ .irq = dwc_otg_hcd_irq,
7958+ .flags = HCD_MEMORY | HCD_USB2,
7959+ .start = dwc_otg_hcd_start,
7960+ .stop = dwc_otg_hcd_stop,
7961+ .urb_enqueue = dwc_otg_hcd_urb_enqueue,
7962+ .urb_dequeue = dwc_otg_hcd_urb_dequeue,
7963+ .endpoint_disable = dwc_otg_hcd_endpoint_disable,
7964+ .get_frame_number = dwc_otg_hcd_get_frame_number,
7965+ .hub_status_data = dwc_otg_hcd_hub_status_data,
7966+ .hub_control = dwc_otg_hcd_hub_control,
7967+};
7968+
7969+/**
7970+ * Work queue function for starting the HCD when A-Cable is connected.
7971+ * The dwc_otg_hcd_start() must be called in a process context.
7972+ */
7973+static void hcd_start_func(struct work_struct *_work)
7974+{
7975+ struct delayed_work *dw = container_of(_work, struct delayed_work, work);
7976+ struct dwc_otg_hcd *otg_hcd = container_of(dw, struct dwc_otg_hcd, start_work);
7977+ struct usb_hcd *usb_hcd = container_of((void *)otg_hcd, struct usb_hcd, hcd_priv);
7978+ DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, usb_hcd);
7979+ if (usb_hcd) {
7980+ dwc_otg_hcd_start(usb_hcd);
7981+ }
7982+}
7983+
7984+/**
7985+ * HCD Callback function for starting the HCD when A-Cable is
7986+ * connected.
7987+ *
7988+ * @param p void pointer to the <code>struct usb_hcd</code>
7989+ */
7990+static int32_t dwc_otg_hcd_start_cb(void *p)
7991+{
7992+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(p);
7993+ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
7994+ hprt0_data_t hprt0;
7995+
7996+ if (core_if->op_state == B_HOST) {
7997+ /*
7998+ * Reset the port. During a HNP mode switch the reset
7999+ * needs to occur within 1ms and have a duration of at
8000+ * least 50ms.
8001+ */
8002+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
8003+ hprt0.b.prtrst = 1;
8004+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8005+ ((struct usb_hcd *)p)->self.is_b_host = 1;
8006+ } else {
8007+ ((struct usb_hcd *)p)->self.is_b_host = 0;
8008+ }
8009+
8010+ /* Need to start the HCD in a non-interrupt context. */
8011+// INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func);
8012+ INIT_DELAYED_WORK(&dwc_otg_hcd->start_work, hcd_start_func);
8013+// schedule_work(&dwc_otg_hcd->start_work);
8014+ queue_delayed_work(core_if->wq_otg, &dwc_otg_hcd->start_work, 50 * HZ / 1000);
8015+
8016+ return 1;
8017+}
8018+
8019+/**
8020+ * HCD Callback function for stopping the HCD.
8021+ *
8022+ * @param p void pointer to the <code>struct usb_hcd</code>
8023+ */
8024+static int32_t dwc_otg_hcd_stop_cb(void *p)
8025+{
8026+ struct usb_hcd *usb_hcd = (struct usb_hcd *)p;
8027+ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
8028+ dwc_otg_hcd_stop(usb_hcd);
8029+ return 1;
8030+}
8031+
8032+static void del_xfer_timers(dwc_otg_hcd_t *hcd)
8033+{
8034+#ifdef DEBUG
8035+ int i;
8036+ int num_channels = hcd->core_if->core_params->host_channels;
8037+ for (i = 0; i < num_channels; i++) {
8038+ del_timer(&hcd->core_if->hc_xfer_timer[i]);
8039+ }
8040+#endif
8041+}
8042+
8043+static void del_timers(dwc_otg_hcd_t *hcd)
8044+{
8045+ del_xfer_timers(hcd);
8046+ del_timer(&hcd->conn_timer);
8047+}
8048+
8049+/**
8050+ * Processes all the URBs in a single list of QHs. Completes them with
8051+ * -ETIMEDOUT and frees the QTD.
8052+ */
8053+static void kill_urbs_in_qh_list(dwc_otg_hcd_t *hcd, struct list_head *qh_list)
8054+{
8055+ struct list_head *qh_item;
8056+ dwc_otg_qh_t *qh;
8057+ struct list_head *qtd_item;
8058+ dwc_otg_qtd_t *qtd;
8059+ unsigned long flags;
8060+
8061+ SPIN_LOCK_IRQSAVE(&hcd->lock, flags);
8062+ list_for_each(qh_item, qh_list) {
8063+ qh = list_entry(qh_item, dwc_otg_qh_t, qh_list_entry);
8064+ for (qtd_item = qh->qtd_list.next;
8065+ qtd_item != &qh->qtd_list;
8066+ qtd_item = qh->qtd_list.next) {
8067+ qtd = list_entry(qtd_item, dwc_otg_qtd_t, qtd_list_entry);
8068+ if (qtd->urb != NULL) {
8069+ dwc_otg_hcd_complete_urb(hcd, qtd->urb,
8070+ -ETIMEDOUT);
8071+ }
8072+ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd);
8073+ }
8074+ }
8075+ SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags);
8076+}
8077+
8078+/**
8079+ * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic
8080+ * and periodic schedules. The QTD associated with each URB is removed from
8081+ * the schedule and freed. This function may be called when a disconnect is
8082+ * detected or when the HCD is being stopped.
8083+ */
8084+static void kill_all_urbs(dwc_otg_hcd_t *hcd)
8085+{
8086+ kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
8087+ kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
8088+ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
8089+ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
8090+ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
8091+ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
8092+}
8093+
8094+/**
8095+ * HCD Callback function for disconnect of the HCD.
8096+ *
8097+ * @param p void pointer to the <code>struct usb_hcd</code>
8098+ */
8099+static int32_t dwc_otg_hcd_disconnect_cb(void *p)
8100+{
8101+ gintsts_data_t intr;
8102+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(p);
8103+
8104+ //DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
8105+
8106+ /*
8107+ * Set status flags for the hub driver.
8108+ */
8109+ dwc_otg_hcd->flags.b.port_connect_status_change = 1;
8110+ dwc_otg_hcd->flags.b.port_connect_status = 0;
8111+
8112+ /*
8113+ * Shutdown any transfers in process by clearing the Tx FIFO Empty
8114+ * interrupt mask and status bits and disabling subsequent host
8115+ * channel interrupts.
8116+ */
8117+ intr.d32 = 0;
8118+ intr.b.nptxfempty = 1;
8119+ intr.b.ptxfempty = 1;
8120+ intr.b.hcintr = 1;
8121+ dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, intr.d32, 0);
8122+ dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintsts, intr.d32, 0);
8123+
8124+ del_timers(dwc_otg_hcd);
8125+
8126+ /*
8127+ * Turn off the vbus power only if the core has transitioned to device
8128+ * mode. If still in host mode, need to keep power on to detect a
8129+ * reconnection.
8130+ */
8131+ if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
8132+ if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
8133+ hprt0_data_t hprt0 = { .d32=0 };
8134+ DWC_PRINT("Disconnect: PortPower off\n");
8135+ hprt0.b.prtpwr = 0;
8136+ dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
8137+ }
8138+
8139+ dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
8140+ }
8141+
8142+ /* Respond with an error status to all URBs in the schedule. */
8143+ kill_all_urbs(dwc_otg_hcd);
8144+
8145+ if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
8146+ /* Clean up any host channels that were in use. */
8147+ int num_channels;
8148+ int i;
8149+ dwc_hc_t *channel;
8150+ dwc_otg_hc_regs_t *hc_regs;
8151+ hcchar_data_t hcchar;
8152+
8153+ num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
8154+
8155+ if (!dwc_otg_hcd->core_if->dma_enable) {
8156+ /* Flush out any channel requests in slave mode. */
8157+ for (i = 0; i < num_channels; i++) {
8158+ channel = dwc_otg_hcd->hc_ptr_array[i];
8159+ if (list_empty(&channel->hc_list_entry)) {
8160+ hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
8161+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8162+ if (hcchar.b.chen) {
8163+ hcchar.b.chen = 0;
8164+ hcchar.b.chdis = 1;
8165+ hcchar.b.epdir = 0;
8166+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
8167+ }
8168+ }
8169+ }
8170+ }
8171+
8172+ for (i = 0; i < num_channels; i++) {
8173+ channel = dwc_otg_hcd->hc_ptr_array[i];
8174+ if (list_empty(&channel->hc_list_entry)) {
8175+ hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
8176+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8177+ if (hcchar.b.chen) {
8178+ /* Halt the channel. */
8179+ hcchar.b.chdis = 1;
8180+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
8181+ }
8182+
8183+ dwc_otg_hc_cleanup(dwc_otg_hcd->core_if, channel);
8184+ list_add_tail(&channel->hc_list_entry,
8185+ &dwc_otg_hcd->free_hc_list);
8186+ }
8187+ }
8188+ }
8189+
8190+ /* A disconnect will end the session so the B-Device is no
8191+ * longer a B-host. */
8192+ ((struct usb_hcd *)p)->self.is_b_host = 0;
8193+ return 1;
8194+}
8195+
8196+/**
8197+ * Connection timeout function. An OTG host is required to display a
8198+ * message if the device does not connect within 10 seconds.
8199+ */
8200+void dwc_otg_hcd_connect_timeout(unsigned long ptr)
8201+{
8202+ DWC_DEBUGPL(DBG_HCDV, "%s(%x)\n", __func__, (int)ptr);
8203+ DWC_PRINT("Connect Timeout\n");
8204+ DWC_ERROR("Device Not Connected/Responding\n");
8205+}
8206+
8207+/**
8208+ * Start the connection timer. An OTG host is required to display a
8209+ * message if the device does not connect within 10 seconds. The
8210+ * timer is deleted if a port connect interrupt occurs before the
8211+ * timer expires.
8212+ */
8213+static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t *hcd)
8214+{
8215+ init_timer(&hcd->conn_timer);
8216+ hcd->conn_timer.function = dwc_otg_hcd_connect_timeout;
8217+ hcd->conn_timer.data = 0;
8218+ hcd->conn_timer.expires = jiffies + (HZ * 10);
8219+ add_timer(&hcd->conn_timer);
8220+}
8221+
8222+/**
8223+ * HCD Callback function for disconnect of the HCD.
8224+ *
8225+ * @param p void pointer to the <code>struct usb_hcd</code>
8226+ */
8227+static int32_t dwc_otg_hcd_session_start_cb(void *p)
8228+{
8229+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(p);
8230+ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
8231+ dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
8232+ return 1;
8233+}
8234+
8235+/**
8236+ * HCD Callback structure for handling mode switching.
8237+ */
8238+static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
8239+ .start = dwc_otg_hcd_start_cb,
8240+ .stop = dwc_otg_hcd_stop_cb,
8241+ .disconnect = dwc_otg_hcd_disconnect_cb,
8242+ .session_start = dwc_otg_hcd_session_start_cb,
8243+ .p = 0,
8244+};
8245+
8246+/**
8247+ * Reset tasklet function
8248+ */
8249+static void reset_tasklet_func(unsigned long data)
8250+{
8251+ dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *)data;
8252+ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
8253+ hprt0_data_t hprt0;
8254+
8255+ DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
8256+
8257+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
8258+ hprt0.b.prtrst = 1;
8259+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8260+ mdelay(60);
8261+
8262+ hprt0.b.prtrst = 0;
8263+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8264+ dwc_otg_hcd->flags.b.port_reset_change = 1;
8265+}
8266+
8267+static struct tasklet_struct reset_tasklet = {
8268+ .next = NULL,
8269+ .state = 0,
8270+ .count = ATOMIC_INIT(0),
8271+ .func = reset_tasklet_func,
8272+ .data = 0,
8273+};
8274+
8275+/**
8276+ * Initializes the HCD. This function allocates memory for and initializes the
8277+ * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the
8278+ * USB bus with the core and calls the hc_driver->start() function. It returns
8279+ * a negative error on failure.
8280+ */
8281+int dwc_otg_hcd_init(struct platform_device *pdev)
8282+{
8283+ struct usb_hcd *hcd = NULL;
8284+ dwc_otg_hcd_t *dwc_otg_hcd = NULL;
8285+ dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev);
8286+
8287+ int num_channels;
8288+ int i;
8289+ dwc_hc_t *channel;
8290+
8291+ int retval = 0;
8292+
8293+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
8294+
8295+ /* Set device flags indicating whether the HCD supports DMA. */
8296+ if (otg_dev->core_if->dma_enable) {
8297+ DWC_PRINT("Using DMA mode\n");
8298+
8299+ if (otg_dev->core_if->dma_desc_enable) {
8300+ DWC_PRINT("Device using Descriptor DMA mode\n");
8301+ } else {
8302+ DWC_PRINT("Device using Buffer DMA mode\n");
8303+ }
8304+ }
8305+ /*
8306+ * Allocate memory for the base HCD plus the DWC OTG HCD.
8307+ * Initialize the base HCD.
8308+ */
8309+
8310+ hcd = usb_create_hcd(&dwc_otg_hc_driver, &pdev->dev, "gadget");
8311+ if (!hcd) {
8312+ retval = -ENOMEM;
8313+ goto error1;
8314+ }
8315+
8316+ hcd->regs = otg_dev->base;
8317+ hcd->self.otg_port = 1;
8318+
8319+ /* Integrate TT in root hub, by default this is disbled. */
8320+ hcd->has_tt = 1;
8321+
8322+ /* Initialize the DWC OTG HCD. */
8323+ dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
8324+ dwc_otg_hcd->core_if = otg_dev->core_if;
8325+ otg_dev->hcd = dwc_otg_hcd;
8326+ init_hcd_usecs(dwc_otg_hcd);
8327+
8328+ /* */
8329+ spin_lock_init(&dwc_otg_hcd->lock);
8330+
8331+ /* Register the HCD CIL Callbacks */
8332+ dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
8333+ &hcd_cil_callbacks, hcd);
8334+
8335+ /* Initialize the non-periodic schedule. */
8336+ INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
8337+ INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
8338+
8339+ /* Initialize the periodic schedule. */
8340+ INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
8341+ INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
8342+ INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
8343+ INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
8344+
8345+ /*
8346+ * Create a host channel descriptor for each host channel implemented
8347+ * in the controller. Initialize the channel descriptor array.
8348+ */
8349+ INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
8350+ num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
8351+ memset(dwc_otg_hcd->hc_ptr_array, 0, sizeof(dwc_otg_hcd->hc_ptr_array));
8352+ for (i = 0; i < num_channels; i++) {
8353+ channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
8354+ if (channel == NULL) {
8355+ retval = -ENOMEM;
8356+ DWC_ERROR("%s: host channel allocation failed\n", __func__);
8357+ goto error2;
8358+ }
8359+ memset(channel, 0, sizeof(dwc_hc_t));
8360+ channel->hc_num = i;
8361+ dwc_otg_hcd->hc_ptr_array[i] = channel;
8362+#ifdef DEBUG
8363+ init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
8364+#endif
8365+ DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
8366+ }
8367+
8368+ /* Initialize the Connection timeout timer. */
8369+ init_timer(&dwc_otg_hcd->conn_timer);
8370+
8371+ /* Initialize reset tasklet. */
8372+ reset_tasklet.data = (unsigned long) dwc_otg_hcd;
8373+ dwc_otg_hcd->reset_tasklet = &reset_tasklet;
8374+
8375+ /*
8376+ * Finish generic HCD initialization and start the HCD. This function
8377+ * allocates the DMA buffer pool, registers the USB bus, requests the
8378+ * IRQ line, and calls dwc_otg_hcd_start method.
8379+ */
8380+ retval = usb_add_hcd(hcd, otg_dev->irq, IRQF_SHARED);
8381+ if (retval < 0) {
8382+ goto error2;
8383+ }
8384+
8385+ /*
8386+ * Allocate space for storing data on status transactions. Normally no
8387+ * data is sent, but this space acts as a bit bucket. This must be
8388+ * done after usb_add_hcd since that function allocates the DMA buffer
8389+ * pool.
8390+ */
8391+ if (otg_dev->core_if->dma_enable) {
8392+ dwc_otg_hcd->status_buf =
8393+ dma_alloc_coherent(&pdev->dev,
8394+ DWC_OTG_HCD_STATUS_BUF_SIZE,
8395+ &dwc_otg_hcd->status_buf_dma,
8396+ GFP_KERNEL | GFP_DMA);
8397+ } else {
8398+ dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
8399+ GFP_KERNEL);
8400+ }
8401+ if (!dwc_otg_hcd->status_buf) {
8402+ retval = -ENOMEM;
8403+ DWC_ERROR("%s: status_buf allocation failed\n", __func__);
8404+ goto error3;
8405+ }
8406+
8407+ dwc_otg_hcd->otg_dev = otg_dev;
8408+
8409+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, usbbus=%d\n",
8410+ hcd->self.busnum);
8411+ return 0;
8412+
8413+ /* Error conditions */
8414+ error3:
8415+ usb_remove_hcd(hcd);
8416+ error2:
8417+ dwc_otg_hcd_free(hcd);
8418+ usb_put_hcd(hcd);
8419+ error1:
8420+ return retval;
8421+}
8422+
8423+/**
8424+ * Removes the HCD.
8425+ * Frees memory and resources associated with the HCD and deregisters the bus.
8426+ */
8427+void dwc_otg_hcd_remove(struct platform_device *pdev)
8428+{
8429+ dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev);
8430+ dwc_otg_hcd_t *dwc_otg_hcd;
8431+ struct usb_hcd *hcd;
8432+
8433+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE\n");
8434+
8435+ if (!otg_dev) {
8436+ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
8437+ return;
8438+ }
8439+
8440+ dwc_otg_hcd = otg_dev->hcd;
8441+
8442+ if (!dwc_otg_hcd) {
8443+ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
8444+ return;
8445+ }
8446+
8447+ hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
8448+
8449+ if (!hcd) {
8450+ DWC_DEBUGPL(DBG_ANY, "%s: dwc_otg_hcd_to_hcd(dwc_otg_hcd) NULL!\n", __func__);
8451+ return;
8452+ }
8453+
8454+ /* Turn off all interrupts */
8455+ dwc_write_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0);
8456+ dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gahbcfg, 1, 0);
8457+
8458+ usb_remove_hcd(hcd);
8459+ dwc_otg_hcd_free(hcd);
8460+ usb_put_hcd(hcd);
8461+}
8462+
8463+/* =========================================================================
8464+ * Linux HC Driver Functions
8465+ * ========================================================================= */
8466+
8467+/**
8468+ * Initializes dynamic portions of the DWC_otg HCD state.
8469+ */
8470+static void hcd_reinit(dwc_otg_hcd_t *hcd)
8471+{
8472+ struct list_head *item;
8473+ int num_channels;
8474+ int i;
8475+ dwc_hc_t *channel;
8476+
8477+ hcd->flags.d32 = 0;
8478+
8479+ hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
8480+ hcd->non_periodic_channels = 0;
8481+ hcd->periodic_channels = 0;
8482+
8483+ /*
8484+ * Put all channels in the free channel list and clean up channel
8485+ * states.
8486+ */
8487+ item = hcd->free_hc_list.next;
8488+ while (item != &hcd->free_hc_list) {
8489+ list_del(item);
8490+ item = hcd->free_hc_list.next;
8491+ }
8492+ num_channels = hcd->core_if->core_params->host_channels;
8493+ for (i = 0; i < num_channels; i++) {
8494+ channel = hcd->hc_ptr_array[i];
8495+ list_add_tail(&channel->hc_list_entry, &hcd->free_hc_list);
8496+ dwc_otg_hc_cleanup(hcd->core_if, channel);
8497+ }
8498+
8499+ /* Initialize the DWC core for host mode operation. */
8500+ dwc_otg_core_host_init(hcd->core_if);
8501+}
8502+
8503+/** Initializes the DWC_otg controller and its root hub and prepares it for host
8504+ * mode operation. Activates the root port. Returns 0 on success and a negative
8505+ * error code on failure. */
8506+int dwc_otg_hcd_start(struct usb_hcd *hcd)
8507+{
8508+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
8509+ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
8510+ struct usb_bus *bus;
8511+
8512+
8513+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
8514+
8515+ bus = hcd_to_bus(hcd);
8516+
8517+ /* Initialize the bus state. If the core is in Device Mode
8518+ * HALT the USB bus and return. */
8519+ if (dwc_otg_is_device_mode(core_if)) {
8520+ hcd->state = HC_STATE_RUNNING;
8521+ return 0;
8522+ }
8523+ hcd->state = HC_STATE_RUNNING;
8524+
8525+ /* Initialize and connect root hub if one is not already attached */
8526+ if (bus->root_hub) {
8527+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n");
8528+ /* Inform the HUB driver to resume. */
8529+ usb_hcd_resume_root_hub(hcd);
8530+ }
8531+ else {
8532+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Does Not Have Root Hub\n");
8533+ }
8534+
8535+ hcd_reinit(dwc_otg_hcd);
8536+
8537+ return 0;
8538+}
8539+
8540+static void qh_list_free(dwc_otg_hcd_t *hcd, struct list_head *qh_list)
8541+{
8542+ struct list_head *item;
8543+ dwc_otg_qh_t *qh;
8544+ unsigned long flags;
8545+
8546+ if (!qh_list->next) {
8547+ /* The list hasn't been initialized yet. */
8548+ return;
8549+ }
8550+
8551+ /* Ensure there are no QTDs or URBs left. */
8552+ kill_urbs_in_qh_list(hcd, qh_list);
8553+
8554+ SPIN_LOCK_IRQSAVE(&hcd->lock, flags);
8555+ for (item = qh_list->next; item != qh_list; item = qh_list->next) {
8556+ qh = list_entry(item, dwc_otg_qh_t, qh_list_entry);
8557+ dwc_otg_hcd_qh_remove_and_free(hcd, qh);
8558+ }
8559+ SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags);
8560+}
8561+
8562+/**
8563+ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
8564+ * stopped.
8565+ */
8566+void dwc_otg_hcd_stop(struct usb_hcd *hcd)
8567+{
8568+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
8569+ hprt0_data_t hprt0 = { .d32=0 };
8570+
8571+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
8572+
8573+ /* Turn off all host-specific interrupts. */
8574+ dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
8575+
8576+ /*
8577+ * The root hub should be disconnected before this function is called.
8578+ * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
8579+ * and the QH lists (via ..._hcd_endpoint_disable).
8580+ */
8581+
8582+ /* Turn off the vbus power */
8583+ DWC_PRINT("PortPower off\n");
8584+ hprt0.b.prtpwr = 0;
8585+ dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
8586+}
8587+
8588+/** Returns the current frame number. */
8589+int dwc_otg_hcd_get_frame_number(struct usb_hcd *hcd)
8590+{
8591+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
8592+ hfnum_data_t hfnum;
8593+
8594+ hfnum.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if->
8595+ host_if->host_global_regs->hfnum);
8596+
8597+#ifdef DEBUG_SOF
8598+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n", hfnum.b.frnum);
8599+#endif
8600+ return hfnum.b.frnum;
8601+}
8602+
8603+/**
8604+ * Frees secondary storage associated with the dwc_otg_hcd structure contained
8605+ * in the struct usb_hcd field.
8606+ */
8607+void dwc_otg_hcd_free(struct usb_hcd *hcd)
8608+{
8609+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
8610+ int i;
8611+
8612+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
8613+
8614+ del_timers(dwc_otg_hcd);
8615+
8616+ /* Free memory for QH/QTD lists */
8617+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
8618+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
8619+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
8620+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
8621+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
8622+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
8623+
8624+ /* Free memory for the host channels. */
8625+ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
8626+ dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
8627+ if (hc != NULL) {
8628+ DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n", i, hc);
8629+ kfree(hc);
8630+ }
8631+ }
8632+
8633+ if (dwc_otg_hcd->core_if->dma_enable) {
8634+ if (dwc_otg_hcd->status_buf_dma) {
8635+ dma_free_coherent(hcd->self.controller,
8636+ DWC_OTG_HCD_STATUS_BUF_SIZE,
8637+ dwc_otg_hcd->status_buf,
8638+ dwc_otg_hcd->status_buf_dma);
8639+ }
8640+ } else if (dwc_otg_hcd->status_buf != NULL) {
8641+ kfree(dwc_otg_hcd->status_buf);
8642+ }
8643+}
8644+
8645+#ifdef DEBUG
8646+static void dump_urb_info(struct urb *urb, char* fn_name)
8647+{
8648+ DWC_PRINT("%s, urb %p\n", fn_name, urb);
8649+ DWC_PRINT(" Device address: %d\n", usb_pipedevice(urb->pipe));
8650+ DWC_PRINT(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
8651+ (usb_pipein(urb->pipe) ? "IN" : "OUT"));
8652+ DWC_PRINT(" Endpoint type: %s\n",
8653+ ({char *pipetype;
8654+ switch (usb_pipetype(urb->pipe)) {
8655+ case PIPE_CONTROL: pipetype = "CONTROL"; break;
8656+ case PIPE_BULK: pipetype = "BULK"; break;
8657+ case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break;
8658+ case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break;
8659+ default: pipetype = "UNKNOWN"; break;
8660+ }; pipetype;}));
8661+ DWC_PRINT(" Speed: %s\n",
8662+ ({char *speed;
8663+ switch (urb->dev->speed) {
8664+ case USB_SPEED_HIGH: speed = "HIGH"; break;
8665+ case USB_SPEED_FULL: speed = "FULL"; break;
8666+ case USB_SPEED_LOW: speed = "LOW"; break;
8667+ default: speed = "UNKNOWN"; break;
8668+ }; speed;}));
8669+ DWC_PRINT(" Max packet size: %d\n",
8670+ usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
8671+ DWC_PRINT(" Data buffer length: %d\n", urb->transfer_buffer_length);
8672+ DWC_PRINT(" Transfer buffer: %p, Transfer DMA: %p\n",
8673+ urb->transfer_buffer, (void *)urb->transfer_dma);
8674+ DWC_PRINT(" Setup buffer: %p, Setup DMA: %p\n",
8675+ urb->setup_packet, (void *)urb->setup_dma);
8676+ DWC_PRINT(" Interval: %d\n", urb->interval);
8677+ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
8678+ int i;
8679+ for (i = 0; i < urb->number_of_packets; i++) {
8680+ DWC_PRINT(" ISO Desc %d:\n", i);
8681+ DWC_PRINT(" offset: %d, length %d\n",
8682+ urb->iso_frame_desc[i].offset,
8683+ urb->iso_frame_desc[i].length);
8684+ }
8685+ }
8686+}
8687+
8688+static void dump_channel_info(dwc_otg_hcd_t *hcd,
8689+ dwc_otg_qh_t *qh)
8690+{
8691+ if (qh->channel != NULL) {
8692+ dwc_hc_t *hc = qh->channel;
8693+ struct list_head *item;
8694+ dwc_otg_qh_t *qh_item;
8695+ int num_channels = hcd->core_if->core_params->host_channels;
8696+ int i;
8697+
8698+ dwc_otg_hc_regs_t *hc_regs;
8699+ hcchar_data_t hcchar;
8700+ hcsplt_data_t hcsplt;
8701+ hctsiz_data_t hctsiz;
8702+ uint32_t hcdma;
8703+
8704+ hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
8705+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8706+ hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
8707+ hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
8708+ hcdma = dwc_read_reg32(&hc_regs->hcdma);
8709+
8710+ DWC_PRINT(" Assigned to channel %p:\n", hc);
8711+ DWC_PRINT(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
8712+ DWC_PRINT(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
8713+ DWC_PRINT(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
8714+ hc->dev_addr, hc->ep_num, hc->ep_is_in);
8715+ DWC_PRINT(" ep_type: %d\n", hc->ep_type);
8716+ DWC_PRINT(" max_packet: %d\n", hc->max_packet);
8717+ DWC_PRINT(" data_pid_start: %d\n", hc->data_pid_start);
8718+ DWC_PRINT(" xfer_started: %d\n", hc->xfer_started);
8719+ DWC_PRINT(" halt_status: %d\n", hc->halt_status);
8720+ DWC_PRINT(" xfer_buff: %p\n", hc->xfer_buff);
8721+ DWC_PRINT(" xfer_len: %d\n", hc->xfer_len);
8722+ DWC_PRINT(" qh: %p\n", hc->qh);
8723+ DWC_PRINT(" NP inactive sched:\n");
8724+ list_for_each(item, &hcd->non_periodic_sched_inactive) {
8725+ qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
8726+ DWC_PRINT(" %p\n", qh_item);
8727+ }
8728+ DWC_PRINT(" NP active sched:\n");
8729+ list_for_each(item, &hcd->non_periodic_sched_active) {
8730+ qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
8731+ DWC_PRINT(" %p\n", qh_item);
8732+ }
8733+ DWC_PRINT(" Channels: \n");
8734+ for (i = 0; i < num_channels; i++) {
8735+ dwc_hc_t *hc = hcd->hc_ptr_array[i];
8736+ DWC_PRINT(" %2d: %p\n", i, hc);
8737+ }
8738+ }
8739+}
8740+#endif
8741+
8742+
8743+//OTG host require the DMA addr is DWORD-aligned,
8744+//patch it if the buffer is not DWORD-aligned
8745+inline
8746+void hcd_check_and_patch_dma_addr(struct urb *urb){
8747+
8748+ if((!urb->transfer_buffer)||!urb->transfer_dma||urb->transfer_dma==0xffffffff)
8749+ return;
8750+
8751+ if(((u32)urb->transfer_buffer)& 0x3){
8752+ /*
8753+ printk("%s: "
8754+ "urb(%.8x) "
8755+ "transfer_buffer=%.8x, "
8756+ "transfer_dma=%.8x, "
8757+ "transfer_buffer_length=%d, "
8758+ "actual_length=%d(%x), "
8759+ "\n",
8760+ ((urb->transfer_flags & URB_DIR_MASK)==URB_DIR_OUT)?"OUT":"IN",
8761+ urb,
8762+ urb->transfer_buffer,
8763+ urb->transfer_dma,
8764+ urb->transfer_buffer_length,
8765+ urb->actual_length,urb->actual_length
8766+ );
8767+ */
8768+ if(!urb->aligned_transfer_buffer||urb->aligned_transfer_buffer_length<urb->transfer_buffer_length){
8769+ urb->aligned_transfer_buffer_length=urb->transfer_buffer_length;
8770+ if(urb->aligned_transfer_buffer) {
8771+ kfree(urb->aligned_transfer_buffer);
8772+ }
8773+ urb->aligned_transfer_buffer=kmalloc(urb->aligned_transfer_buffer_length,GFP_KERNEL|GFP_DMA|GFP_ATOMIC);
8774+ urb->aligned_transfer_dma=dma_map_single(NULL,(void *)(urb->aligned_transfer_buffer),(urb->aligned_transfer_buffer_length),DMA_FROM_DEVICE);
8775+ if(!urb->aligned_transfer_buffer){
8776+ DWC_ERROR("Cannot alloc required buffer!!\n");
8777+ BUG();
8778+ }
8779+ //printk(" new allocated aligned_buf=%.8x aligned_buf_len=%d\n", (u32)urb->aligned_transfer_buffer, urb->aligned_transfer_buffer_length);
8780+ }
8781+ urb->transfer_dma=urb->aligned_transfer_dma;
8782+ if((urb->transfer_flags & URB_DIR_MASK)==URB_DIR_OUT) {
8783+ memcpy(urb->aligned_transfer_buffer,urb->transfer_buffer,urb->transfer_buffer_length);
8784+ dma_sync_single_for_device(NULL,urb->transfer_dma,urb->transfer_buffer_length,DMA_TO_DEVICE);
8785+ }
8786+ }
8787+}
8788+
8789+
8790+
8791+/** Starts processing a USB transfer request specified by a USB Request Block
8792+ * (URB). mem_flags indicates the type of memory allocation to use while
8793+ * processing this URB. */
8794+int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd,
8795+// struct usb_host_endpoint *ep,
8796+ struct urb *urb,
8797+ gfp_t mem_flags
8798+ )
8799+{
8800+ int retval = 0;
8801+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
8802+ dwc_otg_qtd_t *qtd;
8803+
8804+#ifdef DEBUG
8805+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
8806+ dump_urb_info(urb, "dwc_otg_hcd_urb_enqueue");
8807+ }
8808+#endif
8809+ if (!dwc_otg_hcd->flags.b.port_connect_status) {
8810+ /* No longer connected. */
8811+ return -ENODEV;
8812+ }
8813+
8814+ hcd_check_and_patch_dma_addr(urb);
8815+ qtd = dwc_otg_hcd_qtd_create(urb);
8816+ if (qtd == NULL) {
8817+ DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
8818+ return -ENOMEM;
8819+ }
8820+
8821+ retval = dwc_otg_hcd_qtd_add(qtd, dwc_otg_hcd);
8822+ if (retval < 0) {
8823+ DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
8824+ "Error status %d\n", retval);
8825+ dwc_otg_hcd_qtd_free(qtd);
8826+ }
8827+
8828+ return retval;
8829+}
8830+
8831+/** Aborts/cancels a USB transfer request. Always returns 0 to indicate
8832+ * success. */
8833+int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd,
8834+ struct urb *urb, int status)
8835+{
8836+ unsigned long flags;
8837+ dwc_otg_hcd_t *dwc_otg_hcd;
8838+ dwc_otg_qtd_t *urb_qtd;
8839+ dwc_otg_qh_t *qh;
8840+ struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb);
8841+
8842+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
8843+
8844+ dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
8845+
8846+ SPIN_LOCK_IRQSAVE(&dwc_otg_hcd->lock, flags);
8847+
8848+ urb_qtd = (dwc_otg_qtd_t *)urb->hcpriv;
8849+ qh = (dwc_otg_qh_t *)ep->hcpriv;
8850+
8851+ if (urb_qtd == NULL) {
8852+ SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
8853+ return 0;
8854+ }
8855+#ifdef DEBUG
8856+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
8857+ dump_urb_info(urb, "dwc_otg_hcd_urb_dequeue");
8858+ if (urb_qtd == qh->qtd_in_process) {
8859+ dump_channel_info(dwc_otg_hcd, qh);
8860+ }
8861+ }
8862+#endif
8863+
8864+ if (urb_qtd == qh->qtd_in_process) {
8865+ /* The QTD is in process (it has been assigned to a channel). */
8866+
8867+ if (dwc_otg_hcd->flags.b.port_connect_status) {
8868+ /*
8869+ * If still connected (i.e. in host mode), halt the
8870+ * channel so it can be used for other transfers. If
8871+ * no longer connected, the host registers can't be
8872+ * written to halt the channel since the core is in
8873+ * device mode.
8874+ */
8875+ dwc_otg_hc_halt(dwc_otg_hcd->core_if, qh->channel,
8876+ DWC_OTG_HC_XFER_URB_DEQUEUE);
8877+ }
8878+ }
8879+
8880+ /*
8881+ * Free the QTD and clean up the associated QH. Leave the QH in the
8882+ * schedule if it has any remaining QTDs.
8883+ */
8884+ dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd, urb_qtd);
8885+ if (urb_qtd == qh->qtd_in_process) {
8886+ /* Note that dwc_otg_hcd_qh_deactivate() locks the spin_lock again */
8887+ SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
8888+ dwc_otg_hcd_qh_deactivate(dwc_otg_hcd, qh, 0);
8889+ qh->channel = NULL;
8890+ qh->qtd_in_process = NULL;
8891+ } else {
8892+ if (list_empty(&qh->qtd_list))
8893+ dwc_otg_hcd_qh_remove(dwc_otg_hcd, qh);
8894+ SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
8895+ }
8896+
8897+ urb->hcpriv = NULL;
8898+
8899+ /* Higher layer software sets URB status. */
8900+ usb_hcd_giveback_urb(hcd, urb, status);
8901+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
8902+ DWC_PRINT("Called usb_hcd_giveback_urb()\n");
8903+ DWC_PRINT(" urb->status = %d\n", urb->status);
8904+ }
8905+
8906+ return 0;
8907+}
8908+
8909+/** Frees resources in the DWC_otg controller related to a given endpoint. Also
8910+ * clears state in the HCD related to the endpoint. Any URBs for the endpoint
8911+ * must already be dequeued. */
8912+void dwc_otg_hcd_endpoint_disable(struct usb_hcd *hcd,
8913+ struct usb_host_endpoint *ep)
8914+{
8915+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
8916+ dwc_otg_qh_t *qh;
8917+
8918+ unsigned long flags;
8919+ int retry = 0;
8920+
8921+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "
8922+ "endpoint=%d\n", ep->desc.bEndpointAddress,
8923+ dwc_ep_addr_to_endpoint(ep->desc.bEndpointAddress));
8924+
8925+rescan:
8926+ SPIN_LOCK_IRQSAVE(&dwc_otg_hcd->lock, flags);
8927+ qh = (dwc_otg_qh_t *)(ep->hcpriv);
8928+ if (!qh)
8929+ goto done;
8930+
8931+ /** Check that the QTD list is really empty */
8932+ if (!list_empty(&qh->qtd_list)) {
8933+ if (retry++ < 250) {
8934+ SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
8935+ schedule_timeout_uninterruptible(1);
8936+ goto rescan;
8937+ }
8938+
8939+ DWC_WARN("DWC OTG HCD EP DISABLE:"
8940+ " QTD List for this endpoint is not empty\n");
8941+ }
8942+
8943+ dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd, qh);
8944+ ep->hcpriv = NULL;
8945+done:
8946+ SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
8947+}
8948+
8949+/** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
8950+ * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
8951+ * interrupt.
8952+ *
8953+ * This function is called by the USB core when an interrupt occurs */
8954+irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd)
8955+{
8956+ int retVal = 0;
8957+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
8958+ retVal = dwc_otg_hcd_handle_intr(dwc_otg_hcd);
8959+ if (dwc_otg_hcd->flags.b.port_connect_status_change == 1)
8960+ usb_hcd_poll_rh_status(hcd);
8961+ return IRQ_RETVAL(retVal);
8962+}
8963+
8964+/** Creates Status Change bitmap for the root hub and root port. The bitmap is
8965+ * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
8966+ * is the status change indicator for the single root port. Returns 1 if either
8967+ * change indicator is 1, otherwise returns 0. */
8968+int dwc_otg_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
8969+{
8970+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
8971+
8972+ buf[0] = 0;
8973+ buf[0] |= (dwc_otg_hcd->flags.b.port_connect_status_change ||
8974+ dwc_otg_hcd->flags.b.port_reset_change ||
8975+ dwc_otg_hcd->flags.b.port_enable_change ||
8976+ dwc_otg_hcd->flags.b.port_suspend_change ||
8977+ dwc_otg_hcd->flags.b.port_over_current_change) << 1;
8978+
8979+#ifdef DEBUG
8980+ if (buf[0]) {
8981+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
8982+ " Root port status changed\n");
8983+ DWC_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n",
8984+ dwc_otg_hcd->flags.b.port_connect_status_change);
8985+ DWC_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n",
8986+ dwc_otg_hcd->flags.b.port_reset_change);
8987+ DWC_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n",
8988+ dwc_otg_hcd->flags.b.port_enable_change);
8989+ DWC_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n",
8990+ dwc_otg_hcd->flags.b.port_suspend_change);
8991+ DWC_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n",
8992+ dwc_otg_hcd->flags.b.port_over_current_change);
8993+ }
8994+#endif
8995+ return (buf[0] != 0);
8996+}
8997+
8998+#ifdef DWC_HS_ELECT_TST
8999+/*
9000+ * Quick and dirty hack to implement the HS Electrical Test
9001+ * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
9002+ *
9003+ * This code was copied from our userspace app "hset". It sends a
9004+ * Get Device Descriptor control sequence in two parts, first the
9005+ * Setup packet by itself, followed some time later by the In and
9006+ * Ack packets. Rather than trying to figure out how to add this
9007+ * functionality to the normal driver code, we just hijack the
9008+ * hardware, using these two function to drive the hardware
9009+ * directly.
9010+ */
9011+
9012+dwc_otg_core_global_regs_t *global_regs;
9013+dwc_otg_host_global_regs_t *hc_global_regs;
9014+dwc_otg_hc_regs_t *hc_regs;
9015+uint32_t *data_fifo;
9016+
9017+static void do_setup(void)
9018+{
9019+ gintsts_data_t gintsts;
9020+ hctsiz_data_t hctsiz;
9021+ hcchar_data_t hcchar;
9022+ haint_data_t haint;
9023+ hcint_data_t hcint;
9024+
9025+ /* Enable HAINTs */
9026+ dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
9027+
9028+ /* Enable HCINTs */
9029+ dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
9030+
9031+ /* Read GINTSTS */
9032+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9033+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
9034+
9035+ /* Read HAINT */
9036+ haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
9037+ //fprintf(stderr, "HAINT: %08x\n", haint.d32);
9038+
9039+ /* Read HCINT */
9040+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
9041+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
9042+
9043+ /* Read HCCHAR */
9044+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9045+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
9046+
9047+ /* Clear HCINT */
9048+ dwc_write_reg32(&hc_regs->hcint, hcint.d32);
9049+
9050+ /* Clear HAINT */
9051+ dwc_write_reg32(&hc_global_regs->haint, haint.d32);
9052+
9053+ /* Clear GINTSTS */
9054+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
9055+
9056+ /* Read GINTSTS */
9057+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9058+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
9059+
9060+ /*
9061+ * Send Setup packet (Get Device Descriptor)
9062+ */
9063+
9064+ /* Make sure channel is disabled */
9065+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9066+ if (hcchar.b.chen) {
9067+ //fprintf(stderr, "Channel already enabled 1, HCCHAR = %08x\n", hcchar.d32);
9068+ hcchar.b.chdis = 1;
9069+// hcchar.b.chen = 1;
9070+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
9071+ //sleep(1);
9072+ mdelay(1000);
9073+
9074+ /* Read GINTSTS */
9075+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9076+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
9077+
9078+ /* Read HAINT */
9079+ haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
9080+ //fprintf(stderr, "HAINT: %08x\n", haint.d32);
9081+
9082+ /* Read HCINT */
9083+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
9084+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
9085+
9086+ /* Read HCCHAR */
9087+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9088+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
9089+
9090+ /* Clear HCINT */
9091+ dwc_write_reg32(&hc_regs->hcint, hcint.d32);
9092+
9093+ /* Clear HAINT */
9094+ dwc_write_reg32(&hc_global_regs->haint, haint.d32);
9095+
9096+ /* Clear GINTSTS */
9097+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
9098+
9099+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9100+ //if (hcchar.b.chen) {
9101+ // fprintf(stderr, "** Channel _still_ enabled 1, HCCHAR = %08x **\n", hcchar.d32);
9102+ //}
9103+ }
9104+
9105+ /* Set HCTSIZ */
9106+ hctsiz.d32 = 0;
9107+ hctsiz.b.xfersize = 8;
9108+ hctsiz.b.pktcnt = 1;
9109+ hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
9110+ dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
9111+
9112+ /* Set HCCHAR */
9113+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9114+ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
9115+ hcchar.b.epdir = 0;
9116+ hcchar.b.epnum = 0;
9117+ hcchar.b.mps = 8;
9118+ hcchar.b.chen = 1;
9119+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
9120+
9121+ /* Fill FIFO with Setup data for Get Device Descriptor */
9122+ data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
9123+ dwc_write_reg32(data_fifo++, 0x01000680);
9124+ dwc_write_reg32(data_fifo++, 0x00080000);
9125+
9126+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9127+ //fprintf(stderr, "Waiting for HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
9128+
9129+ /* Wait for host channel interrupt */
9130+ do {
9131+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9132+ } while (gintsts.b.hcintr == 0);
9133+
9134+ //fprintf(stderr, "Got HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
9135+
9136+ /* Disable HCINTs */
9137+ dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
9138+
9139+ /* Disable HAINTs */
9140+ dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
9141+
9142+ /* Read HAINT */
9143+ haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
9144+ //fprintf(stderr, "HAINT: %08x\n", haint.d32);
9145+
9146+ /* Read HCINT */
9147+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
9148+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
9149+
9150+ /* Read HCCHAR */
9151+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9152+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
9153+
9154+ /* Clear HCINT */
9155+ dwc_write_reg32(&hc_regs->hcint, hcint.d32);
9156+
9157+ /* Clear HAINT */
9158+ dwc_write_reg32(&hc_global_regs->haint, haint.d32);
9159+
9160+ /* Clear GINTSTS */
9161+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
9162+
9163+ /* Read GINTSTS */
9164+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9165+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
9166+}
9167+
9168+static void do_in_ack(void)
9169+{
9170+ gintsts_data_t gintsts;
9171+ hctsiz_data_t hctsiz;
9172+ hcchar_data_t hcchar;
9173+ haint_data_t haint;
9174+ hcint_data_t hcint;
9175+ host_grxsts_data_t grxsts;
9176+
9177+ /* Enable HAINTs */
9178+ dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
9179+
9180+ /* Enable HCINTs */
9181+ dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
9182+
9183+ /* Read GINTSTS */
9184+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9185+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
9186+
9187+ /* Read HAINT */
9188+ haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
9189+ //fprintf(stderr, "HAINT: %08x\n", haint.d32);
9190+
9191+ /* Read HCINT */
9192+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
9193+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
9194+
9195+ /* Read HCCHAR */
9196+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9197+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
9198+
9199+ /* Clear HCINT */
9200+ dwc_write_reg32(&hc_regs->hcint, hcint.d32);
9201+
9202+ /* Clear HAINT */
9203+ dwc_write_reg32(&hc_global_regs->haint, haint.d32);
9204+
9205+ /* Clear GINTSTS */
9206+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
9207+
9208+ /* Read GINTSTS */
9209+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9210+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
9211+
9212+ /*
9213+ * Receive Control In packet
9214+ */
9215+
9216+ /* Make sure channel is disabled */
9217+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9218+ if (hcchar.b.chen) {
9219+ //fprintf(stderr, "Channel already enabled 2, HCCHAR = %08x\n", hcchar.d32);
9220+ hcchar.b.chdis = 1;
9221+ hcchar.b.chen = 1;
9222+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
9223+ //sleep(1);
9224+ mdelay(1000);
9225+
9226+ /* Read GINTSTS */
9227+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9228+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
9229+
9230+ /* Read HAINT */
9231+ haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
9232+ //fprintf(stderr, "HAINT: %08x\n", haint.d32);
9233+
9234+ /* Read HCINT */
9235+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
9236+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
9237+
9238+ /* Read HCCHAR */
9239+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9240+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
9241+
9242+ /* Clear HCINT */
9243+ dwc_write_reg32(&hc_regs->hcint, hcint.d32);
9244+
9245+ /* Clear HAINT */
9246+ dwc_write_reg32(&hc_global_regs->haint, haint.d32);
9247+
9248+ /* Clear GINTSTS */
9249+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
9250+
9251+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9252+ //if (hcchar.b.chen) {
9253+ // fprintf(stderr, "** Channel _still_ enabled 2, HCCHAR = %08x **\n", hcchar.d32);
9254+ //}
9255+ }
9256+
9257+ /* Set HCTSIZ */
9258+ hctsiz.d32 = 0;
9259+ hctsiz.b.xfersize = 8;
9260+ hctsiz.b.pktcnt = 1;
9261+ hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
9262+ dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
9263+
9264+ /* Set HCCHAR */
9265+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9266+ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
9267+ hcchar.b.epdir = 1;
9268+ hcchar.b.epnum = 0;
9269+ hcchar.b.mps = 8;
9270+ hcchar.b.chen = 1;
9271+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
9272+
9273+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9274+ //fprintf(stderr, "Waiting for RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
9275+
9276+ /* Wait for receive status queue interrupt */
9277+ do {
9278+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9279+ } while (gintsts.b.rxstsqlvl == 0);
9280+
9281+ //fprintf(stderr, "Got RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
9282+
9283+ /* Read RXSTS */
9284+ grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
9285+ //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
9286+
9287+ /* Clear RXSTSQLVL in GINTSTS */
9288+ gintsts.d32 = 0;
9289+ gintsts.b.rxstsqlvl = 1;
9290+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
9291+
9292+ switch (grxsts.b.pktsts) {
9293+ case DWC_GRXSTS_PKTSTS_IN:
9294+ /* Read the data into the host buffer */
9295+ if (grxsts.b.bcnt > 0) {
9296+ int i;
9297+ int word_count = (grxsts.b.bcnt + 3) / 4;
9298+
9299+ data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
9300+
9301+ for (i = 0; i < word_count; i++) {
9302+ (void)dwc_read_reg32(data_fifo++);
9303+ }
9304+ }
9305+
9306+ //fprintf(stderr, "Received %u bytes\n", (unsigned)grxsts.b.bcnt);
9307+ break;
9308+
9309+ default:
9310+ //fprintf(stderr, "** Unexpected GRXSTS packet status 1 **\n");
9311+ break;
9312+ }
9313+
9314+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9315+ //fprintf(stderr, "Waiting for RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
9316+
9317+ /* Wait for receive status queue interrupt */
9318+ do {
9319+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9320+ } while (gintsts.b.rxstsqlvl == 0);
9321+
9322+ //fprintf(stderr, "Got RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
9323+
9324+ /* Read RXSTS */
9325+ grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
9326+ //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
9327+
9328+ /* Clear RXSTSQLVL in GINTSTS */
9329+ gintsts.d32 = 0;
9330+ gintsts.b.rxstsqlvl = 1;
9331+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
9332+
9333+ switch (grxsts.b.pktsts) {
9334+ case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
9335+ break;
9336+
9337+ default:
9338+ //fprintf(stderr, "** Unexpected GRXSTS packet status 2 **\n");
9339+ break;
9340+ }
9341+
9342+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9343+ //fprintf(stderr, "Waiting for HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
9344+
9345+ /* Wait for host channel interrupt */
9346+ do {
9347+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9348+ } while (gintsts.b.hcintr == 0);
9349+
9350+ //fprintf(stderr, "Got HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
9351+
9352+ /* Read HAINT */
9353+ haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
9354+ //fprintf(stderr, "HAINT: %08x\n", haint.d32);
9355+
9356+ /* Read HCINT */
9357+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
9358+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
9359+
9360+ /* Read HCCHAR */
9361+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9362+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
9363+
9364+ /* Clear HCINT */
9365+ dwc_write_reg32(&hc_regs->hcint, hcint.d32);
9366+
9367+ /* Clear HAINT */
9368+ dwc_write_reg32(&hc_global_regs->haint, haint.d32);
9369+
9370+ /* Clear GINTSTS */
9371+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
9372+
9373+ /* Read GINTSTS */
9374+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9375+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
9376+
9377+// usleep(100000);
9378+// mdelay(100);
9379+ mdelay(1);
9380+
9381+ /*
9382+ * Send handshake packet
9383+ */
9384+
9385+ /* Read HAINT */
9386+ haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
9387+ //fprintf(stderr, "HAINT: %08x\n", haint.d32);
9388+
9389+ /* Read HCINT */
9390+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
9391+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
9392+
9393+ /* Read HCCHAR */
9394+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9395+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
9396+
9397+ /* Clear HCINT */
9398+ dwc_write_reg32(&hc_regs->hcint, hcint.d32);
9399+
9400+ /* Clear HAINT */
9401+ dwc_write_reg32(&hc_global_regs->haint, haint.d32);
9402+
9403+ /* Clear GINTSTS */
9404+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
9405+
9406+ /* Read GINTSTS */
9407+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9408+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
9409+
9410+ /* Make sure channel is disabled */
9411+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9412+ if (hcchar.b.chen) {
9413+ //fprintf(stderr, "Channel already enabled 3, HCCHAR = %08x\n", hcchar.d32);
9414+ hcchar.b.chdis = 1;
9415+ hcchar.b.chen = 1;
9416+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
9417+ //sleep(1);
9418+ mdelay(1000);
9419+
9420+ /* Read GINTSTS */
9421+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9422+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
9423+
9424+ /* Read HAINT */
9425+ haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
9426+ //fprintf(stderr, "HAINT: %08x\n", haint.d32);
9427+
9428+ /* Read HCINT */
9429+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
9430+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
9431+
9432+ /* Read HCCHAR */
9433+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9434+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
9435+
9436+ /* Clear HCINT */
9437+ dwc_write_reg32(&hc_regs->hcint, hcint.d32);
9438+
9439+ /* Clear HAINT */
9440+ dwc_write_reg32(&hc_global_regs->haint, haint.d32);
9441+
9442+ /* Clear GINTSTS */
9443+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
9444+
9445+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9446+ //if (hcchar.b.chen) {
9447+ // fprintf(stderr, "** Channel _still_ enabled 3, HCCHAR = %08x **\n", hcchar.d32);
9448+ //}
9449+ }
9450+
9451+ /* Set HCTSIZ */
9452+ hctsiz.d32 = 0;
9453+ hctsiz.b.xfersize = 0;
9454+ hctsiz.b.pktcnt = 1;
9455+ hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
9456+ dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
9457+
9458+ /* Set HCCHAR */
9459+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9460+ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
9461+ hcchar.b.epdir = 0;
9462+ hcchar.b.epnum = 0;
9463+ hcchar.b.mps = 8;
9464+ hcchar.b.chen = 1;
9465+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
9466+
9467+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9468+ //fprintf(stderr, "Waiting for HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
9469+
9470+ /* Wait for host channel interrupt */
9471+ do {
9472+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9473+ } while (gintsts.b.hcintr == 0);
9474+
9475+ //fprintf(stderr, "Got HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
9476+
9477+ /* Disable HCINTs */
9478+ dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
9479+
9480+ /* Disable HAINTs */
9481+ dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
9482+
9483+ /* Read HAINT */
9484+ haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
9485+ //fprintf(stderr, "HAINT: %08x\n", haint.d32);
9486+
9487+ /* Read HCINT */
9488+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
9489+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
9490+
9491+ /* Read HCCHAR */
9492+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
9493+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
9494+
9495+ /* Clear HCINT */
9496+ dwc_write_reg32(&hc_regs->hcint, hcint.d32);
9497+
9498+ /* Clear HAINT */
9499+ dwc_write_reg32(&hc_global_regs->haint, haint.d32);
9500+
9501+ /* Clear GINTSTS */
9502+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
9503+
9504+ /* Read GINTSTS */
9505+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
9506+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
9507+}
9508+#endif /* DWC_HS_ELECT_TST */
9509+
9510+/** Handles hub class-specific requests. */
9511+int dwc_otg_hcd_hub_control(struct usb_hcd *hcd,
9512+ u16 typeReq,
9513+ u16 wValue,
9514+ u16 wIndex,
9515+ char *buf,
9516+ u16 wLength)
9517+{
9518+ int retval = 0;
9519+
9520+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
9521+ dwc_otg_core_if_t *core_if = hcd_to_dwc_otg_hcd(hcd)->core_if;
9522+ struct usb_hub_descriptor *desc;
9523+ hprt0_data_t hprt0 = {.d32 = 0};
9524+
9525+ uint32_t port_status;
9526+
9527+ switch (typeReq) {
9528+ case ClearHubFeature:
9529+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9530+ "ClearHubFeature 0x%x\n", wValue);
9531+ switch (wValue) {
9532+ case C_HUB_LOCAL_POWER:
9533+ case C_HUB_OVER_CURRENT:
9534+ /* Nothing required here */
9535+ break;
9536+ default:
9537+ retval = -EINVAL;
9538+ DWC_ERROR("DWC OTG HCD - "
9539+ "ClearHubFeature request %xh unknown\n", wValue);
9540+ }
9541+ break;
9542+ case ClearPortFeature:
9543+ if (!wIndex || wIndex > 1)
9544+ goto error;
9545+
9546+ switch (wValue) {
9547+ case USB_PORT_FEAT_ENABLE:
9548+ DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
9549+ "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
9550+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
9551+ hprt0.b.prtena = 1;
9552+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9553+ break;
9554+ case USB_PORT_FEAT_SUSPEND:
9555+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9556+ "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
9557+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
9558+ hprt0.b.prtres = 1;
9559+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9560+ /* Clear Resume bit */
9561+ mdelay(100);
9562+ hprt0.b.prtres = 0;
9563+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9564+ break;
9565+ case USB_PORT_FEAT_POWER:
9566+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9567+ "ClearPortFeature USB_PORT_FEAT_POWER\n");
9568+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
9569+ hprt0.b.prtpwr = 0;
9570+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9571+ break;
9572+ case USB_PORT_FEAT_INDICATOR:
9573+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9574+ "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
9575+ /* Port inidicator not supported */
9576+ break;
9577+ case USB_PORT_FEAT_C_CONNECTION:
9578+ /* Clears drivers internal connect status change
9579+ * flag */
9580+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9581+ "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
9582+ dwc_otg_hcd->flags.b.port_connect_status_change = 0;
9583+ break;
9584+ case USB_PORT_FEAT_C_RESET:
9585+ /* Clears the driver's internal Port Reset Change
9586+ * flag */
9587+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9588+ "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
9589+ dwc_otg_hcd->flags.b.port_reset_change = 0;
9590+ break;
9591+ case USB_PORT_FEAT_C_ENABLE:
9592+ /* Clears the driver's internal Port
9593+ * Enable/Disable Change flag */
9594+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9595+ "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
9596+ dwc_otg_hcd->flags.b.port_enable_change = 0;
9597+ break;
9598+ case USB_PORT_FEAT_C_SUSPEND:
9599+ /* Clears the driver's internal Port Suspend
9600+ * Change flag, which is set when resume signaling on
9601+ * the host port is complete */
9602+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9603+ "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
9604+ dwc_otg_hcd->flags.b.port_suspend_change = 0;
9605+ break;
9606+ case USB_PORT_FEAT_C_OVER_CURRENT:
9607+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9608+ "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
9609+ dwc_otg_hcd->flags.b.port_over_current_change = 0;
9610+ break;
9611+ default:
9612+ retval = -EINVAL;
9613+ DWC_ERROR("DWC OTG HCD - "
9614+ "ClearPortFeature request %xh "
9615+ "unknown or unsupported\n", wValue);
9616+ }
9617+ break;
9618+ case GetHubDescriptor:
9619+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9620+ "GetHubDescriptor\n");
9621+ desc = (struct usb_hub_descriptor *)buf;
9622+ desc->bDescLength = 9;
9623+ desc->bDescriptorType = 0x29;
9624+ desc->bNbrPorts = 1;
9625+ desc->wHubCharacteristics = 0x08;
9626+ desc->bPwrOn2PwrGood = 1;
9627+ desc->bHubContrCurrent = 0;
9628+ desc->u.hs.DeviceRemovable[0] = 0;
9629+ desc->u.hs.DeviceRemovable[1] = 0xff;
9630+ break;
9631+ case GetHubStatus:
9632+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9633+ "GetHubStatus\n");
9634+ memset(buf, 0, 4);
9635+ break;
9636+ case GetPortStatus:
9637+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9638+ "GetPortStatus\n");
9639+
9640+ if (!wIndex || wIndex > 1)
9641+ goto error;
9642+
9643+ port_status = 0;
9644+
9645+ if (dwc_otg_hcd->flags.b.port_connect_status_change)
9646+ port_status |= (1 << USB_PORT_FEAT_C_CONNECTION);
9647+
9648+ if (dwc_otg_hcd->flags.b.port_enable_change)
9649+ port_status |= (1 << USB_PORT_FEAT_C_ENABLE);
9650+
9651+ if (dwc_otg_hcd->flags.b.port_suspend_change)
9652+ port_status |= (1 << USB_PORT_FEAT_C_SUSPEND);
9653+
9654+ if (dwc_otg_hcd->flags.b.port_reset_change)
9655+ port_status |= (1 << USB_PORT_FEAT_C_RESET);
9656+
9657+ if (dwc_otg_hcd->flags.b.port_over_current_change) {
9658+ DWC_ERROR("Device Not Supported\n");
9659+ port_status |= (1 << USB_PORT_FEAT_C_OVER_CURRENT);
9660+ }
9661+
9662+ if (!dwc_otg_hcd->flags.b.port_connect_status) {
9663+ /*
9664+ * The port is disconnected, which means the core is
9665+ * either in device mode or it soon will be. Just
9666+ * return 0's for the remainder of the port status
9667+ * since the port register can't be read if the core
9668+ * is in device mode.
9669+ */
9670+ *((__le32 *) buf) = cpu_to_le32(port_status);
9671+ break;
9672+ }
9673+
9674+ hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
9675+ DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32);
9676+
9677+ if (hprt0.b.prtconnsts)
9678+ port_status |= (1 << USB_PORT_FEAT_CONNECTION);
9679+
9680+ if (hprt0.b.prtena)
9681+ port_status |= (1 << USB_PORT_FEAT_ENABLE);
9682+
9683+ if (hprt0.b.prtsusp)
9684+ port_status |= (1 << USB_PORT_FEAT_SUSPEND);
9685+
9686+ if (hprt0.b.prtovrcurract)
9687+ port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT);
9688+
9689+ if (hprt0.b.prtrst)
9690+ port_status |= (1 << USB_PORT_FEAT_RESET);
9691+
9692+ if (hprt0.b.prtpwr)
9693+ port_status |= (1 << USB_PORT_FEAT_POWER);
9694+
9695+ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
9696+ port_status |= (USB_PORT_STAT_HIGH_SPEED);
9697+ else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
9698+ port_status |= (USB_PORT_STAT_LOW_SPEED);
9699+
9700+ if (hprt0.b.prttstctl)
9701+ port_status |= (1 << USB_PORT_FEAT_TEST);
9702+
9703+ /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
9704+
9705+ *((__le32 *) buf) = cpu_to_le32(port_status);
9706+
9707+ break;
9708+ case SetHubFeature:
9709+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9710+ "SetHubFeature\n");
9711+ /* No HUB features supported */
9712+ break;
9713+ case SetPortFeature:
9714+ if (wValue != USB_PORT_FEAT_TEST && (!wIndex || wIndex > 1))
9715+ goto error;
9716+
9717+ if (!dwc_otg_hcd->flags.b.port_connect_status) {
9718+ /*
9719+ * The port is disconnected, which means the core is
9720+ * either in device mode or it soon will be. Just
9721+ * return without doing anything since the port
9722+ * register can't be written if the core is in device
9723+ * mode.
9724+ */
9725+ break;
9726+ }
9727+
9728+ switch (wValue) {
9729+ case USB_PORT_FEAT_SUSPEND:
9730+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9731+ "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
9732+ if (hcd->self.otg_port == wIndex &&
9733+ hcd->self.b_hnp_enable) {
9734+ gotgctl_data_t gotgctl = {.d32=0};
9735+ gotgctl.b.hstsethnpen = 1;
9736+ dwc_modify_reg32(&core_if->core_global_regs->gotgctl,
9737+ 0, gotgctl.d32);
9738+ core_if->op_state = A_SUSPEND;
9739+ }
9740+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
9741+ hprt0.b.prtsusp = 1;
9742+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9743+ //DWC_PRINT("SUSPEND: HPRT0=%0x\n", hprt0.d32);
9744+ /* Suspend the Phy Clock */
9745+ {
9746+ pcgcctl_data_t pcgcctl = {.d32=0};
9747+ pcgcctl.b.stoppclk = 1;
9748+ dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
9749+ }
9750+
9751+ /* For HNP the bus must be suspended for at least 200ms. */
9752+ if (hcd->self.b_hnp_enable) {
9753+ mdelay(200);
9754+ //DWC_PRINT("SUSPEND: wait complete! (%d)\n", _hcd->state);
9755+ }
9756+ break;
9757+ case USB_PORT_FEAT_POWER:
9758+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9759+ "SetPortFeature - USB_PORT_FEAT_POWER\n");
9760+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
9761+ hprt0.b.prtpwr = 1;
9762+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9763+ break;
9764+ case USB_PORT_FEAT_RESET:
9765+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9766+ "SetPortFeature - USB_PORT_FEAT_RESET\n");
9767+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
9768+ /* When B-Host the Port reset bit is set in
9769+ * the Start HCD Callback function, so that
9770+ * the reset is started within 1ms of the HNP
9771+ * success interrupt. */
9772+ if (!hcd->self.is_b_host) {
9773+ hprt0.b.prtrst = 1;
9774+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9775+ }
9776+ /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
9777+ MDELAY(60);
9778+ hprt0.b.prtrst = 0;
9779+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9780+ break;
9781+
9782+#ifdef DWC_HS_ELECT_TST
9783+ case USB_PORT_FEAT_TEST:
9784+ {
9785+ uint32_t t;
9786+ gintmsk_data_t gintmsk;
9787+
9788+ t = (wIndex >> 8); /* MSB wIndex USB */
9789+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9790+ "SetPortFeature - USB_PORT_FEAT_TEST %d\n", t);
9791+ warn("USB_PORT_FEAT_TEST %d\n", t);
9792+ if (t < 6) {
9793+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
9794+ hprt0.b.prttstctl = t;
9795+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9796+ } else {
9797+ /* Setup global vars with reg addresses (quick and
9798+ * dirty hack, should be cleaned up)
9799+ */
9800+ global_regs = core_if->core_global_regs;
9801+ hc_global_regs = core_if->host_if->host_global_regs;
9802+ hc_regs = (dwc_otg_hc_regs_t *)((char *)global_regs + 0x500);
9803+ data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
9804+
9805+ if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */
9806+ /* Save current interrupt mask */
9807+ gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
9808+
9809+ /* Disable all interrupts while we muck with
9810+ * the hardware directly
9811+ */
9812+ dwc_write_reg32(&global_regs->gintmsk, 0);
9813+
9814+ /* 15 second delay per the test spec */
9815+ mdelay(15000);
9816+
9817+ /* Drive suspend on the root port */
9818+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
9819+ hprt0.b.prtsusp = 1;
9820+ hprt0.b.prtres = 0;
9821+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9822+
9823+ /* 15 second delay per the test spec */
9824+ mdelay(15000);
9825+
9826+ /* Drive resume on the root port */
9827+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
9828+ hprt0.b.prtsusp = 0;
9829+ hprt0.b.prtres = 1;
9830+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9831+ mdelay(100);
9832+
9833+ /* Clear the resume bit */
9834+ hprt0.b.prtres = 0;
9835+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
9836+
9837+ /* Restore interrupts */
9838+ dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
9839+ } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
9840+ /* Save current interrupt mask */
9841+ gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
9842+
9843+ /* Disable all interrupts while we muck with
9844+ * the hardware directly
9845+ */
9846+ dwc_write_reg32(&global_regs->gintmsk, 0);
9847+
9848+ /* 15 second delay per the test spec */
9849+ mdelay(15000);
9850+
9851+ /* Send the Setup packet */
9852+ do_setup();
9853+
9854+ /* 15 second delay so nothing else happens for awhile */
9855+ mdelay(15000);
9856+
9857+ /* Restore interrupts */
9858+ dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
9859+ } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
9860+ /* Save current interrupt mask */
9861+ gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
9862+
9863+ /* Disable all interrupts while we muck with
9864+ * the hardware directly
9865+ */
9866+ dwc_write_reg32(&global_regs->gintmsk, 0);
9867+
9868+ /* Send the Setup packet */
9869+ do_setup();
9870+
9871+ /* 15 second delay so nothing else happens for awhile */
9872+ mdelay(15000);
9873+
9874+ /* Send the In and Ack packets */
9875+ do_in_ack();
9876+
9877+ /* 15 second delay so nothing else happens for awhile */
9878+ mdelay(15000);
9879+
9880+ /* Restore interrupts */
9881+ dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
9882+ }
9883+ }
9884+ break;
9885+ }
9886+#endif /* DWC_HS_ELECT_TST */
9887+
9888+ case USB_PORT_FEAT_INDICATOR:
9889+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9890+ "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
9891+ /* Not supported */
9892+ break;
9893+ default:
9894+ retval = -EINVAL;
9895+ DWC_ERROR("DWC OTG HCD - "
9896+ "SetPortFeature request %xh "
9897+ "unknown or unsupported\n", wValue);
9898+ break;
9899+ }
9900+ break;
9901+ default:
9902+ error:
9903+ retval = -EINVAL;
9904+ DWC_WARN("DWC OTG HCD - "
9905+ "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
9906+ typeReq, wIndex, wValue);
9907+ break;
9908+ }
9909+
9910+ return retval;
9911+}
9912+
9913+/**
9914+ * Assigns transactions from a QTD to a free host channel and initializes the
9915+ * host channel to perform the transactions. The host channel is removed from
9916+ * the free list.
9917+ *
9918+ * @param hcd The HCD state structure.
9919+ * @param qh Transactions from the first QTD for this QH are selected and
9920+ * assigned to a free host channel.
9921+ */
9922+static void assign_and_init_hc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
9923+{
9924+ dwc_hc_t *hc;
9925+ dwc_otg_qtd_t *qtd;
9926+ struct urb *urb;
9927+
9928+ DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, hcd, qh);
9929+
9930+ hc = list_entry(hcd->free_hc_list.next, dwc_hc_t, hc_list_entry);
9931+
9932+ /* Remove the host channel from the free list. */
9933+ list_del_init(&hc->hc_list_entry);
9934+
9935+ qtd = list_entry(qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
9936+ urb = qtd->urb;
9937+ qh->channel = hc;
9938+ qh->qtd_in_process = qtd;
9939+
9940+ /*
9941+ * Use usb_pipedevice to determine device address. This address is
9942+ * 0 before the SET_ADDRESS command and the correct address afterward.
9943+ */
9944+ hc->dev_addr = usb_pipedevice(urb->pipe);
9945+ hc->ep_num = usb_pipeendpoint(urb->pipe);
9946+
9947+ if (urb->dev->speed == USB_SPEED_LOW) {
9948+ hc->speed = DWC_OTG_EP_SPEED_LOW;
9949+ } else if (urb->dev->speed == USB_SPEED_FULL) {
9950+ hc->speed = DWC_OTG_EP_SPEED_FULL;
9951+ } else {
9952+ hc->speed = DWC_OTG_EP_SPEED_HIGH;
9953+ }
9954+
9955+ hc->max_packet = dwc_max_packet(qh->maxp);
9956+
9957+ hc->xfer_started = 0;
9958+ hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
9959+ hc->error_state = (qtd->error_count > 0);
9960+ hc->halt_on_queue = 0;
9961+ hc->halt_pending = 0;
9962+ hc->requests = 0;
9963+
9964+ /*
9965+ * The following values may be modified in the transfer type section
9966+ * below. The xfer_len value may be reduced when the transfer is
9967+ * started to accommodate the max widths of the XferSize and PktCnt
9968+ * fields in the HCTSIZn register.
9969+ */
9970+ hc->do_ping = qh->ping_state;
9971+ hc->ep_is_in = (usb_pipein(urb->pipe) != 0);
9972+ hc->data_pid_start = qh->data_toggle;
9973+ hc->multi_count = 1;
9974+
9975+ if (hcd->core_if->dma_enable) {
9976+ hc->xfer_buff = (uint8_t *)urb->transfer_dma + urb->actual_length;
9977+ } else {
9978+ hc->xfer_buff = (uint8_t *)urb->transfer_buffer + urb->actual_length;
9979+ }
9980+ hc->xfer_len = urb->transfer_buffer_length - urb->actual_length;
9981+ hc->xfer_count = 0;
9982+
9983+ /*
9984+ * Set the split attributes
9985+ */
9986+ hc->do_split = 0;
9987+ if (qh->do_split) {
9988+ hc->do_split = 1;
9989+ hc->xact_pos = qtd->isoc_split_pos;
9990+ hc->complete_split = qtd->complete_split;
9991+ hc->hub_addr = urb->dev->tt->hub->devnum;
9992+ hc->port_addr = urb->dev->ttport;
9993+ }
9994+
9995+ switch (usb_pipetype(urb->pipe)) {
9996+ case PIPE_CONTROL:
9997+ hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
9998+ switch (qtd->control_phase) {
9999+ case DWC_OTG_CONTROL_SETUP:
10000+ DWC_DEBUGPL(DBG_HCDV, " Control setup transaction\n");
10001+ hc->do_ping = 0;
10002+ hc->ep_is_in = 0;
10003+ hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
10004+ if (hcd->core_if->dma_enable) {
10005+ hc->xfer_buff = (uint8_t *)urb->setup_dma;
10006+ } else {
10007+ hc->xfer_buff = (uint8_t *)urb->setup_packet;
10008+ }
10009+ hc->xfer_len = 8;
10010+ break;
10011+ case DWC_OTG_CONTROL_DATA:
10012+ DWC_DEBUGPL(DBG_HCDV, " Control data transaction\n");
10013+ hc->data_pid_start = qtd->data_toggle;
10014+ break;
10015+ case DWC_OTG_CONTROL_STATUS:
10016+ /*
10017+ * Direction is opposite of data direction or IN if no
10018+ * data.
10019+ */
10020+ DWC_DEBUGPL(DBG_HCDV, " Control status transaction\n");
10021+ if (urb->transfer_buffer_length == 0) {
10022+ hc->ep_is_in = 1;
10023+ } else {
10024+ hc->ep_is_in = (usb_pipein(urb->pipe) != USB_DIR_IN);
10025+ }
10026+ if (hc->ep_is_in) {
10027+ hc->do_ping = 0;
10028+ }
10029+ hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
10030+ hc->xfer_len = 0;
10031+ if (hcd->core_if->dma_enable) {
10032+ hc->xfer_buff = (uint8_t *)hcd->status_buf_dma;
10033+ } else {
10034+ hc->xfer_buff = (uint8_t *)hcd->status_buf;
10035+ }
10036+ break;
10037+ }
10038+ break;
10039+ case PIPE_BULK:
10040+ hc->ep_type = DWC_OTG_EP_TYPE_BULK;
10041+ break;
10042+ case PIPE_INTERRUPT:
10043+ hc->ep_type = DWC_OTG_EP_TYPE_INTR;
10044+ break;
10045+ case PIPE_ISOCHRONOUS:
10046+ {
10047+ struct usb_iso_packet_descriptor *frame_desc;
10048+ frame_desc = &urb->iso_frame_desc[qtd->isoc_frame_index];
10049+ hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
10050+ if (hcd->core_if->dma_enable) {
10051+ hc->xfer_buff = (uint8_t *)urb->transfer_dma;
10052+ } else {
10053+ hc->xfer_buff = (uint8_t *)urb->transfer_buffer;
10054+ }
10055+ hc->xfer_buff += frame_desc->offset + qtd->isoc_split_offset;
10056+ hc->xfer_len = frame_desc->length - qtd->isoc_split_offset;
10057+
10058+ if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
10059+ if (hc->xfer_len <= 188) {
10060+ hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
10061+ }
10062+ else {
10063+ hc->xact_pos = DWC_HCSPLIT_XACTPOS_BEGIN;
10064+ }
10065+ }
10066+ }
10067+ break;
10068+ }
10069+
10070+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
10071+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
10072+ /*
10073+ * This value may be modified when the transfer is started to
10074+ * reflect the actual transfer length.
10075+ */
10076+ hc->multi_count = dwc_hb_mult(qh->maxp);
10077+ }
10078+
10079+ dwc_otg_hc_init(hcd->core_if, hc);
10080+ hc->qh = qh;
10081+}
10082+
10083+/**
10084+ * This function selects transactions from the HCD transfer schedule and
10085+ * assigns them to available host channels. It is called from HCD interrupt
10086+ * handler functions.
10087+ *
10088+ * @param hcd The HCD state structure.
10089+ *
10090+ * @return The types of new transactions that were assigned to host channels.
10091+ */
10092+dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd)
10093+{
10094+ struct list_head *qh_ptr;
10095+ dwc_otg_qh_t *qh;
10096+ int num_channels;
10097+ dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
10098+
10099+#ifdef DEBUG_SOF
10100+ DWC_DEBUGPL(DBG_HCD, " Select Transactions\n");
10101+#endif
10102+
10103+ spin_lock(&hcd->lock);
10104+ /* Process entries in the periodic ready list. */
10105+ qh_ptr = hcd->periodic_sched_ready.next;
10106+ while (qh_ptr != &hcd->periodic_sched_ready &&
10107+ !list_empty(&hcd->free_hc_list)) {
10108+
10109+ qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
10110+ assign_and_init_hc(hcd, qh);
10111+
10112+ /*
10113+ * Move the QH from the periodic ready schedule to the
10114+ * periodic assigned schedule.
10115+ */
10116+ qh_ptr = qh_ptr->next;
10117+ list_move(&qh->qh_list_entry, &hcd->periodic_sched_assigned);
10118+
10119+ ret_val = DWC_OTG_TRANSACTION_PERIODIC;
10120+ }
10121+
10122+ /*
10123+ * Process entries in the inactive portion of the non-periodic
10124+ * schedule. Some free host channels may not be used if they are
10125+ * reserved for periodic transfers.
10126+ */
10127+ qh_ptr = hcd->non_periodic_sched_inactive.next;
10128+ num_channels = hcd->core_if->core_params->host_channels;
10129+ while (qh_ptr != &hcd->non_periodic_sched_inactive &&
10130+ (hcd->non_periodic_channels <
10131+ num_channels - hcd->periodic_channels) &&
10132+ !list_empty(&hcd->free_hc_list)) {
10133+
10134+ qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
10135+ assign_and_init_hc(hcd, qh);
10136+
10137+ /*
10138+ * Move the QH from the non-periodic inactive schedule to the
10139+ * non-periodic active schedule.
10140+ */
10141+ qh_ptr = qh_ptr->next;
10142+ list_move(&qh->qh_list_entry, &hcd->non_periodic_sched_active);
10143+
10144+ if (ret_val == DWC_OTG_TRANSACTION_NONE) {
10145+ ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
10146+ } else {
10147+ ret_val = DWC_OTG_TRANSACTION_ALL;
10148+ }
10149+
10150+ hcd->non_periodic_channels++;
10151+ }
10152+ spin_unlock(&hcd->lock);
10153+
10154+ return ret_val;
10155+}
10156+
10157+/**
10158+ * Attempts to queue a single transaction request for a host channel
10159+ * associated with either a periodic or non-periodic transfer. This function
10160+ * assumes that there is space available in the appropriate request queue. For
10161+ * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
10162+ * is available in the appropriate Tx FIFO.
10163+ *
10164+ * @param hcd The HCD state structure.
10165+ * @param hc Host channel descriptor associated with either a periodic or
10166+ * non-periodic transfer.
10167+ * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx
10168+ * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
10169+ * transfers.
10170+ *
10171+ * @return 1 if a request is queued and more requests may be needed to
10172+ * complete the transfer, 0 if no more requests are required for this
10173+ * transfer, -1 if there is insufficient space in the Tx FIFO.
10174+ */
10175+static int queue_transaction(dwc_otg_hcd_t *hcd,
10176+ dwc_hc_t *hc,
10177+ uint16_t fifo_dwords_avail)
10178+{
10179+ int retval;
10180+
10181+ if (hcd->core_if->dma_enable) {
10182+ if (!hc->xfer_started) {
10183+ dwc_otg_hc_start_transfer(hcd->core_if, hc);
10184+ hc->qh->ping_state = 0;
10185+ }
10186+ retval = 0;
10187+ } else if (hc->halt_pending) {
10188+ /* Don't queue a request if the channel has been halted. */
10189+ retval = 0;
10190+ } else if (hc->halt_on_queue) {
10191+ dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
10192+ retval = 0;
10193+ } else if (hc->do_ping) {
10194+ if (!hc->xfer_started) {
10195+ dwc_otg_hc_start_transfer(hcd->core_if, hc);
10196+ }
10197+ retval = 0;
10198+ } else if (!hc->ep_is_in ||
10199+ hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
10200+ if ((fifo_dwords_avail * 4) >= hc->max_packet) {
10201+ if (!hc->xfer_started) {
10202+ dwc_otg_hc_start_transfer(hcd->core_if, hc);
10203+ retval = 1;
10204+ } else {
10205+ retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
10206+ }
10207+ } else {
10208+ retval = -1;
10209+ }
10210+ } else {
10211+ if (!hc->xfer_started) {
10212+ dwc_otg_hc_start_transfer(hcd->core_if, hc);
10213+ retval = 1;
10214+ } else {
10215+ retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
10216+ }
10217+ }
10218+
10219+ return retval;
10220+}
10221+
10222+/**
10223+ * Processes active non-periodic channels and queues transactions for these
10224+ * channels to the DWC_otg controller. After queueing transactions, the NP Tx
10225+ * FIFO Empty interrupt is enabled if there are more transactions to queue as
10226+ * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
10227+ * FIFO Empty interrupt is disabled.
10228+ */
10229+static void process_non_periodic_channels(dwc_otg_hcd_t *hcd)
10230+{
10231+ gnptxsts_data_t tx_status;
10232+ struct list_head *orig_qh_ptr;
10233+ dwc_otg_qh_t *qh;
10234+ int status;
10235+ int no_queue_space = 0;
10236+ int no_fifo_space = 0;
10237+ int more_to_do = 0;
10238+
10239+ dwc_otg_core_global_regs_t *global_regs = hcd->core_if->core_global_regs;
10240+
10241+ DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
10242+#ifdef DEBUG
10243+ tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
10244+ DWC_DEBUGPL(DBG_HCDV, " NP Tx Req Queue Space Avail (before queue): %d\n",
10245+ tx_status.b.nptxqspcavail);
10246+ DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (before queue): %d\n",
10247+ tx_status.b.nptxfspcavail);
10248+#endif
10249+ /*
10250+ * Keep track of the starting point. Skip over the start-of-list
10251+ * entry.
10252+ */
10253+ if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
10254+ hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
10255+ }
10256+ orig_qh_ptr = hcd->non_periodic_qh_ptr;
10257+
10258+ /*
10259+ * Process once through the active list or until no more space is
10260+ * available in the request queue or the Tx FIFO.
10261+ */
10262+ do {
10263+ tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
10264+ if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
10265+ no_queue_space = 1;
10266+ break;
10267+ }
10268+
10269+ qh = list_entry(hcd->non_periodic_qh_ptr, dwc_otg_qh_t, qh_list_entry);
10270+ status = queue_transaction(hcd, qh->channel, tx_status.b.nptxfspcavail);
10271+
10272+ if (status > 0) {
10273+ more_to_do = 1;
10274+ } else if (status < 0) {
10275+ no_fifo_space = 1;
10276+ break;
10277+ }
10278+
10279+ /* Advance to next QH, skipping start-of-list entry. */
10280+ hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
10281+ if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
10282+ hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
10283+ }
10284+
10285+ } while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
10286+
10287+ if (!hcd->core_if->dma_enable) {
10288+ gintmsk_data_t intr_mask = {.d32 = 0};
10289+ intr_mask.b.nptxfempty = 1;
10290+
10291+#ifdef DEBUG
10292+ tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
10293+ DWC_DEBUGPL(DBG_HCDV, " NP Tx Req Queue Space Avail (after queue): %d\n",
10294+ tx_status.b.nptxqspcavail);
10295+ DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (after queue): %d\n",
10296+ tx_status.b.nptxfspcavail);
10297+#endif
10298+ if (more_to_do || no_queue_space || no_fifo_space) {
10299+ /*
10300+ * May need to queue more transactions as the request
10301+ * queue or Tx FIFO empties. Enable the non-periodic
10302+ * Tx FIFO empty interrupt. (Always use the half-empty
10303+ * level to ensure that new requests are loaded as
10304+ * soon as possible.)
10305+ */
10306+ dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
10307+ } else {
10308+ /*
10309+ * Disable the Tx FIFO empty interrupt since there are
10310+ * no more transactions that need to be queued right
10311+ * now. This function is called from interrupt
10312+ * handlers to queue more transactions as transfer
10313+ * states change.
10314+ */
10315+ dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
10316+ }
10317+ }
10318+}
10319+
10320+/**
10321+ * Processes periodic channels for the next frame and queues transactions for
10322+ * these channels to the DWC_otg controller. After queueing transactions, the
10323+ * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
10324+ * to queue as Periodic Tx FIFO or request queue space becomes available.
10325+ * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
10326+ */
10327+static void process_periodic_channels(dwc_otg_hcd_t *hcd)
10328+{
10329+ hptxsts_data_t tx_status;
10330+ struct list_head *qh_ptr;
10331+ dwc_otg_qh_t *qh;
10332+ int status;
10333+ int no_queue_space = 0;
10334+ int no_fifo_space = 0;
10335+
10336+ dwc_otg_host_global_regs_t *host_regs;
10337+ host_regs = hcd->core_if->host_if->host_global_regs;
10338+
10339+ DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
10340+#ifdef DEBUG
10341+ tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
10342+ DWC_DEBUGPL(DBG_HCDV, " P Tx Req Queue Space Avail (before queue): %d\n",
10343+ tx_status.b.ptxqspcavail);
10344+ DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (before queue): %d\n",
10345+ tx_status.b.ptxfspcavail);
10346+#endif
10347+
10348+ qh_ptr = hcd->periodic_sched_assigned.next;
10349+ while (qh_ptr != &hcd->periodic_sched_assigned) {
10350+ tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
10351+ if (tx_status.b.ptxqspcavail == 0) {
10352+ no_queue_space = 1;
10353+ break;
10354+ }
10355+
10356+ qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
10357+
10358+ /*
10359+ * Set a flag if we're queuing high-bandwidth in slave mode.
10360+ * The flag prevents any halts to get into the request queue in
10361+ * the middle of multiple high-bandwidth packets getting queued.
10362+ */
10363+ if (!hcd->core_if->dma_enable &&
10364+ qh->channel->multi_count > 1)
10365+ {
10366+ hcd->core_if->queuing_high_bandwidth = 1;
10367+ }
10368+
10369+ status = queue_transaction(hcd, qh->channel, tx_status.b.ptxfspcavail);
10370+ if (status < 0) {
10371+ no_fifo_space = 1;
10372+ break;
10373+ }
10374+
10375+ /*
10376+ * In Slave mode, stay on the current transfer until there is
10377+ * nothing more to do or the high-bandwidth request count is
10378+ * reached. In DMA mode, only need to queue one request. The
10379+ * controller automatically handles multiple packets for
10380+ * high-bandwidth transfers.
10381+ */
10382+ if (hcd->core_if->dma_enable || status == 0 ||
10383+ qh->channel->requests == qh->channel->multi_count) {
10384+ qh_ptr = qh_ptr->next;
10385+ /*
10386+ * Move the QH from the periodic assigned schedule to
10387+ * the periodic queued schedule.
10388+ */
10389+ list_move(&qh->qh_list_entry, &hcd->periodic_sched_queued);
10390+
10391+ /* done queuing high bandwidth */
10392+ hcd->core_if->queuing_high_bandwidth = 0;
10393+ }
10394+ }
10395+
10396+ if (!hcd->core_if->dma_enable) {
10397+ dwc_otg_core_global_regs_t *global_regs;
10398+ gintmsk_data_t intr_mask = {.d32 = 0};
10399+
10400+ global_regs = hcd->core_if->core_global_regs;
10401+ intr_mask.b.ptxfempty = 1;
10402+#ifdef DEBUG
10403+ tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
10404+ DWC_DEBUGPL(DBG_HCDV, " P Tx Req Queue Space Avail (after queue): %d\n",
10405+ tx_status.b.ptxqspcavail);
10406+ DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (after queue): %d\n",
10407+ tx_status.b.ptxfspcavail);
10408+#endif
10409+ if (!list_empty(&hcd->periodic_sched_assigned) ||
10410+ no_queue_space || no_fifo_space) {
10411+ /*
10412+ * May need to queue more transactions as the request
10413+ * queue or Tx FIFO empties. Enable the periodic Tx
10414+ * FIFO empty interrupt. (Always use the half-empty
10415+ * level to ensure that new requests are loaded as
10416+ * soon as possible.)
10417+ */
10418+ dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
10419+ } else {
10420+ /*
10421+ * Disable the Tx FIFO empty interrupt since there are
10422+ * no more transactions that need to be queued right
10423+ * now. This function is called from interrupt
10424+ * handlers to queue more transactions as transfer
10425+ * states change.
10426+ */
10427+ dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
10428+ }
10429+ }
10430+}
10431+
10432+/**
10433+ * This function processes the currently active host channels and queues
10434+ * transactions for these channels to the DWC_otg controller. It is called
10435+ * from HCD interrupt handler functions.
10436+ *
10437+ * @param hcd The HCD state structure.
10438+ * @param tr_type The type(s) of transactions to queue (non-periodic,
10439+ * periodic, or both).
10440+ */
10441+void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd,
10442+ dwc_otg_transaction_type_e tr_type)
10443+{
10444+#ifdef DEBUG_SOF
10445+ DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
10446+#endif
10447+ /* Process host channels associated with periodic transfers. */
10448+ if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
10449+ tr_type == DWC_OTG_TRANSACTION_ALL) &&
10450+ !list_empty(&hcd->periodic_sched_assigned)) {
10451+
10452+ process_periodic_channels(hcd);
10453+ }
10454+
10455+ /* Process host channels associated with non-periodic transfers. */
10456+ if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
10457+ tr_type == DWC_OTG_TRANSACTION_ALL) {
10458+ if (!list_empty(&hcd->non_periodic_sched_active)) {
10459+ process_non_periodic_channels(hcd);
10460+ } else {
10461+ /*
10462+ * Ensure NP Tx FIFO empty interrupt is disabled when
10463+ * there are no non-periodic transfers to process.
10464+ */
10465+ gintmsk_data_t gintmsk = {.d32 = 0};
10466+ gintmsk.b.nptxfempty = 1;
10467+ dwc_modify_reg32(&hcd->core_if->core_global_regs->gintmsk,
10468+ gintmsk.d32, 0);
10469+ }
10470+ }
10471+}
10472+
10473+/**
10474+ * Sets the final status of an URB and returns it to the device driver. Any
10475+ * required cleanup of the URB is performed.
10476+ */
10477+void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t *hcd, struct urb *urb, int status)
10478+{
10479+#ifdef DEBUG
10480+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
10481+ DWC_PRINT("%s: urb %p, device %d, ep %d %s, status=%d\n",
10482+ __func__, urb, usb_pipedevice(urb->pipe),
10483+ usb_pipeendpoint(urb->pipe),
10484+ usb_pipein(urb->pipe) ? "IN" : "OUT", status);
10485+ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
10486+ int i;
10487+ for (i = 0; i < urb->number_of_packets; i++) {
10488+ DWC_PRINT(" ISO Desc %d status: %d\n",
10489+ i, urb->iso_frame_desc[i].status);
10490+ }
10491+ }
10492+ }
10493+#endif
10494+
10495+ //if we use the aligned buffer instead of the original unaligned buffer,
10496+ //for IN data, we have to move the data to the original buffer
10497+ if((urb->transfer_dma==urb->aligned_transfer_dma)&&((urb->transfer_flags & URB_DIR_MASK)==URB_DIR_IN)){
10498+ dma_sync_single_for_device(NULL,urb->transfer_dma,urb->actual_length,DMA_FROM_DEVICE);
10499+ memcpy(urb->transfer_buffer,urb->aligned_transfer_buffer,urb->actual_length);
10500+ }
10501+
10502+
10503+ urb->status = status;
10504+ urb->hcpriv = NULL;
10505+ usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, status);
10506+}
10507+
10508+/*
10509+ * Returns the Queue Head for an URB.
10510+ */
10511+dwc_otg_qh_t *dwc_urb_to_qh(struct urb *urb)
10512+{
10513+ struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb);
10514+ return (dwc_otg_qh_t *)ep->hcpriv;
10515+}
10516+
10517+#ifdef DEBUG
10518+void dwc_print_setup_data(uint8_t *setup)
10519+{
10520+ int i;
10521+ if (CHK_DEBUG_LEVEL(DBG_HCD)){
10522+ DWC_PRINT("Setup Data = MSB ");
10523+ for (i = 7; i >= 0; i--) DWC_PRINT("%02x ", setup[i]);
10524+ DWC_PRINT("\n");
10525+ DWC_PRINT(" bmRequestType Tranfer = %s\n", (setup[0] & 0x80) ? "Device-to-Host" : "Host-to-Device");
10526+ DWC_PRINT(" bmRequestType Type = ");
10527+ switch ((setup[0] & 0x60) >> 5) {
10528+ case 0: DWC_PRINT("Standard\n"); break;
10529+ case 1: DWC_PRINT("Class\n"); break;
10530+ case 2: DWC_PRINT("Vendor\n"); break;
10531+ case 3: DWC_PRINT("Reserved\n"); break;
10532+ }
10533+ DWC_PRINT(" bmRequestType Recipient = ");
10534+ switch (setup[0] & 0x1f) {
10535+ case 0: DWC_PRINT("Device\n"); break;
10536+ case 1: DWC_PRINT("Interface\n"); break;
10537+ case 2: DWC_PRINT("Endpoint\n"); break;
10538+ case 3: DWC_PRINT("Other\n"); break;
10539+ default: DWC_PRINT("Reserved\n"); break;
10540+ }
10541+ DWC_PRINT(" bRequest = 0x%0x\n", setup[1]);
10542+ DWC_PRINT(" wValue = 0x%0x\n", *((uint16_t *)&setup[2]));
10543+ DWC_PRINT(" wIndex = 0x%0x\n", *((uint16_t *)&setup[4]));
10544+ DWC_PRINT(" wLength = 0x%0x\n\n", *((uint16_t *)&setup[6]));
10545+ }
10546+}
10547+#endif
10548+
10549+void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *hcd) {
10550+}
10551+
10552+void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd)
10553+{
10554+#ifdef DEBUG
10555+ int num_channels;
10556+ int i;
10557+ gnptxsts_data_t np_tx_status;
10558+ hptxsts_data_t p_tx_status;
10559+
10560+ num_channels = hcd->core_if->core_params->host_channels;
10561+ DWC_PRINT("\n");
10562+ DWC_PRINT("************************************************************\n");
10563+ DWC_PRINT("HCD State:\n");
10564+ DWC_PRINT(" Num channels: %d\n", num_channels);
10565+ for (i = 0; i < num_channels; i++) {
10566+ dwc_hc_t *hc = hcd->hc_ptr_array[i];
10567+ DWC_PRINT(" Channel %d:\n", i);
10568+ DWC_PRINT(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
10569+ hc->dev_addr, hc->ep_num, hc->ep_is_in);
10570+ DWC_PRINT(" speed: %d\n", hc->speed);
10571+ DWC_PRINT(" ep_type: %d\n", hc->ep_type);
10572+ DWC_PRINT(" max_packet: %d\n", hc->max_packet);
10573+ DWC_PRINT(" data_pid_start: %d\n", hc->data_pid_start);
10574+ DWC_PRINT(" multi_count: %d\n", hc->multi_count);
10575+ DWC_PRINT(" xfer_started: %d\n", hc->xfer_started);
10576+ DWC_PRINT(" xfer_buff: %p\n", hc->xfer_buff);
10577+ DWC_PRINT(" xfer_len: %d\n", hc->xfer_len);
10578+ DWC_PRINT(" xfer_count: %d\n", hc->xfer_count);
10579+ DWC_PRINT(" halt_on_queue: %d\n", hc->halt_on_queue);
10580+ DWC_PRINT(" halt_pending: %d\n", hc->halt_pending);
10581+ DWC_PRINT(" halt_status: %d\n", hc->halt_status);
10582+ DWC_PRINT(" do_split: %d\n", hc->do_split);
10583+ DWC_PRINT(" complete_split: %d\n", hc->complete_split);
10584+ DWC_PRINT(" hub_addr: %d\n", hc->hub_addr);
10585+ DWC_PRINT(" port_addr: %d\n", hc->port_addr);
10586+ DWC_PRINT(" xact_pos: %d\n", hc->xact_pos);
10587+ DWC_PRINT(" requests: %d\n", hc->requests);
10588+ DWC_PRINT(" qh: %p\n", hc->qh);
10589+ if (hc->xfer_started) {
10590+ hfnum_data_t hfnum;
10591+ hcchar_data_t hcchar;
10592+ hctsiz_data_t hctsiz;
10593+ hcint_data_t hcint;
10594+ hcintmsk_data_t hcintmsk;
10595+ hfnum.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hfnum);
10596+ hcchar.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hcchar);
10597+ hctsiz.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hctsiz);
10598+ hcint.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hcint);
10599+ hcintmsk.d32 = dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->hcintmsk);
10600+ DWC_PRINT(" hfnum: 0x%08x\n", hfnum.d32);
10601+ DWC_PRINT(" hcchar: 0x%08x\n", hcchar.d32);
10602+ DWC_PRINT(" hctsiz: 0x%08x\n", hctsiz.d32);
10603+ DWC_PRINT(" hcint: 0x%08x\n", hcint.d32);
10604+ DWC_PRINT(" hcintmsk: 0x%08x\n", hcintmsk.d32);
10605+ }
10606+ if (hc->xfer_started && hc->qh && hc->qh->qtd_in_process) {
10607+ dwc_otg_qtd_t *qtd;
10608+ struct urb *urb;
10609+ qtd = hc->qh->qtd_in_process;
10610+ urb = qtd->urb;
10611+ DWC_PRINT(" URB Info:\n");
10612+ DWC_PRINT(" qtd: %p, urb: %p\n", qtd, urb);
10613+ if (urb) {
10614+ DWC_PRINT(" Dev: %d, EP: %d %s\n",
10615+ usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe),
10616+ usb_pipein(urb->pipe) ? "IN" : "OUT");
10617+ DWC_PRINT(" Max packet size: %d\n",
10618+ usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
10619+ DWC_PRINT(" transfer_buffer: %p\n", urb->transfer_buffer);
10620+ DWC_PRINT(" transfer_dma: %p\n", (void *)urb->transfer_dma);
10621+ DWC_PRINT(" transfer_buffer_length: %d\n", urb->transfer_buffer_length);
10622+ DWC_PRINT(" actual_length: %d\n", urb->actual_length);
10623+ }
10624+ }
10625+ }
10626+ DWC_PRINT(" non_periodic_channels: %d\n", hcd->non_periodic_channels);
10627+ DWC_PRINT(" periodic_channels: %d\n", hcd->periodic_channels);
10628+ DWC_PRINT(" periodic_usecs: %d\n", hcd->periodic_usecs);
10629+ np_tx_status.d32 = dwc_read_reg32(&hcd->core_if->core_global_regs->gnptxsts);
10630+ DWC_PRINT(" NP Tx Req Queue Space Avail: %d\n", np_tx_status.b.nptxqspcavail);
10631+ DWC_PRINT(" NP Tx FIFO Space Avail: %d\n", np_tx_status.b.nptxfspcavail);
10632+ p_tx_status.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hptxsts);
10633+ DWC_PRINT(" P Tx Req Queue Space Avail: %d\n", p_tx_status.b.ptxqspcavail);
10634+ DWC_PRINT(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
10635+ dwc_otg_hcd_dump_frrem(hcd);
10636+ dwc_otg_dump_global_registers(hcd->core_if);
10637+ dwc_otg_dump_host_registers(hcd->core_if);
10638+ DWC_PRINT("************************************************************\n");
10639+ DWC_PRINT("\n");
10640+#endif
10641+}
10642+#endif /* DWC_DEVICE_ONLY */
10643--- /dev/null
10644+++ b/drivers/usb/dwc/otg_hcd.h
10645@@ -0,0 +1,652 @@
10646+/* ==========================================================================
10647+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $
10648+ * $Revision: #45 $
10649+ * $Date: 2008/07/15 $
10650+ * $Change: 1064918 $
10651+ *
10652+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
10653+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
10654+ * otherwise expressly agreed to in writing between Synopsys and you.
10655+ *
10656+ * The Software IS NOT an item of Licensed Software or Licensed Product under
10657+ * any End User Software License Agreement or Agreement for Licensed Product
10658+ * with Synopsys or any supplement thereto. You are permitted to use and
10659+ * redistribute this Software in source and binary forms, with or without
10660+ * modification, provided that redistributions of source code must retain this
10661+ * notice. You may not view, use, disclose, copy or distribute this file or
10662+ * any information contained herein except pursuant to this license grant from
10663+ * Synopsys. If you do not agree with this notice, including the disclaimer
10664+ * below, then you are not authorized to use the Software.
10665+ *
10666+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
10667+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
10668+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
10669+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
10670+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10671+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
10672+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
10673+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
10674+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
10675+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
10676+ * DAMAGE.
10677+ * ========================================================================== */
10678+#ifndef DWC_DEVICE_ONLY
10679+#ifndef __DWC_HCD_H__
10680+#define __DWC_HCD_H__
10681+
10682+#include <linux/list.h>
10683+#include <linux/usb.h>
10684+#include <linux/usb/hcd.h>
10685+
10686+struct dwc_otg_device;
10687+
10688+#include "otg_cil.h"
10689+
10690+/**
10691+ * @file
10692+ *
10693+ * This file contains the structures, constants, and interfaces for
10694+ * the Host Contoller Driver (HCD).
10695+ *
10696+ * The Host Controller Driver (HCD) is responsible for translating requests
10697+ * from the USB Driver into the appropriate actions on the DWC_otg controller.
10698+ * It isolates the USBD from the specifics of the controller by providing an
10699+ * API to the USBD.
10700+ */
10701+
10702+/**
10703+ * Phases for control transfers.
10704+ */
10705+typedef enum dwc_otg_control_phase {
10706+ DWC_OTG_CONTROL_SETUP,
10707+ DWC_OTG_CONTROL_DATA,
10708+ DWC_OTG_CONTROL_STATUS
10709+} dwc_otg_control_phase_e;
10710+
10711+/** Transaction types. */
10712+typedef enum dwc_otg_transaction_type {
10713+ DWC_OTG_TRANSACTION_NONE,
10714+ DWC_OTG_TRANSACTION_PERIODIC,
10715+ DWC_OTG_TRANSACTION_NON_PERIODIC,
10716+ DWC_OTG_TRANSACTION_ALL
10717+} dwc_otg_transaction_type_e;
10718+
10719+/**
10720+ * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
10721+ * interrupt, or isochronous transfer. A single QTD is created for each URB
10722+ * (of one of these types) submitted to the HCD. The transfer associated with
10723+ * a QTD may require one or multiple transactions.
10724+ *
10725+ * A QTD is linked to a Queue Head, which is entered in either the
10726+ * non-periodic or periodic schedule for execution. When a QTD is chosen for
10727+ * execution, some or all of its transactions may be executed. After
10728+ * execution, the state of the QTD is updated. The QTD may be retired if all
10729+ * its transactions are complete or if an error occurred. Otherwise, it
10730+ * remains in the schedule so more transactions can be executed later.
10731+ */
10732+typedef struct dwc_otg_qtd {
10733+ /**
10734+ * Determines the PID of the next data packet for the data phase of
10735+ * control transfers. Ignored for other transfer types.<br>
10736+ * One of the following values:
10737+ * - DWC_OTG_HC_PID_DATA0
10738+ * - DWC_OTG_HC_PID_DATA1
10739+ */
10740+ uint8_t data_toggle;
10741+
10742+ /** Current phase for control transfers (Setup, Data, or Status). */
10743+ dwc_otg_control_phase_e control_phase;
10744+
10745+ /** Keep track of the current split type
10746+ * for FS/LS endpoints on a HS Hub */
10747+ uint8_t complete_split;
10748+
10749+ /** How many bytes transferred during SSPLIT OUT */
10750+ uint32_t ssplit_out_xfer_count;
10751+
10752+ /**
10753+ * Holds the number of bus errors that have occurred for a transaction
10754+ * within this transfer.
10755+ */
10756+ uint8_t error_count;
10757+
10758+ /**
10759+ * Index of the next frame descriptor for an isochronous transfer. A
10760+ * frame descriptor describes the buffer position and length of the
10761+ * data to be transferred in the next scheduled (micro)frame of an
10762+ * isochronous transfer. It also holds status for that transaction.
10763+ * The frame index starts at 0.
10764+ */
10765+ int isoc_frame_index;
10766+
10767+ /** Position of the ISOC split on full/low speed */
10768+ uint8_t isoc_split_pos;
10769+
10770+ /** Position of the ISOC split in the buffer for the current frame */
10771+ uint16_t isoc_split_offset;
10772+
10773+ /** URB for this transfer */
10774+ struct urb *urb;
10775+
10776+ /** This list of QTDs */
10777+ struct list_head qtd_list_entry;
10778+
10779+} dwc_otg_qtd_t;
10780+
10781+/**
10782+ * A Queue Head (QH) holds the static characteristics of an endpoint and
10783+ * maintains a list of transfers (QTDs) for that endpoint. A QH structure may
10784+ * be entered in either the non-periodic or periodic schedule.
10785+ */
10786+typedef struct dwc_otg_qh {
10787+ /**
10788+ * Endpoint type.
10789+ * One of the following values:
10790+ * - USB_ENDPOINT_XFER_CONTROL
10791+ * - USB_ENDPOINT_XFER_ISOC
10792+ * - USB_ENDPOINT_XFER_BULK
10793+ * - USB_ENDPOINT_XFER_INT
10794+ */
10795+ uint8_t ep_type;
10796+ uint8_t ep_is_in;
10797+
10798+ /** wMaxPacketSize Field of Endpoint Descriptor. */
10799+ uint16_t maxp;
10800+
10801+ /**
10802+ * Determines the PID of the next data packet for non-control
10803+ * transfers. Ignored for control transfers.<br>
10804+ * One of the following values:
10805+ * - DWC_OTG_HC_PID_DATA0
10806+ * - DWC_OTG_HC_PID_DATA1
10807+ */
10808+ uint8_t data_toggle;
10809+
10810+ /** Ping state if 1. */
10811+ uint8_t ping_state;
10812+
10813+ /**
10814+ * List of QTDs for this QH.
10815+ */
10816+ struct list_head qtd_list;
10817+
10818+ /** Host channel currently processing transfers for this QH. */
10819+ dwc_hc_t *channel;
10820+
10821+ /** QTD currently assigned to a host channel for this QH. */
10822+ dwc_otg_qtd_t *qtd_in_process;
10823+
10824+ /** Full/low speed endpoint on high-speed hub requires split. */
10825+ uint8_t do_split;
10826+
10827+ /** @name Periodic schedule information */
10828+ /** @{ */
10829+
10830+ /** Bandwidth in microseconds per (micro)frame. */
10831+ uint8_t usecs;
10832+
10833+ /** Interval between transfers in (micro)frames. */
10834+ uint16_t interval;
10835+
10836+ /**
10837+ * (micro)frame to initialize a periodic transfer. The transfer
10838+ * executes in the following (micro)frame.
10839+ */
10840+ uint16_t sched_frame;
10841+
10842+ /** (micro)frame at which last start split was initialized. */
10843+ uint16_t start_split_frame;
10844+
10845+ u16 speed;
10846+ u16 frame_usecs[8];
10847+
10848+ /** @} */
10849+
10850+ /** Entry for QH in either the periodic or non-periodic schedule. */
10851+ struct list_head qh_list_entry;
10852+} dwc_otg_qh_t;
10853+
10854+/**
10855+ * This structure holds the state of the HCD, including the non-periodic and
10856+ * periodic schedules.
10857+ */
10858+typedef struct dwc_otg_hcd {
10859+ /** The DWC otg device pointer */
10860+ struct dwc_otg_device *otg_dev;
10861+
10862+ /** DWC OTG Core Interface Layer */
10863+ dwc_otg_core_if_t *core_if;
10864+
10865+ /** Internal DWC HCD Flags */
10866+ volatile union dwc_otg_hcd_internal_flags {
10867+ uint32_t d32;
10868+ struct {
10869+ unsigned port_connect_status_change : 1;
10870+ unsigned port_connect_status : 1;
10871+ unsigned port_reset_change : 1;
10872+ unsigned port_enable_change : 1;
10873+ unsigned port_suspend_change : 1;
10874+ unsigned port_over_current_change : 1;
10875+ unsigned reserved : 27;
10876+ } b;
10877+ } flags;
10878+
10879+ /**
10880+ * Inactive items in the non-periodic schedule. This is a list of
10881+ * Queue Heads. Transfers associated with these Queue Heads are not
10882+ * currently assigned to a host channel.
10883+ */
10884+ struct list_head non_periodic_sched_inactive;
10885+
10886+ /**
10887+ * Active items in the non-periodic schedule. This is a list of
10888+ * Queue Heads. Transfers associated with these Queue Heads are
10889+ * currently assigned to a host channel.
10890+ */
10891+ struct list_head non_periodic_sched_active;
10892+
10893+ /**
10894+ * Pointer to the next Queue Head to process in the active
10895+ * non-periodic schedule.
10896+ */
10897+ struct list_head *non_periodic_qh_ptr;
10898+
10899+ /**
10900+ * Inactive items in the periodic schedule. This is a list of QHs for
10901+ * periodic transfers that are _not_ scheduled for the next frame.
10902+ * Each QH in the list has an interval counter that determines when it
10903+ * needs to be scheduled for execution. This scheduling mechanism
10904+ * allows only a simple calculation for periodic bandwidth used (i.e.
10905+ * must assume that all periodic transfers may need to execute in the
10906+ * same frame). However, it greatly simplifies scheduling and should
10907+ * be sufficient for the vast majority of OTG hosts, which need to
10908+ * connect to a small number of peripherals at one time.
10909+ *
10910+ * Items move from this list to periodic_sched_ready when the QH
10911+ * interval counter is 0 at SOF.
10912+ */
10913+ struct list_head periodic_sched_inactive;
10914+
10915+ /**
10916+ * List of periodic QHs that are ready for execution in the next
10917+ * frame, but have not yet been assigned to host channels.
10918+ *
10919+ * Items move from this list to periodic_sched_assigned as host
10920+ * channels become available during the current frame.
10921+ */
10922+ struct list_head periodic_sched_ready;
10923+
10924+ /**
10925+ * List of periodic QHs to be executed in the next frame that are
10926+ * assigned to host channels.
10927+ *
10928+ * Items move from this list to periodic_sched_queued as the
10929+ * transactions for the QH are queued to the DWC_otg controller.
10930+ */
10931+ struct list_head periodic_sched_assigned;
10932+
10933+ /**
10934+ * List of periodic QHs that have been queued for execution.
10935+ *
10936+ * Items move from this list to either periodic_sched_inactive or
10937+ * periodic_sched_ready when the channel associated with the transfer
10938+ * is released. If the interval for the QH is 1, the item moves to
10939+ * periodic_sched_ready because it must be rescheduled for the next
10940+ * frame. Otherwise, the item moves to periodic_sched_inactive.
10941+ */
10942+ struct list_head periodic_sched_queued;
10943+
10944+ /**
10945+ * Total bandwidth claimed so far for periodic transfers. This value
10946+ * is in microseconds per (micro)frame. The assumption is that all
10947+ * periodic transfers may occur in the same (micro)frame.
10948+ */
10949+ uint16_t periodic_usecs;
10950+
10951+ /*
10952+ * Total bandwidth claimed so far for all periodic transfers
10953+ * in a frame.
10954+ * This will include a mixture of HS and FS transfers.
10955+ * Units are microseconds per (micro)frame.
10956+ * We have a budget per frame and have to schedule
10957+ * transactions accordingly.
10958+ * Watch out for the fact that things are actually scheduled for the
10959+ * "next frame".
10960+ */
10961+ u16 frame_usecs[8];
10962+
10963+ /**
10964+ * Frame number read from the core at SOF. The value ranges from 0 to
10965+ * DWC_HFNUM_MAX_FRNUM.
10966+ */
10967+ uint16_t frame_number;
10968+
10969+ /**
10970+ * Free host channels in the controller. This is a list of
10971+ * dwc_hc_t items.
10972+ */
10973+ struct list_head free_hc_list;
10974+
10975+ /**
10976+ * Number of host channels assigned to periodic transfers. Currently
10977+ * assuming that there is a dedicated host channel for each periodic
10978+ * transaction and at least one host channel available for
10979+ * non-periodic transactions.
10980+ */
10981+ int periodic_channels;
10982+
10983+ /**
10984+ * Number of host channels assigned to non-periodic transfers.
10985+ */
10986+ int non_periodic_channels;
10987+
10988+ /**
10989+ * Array of pointers to the host channel descriptors. Allows accessing
10990+ * a host channel descriptor given the host channel number. This is
10991+ * useful in interrupt handlers.
10992+ */
10993+ dwc_hc_t *hc_ptr_array[MAX_EPS_CHANNELS];
10994+
10995+ /**
10996+ * Buffer to use for any data received during the status phase of a
10997+ * control transfer. Normally no data is transferred during the status
10998+ * phase. This buffer is used as a bit bucket.
10999+ */
11000+ uint8_t *status_buf;
11001+
11002+ /**
11003+ * DMA address for status_buf.
11004+ */
11005+ dma_addr_t status_buf_dma;
11006+#define DWC_OTG_HCD_STATUS_BUF_SIZE 64
11007+
11008+ /**
11009+ * Structure to allow starting the HCD in a non-interrupt context
11010+ * during an OTG role change.
11011+ */
11012+ struct delayed_work start_work;
11013+
11014+ /**
11015+ * Connection timer. An OTG host must display a message if the device
11016+ * does not connect. Started when the VBus power is turned on via
11017+ * sysfs attribute "buspower".
11018+ */
11019+ struct timer_list conn_timer;
11020+
11021+ /* Tasket to do a reset */
11022+ struct tasklet_struct *reset_tasklet;
11023+
11024+ /* */
11025+ spinlock_t lock;
11026+
11027+#ifdef DEBUG
11028+ uint32_t frrem_samples;
11029+ uint64_t frrem_accum;
11030+
11031+ uint32_t hfnum_7_samples_a;
11032+ uint64_t hfnum_7_frrem_accum_a;
11033+ uint32_t hfnum_0_samples_a;
11034+ uint64_t hfnum_0_frrem_accum_a;
11035+ uint32_t hfnum_other_samples_a;
11036+ uint64_t hfnum_other_frrem_accum_a;
11037+
11038+ uint32_t hfnum_7_samples_b;
11039+ uint64_t hfnum_7_frrem_accum_b;
11040+ uint32_t hfnum_0_samples_b;
11041+ uint64_t hfnum_0_frrem_accum_b;
11042+ uint32_t hfnum_other_samples_b;
11043+ uint64_t hfnum_other_frrem_accum_b;
11044+#endif
11045+} dwc_otg_hcd_t;
11046+
11047+/** Gets the dwc_otg_hcd from a struct usb_hcd */
11048+static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd)
11049+{
11050+ return (dwc_otg_hcd_t *)(hcd->hcd_priv);
11051+}
11052+
11053+/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */
11054+static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t *dwc_otg_hcd)
11055+{
11056+ return container_of((void *)dwc_otg_hcd, struct usb_hcd, hcd_priv);
11057+}
11058+
11059+/** @name HCD Create/Destroy Functions */
11060+/** @{ */
11061+extern int dwc_otg_hcd_init(struct platform_device *pdev);
11062+extern void dwc_otg_hcd_remove(struct platform_device *pdev);
11063+/** @} */
11064+
11065+/** @name Linux HC Driver API Functions */
11066+/** @{ */
11067+
11068+extern int dwc_otg_hcd_start(struct usb_hcd *hcd);
11069+extern void dwc_otg_hcd_stop(struct usb_hcd *hcd);
11070+extern int dwc_otg_hcd_get_frame_number(struct usb_hcd *hcd);
11071+extern void dwc_otg_hcd_free(struct usb_hcd *hcd);
11072+extern int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd,
11073+ // struct usb_host_endpoint *ep,
11074+ struct urb *urb,
11075+ gfp_t mem_flags
11076+ );
11077+extern int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd,
11078+ struct urb *urb, int status);
11079+extern void dwc_otg_hcd_endpoint_disable(struct usb_hcd *hcd,
11080+ struct usb_host_endpoint *ep);
11081+extern irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd);
11082+extern int dwc_otg_hcd_hub_status_data(struct usb_hcd *hcd,
11083+ char *buf);
11084+extern int dwc_otg_hcd_hub_control(struct usb_hcd *hcd,
11085+ u16 typeReq,
11086+ u16 wValue,
11087+ u16 wIndex,
11088+ char *buf,
11089+ u16 wLength);
11090+
11091+/** @} */
11092+
11093+/** @name Transaction Execution Functions */
11094+/** @{ */
11095+extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd);
11096+extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd,
11097+ dwc_otg_transaction_type_e tr_type);
11098+extern void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t *_hcd, struct urb *urb,
11099+ int status);
11100+/** @} */
11101+
11102+/** @name Interrupt Handler Functions */
11103+/** @{ */
11104+extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t *dwc_otg_hcd);
11105+extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t *dwc_otg_hcd);
11106+extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *dwc_otg_hcd);
11107+extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd);
11108+extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd);
11109+extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *dwc_otg_hcd);
11110+extern int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t *dwc_otg_hcd);
11111+extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t *dwc_otg_hcd);
11112+extern int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t *dwc_otg_hcd);
11113+extern int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t *dwc_otg_hcd);
11114+extern int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num);
11115+extern int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t *dwc_otg_hcd);
11116+extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t *dwc_otg_hcd);
11117+/** @} */
11118+
11119+
11120+/** @name Schedule Queue Functions */
11121+/** @{ */
11122+
11123+/* Implemented in dwc_otg_hcd_queue.c */
11124+extern int init_hcd_usecs(dwc_otg_hcd_t *hcd);
11125+extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t *hcd, struct urb *urb);
11126+extern void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, struct urb *urb);
11127+extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
11128+extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
11129+extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
11130+extern void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_csplit);
11131+
11132+/** Remove and free a QH */
11133+static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t *hcd,
11134+ dwc_otg_qh_t *qh)
11135+{
11136+ dwc_otg_hcd_qh_remove(hcd, qh);
11137+ dwc_otg_hcd_qh_free(hcd, qh);
11138+}
11139+
11140+/** Allocates memory for a QH structure.
11141+ * @return Returns the memory allocate or NULL on error. */
11142+static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(void)
11143+{
11144+ return (dwc_otg_qh_t *) kmalloc(sizeof(dwc_otg_qh_t), GFP_KERNEL);
11145+}
11146+
11147+extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(struct urb *urb);
11148+extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t *qtd, struct urb *urb);
11149+extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t *qtd, dwc_otg_hcd_t *dwc_otg_hcd);
11150+
11151+/** Allocates memory for a QTD structure.
11152+ * @return Returns the memory allocate or NULL on error. */
11153+static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(void)
11154+{
11155+ return (dwc_otg_qtd_t *) kmalloc(sizeof(dwc_otg_qtd_t), GFP_KERNEL);
11156+}
11157+
11158+/** Frees the memory for a QTD structure. QTD should already be removed from
11159+ * list.
11160+ * @param[in] qtd QTD to free.*/
11161+static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t *qtd)
11162+{
11163+ kfree(qtd);
11164+}
11165+
11166+/** Remove and free a QTD */
11167+static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd)
11168+{
11169+ list_del(&qtd->qtd_list_entry);
11170+ dwc_otg_hcd_qtd_free(qtd);
11171+}
11172+
11173+/** @} */
11174+
11175+
11176+/** @name Internal Functions */
11177+/** @{ */
11178+dwc_otg_qh_t *dwc_urb_to_qh(struct urb *urb);
11179+void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *hcd);
11180+void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd);
11181+/** @} */
11182+
11183+/** Gets the usb_host_endpoint associated with an URB. */
11184+static inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *urb)
11185+{
11186+ struct usb_device *dev = urb->dev;
11187+ int ep_num = usb_pipeendpoint(urb->pipe);
11188+
11189+ if (usb_pipein(urb->pipe))
11190+ return dev->ep_in[ep_num];
11191+ else
11192+ return dev->ep_out[ep_num];
11193+}
11194+
11195+/**
11196+ * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is
11197+ * qualified with its direction (possible 32 endpoints per device).
11198+ */
11199+#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
11200+ ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
11201+
11202+/** Gets the QH that contains the list_head */
11203+#define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry)
11204+
11205+/** Gets the QTD that contains the list_head */
11206+#define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry)
11207+
11208+/** Check if QH is non-periodic */
11209+#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == USB_ENDPOINT_XFER_BULK) || \
11210+ (_qh_ptr_->ep_type == USB_ENDPOINT_XFER_CONTROL))
11211+
11212+/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */
11213+#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
11214+
11215+/** Packet size for any kind of endpoint descriptor */
11216+#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
11217+
11218+/**
11219+ * Returns true if _frame1 is less than or equal to _frame2. The comparison is
11220+ * done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the
11221+ * frame number when the max frame number is reached.
11222+ */
11223+static inline int dwc_frame_num_le(uint16_t frame1, uint16_t frame2)
11224+{
11225+ return ((frame2 - frame1) & DWC_HFNUM_MAX_FRNUM) <=
11226+ (DWC_HFNUM_MAX_FRNUM >> 1);
11227+}
11228+
11229+/**
11230+ * Returns true if _frame1 is greater than _frame2. The comparison is done
11231+ * modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
11232+ * number when the max frame number is reached.
11233+ */
11234+static inline int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2)
11235+{
11236+ return (frame1 != frame2) &&
11237+ (((frame1 - frame2) & DWC_HFNUM_MAX_FRNUM) <
11238+ (DWC_HFNUM_MAX_FRNUM >> 1));
11239+}
11240+
11241+/**
11242+ * Increments _frame by the amount specified by _inc. The addition is done
11243+ * modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value.
11244+ */
11245+static inline uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc)
11246+{
11247+ return (frame + inc) & DWC_HFNUM_MAX_FRNUM;
11248+}
11249+
11250+static inline uint16_t dwc_full_frame_num(uint16_t frame)
11251+{
11252+ return (frame & DWC_HFNUM_MAX_FRNUM) >> 3;
11253+}
11254+
11255+static inline uint16_t dwc_micro_frame_num(uint16_t frame)
11256+{
11257+ return frame & 0x7;
11258+}
11259+
11260+#ifdef DEBUG
11261+/**
11262+ * Macro to sample the remaining PHY clocks left in the current frame. This
11263+ * may be used during debugging to determine the average time it takes to
11264+ * execute sections of code. There are two possible sample points, "a" and
11265+ * "b", so the _letter argument must be one of these values.
11266+ *
11267+ * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
11268+ * example, "cat /sys/devices/lm0/hcd_frrem".
11269+ */
11270+#define dwc_sample_frrem(_hcd, _qh, _letter) \
11271+{ \
11272+ hfnum_data_t hfnum; \
11273+ dwc_otg_qtd_t *qtd; \
11274+ qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \
11275+ if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \
11276+ hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); \
11277+ switch (hfnum.b.frnum & 0x7) { \
11278+ case 7: \
11279+ _hcd->hfnum_7_samples_##_letter++; \
11280+ _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \
11281+ break; \
11282+ case 0: \
11283+ _hcd->hfnum_0_samples_##_letter++; \
11284+ _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \
11285+ break; \
11286+ default: \
11287+ _hcd->hfnum_other_samples_##_letter++; \
11288+ _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \
11289+ break; \
11290+ } \
11291+ } \
11292+}
11293+#else
11294+#define dwc_sample_frrem(_hcd, _qh, _letter)
11295+#endif
11296+#endif
11297+#endif /* DWC_DEVICE_ONLY */
11298--- /dev/null
11299+++ b/drivers/usb/dwc/otg_hcd_intr.c
11300@@ -0,0 +1,1828 @@
11301+/* ==========================================================================
11302+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $
11303+ * $Revision: #70 $
11304+ * $Date: 2008/10/16 $
11305+ * $Change: 1117667 $
11306+ *
11307+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
11308+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
11309+ * otherwise expressly agreed to in writing between Synopsys and you.
11310+ *
11311+ * The Software IS NOT an item of Licensed Software or Licensed Product under
11312+ * any End User Software License Agreement or Agreement for Licensed Product
11313+ * with Synopsys or any supplement thereto. You are permitted to use and
11314+ * redistribute this Software in source and binary forms, with or without
11315+ * modification, provided that redistributions of source code must retain this
11316+ * notice. You may not view, use, disclose, copy or distribute this file or
11317+ * any information contained herein except pursuant to this license grant from
11318+ * Synopsys. If you do not agree with this notice, including the disclaimer
11319+ * below, then you are not authorized to use the Software.
11320+ *
11321+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
11322+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
11323+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
11324+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
11325+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11326+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
11327+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
11328+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
11329+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
11330+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
11331+ * DAMAGE.
11332+ * ========================================================================== */
11333+#ifndef DWC_DEVICE_ONLY
11334+
11335+#include <linux/version.h>
11336+
11337+#include "otg_driver.h"
11338+#include "otg_hcd.h"
11339+#include "otg_regs.h"
11340+
11341+/** @file
11342+ * This file contains the implementation of the HCD Interrupt handlers.
11343+ */
11344+
11345+/** This function handles interrupts for the HCD. */
11346+int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t *dwc_otg_hcd)
11347+{
11348+ int retval = 0;
11349+
11350+ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
11351+ gintsts_data_t gintsts;
11352+#ifdef DEBUG
11353+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
11354+#endif
11355+
11356+ /* Check if HOST Mode */
11357+ if (dwc_otg_is_host_mode(core_if)) {
11358+ gintsts.d32 = dwc_otg_read_core_intr(core_if);
11359+ if (!gintsts.d32) {
11360+ return 0;
11361+ }
11362+
11363+#ifdef DEBUG
11364+ /* Don't print debug message in the interrupt handler on SOF */
11365+# ifndef DEBUG_SOF
11366+ if (gintsts.d32 != DWC_SOF_INTR_MASK)
11367+# endif
11368+ DWC_DEBUGPL(DBG_HCD, "\n");
11369+#endif
11370+
11371+#ifdef DEBUG
11372+# ifndef DEBUG_SOF
11373+ if (gintsts.d32 != DWC_SOF_INTR_MASK)
11374+# endif
11375+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n", gintsts.d32);
11376+#endif
11377+ if (gintsts.b.usbreset) {
11378+ DWC_PRINT("Usb Reset In Host Mode\n");
11379+ }
11380+ if (gintsts.b.sofintr) {
11381+ retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd);
11382+ }
11383+ if (gintsts.b.rxstsqlvl) {
11384+ retval |= dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd);
11385+ }
11386+ if (gintsts.b.nptxfempty) {
11387+ retval |= dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd);
11388+ }
11389+ if (gintsts.b.i2cintr) {
11390+ /** @todo Implement i2cintr handler. */
11391+ }
11392+ if (gintsts.b.portintr) {
11393+ retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
11394+ }
11395+ if (gintsts.b.hcintr) {
11396+ retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
11397+ }
11398+ if (gintsts.b.ptxfempty) {
11399+ retval |= dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd);
11400+ }
11401+#ifdef DEBUG
11402+# ifndef DEBUG_SOF
11403+ if (gintsts.d32 != DWC_SOF_INTR_MASK)
11404+# endif
11405+ {
11406+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Finished Servicing Interrupts\n");
11407+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
11408+ dwc_read_reg32(&global_regs->gintsts));
11409+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
11410+ dwc_read_reg32(&global_regs->gintmsk));
11411+ }
11412+#endif
11413+
11414+#ifdef DEBUG
11415+# ifndef DEBUG_SOF
11416+ if (gintsts.d32 != DWC_SOF_INTR_MASK)
11417+# endif
11418+ DWC_DEBUGPL(DBG_HCD, "\n");
11419+#endif
11420+
11421+ }
11422+ S3C2410X_CLEAR_EINTPEND();
11423+
11424+ return retval;
11425+}
11426+
11427+#ifdef DWC_TRACK_MISSED_SOFS
11428+#warning Compiling code to track missed SOFs
11429+#define FRAME_NUM_ARRAY_SIZE 1000
11430+/**
11431+ * This function is for debug only.
11432+ */
11433+static inline void track_missed_sofs(uint16_t curr_frame_number)
11434+{
11435+ static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];
11436+ static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
11437+ static int frame_num_idx = 0;
11438+ static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM;
11439+ static int dumped_frame_num_array = 0;
11440+
11441+ if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
11442+ if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) != curr_frame_number) {
11443+ frame_num_array[frame_num_idx] = curr_frame_number;
11444+ last_frame_num_array[frame_num_idx++] = last_frame_num;
11445+ }
11446+ } else if (!dumped_frame_num_array) {
11447+ int i;
11448+ printk(KERN_EMERG USB_DWC "Frame Last Frame\n");
11449+ printk(KERN_EMERG USB_DWC "----- ----------\n");
11450+ for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
11451+ printk(KERN_EMERG USB_DWC "0x%04x 0x%04x\n",
11452+ frame_num_array[i], last_frame_num_array[i]);
11453+ }
11454+ dumped_frame_num_array = 1;
11455+ }
11456+ last_frame_num = curr_frame_number;
11457+}
11458+#endif
11459+
11460+/**
11461+ * Handles the start-of-frame interrupt in host mode. Non-periodic
11462+ * transactions may be queued to the DWC_otg controller for the current
11463+ * (micro)frame. Periodic transactions may be queued to the controller for the
11464+ * next (micro)frame.
11465+ */
11466+int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t *hcd)
11467+{
11468+ hfnum_data_t hfnum;
11469+ struct list_head *qh_entry;
11470+ dwc_otg_qh_t *qh;
11471+ dwc_otg_transaction_type_e tr_type;
11472+ gintsts_data_t gintsts = {.d32 = 0};
11473+
11474+ hfnum.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hfnum);
11475+
11476+#ifdef DEBUG_SOF
11477+ DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
11478+#endif
11479+ hcd->frame_number = hfnum.b.frnum;
11480+
11481+#ifdef DEBUG
11482+ hcd->frrem_accum += hfnum.b.frrem;
11483+ hcd->frrem_samples++;
11484+#endif
11485+
11486+#ifdef DWC_TRACK_MISSED_SOFS
11487+ track_missed_sofs(hcd->frame_number);
11488+#endif
11489+
11490+ /* Determine whether any periodic QHs should be executed. */
11491+ qh_entry = hcd->periodic_sched_inactive.next;
11492+ while (qh_entry != &hcd->periodic_sched_inactive) {
11493+ qh = list_entry(qh_entry, dwc_otg_qh_t, qh_list_entry);
11494+ qh_entry = qh_entry->next;
11495+ if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) {
11496+ /*
11497+ * Move QH to the ready list to be executed next
11498+ * (micro)frame.
11499+ */
11500+ list_move(&qh->qh_list_entry, &hcd->periodic_sched_ready);
11501+ }
11502+ }
11503+
11504+ tr_type = dwc_otg_hcd_select_transactions(hcd);
11505+ if (tr_type != DWC_OTG_TRANSACTION_NONE) {
11506+ dwc_otg_hcd_queue_transactions(hcd, tr_type);
11507+ }
11508+
11509+ /* Clear interrupt */
11510+ gintsts.b.sofintr = 1;
11511+ dwc_write_reg32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32);
11512+
11513+ return 1;
11514+}
11515+
11516+/** Handles the Rx Status Queue Level Interrupt, which indicates that there is at
11517+ * least one packet in the Rx FIFO. The packets are moved from the FIFO to
11518+ * memory if the DWC_otg controller is operating in Slave mode. */
11519+int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *dwc_otg_hcd)
11520+{
11521+ host_grxsts_data_t grxsts;
11522+ dwc_hc_t *hc = NULL;
11523+
11524+ DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
11525+
11526+ grxsts.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp);
11527+
11528+ hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
11529+
11530+ /* Packet Status */
11531+ DWC_DEBUGPL(DBG_HCDV, " Ch num = %d\n", grxsts.b.chnum);
11532+ DWC_DEBUGPL(DBG_HCDV, " Count = %d\n", grxsts.b.bcnt);
11533+ DWC_DEBUGPL(DBG_HCDV, " DPID = %d, hc.dpid = %d\n", grxsts.b.dpid, hc->data_pid_start);
11534+ DWC_DEBUGPL(DBG_HCDV, " PStatus = %d\n", grxsts.b.pktsts);
11535+
11536+ switch (grxsts.b.pktsts) {
11537+ case DWC_GRXSTS_PKTSTS_IN:
11538+ /* Read the data into the host buffer. */
11539+ if (grxsts.b.bcnt > 0) {
11540+ dwc_otg_read_packet(dwc_otg_hcd->core_if,
11541+ hc->xfer_buff,
11542+ grxsts.b.bcnt);
11543+
11544+ /* Update the HC fields for the next packet received. */
11545+ hc->xfer_count += grxsts.b.bcnt;
11546+ hc->xfer_buff += grxsts.b.bcnt;
11547+ }
11548+
11549+ case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
11550+ case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
11551+ case DWC_GRXSTS_PKTSTS_CH_HALTED:
11552+ /* Handled in interrupt, just ignore data */
11553+ break;
11554+ default:
11555+ DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n", grxsts.b.pktsts);
11556+ break;
11557+ }
11558+
11559+ return 1;
11560+}
11561+
11562+/** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
11563+ * data packets may be written to the FIFO for OUT transfers. More requests
11564+ * may be written to the non-periodic request queue for IN transfers. This
11565+ * interrupt is enabled only in Slave mode. */
11566+int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd)
11567+{
11568+ DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
11569+ dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
11570+ DWC_OTG_TRANSACTION_NON_PERIODIC);
11571+ return 1;
11572+}
11573+
11574+/** This interrupt occurs when the periodic Tx FIFO is half-empty. More data
11575+ * packets may be written to the FIFO for OUT transfers. More requests may be
11576+ * written to the periodic request queue for IN transfers. This interrupt is
11577+ * enabled only in Slave mode. */
11578+int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd)
11579+{
11580+ DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
11581+ dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
11582+ DWC_OTG_TRANSACTION_PERIODIC);
11583+ return 1;
11584+}
11585+
11586+/** There are multiple conditions that can cause a port interrupt. This function
11587+ * determines which interrupt conditions have occurred and handles them
11588+ * appropriately. */
11589+int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t *dwc_otg_hcd)
11590+{
11591+ int retval = 0;
11592+ hprt0_data_t hprt0;
11593+ hprt0_data_t hprt0_modify;
11594+
11595+ hprt0.d32 = dwc_read_reg32(dwc_otg_hcd->core_if->host_if->hprt0);
11596+ hprt0_modify.d32 = dwc_read_reg32(dwc_otg_hcd->core_if->host_if->hprt0);
11597+
11598+ /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
11599+ * GINTSTS */
11600+
11601+ hprt0_modify.b.prtena = 0;
11602+ hprt0_modify.b.prtconndet = 0;
11603+ hprt0_modify.b.prtenchng = 0;
11604+ hprt0_modify.b.prtovrcurrchng = 0;
11605+
11606+ /* Port Connect Detected
11607+ * Set flag and clear if detected */
11608+ if (hprt0.b.prtconndet) {
11609+ DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
11610+ "Port Connect Detected--\n", hprt0.d32);
11611+ dwc_otg_hcd->flags.b.port_connect_status_change = 1;
11612+ dwc_otg_hcd->flags.b.port_connect_status = 1;
11613+ hprt0_modify.b.prtconndet = 1;
11614+
11615+ /* B-Device has connected, Delete the connection timer. */
11616+ del_timer( &dwc_otg_hcd->conn_timer );
11617+
11618+ /* The Hub driver asserts a reset when it sees port connect
11619+ * status change flag */
11620+ retval |= 1;
11621+ }
11622+
11623+ /* Port Enable Changed
11624+ * Clear if detected - Set internal flag if disabled */
11625+ if (hprt0.b.prtenchng) {
11626+ DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x "
11627+ "Port Enable Changed--\n", hprt0.d32);
11628+ hprt0_modify.b.prtenchng = 1;
11629+ if (hprt0.b.prtena == 1) {
11630+ int do_reset = 0;
11631+ dwc_otg_core_params_t *params = dwc_otg_hcd->core_if->core_params;
11632+ dwc_otg_core_global_regs_t *global_regs = dwc_otg_hcd->core_if->core_global_regs;
11633+ dwc_otg_host_if_t *host_if = dwc_otg_hcd->core_if->host_if;
11634+
11635+ /* Check if we need to adjust the PHY clock speed for
11636+ * low power and adjust it */
11637+ if (params->host_support_fs_ls_low_power) {
11638+ gusbcfg_data_t usbcfg;
11639+
11640+ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
11641+
11642+ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED ||
11643+ hprt0.b.prtspd == DWC_HPRT0_PRTSPD_FULL_SPEED) {
11644+ /*
11645+ * Low power
11646+ */
11647+ hcfg_data_t hcfg;
11648+ if (usbcfg.b.phylpwrclksel == 0) {
11649+ /* Set PHY low power clock select for FS/LS devices */
11650+ usbcfg.b.phylpwrclksel = 1;
11651+ dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
11652+ do_reset = 1;
11653+ }
11654+
11655+ hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg);
11656+
11657+ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED &&
11658+ params->host_ls_low_power_phy_clk ==
11659+ DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) {
11660+ /* 6 MHZ */
11661+ DWC_DEBUGPL(DBG_CIL, "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
11662+ if (hcfg.b.fslspclksel != DWC_HCFG_6_MHZ) {
11663+ hcfg.b.fslspclksel = DWC_HCFG_6_MHZ;
11664+ dwc_write_reg32(&host_if->host_global_regs->hcfg,
11665+ hcfg.d32);
11666+ do_reset = 1;
11667+ }
11668+ } else {
11669+ /* 48 MHZ */
11670+ DWC_DEBUGPL(DBG_CIL, "FS_PHY programming HCFG to 48 MHz ()\n");
11671+ if (hcfg.b.fslspclksel != DWC_HCFG_48_MHZ) {
11672+ hcfg.b.fslspclksel = DWC_HCFG_48_MHZ;
11673+ dwc_write_reg32(&host_if->host_global_regs->hcfg,
11674+ hcfg.d32);
11675+ do_reset = 1;
11676+ }
11677+ }
11678+ } else {
11679+ /*
11680+ * Not low power
11681+ */
11682+ if (usbcfg.b.phylpwrclksel == 1) {
11683+ usbcfg.b.phylpwrclksel = 0;
11684+ dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
11685+ do_reset = 1;
11686+ }
11687+ }
11688+
11689+ if (do_reset) {
11690+ tasklet_schedule(dwc_otg_hcd->reset_tasklet);
11691+ }
11692+ }
11693+
11694+ if (!do_reset) {
11695+ /* Port has been enabled set the reset change flag */
11696+ dwc_otg_hcd->flags.b.port_reset_change = 1;
11697+ }
11698+ } else {
11699+ dwc_otg_hcd->flags.b.port_enable_change = 1;
11700+ }
11701+ retval |= 1;
11702+ }
11703+
11704+ /** Overcurrent Change Interrupt */
11705+ if (hprt0.b.prtovrcurrchng) {
11706+ DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x "
11707+ "Port Overcurrent Changed--\n", hprt0.d32);
11708+ dwc_otg_hcd->flags.b.port_over_current_change = 1;
11709+ hprt0_modify.b.prtovrcurrchng = 1;
11710+ retval |= 1;
11711+ }
11712+
11713+ /* Clear Port Interrupts */
11714+ dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
11715+
11716+ return retval;
11717+}
11718+
11719+/** This interrupt indicates that one or more host channels has a pending
11720+ * interrupt. There are multiple conditions that can cause each host channel
11721+ * interrupt. This function determines which conditions have occurred for each
11722+ * host channel interrupt and handles them appropriately. */
11723+int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t *dwc_otg_hcd)
11724+{
11725+ int i;
11726+ int retval = 0;
11727+ haint_data_t haint;
11728+
11729+ /* Clear appropriate bits in HCINTn to clear the interrupt bit in
11730+ * GINTSTS */
11731+
11732+ haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if);
11733+
11734+ for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) {
11735+ if (haint.b2.chint & (1 << i)) {
11736+ retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i);
11737+ }
11738+ }
11739+
11740+ return retval;
11741+}
11742+
11743+/* Macro used to clear one channel interrupt */
11744+#define clear_hc_int(_hc_regs_, _intr_) \
11745+do { \
11746+ hcint_data_t hcint_clear = {.d32 = 0}; \
11747+ hcint_clear.b._intr_ = 1; \
11748+ dwc_write_reg32(&(_hc_regs_)->hcint, hcint_clear.d32); \
11749+} while (0)
11750+
11751+/*
11752+ * Macro used to disable one channel interrupt. Channel interrupts are
11753+ * disabled when the channel is halted or released by the interrupt handler.
11754+ * There is no need to handle further interrupts of that type until the
11755+ * channel is re-assigned. In fact, subsequent handling may cause crashes
11756+ * because the channel structures are cleaned up when the channel is released.
11757+ */
11758+#define disable_hc_int(_hc_regs_, _intr_) \
11759+do { \
11760+ hcintmsk_data_t hcintmsk = {.d32 = 0}; \
11761+ hcintmsk.b._intr_ = 1; \
11762+ dwc_modify_reg32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \
11763+} while (0)
11764+
11765+/**
11766+ * Gets the actual length of a transfer after the transfer halts. _halt_status
11767+ * holds the reason for the halt.
11768+ *
11769+ * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE,
11770+ * *short_read is set to 1 upon return if less than the requested
11771+ * number of bytes were transferred. Otherwise, *short_read is set to 0 upon
11772+ * return. short_read may also be NULL on entry, in which case it remains
11773+ * unchanged.
11774+ */
11775+static uint32_t get_actual_xfer_length(dwc_hc_t *hc,
11776+ dwc_otg_hc_regs_t *hc_regs,
11777+ dwc_otg_qtd_t *qtd,
11778+ dwc_otg_halt_status_e halt_status,
11779+ int *short_read)
11780+{
11781+ hctsiz_data_t hctsiz;
11782+ uint32_t length;
11783+
11784+ if (short_read != NULL) {
11785+ *short_read = 0;
11786+ }
11787+ hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
11788+
11789+ if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
11790+ if (hc->ep_is_in) {
11791+ length = hc->xfer_len - hctsiz.b.xfersize;
11792+ if (short_read != NULL) {
11793+ *short_read = (hctsiz.b.xfersize != 0);
11794+ }
11795+ } else if (hc->qh->do_split) {
11796+ length = qtd->ssplit_out_xfer_count;
11797+ } else {
11798+ length = hc->xfer_len;
11799+ }
11800+ } else {
11801+ /*
11802+ * Must use the hctsiz.pktcnt field to determine how much data
11803+ * has been transferred. This field reflects the number of
11804+ * packets that have been transferred via the USB. This is
11805+ * always an integral number of packets if the transfer was
11806+ * halted before its normal completion. (Can't use the
11807+ * hctsiz.xfersize field because that reflects the number of
11808+ * bytes transferred via the AHB, not the USB).
11809+ */
11810+ length = (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet;
11811+ }
11812+
11813+ return length;
11814+}
11815+
11816+/**
11817+ * Updates the state of the URB after a Transfer Complete interrupt on the
11818+ * host channel. Updates the actual_length field of the URB based on the
11819+ * number of bytes transferred via the host channel. Sets the URB status
11820+ * if the data transfer is finished.
11821+ *
11822+ * @return 1 if the data transfer specified by the URB is completely finished,
11823+ * 0 otherwise.
11824+ */
11825+static int update_urb_state_xfer_comp(dwc_hc_t *hc,
11826+ dwc_otg_hc_regs_t *hc_regs,
11827+ struct urb *urb,
11828+ dwc_otg_qtd_t *qtd)
11829+{
11830+ int xfer_done = 0;
11831+ int short_read = 0;
11832+
11833+ urb->actual_length += get_actual_xfer_length(hc, hc_regs, qtd,
11834+ DWC_OTG_HC_XFER_COMPLETE,
11835+ &short_read);
11836+
11837+ if (short_read || urb->actual_length == urb->transfer_buffer_length) {
11838+ xfer_done = 1;
11839+ if (short_read && (urb->transfer_flags & URB_SHORT_NOT_OK)) {
11840+ urb->status = -EREMOTEIO;
11841+ } else {
11842+ urb->status = 0;
11843+ }
11844+ }
11845+
11846+#ifdef DEBUG
11847+ {
11848+ hctsiz_data_t hctsiz;
11849+ hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
11850+ DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
11851+ __func__, (hc->ep_is_in ? "IN" : "OUT"), hc->hc_num);
11852+ DWC_DEBUGPL(DBG_HCDV, " hc->xfer_len %d\n", hc->xfer_len);
11853+ DWC_DEBUGPL(DBG_HCDV, " hctsiz.xfersize %d\n", hctsiz.b.xfersize);
11854+ DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n",
11855+ urb->transfer_buffer_length);
11856+ DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n", urb->actual_length);
11857+ DWC_DEBUGPL(DBG_HCDV, " short_read %d, xfer_done %d\n",
11858+ short_read, xfer_done);
11859+ }
11860+#endif
11861+
11862+ return xfer_done;
11863+}
11864+
11865+/*
11866+ * Save the starting data toggle for the next transfer. The data toggle is
11867+ * saved in the QH for non-control transfers and it's saved in the QTD for
11868+ * control transfers.
11869+ */
11870+static void save_data_toggle(dwc_hc_t *hc,
11871+ dwc_otg_hc_regs_t *hc_regs,
11872+ dwc_otg_qtd_t *qtd)
11873+{
11874+ hctsiz_data_t hctsiz;
11875+ hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
11876+
11877+ if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
11878+ dwc_otg_qh_t *qh = hc->qh;
11879+ if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
11880+ qh->data_toggle = DWC_OTG_HC_PID_DATA0;
11881+ } else {
11882+ qh->data_toggle = DWC_OTG_HC_PID_DATA1;
11883+ }
11884+ } else {
11885+ if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
11886+ qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
11887+ } else {
11888+ qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
11889+ }
11890+ }
11891+}
11892+
11893+/**
11894+ * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
11895+ * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
11896+ * still linked to the QH, the QH is added to the end of the inactive
11897+ * non-periodic schedule. For periodic QHs, removes the QH from the periodic
11898+ * schedule if no more QTDs are linked to the QH.
11899+ */
11900+static void deactivate_qh(dwc_otg_hcd_t *hcd,
11901+ dwc_otg_qh_t *qh,
11902+ int free_qtd)
11903+{
11904+ int continue_split = 0;
11905+ dwc_otg_qtd_t *qtd;
11906+
11907+ DWC_DEBUGPL(DBG_HCDV, " %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd);
11908+
11909+ spin_lock(&hcd->lock);
11910+ qtd = list_entry(qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
11911+
11912+ if (qtd->complete_split) {
11913+ continue_split = 1;
11914+ } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID ||
11915+ qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) {
11916+ continue_split = 1;
11917+ }
11918+
11919+ if (free_qtd) {
11920+ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd);
11921+ continue_split = 0;
11922+ }
11923+
11924+ qh->channel = NULL;
11925+ qh->qtd_in_process = NULL;
11926+ spin_unlock(&hcd->lock);
11927+ dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);
11928+}
11929+
11930+/**
11931+ * Updates the state of an Isochronous URB when the transfer is stopped for
11932+ * any reason. The fields of the current entry in the frame descriptor array
11933+ * are set based on the transfer state and the input _halt_status. Completes
11934+ * the Isochronous URB if all the URB frames have been completed.
11935+ *
11936+ * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be
11937+ * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
11938+ */
11939+static dwc_otg_halt_status_e
11940+update_isoc_urb_state(dwc_otg_hcd_t *hcd,
11941+ dwc_hc_t *hc,
11942+ dwc_otg_hc_regs_t *hc_regs,
11943+ dwc_otg_qtd_t *qtd,
11944+ dwc_otg_halt_status_e halt_status)
11945+{
11946+ struct urb *urb = qtd->urb;
11947+ dwc_otg_halt_status_e ret_val = halt_status;
11948+ struct usb_iso_packet_descriptor *frame_desc;
11949+
11950+ frame_desc = &urb->iso_frame_desc[qtd->isoc_frame_index];
11951+ switch (halt_status) {
11952+ case DWC_OTG_HC_XFER_COMPLETE:
11953+ frame_desc->status = 0;
11954+ frame_desc->actual_length =
11955+ get_actual_xfer_length(hc, hc_regs, qtd,
11956+ halt_status, NULL);
11957+ break;
11958+ case DWC_OTG_HC_XFER_FRAME_OVERRUN:
11959+ urb->error_count++;
11960+ if (hc->ep_is_in) {
11961+ frame_desc->status = -ENOSR;
11962+ } else {
11963+ frame_desc->status = -ECOMM;
11964+ }
11965+ frame_desc->actual_length = 0;
11966+ break;
11967+ case DWC_OTG_HC_XFER_BABBLE_ERR:
11968+ urb->error_count++;
11969+ frame_desc->status = -EOVERFLOW;
11970+ /* Don't need to update actual_length in this case. */
11971+ break;
11972+ case DWC_OTG_HC_XFER_XACT_ERR:
11973+ urb->error_count++;
11974+ frame_desc->status = -EPROTO;
11975+ frame_desc->actual_length =
11976+ get_actual_xfer_length(hc, hc_regs, qtd,
11977+ halt_status, NULL);
11978+ default:
11979+ DWC_ERROR("%s: Unhandled _halt_status (%d)\n", __func__,
11980+ halt_status);
11981+ BUG();
11982+ break;
11983+ }
11984+
11985+ if (++qtd->isoc_frame_index == urb->number_of_packets) {
11986+ /*
11987+ * urb->status is not used for isoc transfers.
11988+ * The individual frame_desc statuses are used instead.
11989+ */
11990+ dwc_otg_hcd_complete_urb(hcd, urb, 0);
11991+ ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
11992+ } else {
11993+ ret_val = DWC_OTG_HC_XFER_COMPLETE;
11994+ }
11995+
11996+ return ret_val;
11997+}
11998+
11999+/**
12000+ * Releases a host channel for use by other transfers. Attempts to select and
12001+ * queue more transactions since at least one host channel is available.
12002+ *
12003+ * @param hcd The HCD state structure.
12004+ * @param hc The host channel to release.
12005+ * @param qtd The QTD associated with the host channel. This QTD may be freed
12006+ * if the transfer is complete or an error has occurred.
12007+ * @param halt_status Reason the channel is being released. This status
12008+ * determines the actions taken by this function.
12009+ */
12010+static void release_channel(dwc_otg_hcd_t *hcd,
12011+ dwc_hc_t *hc,
12012+ dwc_otg_qtd_t *qtd,
12013+ dwc_otg_halt_status_e halt_status)
12014+{
12015+ dwc_otg_transaction_type_e tr_type;
12016+ int free_qtd;
12017+
12018+ DWC_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d\n",
12019+ __func__, hc->hc_num, halt_status);
12020+
12021+ switch (halt_status) {
12022+ case DWC_OTG_HC_XFER_URB_COMPLETE:
12023+ free_qtd = 1;
12024+ break;
12025+ case DWC_OTG_HC_XFER_AHB_ERR:
12026+ case DWC_OTG_HC_XFER_STALL:
12027+ case DWC_OTG_HC_XFER_BABBLE_ERR:
12028+ free_qtd = 1;
12029+ break;
12030+ case DWC_OTG_HC_XFER_XACT_ERR:
12031+ if (qtd->error_count >= 3) {
12032+ DWC_DEBUGPL(DBG_HCDV, " Complete URB with transaction error\n");
12033+ free_qtd = 1;
12034+ qtd->urb->status = -EPROTO;
12035+ dwc_otg_hcd_complete_urb(hcd, qtd->urb, -EPROTO);
12036+ } else {
12037+ free_qtd = 0;
12038+ }
12039+ break;
12040+ case DWC_OTG_HC_XFER_URB_DEQUEUE:
12041+ /*
12042+ * The QTD has already been removed and the QH has been
12043+ * deactivated. Don't want to do anything except release the
12044+ * host channel and try to queue more transfers.
12045+ */
12046+ goto cleanup;
12047+ case DWC_OTG_HC_XFER_NO_HALT_STATUS:
12048+ DWC_ERROR("%s: No halt_status, channel %d\n", __func__, hc->hc_num);
12049+ free_qtd = 0;
12050+ break;
12051+ default:
12052+ free_qtd = 0;
12053+ break;
12054+ }
12055+
12056+ deactivate_qh(hcd, hc->qh, free_qtd);
12057+
12058+ cleanup:
12059+ /*
12060+ * Release the host channel for use by other transfers. The cleanup
12061+ * function clears the channel interrupt enables and conditions, so
12062+ * there's no need to clear the Channel Halted interrupt separately.
12063+ */
12064+ dwc_otg_hc_cleanup(hcd->core_if, hc);
12065+ list_add_tail(&hc->hc_list_entry, &hcd->free_hc_list);
12066+
12067+ switch (hc->ep_type) {
12068+ case DWC_OTG_EP_TYPE_CONTROL:
12069+ case DWC_OTG_EP_TYPE_BULK:
12070+ hcd->non_periodic_channels--;
12071+ break;
12072+
12073+ default:
12074+ /*
12075+ * Don't release reservations for periodic channels here.
12076+ * That's done when a periodic transfer is descheduled (i.e.
12077+ * when the QH is removed from the periodic schedule).
12078+ */
12079+ break;
12080+ }
12081+
12082+ /* Try to queue more transfers now that there's a free channel. */
12083+ tr_type = dwc_otg_hcd_select_transactions(hcd);
12084+ if (tr_type != DWC_OTG_TRANSACTION_NONE) {
12085+ dwc_otg_hcd_queue_transactions(hcd, tr_type);
12086+ }
12087+}
12088+
12089+/**
12090+ * Halts a host channel. If the channel cannot be halted immediately because
12091+ * the request queue is full, this function ensures that the FIFO empty
12092+ * interrupt for the appropriate queue is enabled so that the halt request can
12093+ * be queued when there is space in the request queue.
12094+ *
12095+ * This function may also be called in DMA mode. In that case, the channel is
12096+ * simply released since the core always halts the channel automatically in
12097+ * DMA mode.
12098+ */
12099+static void halt_channel(dwc_otg_hcd_t *hcd,
12100+ dwc_hc_t *hc,
12101+ dwc_otg_qtd_t *qtd,
12102+ dwc_otg_halt_status_e halt_status)
12103+{
12104+ if (hcd->core_if->dma_enable) {
12105+ release_channel(hcd, hc, qtd, halt_status);
12106+ return;
12107+ }
12108+
12109+ /* Slave mode processing... */
12110+ dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
12111+
12112+ if (hc->halt_on_queue) {
12113+ gintmsk_data_t gintmsk = {.d32 = 0};
12114+ dwc_otg_core_global_regs_t *global_regs;
12115+ global_regs = hcd->core_if->core_global_regs;
12116+
12117+ if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
12118+ hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
12119+ /*
12120+ * Make sure the Non-periodic Tx FIFO empty interrupt
12121+ * is enabled so that the non-periodic schedule will
12122+ * be processed.
12123+ */
12124+ gintmsk.b.nptxfempty = 1;
12125+ dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32);
12126+ } else {
12127+ /*
12128+ * Move the QH from the periodic queued schedule to
12129+ * the periodic assigned schedule. This allows the
12130+ * halt to be queued when the periodic schedule is
12131+ * processed.
12132+ */
12133+ list_move(&hc->qh->qh_list_entry,
12134+ &hcd->periodic_sched_assigned);
12135+
12136+ /*
12137+ * Make sure the Periodic Tx FIFO Empty interrupt is
12138+ * enabled so that the periodic schedule will be
12139+ * processed.
12140+ */
12141+ gintmsk.b.ptxfempty = 1;
12142+ dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32);
12143+ }
12144+ }
12145+}
12146+
12147+/**
12148+ * Performs common cleanup for non-periodic transfers after a Transfer
12149+ * Complete interrupt. This function should be called after any endpoint type
12150+ * specific handling is finished to release the host channel.
12151+ */
12152+static void complete_non_periodic_xfer(dwc_otg_hcd_t *hcd,
12153+ dwc_hc_t *hc,
12154+ dwc_otg_hc_regs_t *hc_regs,
12155+ dwc_otg_qtd_t *qtd,
12156+ dwc_otg_halt_status_e halt_status)
12157+{
12158+ hcint_data_t hcint;
12159+
12160+ qtd->error_count = 0;
12161+
12162+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
12163+ if (hcint.b.nyet) {
12164+ /*
12165+ * Got a NYET on the last transaction of the transfer. This
12166+ * means that the endpoint should be in the PING state at the
12167+ * beginning of the next transfer.
12168+ */
12169+ hc->qh->ping_state = 1;
12170+ clear_hc_int(hc_regs, nyet);
12171+ }
12172+
12173+ /*
12174+ * Always halt and release the host channel to make it available for
12175+ * more transfers. There may still be more phases for a control
12176+ * transfer or more data packets for a bulk transfer at this point,
12177+ * but the host channel is still halted. A channel will be reassigned
12178+ * to the transfer when the non-periodic schedule is processed after
12179+ * the channel is released. This allows transactions to be queued
12180+ * properly via dwc_otg_hcd_queue_transactions, which also enables the
12181+ * Tx FIFO Empty interrupt if necessary.
12182+ */
12183+ if (hc->ep_is_in) {
12184+ /*
12185+ * IN transfers in Slave mode require an explicit disable to
12186+ * halt the channel. (In DMA mode, this call simply releases
12187+ * the channel.)
12188+ */
12189+ halt_channel(hcd, hc, qtd, halt_status);
12190+ } else {
12191+ /*
12192+ * The channel is automatically disabled by the core for OUT
12193+ * transfers in Slave mode.
12194+ */
12195+ release_channel(hcd, hc, qtd, halt_status);
12196+ }
12197+}
12198+
12199+/**
12200+ * Performs common cleanup for periodic transfers after a Transfer Complete
12201+ * interrupt. This function should be called after any endpoint type specific
12202+ * handling is finished to release the host channel.
12203+ */
12204+static void complete_periodic_xfer(dwc_otg_hcd_t *hcd,
12205+ dwc_hc_t *hc,
12206+ dwc_otg_hc_regs_t *hc_regs,
12207+ dwc_otg_qtd_t *qtd,
12208+ dwc_otg_halt_status_e halt_status)
12209+{
12210+ hctsiz_data_t hctsiz;
12211+ qtd->error_count = 0;
12212+
12213+ hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
12214+ if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) {
12215+ /* Core halts channel in these cases. */
12216+ release_channel(hcd, hc, qtd, halt_status);
12217+ } else {
12218+ /* Flush any outstanding requests from the Tx queue. */
12219+ halt_channel(hcd, hc, qtd, halt_status);
12220+ }
12221+}
12222+
12223+/**
12224+ * Handles a host channel Transfer Complete interrupt. This handler may be
12225+ * called in either DMA mode or Slave mode.
12226+ */
12227+static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t *hcd,
12228+ dwc_hc_t *hc,
12229+ dwc_otg_hc_regs_t *hc_regs,
12230+ dwc_otg_qtd_t *qtd)
12231+{
12232+ int urb_xfer_done;
12233+ dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE;
12234+ struct urb *urb = qtd->urb;
12235+ int pipe_type = usb_pipetype(urb->pipe);
12236+
12237+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12238+ "Transfer Complete--\n", hc->hc_num);
12239+
12240+ /*
12241+ * Handle xfer complete on CSPLIT.
12242+ */
12243+ if (hc->qh->do_split) {
12244+ qtd->complete_split = 0;
12245+ }
12246+
12247+ /* Update the QTD and URB states. */
12248+ switch (pipe_type) {
12249+ case PIPE_CONTROL:
12250+ switch (qtd->control_phase) {
12251+ case DWC_OTG_CONTROL_SETUP:
12252+ if (urb->transfer_buffer_length > 0) {
12253+ qtd->control_phase = DWC_OTG_CONTROL_DATA;
12254+ } else {
12255+ qtd->control_phase = DWC_OTG_CONTROL_STATUS;
12256+ }
12257+ DWC_DEBUGPL(DBG_HCDV, " Control setup transaction done\n");
12258+ halt_status = DWC_OTG_HC_XFER_COMPLETE;
12259+ break;
12260+ case DWC_OTG_CONTROL_DATA: {
12261+ urb_xfer_done = update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
12262+ if (urb_xfer_done) {
12263+ qtd->control_phase = DWC_OTG_CONTROL_STATUS;
12264+ DWC_DEBUGPL(DBG_HCDV, " Control data transfer done\n");
12265+ } else {
12266+ save_data_toggle(hc, hc_regs, qtd);
12267+ }
12268+ halt_status = DWC_OTG_HC_XFER_COMPLETE;
12269+ break;
12270+ }
12271+ case DWC_OTG_CONTROL_STATUS:
12272+ DWC_DEBUGPL(DBG_HCDV, " Control transfer complete\n");
12273+ if (urb->status == -EINPROGRESS) {
12274+ urb->status = 0;
12275+ }
12276+ dwc_otg_hcd_complete_urb(hcd, urb, urb->status);
12277+ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
12278+ break;
12279+ }
12280+
12281+ complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
12282+ break;
12283+ case PIPE_BULK:
12284+ DWC_DEBUGPL(DBG_HCDV, " Bulk transfer complete\n");
12285+ urb_xfer_done = update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
12286+ if (urb_xfer_done) {
12287+ dwc_otg_hcd_complete_urb(hcd, urb, urb->status);
12288+ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
12289+ } else {
12290+ halt_status = DWC_OTG_HC_XFER_COMPLETE;
12291+ }
12292+
12293+ save_data_toggle(hc, hc_regs, qtd);
12294+ complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
12295+ break;
12296+ case PIPE_INTERRUPT:
12297+ DWC_DEBUGPL(DBG_HCDV, " Interrupt transfer complete\n");
12298+ update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
12299+
12300+ /*
12301+ * Interrupt URB is done on the first transfer complete
12302+ * interrupt.
12303+ */
12304+ dwc_otg_hcd_complete_urb(hcd, urb, urb->status);
12305+ save_data_toggle(hc, hc_regs, qtd);
12306+ complete_periodic_xfer(hcd, hc, hc_regs, qtd,
12307+ DWC_OTG_HC_XFER_URB_COMPLETE);
12308+ break;
12309+ case PIPE_ISOCHRONOUS:
12310+ DWC_DEBUGPL(DBG_HCDV, " Isochronous transfer complete\n");
12311+ if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) {
12312+ halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
12313+ DWC_OTG_HC_XFER_COMPLETE);
12314+ }
12315+ complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
12316+ break;
12317+ }
12318+
12319+ disable_hc_int(hc_regs, xfercompl);
12320+
12321+ return 1;
12322+}
12323+
12324+/**
12325+ * Handles a host channel STALL interrupt. This handler may be called in
12326+ * either DMA mode or Slave mode.
12327+ */
12328+static int32_t handle_hc_stall_intr(dwc_otg_hcd_t *hcd,
12329+ dwc_hc_t *hc,
12330+ dwc_otg_hc_regs_t *hc_regs,
12331+ dwc_otg_qtd_t *qtd)
12332+{
12333+ struct urb *urb = qtd->urb;
12334+ int pipe_type = usb_pipetype(urb->pipe);
12335+
12336+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12337+ "STALL Received--\n", hc->hc_num);
12338+
12339+ if (pipe_type == PIPE_CONTROL) {
12340+ dwc_otg_hcd_complete_urb(hcd, urb, -EPIPE);
12341+ }
12342+
12343+ if (pipe_type == PIPE_BULK || pipe_type == PIPE_INTERRUPT) {
12344+ dwc_otg_hcd_complete_urb(hcd, urb, -EPIPE);
12345+ /*
12346+ * USB protocol requires resetting the data toggle for bulk
12347+ * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
12348+ * setup command is issued to the endpoint. Anticipate the
12349+ * CLEAR_FEATURE command since a STALL has occurred and reset
12350+ * the data toggle now.
12351+ */
12352+ hc->qh->data_toggle = 0;
12353+ }
12354+
12355+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL);
12356+
12357+ disable_hc_int(hc_regs, stall);
12358+
12359+ return 1;
12360+}
12361+
12362+/*
12363+ * Updates the state of the URB when a transfer has been stopped due to an
12364+ * abnormal condition before the transfer completes. Modifies the
12365+ * actual_length field of the URB to reflect the number of bytes that have
12366+ * actually been transferred via the host channel.
12367+ */
12368+static void update_urb_state_xfer_intr(dwc_hc_t *hc,
12369+ dwc_otg_hc_regs_t *hc_regs,
12370+ struct urb *urb,
12371+ dwc_otg_qtd_t *qtd,
12372+ dwc_otg_halt_status_e halt_status)
12373+{
12374+ uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd,
12375+ halt_status, NULL);
12376+ urb->actual_length += bytes_transferred;
12377+
12378+#ifdef DEBUG
12379+ {
12380+ hctsiz_data_t hctsiz;
12381+ hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
12382+ DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
12383+ __func__, (hc->ep_is_in ? "IN" : "OUT"), hc->hc_num);
12384+ DWC_DEBUGPL(DBG_HCDV, " hc->start_pkt_count %d\n", hc->start_pkt_count);
12385+ DWC_DEBUGPL(DBG_HCDV, " hctsiz.pktcnt %d\n", hctsiz.b.pktcnt);
12386+ DWC_DEBUGPL(DBG_HCDV, " hc->max_packet %d\n", hc->max_packet);
12387+ DWC_DEBUGPL(DBG_HCDV, " bytes_transferred %d\n", bytes_transferred);
12388+ DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n", urb->actual_length);
12389+ DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n",
12390+ urb->transfer_buffer_length);
12391+ }
12392+#endif
12393+}
12394+
12395+/**
12396+ * Handles a host channel NAK interrupt. This handler may be called in either
12397+ * DMA mode or Slave mode.
12398+ */
12399+static int32_t handle_hc_nak_intr(dwc_otg_hcd_t *hcd,
12400+ dwc_hc_t *hc,
12401+ dwc_otg_hc_regs_t *hc_regs,
12402+ dwc_otg_qtd_t *qtd)
12403+{
12404+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12405+ "NAK Received--\n", hc->hc_num);
12406+
12407+ /*
12408+ * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
12409+ * interrupt. Re-start the SSPLIT transfer.
12410+ */
12411+ if (hc->do_split) {
12412+ if (hc->complete_split) {
12413+ qtd->error_count = 0;
12414+ }
12415+ qtd->complete_split = 0;
12416+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
12417+ goto handle_nak_done;
12418+ }
12419+
12420+ switch (usb_pipetype(qtd->urb->pipe)) {
12421+ case PIPE_CONTROL:
12422+ case PIPE_BULK:
12423+ if (hcd->core_if->dma_enable && hc->ep_is_in) {
12424+ /*
12425+ * NAK interrupts are enabled on bulk/control IN
12426+ * transfers in DMA mode for the sole purpose of
12427+ * resetting the error count after a transaction error
12428+ * occurs. The core will continue transferring data.
12429+ */
12430+ qtd->error_count = 0;
12431+ goto handle_nak_done;
12432+ }
12433+
12434+ /*
12435+ * NAK interrupts normally occur during OUT transfers in DMA
12436+ * or Slave mode. For IN transfers, more requests will be
12437+ * queued as request queue space is available.
12438+ */
12439+ qtd->error_count = 0;
12440+
12441+ if (!hc->qh->ping_state) {
12442+ update_urb_state_xfer_intr(hc, hc_regs, qtd->urb,
12443+ qtd, DWC_OTG_HC_XFER_NAK);
12444+ save_data_toggle(hc, hc_regs, qtd);
12445+ if (qtd->urb->dev->speed == USB_SPEED_HIGH) {
12446+ hc->qh->ping_state = 1;
12447+ }
12448+ }
12449+
12450+ /*
12451+ * Halt the channel so the transfer can be re-started from
12452+ * the appropriate point or the PING protocol will
12453+ * start/continue.
12454+ */
12455+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
12456+ break;
12457+ case PIPE_INTERRUPT:
12458+ qtd->error_count = 0;
12459+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
12460+ break;
12461+ case PIPE_ISOCHRONOUS:
12462+ /* Should never get called for isochronous transfers. */
12463+ BUG();
12464+ break;
12465+ }
12466+
12467+ handle_nak_done:
12468+ disable_hc_int(hc_regs, nak);
12469+
12470+ return 1;
12471+}
12472+
12473+/**
12474+ * Handles a host channel ACK interrupt. This interrupt is enabled when
12475+ * performing the PING protocol in Slave mode, when errors occur during
12476+ * either Slave mode or DMA mode, and during Start Split transactions.
12477+ */
12478+static int32_t handle_hc_ack_intr(dwc_otg_hcd_t *hcd,
12479+ dwc_hc_t *hc,
12480+ dwc_otg_hc_regs_t *hc_regs,
12481+ dwc_otg_qtd_t *qtd)
12482+{
12483+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12484+ "ACK Received--\n", hc->hc_num);
12485+
12486+ if (hc->do_split) {
12487+ /*
12488+ * Handle ACK on SSPLIT.
12489+ * ACK should not occur in CSPLIT.
12490+ */
12491+ if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) {
12492+ qtd->ssplit_out_xfer_count = hc->xfer_len;
12493+ }
12494+ if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) {
12495+ /* Don't need complete for isochronous out transfers. */
12496+ qtd->complete_split = 1;
12497+ }
12498+
12499+ /* ISOC OUT */
12500+ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
12501+ switch (hc->xact_pos) {
12502+ case DWC_HCSPLIT_XACTPOS_ALL:
12503+ break;
12504+ case DWC_HCSPLIT_XACTPOS_END:
12505+ qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
12506+ qtd->isoc_split_offset = 0;
12507+ break;
12508+ case DWC_HCSPLIT_XACTPOS_BEGIN:
12509+ case DWC_HCSPLIT_XACTPOS_MID:
12510+ /*
12511+ * For BEGIN or MID, calculate the length for
12512+ * the next microframe to determine the correct
12513+ * SSPLIT token, either MID or END.
12514+ */
12515+ {
12516+ struct usb_iso_packet_descriptor *frame_desc;
12517+
12518+ frame_desc = &qtd->urb->iso_frame_desc[qtd->isoc_frame_index];
12519+ qtd->isoc_split_offset += 188;
12520+
12521+ if ((frame_desc->length - qtd->isoc_split_offset) <= 188) {
12522+ qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_END;
12523+ } else {
12524+ qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_MID;
12525+ }
12526+
12527+ }
12528+ break;
12529+ }
12530+ } else {
12531+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
12532+ }
12533+ } else {
12534+ qtd->error_count = 0;
12535+
12536+ if (hc->qh->ping_state) {
12537+ hc->qh->ping_state = 0;
12538+ /*
12539+ * Halt the channel so the transfer can be re-started
12540+ * from the appropriate point. This only happens in
12541+ * Slave mode. In DMA mode, the ping_state is cleared
12542+ * when the transfer is started because the core
12543+ * automatically executes the PING, then the transfer.
12544+ */
12545+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
12546+ }
12547+ }
12548+
12549+ /*
12550+ * If the ACK occurred when _not_ in the PING state, let the channel
12551+ * continue transferring data after clearing the error count.
12552+ */
12553+
12554+ disable_hc_int(hc_regs, ack);
12555+
12556+ return 1;
12557+}
12558+
12559+/**
12560+ * Handles a host channel NYET interrupt. This interrupt should only occur on
12561+ * Bulk and Control OUT endpoints and for complete split transactions. If a
12562+ * NYET occurs at the same time as a Transfer Complete interrupt, it is
12563+ * handled in the xfercomp interrupt handler, not here. This handler may be
12564+ * called in either DMA mode or Slave mode.
12565+ */
12566+static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t *hcd,
12567+ dwc_hc_t *hc,
12568+ dwc_otg_hc_regs_t *hc_regs,
12569+ dwc_otg_qtd_t *qtd)
12570+{
12571+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12572+ "NYET Received--\n", hc->hc_num);
12573+
12574+ /*
12575+ * NYET on CSPLIT
12576+ * re-do the CSPLIT immediately on non-periodic
12577+ */
12578+ if (hc->do_split && hc->complete_split) {
12579+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
12580+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
12581+ int frnum = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(hcd));
12582+
12583+ if (dwc_full_frame_num(frnum) !=
12584+ dwc_full_frame_num(hc->qh->sched_frame)) {
12585+ /*
12586+ * No longer in the same full speed frame.
12587+ * Treat this as a transaction error.
12588+ */
12589+#if 0
12590+ /** @todo Fix system performance so this can
12591+ * be treated as an error. Right now complete
12592+ * splits cannot be scheduled precisely enough
12593+ * due to other system activity, so this error
12594+ * occurs regularly in Slave mode.
12595+ */
12596+ qtd->error_count++;
12597+#endif
12598+ qtd->complete_split = 0;
12599+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
12600+ /** @todo add support for isoc release */
12601+ goto handle_nyet_done;
12602+ }
12603+ }
12604+
12605+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
12606+ goto handle_nyet_done;
12607+ }
12608+
12609+ hc->qh->ping_state = 1;
12610+ qtd->error_count = 0;
12611+
12612+ update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd,
12613+ DWC_OTG_HC_XFER_NYET);
12614+ save_data_toggle(hc, hc_regs, qtd);
12615+
12616+ /*
12617+ * Halt the channel and re-start the transfer so the PING
12618+ * protocol will start.
12619+ */
12620+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
12621+
12622+handle_nyet_done:
12623+ disable_hc_int(hc_regs, nyet);
12624+ return 1;
12625+}
12626+
12627+/**
12628+ * Handles a host channel babble interrupt. This handler may be called in
12629+ * either DMA mode or Slave mode.
12630+ */
12631+static int32_t handle_hc_babble_intr(dwc_otg_hcd_t *hcd,
12632+ dwc_hc_t *hc,
12633+ dwc_otg_hc_regs_t *hc_regs,
12634+ dwc_otg_qtd_t *qtd)
12635+{
12636+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12637+ "Babble Error--\n", hc->hc_num);
12638+ if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
12639+ dwc_otg_hcd_complete_urb(hcd, qtd->urb, -EOVERFLOW);
12640+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR);
12641+ } else {
12642+ dwc_otg_halt_status_e halt_status;
12643+ halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
12644+ DWC_OTG_HC_XFER_BABBLE_ERR);
12645+ halt_channel(hcd, hc, qtd, halt_status);
12646+ }
12647+ disable_hc_int(hc_regs, bblerr);
12648+ return 1;
12649+}
12650+
12651+/**
12652+ * Handles a host channel AHB error interrupt. This handler is only called in
12653+ * DMA mode.
12654+ */
12655+static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t *hcd,
12656+ dwc_hc_t *hc,
12657+ dwc_otg_hc_regs_t *hc_regs,
12658+ dwc_otg_qtd_t *qtd)
12659+{
12660+ hcchar_data_t hcchar;
12661+ hcsplt_data_t hcsplt;
12662+ hctsiz_data_t hctsiz;
12663+ uint32_t hcdma;
12664+ struct urb *urb = qtd->urb;
12665+
12666+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12667+ "AHB Error--\n", hc->hc_num);
12668+
12669+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
12670+ hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
12671+ hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
12672+ hcdma = dwc_read_reg32(&hc_regs->hcdma);
12673+
12674+ DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num);
12675+ DWC_ERROR(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
12676+ DWC_ERROR(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
12677+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n");
12678+ DWC_ERROR(" Device address: %d\n", usb_pipedevice(urb->pipe));
12679+ DWC_ERROR(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
12680+ (usb_pipein(urb->pipe) ? "IN" : "OUT"));
12681+ DWC_ERROR(" Endpoint type: %s\n",
12682+ ({char *pipetype;
12683+ switch (usb_pipetype(urb->pipe)) {
12684+ case PIPE_CONTROL: pipetype = "CONTROL"; break;
12685+ case PIPE_BULK: pipetype = "BULK"; break;
12686+ case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break;
12687+ case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break;
12688+ default: pipetype = "UNKNOWN"; break;
12689+ }; pipetype;}));
12690+ DWC_ERROR(" Speed: %s\n",
12691+ ({char *speed;
12692+ switch (urb->dev->speed) {
12693+ case USB_SPEED_HIGH: speed = "HIGH"; break;
12694+ case USB_SPEED_FULL: speed = "FULL"; break;
12695+ case USB_SPEED_LOW: speed = "LOW"; break;
12696+ default: speed = "UNKNOWN"; break;
12697+ }; speed;}));
12698+ DWC_ERROR(" Max packet size: %d\n",
12699+ usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
12700+ DWC_ERROR(" Data buffer length: %d\n", urb->transfer_buffer_length);
12701+ DWC_ERROR(" Transfer buffer: %p, Transfer DMA: %p\n",
12702+ urb->transfer_buffer, (void *)urb->transfer_dma);
12703+ DWC_ERROR(" Setup buffer: %p, Setup DMA: %p\n",
12704+ urb->setup_packet, (void *)urb->setup_dma);
12705+ DWC_ERROR(" Interval: %d\n", urb->interval);
12706+
12707+ dwc_otg_hcd_complete_urb(hcd, urb, -EIO);
12708+
12709+ /*
12710+ * Force a channel halt. Don't call halt_channel because that won't
12711+ * write to the HCCHARn register in DMA mode to force the halt.
12712+ */
12713+ dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR);
12714+
12715+ disable_hc_int(hc_regs, ahberr);
12716+ return 1;
12717+}
12718+
12719+/**
12720+ * Handles a host channel transaction error interrupt. This handler may be
12721+ * called in either DMA mode or Slave mode.
12722+ */
12723+static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t *hcd,
12724+ dwc_hc_t *hc,
12725+ dwc_otg_hc_regs_t *hc_regs,
12726+ dwc_otg_qtd_t *qtd)
12727+{
12728+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12729+ "Transaction Error--\n", hc->hc_num);
12730+
12731+ switch (usb_pipetype(qtd->urb->pipe)) {
12732+ case PIPE_CONTROL:
12733+ case PIPE_BULK:
12734+ qtd->error_count++;
12735+ if (!hc->qh->ping_state) {
12736+ update_urb_state_xfer_intr(hc, hc_regs, qtd->urb,
12737+ qtd, DWC_OTG_HC_XFER_XACT_ERR);
12738+ save_data_toggle(hc, hc_regs, qtd);
12739+ if (!hc->ep_is_in && qtd->urb->dev->speed == USB_SPEED_HIGH) {
12740+ hc->qh->ping_state = 1;
12741+ }
12742+ }
12743+
12744+ /*
12745+ * Halt the channel so the transfer can be re-started from
12746+ * the appropriate point or the PING protocol will start.
12747+ */
12748+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
12749+ break;
12750+ case PIPE_INTERRUPT:
12751+ qtd->error_count++;
12752+ if (hc->do_split && hc->complete_split) {
12753+ qtd->complete_split = 0;
12754+ }
12755+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
12756+ break;
12757+ case PIPE_ISOCHRONOUS:
12758+ {
12759+ dwc_otg_halt_status_e halt_status;
12760+ halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
12761+ DWC_OTG_HC_XFER_XACT_ERR);
12762+
12763+ halt_channel(hcd, hc, qtd, halt_status);
12764+ }
12765+ break;
12766+ }
12767+
12768+ disable_hc_int(hc_regs, xacterr);
12769+
12770+ return 1;
12771+}
12772+
12773+/**
12774+ * Handles a host channel frame overrun interrupt. This handler may be called
12775+ * in either DMA mode or Slave mode.
12776+ */
12777+static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t *hcd,
12778+ dwc_hc_t *hc,
12779+ dwc_otg_hc_regs_t *hc_regs,
12780+ dwc_otg_qtd_t *qtd)
12781+{
12782+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12783+ "Frame Overrun--\n", hc->hc_num);
12784+
12785+ switch (usb_pipetype(qtd->urb->pipe)) {
12786+ case PIPE_CONTROL:
12787+ case PIPE_BULK:
12788+ break;
12789+ case PIPE_INTERRUPT:
12790+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN);
12791+ break;
12792+ case PIPE_ISOCHRONOUS:
12793+ {
12794+ dwc_otg_halt_status_e halt_status;
12795+ halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
12796+ DWC_OTG_HC_XFER_FRAME_OVERRUN);
12797+
12798+ halt_channel(hcd, hc, qtd, halt_status);
12799+ }
12800+ break;
12801+ }
12802+
12803+ disable_hc_int(hc_regs, frmovrun);
12804+
12805+ return 1;
12806+}
12807+
12808+/**
12809+ * Handles a host channel data toggle error interrupt. This handler may be
12810+ * called in either DMA mode or Slave mode.
12811+ */
12812+static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t *hcd,
12813+ dwc_hc_t *hc,
12814+ dwc_otg_hc_regs_t *hc_regs,
12815+ dwc_otg_qtd_t *qtd)
12816+{
12817+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12818+ "Data Toggle Error--\n", hc->hc_num);
12819+
12820+ if (hc->ep_is_in) {
12821+ qtd->error_count = 0;
12822+ } else {
12823+ DWC_ERROR("Data Toggle Error on OUT transfer,"
12824+ "channel %d\n", hc->hc_num);
12825+ }
12826+
12827+ disable_hc_int(hc_regs, datatglerr);
12828+
12829+ return 1;
12830+}
12831+
12832+#ifdef DEBUG
12833+/**
12834+ * This function is for debug only. It checks that a valid halt status is set
12835+ * and that HCCHARn.chdis is clear. If there's a problem, corrective action is
12836+ * taken and a warning is issued.
12837+ * @return 1 if halt status is ok, 0 otherwise.
12838+ */
12839+static inline int halt_status_ok(dwc_otg_hcd_t *hcd,
12840+ dwc_hc_t *hc,
12841+ dwc_otg_hc_regs_t *hc_regs,
12842+ dwc_otg_qtd_t *qtd)
12843+{
12844+ hcchar_data_t hcchar;
12845+ hctsiz_data_t hctsiz;
12846+ hcint_data_t hcint;
12847+ hcintmsk_data_t hcintmsk;
12848+ hcsplt_data_t hcsplt;
12849+
12850+ if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
12851+ /*
12852+ * This code is here only as a check. This condition should
12853+ * never happen. Ignore the halt if it does occur.
12854+ */
12855+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
12856+ hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
12857+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
12858+ hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
12859+ hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
12860+ DWC_WARN("%s: hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, "
12861+ "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
12862+ "hcint 0x%08x, hcintmsk 0x%08x, "
12863+ "hcsplt 0x%08x, qtd->complete_split %d\n",
12864+ __func__, hc->hc_num, hcchar.d32, hctsiz.d32,
12865+ hcint.d32, hcintmsk.d32,
12866+ hcsplt.d32, qtd->complete_split);
12867+
12868+ DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
12869+ __func__, hc->hc_num);
12870+ DWC_WARN("\n");
12871+ clear_hc_int(hc_regs, chhltd);
12872+ return 0;
12873+ }
12874+
12875+ /*
12876+ * This code is here only as a check. hcchar.chdis should
12877+ * never be set when the halt interrupt occurs. Halt the
12878+ * channel again if it does occur.
12879+ */
12880+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
12881+ if (hcchar.b.chdis) {
12882+ DWC_WARN("%s: hcchar.chdis set unexpectedly, "
12883+ "hcchar 0x%08x, trying to halt again\n",
12884+ __func__, hcchar.d32);
12885+ clear_hc_int(hc_regs, chhltd);
12886+ hc->halt_pending = 0;
12887+ halt_channel(hcd, hc, qtd, hc->halt_status);
12888+ return 0;
12889+ }
12890+
12891+ return 1;
12892+}
12893+#endif
12894+
12895+/**
12896+ * Handles a host Channel Halted interrupt in DMA mode. This handler
12897+ * determines the reason the channel halted and proceeds accordingly.
12898+ */
12899+static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t *hcd,
12900+ dwc_hc_t *hc,
12901+ dwc_otg_hc_regs_t *hc_regs,
12902+ dwc_otg_qtd_t *qtd)
12903+{
12904+ hcint_data_t hcint;
12905+ hcintmsk_data_t hcintmsk;
12906+ int out_nak_enh = 0;
12907+
12908+ /* For core with OUT NAK enhancement, the flow for high-
12909+ * speed CONTROL/BULK OUT is handled a little differently.
12910+ */
12911+ if (hcd->core_if->snpsid >= 0x4F54271A) {
12912+ if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
12913+ (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
12914+ hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
12915+ DWC_DEBUGPL(DBG_HCD, "OUT NAK enhancement enabled\n");
12916+ out_nak_enh = 1;
12917+ } else {
12918+ DWC_DEBUGPL(DBG_HCD, "OUT NAK enhancement disabled, not HS Ctrl/Bulk OUT EP\n");
12919+ }
12920+ } else {
12921+ DWC_DEBUGPL(DBG_HCD, "OUT NAK enhancement disabled, no core support\n");
12922+ }
12923+
12924+ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
12925+ hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
12926+ /*
12927+ * Just release the channel. A dequeue can happen on a
12928+ * transfer timeout. In the case of an AHB Error, the channel
12929+ * was forced to halt because there's no way to gracefully
12930+ * recover.
12931+ */
12932+ release_channel(hcd, hc, qtd, hc->halt_status);
12933+ return;
12934+ }
12935+
12936+ /* Read the HCINTn register to determine the cause for the halt. */
12937+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
12938+ hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
12939+
12940+ if (hcint.b.xfercomp) {
12941+ /** @todo This is here because of a possible hardware bug. Spec
12942+ * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
12943+ * interrupt w/ACK bit set should occur, but I only see the
12944+ * XFERCOMP bit, even with it masked out. This is a workaround
12945+ * for that behavior. Should fix this when hardware is fixed.
12946+ */
12947+ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
12948+ handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
12949+ }
12950+ handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
12951+ } else if (hcint.b.stall) {
12952+ handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
12953+ } else if (hcint.b.xacterr) {
12954+ if (out_nak_enh) {
12955+ if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
12956+ printk(KERN_DEBUG "XactErr with NYET/NAK/ACK\n");
12957+ qtd->error_count = 0;
12958+ } else {
12959+ printk(KERN_DEBUG "XactErr without NYET/NAK/ACK\n");
12960+ }
12961+ }
12962+
12963+ /*
12964+ * Must handle xacterr before nak or ack. Could get a xacterr
12965+ * at the same time as either of these on a BULK/CONTROL OUT
12966+ * that started with a PING. The xacterr takes precedence.
12967+ */
12968+ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
12969+ } else if (!out_nak_enh) {
12970+ if (hcint.b.nyet) {
12971+ /*
12972+ * Must handle nyet before nak or ack. Could get a nyet at the
12973+ * same time as either of those on a BULK/CONTROL OUT that
12974+ * started with a PING. The nyet takes precedence.
12975+ */
12976+ handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
12977+ } else if (hcint.b.bblerr) {
12978+ handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
12979+ } else if (hcint.b.frmovrun) {
12980+ handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
12981+ } else if (hcint.b.nak && !hcintmsk.b.nak) {
12982+ /*
12983+ * If nak is not masked, it's because a non-split IN transfer
12984+ * is in an error state. In that case, the nak is handled by
12985+ * the nak interrupt handler, not here. Handle nak here for
12986+ * BULK/CONTROL OUT transfers, which halt on a NAK to allow
12987+ * rewinding the buffer pointer.
12988+ */
12989+ handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
12990+ } else if (hcint.b.ack && !hcintmsk.b.ack) {
12991+ /*
12992+ * If ack is not masked, it's because a non-split IN transfer
12993+ * is in an error state. In that case, the ack is handled by
12994+ * the ack interrupt handler, not here. Handle ack here for
12995+ * split transfers. Start splits halt on ACK.
12996+ */
12997+ handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
12998+ } else {
12999+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
13000+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
13001+ /*
13002+ * A periodic transfer halted with no other channel
13003+ * interrupts set. Assume it was halted by the core
13004+ * because it could not be completed in its scheduled
13005+ * (micro)frame.
13006+ */
13007+#ifdef DEBUG
13008+ DWC_PRINT("%s: Halt channel %d (assume incomplete periodic transfer)\n",
13009+ __func__, hc->hc_num);
13010+#endif
13011+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
13012+ } else {
13013+ DWC_ERROR("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
13014+ "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
13015+ __func__, hc->hc_num, hcint.d32,
13016+ dwc_read_reg32(&hcd->core_if->core_global_regs->gintsts));
13017+ }
13018+ }
13019+ } else {
13020+ printk(KERN_DEBUG "NYET/NAK/ACK/other in non-error case, 0x%08x\n", hcint.d32);
13021+ }
13022+}
13023+
13024+/**
13025+ * Handles a host channel Channel Halted interrupt.
13026+ *
13027+ * In slave mode, this handler is called only when the driver specifically
13028+ * requests a halt. This occurs during handling other host channel interrupts
13029+ * (e.g. nak, xacterr, stall, nyet, etc.).
13030+ *
13031+ * In DMA mode, this is the interrupt that occurs when the core has finished
13032+ * processing a transfer on a channel. Other host channel interrupts (except
13033+ * ahberr) are disabled in DMA mode.
13034+ */
13035+static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t *hcd,
13036+ dwc_hc_t *hc,
13037+ dwc_otg_hc_regs_t *hc_regs,
13038+ dwc_otg_qtd_t *qtd)
13039+{
13040+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
13041+ "Channel Halted--\n", hc->hc_num);
13042+
13043+ if (hcd->core_if->dma_enable) {
13044+ handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd);
13045+ } else {
13046+#ifdef DEBUG
13047+ if (!halt_status_ok(hcd, hc, hc_regs, qtd)) {
13048+ return 1;
13049+ }
13050+#endif
13051+ release_channel(hcd, hc, qtd, hc->halt_status);
13052+ }
13053+
13054+ return 1;
13055+}
13056+
13057+/** Handles interrupt for a specific Host Channel */
13058+int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num)
13059+{
13060+ int retval = 0;
13061+ hcint_data_t hcint;
13062+ hcintmsk_data_t hcintmsk;
13063+ dwc_hc_t *hc;
13064+ dwc_otg_hc_regs_t *hc_regs;
13065+ dwc_otg_qtd_t *qtd;
13066+
13067+ DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num);
13068+
13069+ hc = dwc_otg_hcd->hc_ptr_array[num];
13070+ hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num];
13071+ qtd = list_entry(hc->qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
13072+
13073+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
13074+ hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
13075+ DWC_DEBUGPL(DBG_HCDV, " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
13076+ hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32));
13077+ hcint.d32 = hcint.d32 & hcintmsk.d32;
13078+
13079+ if (!dwc_otg_hcd->core_if->dma_enable) {
13080+ if (hcint.b.chhltd && hcint.d32 != 0x2) {
13081+ hcint.b.chhltd = 0;
13082+ }
13083+ }
13084+
13085+ if (hcint.b.xfercomp) {
13086+ retval |= handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd);
13087+ /*
13088+ * If NYET occurred at same time as Xfer Complete, the NYET is
13089+ * handled by the Xfer Complete interrupt handler. Don't want
13090+ * to call the NYET interrupt handler in this case.
13091+ */
13092+ hcint.b.nyet = 0;
13093+ }
13094+ if (hcint.b.chhltd) {
13095+ retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd);
13096+ }
13097+ if (hcint.b.ahberr) {
13098+ retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
13099+ }
13100+ if (hcint.b.stall) {
13101+ retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd);
13102+ }
13103+ if (hcint.b.nak) {
13104+ retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd);
13105+ }
13106+ if (hcint.b.ack) {
13107+ retval |= handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd);
13108+ }
13109+ if (hcint.b.nyet) {
13110+ retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd);
13111+ }
13112+ if (hcint.b.xacterr) {
13113+ retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
13114+ }
13115+ if (hcint.b.bblerr) {
13116+ retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd);
13117+ }
13118+ if (hcint.b.frmovrun) {
13119+ retval |= handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd);
13120+ }
13121+ if (hcint.b.datatglerr) {
13122+ retval |= handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
13123+ }
13124+
13125+ return retval;
13126+}
13127+
13128+#endif /* DWC_DEVICE_ONLY */
13129--- /dev/null
13130+++ b/drivers/usb/dwc/otg_hcd_queue.c
13131@@ -0,0 +1,794 @@
13132+/* ==========================================================================
13133+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_queue.c $
13134+ * $Revision: #33 $
13135+ * $Date: 2008/07/15 $
13136+ * $Change: 1064918 $
13137+ *
13138+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
13139+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
13140+ * otherwise expressly agreed to in writing between Synopsys and you.
13141+ *
13142+ * The Software IS NOT an item of Licensed Software or Licensed Product under
13143+ * any End User Software License Agreement or Agreement for Licensed Product
13144+ * with Synopsys or any supplement thereto. You are permitted to use and
13145+ * redistribute this Software in source and binary forms, with or without
13146+ * modification, provided that redistributions of source code must retain this
13147+ * notice. You may not view, use, disclose, copy or distribute this file or
13148+ * any information contained herein except pursuant to this license grant from
13149+ * Synopsys. If you do not agree with this notice, including the disclaimer
13150+ * below, then you are not authorized to use the Software.
13151+ *
13152+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
13153+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
13154+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
13155+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
13156+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
13157+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
13158+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
13159+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
13160+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
13161+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
13162+ * DAMAGE.
13163+ * ========================================================================== */
13164+#ifndef DWC_DEVICE_ONLY
13165+
13166+/**
13167+ * @file
13168+ *
13169+ * This file contains the functions to manage Queue Heads and Queue
13170+ * Transfer Descriptors.
13171+ */
13172+#include <linux/kernel.h>
13173+#include <linux/module.h>
13174+#include <linux/moduleparam.h>
13175+#include <linux/init.h>
13176+#include <linux/device.h>
13177+#include <linux/errno.h>
13178+#include <linux/list.h>
13179+#include <linux/interrupt.h>
13180+#include <linux/string.h>
13181+#include <linux/version.h>
13182+
13183+#include <mach/irqs.h>
13184+
13185+#include "otg_driver.h"
13186+#include "otg_hcd.h"
13187+#include "otg_regs.h"
13188+
13189+/**
13190+ * This function allocates and initializes a QH.
13191+ *
13192+ * @param hcd The HCD state structure for the DWC OTG controller.
13193+ * @param[in] urb Holds the information about the device/endpoint that we need
13194+ * to initialize the QH.
13195+ *
13196+ * @return Returns pointer to the newly allocated QH, or NULL on error. */
13197+dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *hcd, struct urb *urb)
13198+{
13199+ dwc_otg_qh_t *qh;
13200+
13201+ /* Allocate memory */
13202+ /** @todo add memflags argument */
13203+ qh = dwc_otg_hcd_qh_alloc ();
13204+ if (qh == NULL) {
13205+ return NULL;
13206+ }
13207+
13208+ dwc_otg_hcd_qh_init (hcd, qh, urb);
13209+ return qh;
13210+}
13211+
13212+/** Free each QTD in the QH's QTD-list then free the QH. QH should already be
13213+ * removed from a list. QTD list should already be empty if called from URB
13214+ * Dequeue.
13215+ *
13216+ * @param[in] hcd HCD instance.
13217+ * @param[in] qh The QH to free.
13218+ */
13219+void dwc_otg_hcd_qh_free (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
13220+{
13221+ dwc_otg_qtd_t *qtd;
13222+ struct list_head *pos;
13223+ //unsigned long flags;
13224+
13225+ /* Free each QTD in the QTD list */
13226+
13227+#ifdef CONFIG_SMP
13228+ //the spinlock is locked before this function get called,
13229+ //but in case the lock is needed, the check function is preserved
13230+
13231+ //but in non-SMP mode, all spinlock is lockable.
13232+ //don't do the test in non-SMP mode
13233+
13234+ if(spin_trylock(&hcd->lock)) {
13235+ printk("%s: It is not supposed to be lockable!!\n",__func__);
13236+ BUG();
13237+ }
13238+#endif
13239+// SPIN_LOCK_IRQSAVE(&hcd->lock, flags)
13240+ for (pos = qh->qtd_list.next;
13241+ pos != &qh->qtd_list;
13242+ pos = qh->qtd_list.next)
13243+ {
13244+ list_del (pos);
13245+ qtd = dwc_list_to_qtd (pos);
13246+ dwc_otg_hcd_qtd_free (qtd);
13247+ }
13248+// SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags)
13249+
13250+ kfree (qh);
13251+ return;
13252+}
13253+
13254+/** Initializes a QH structure.
13255+ *
13256+ * @param[in] hcd The HCD state structure for the DWC OTG controller.
13257+ * @param[in] qh The QH to init.
13258+ * @param[in] urb Holds the information about the device/endpoint that we need
13259+ * to initialize the QH. */
13260+#define SCHEDULE_SLOP 10
13261+void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, struct urb *urb)
13262+{
13263+ char *speed, *type;
13264+ memset (qh, 0, sizeof (dwc_otg_qh_t));
13265+
13266+ /* Initialize QH */
13267+ switch (usb_pipetype(urb->pipe)) {
13268+ case PIPE_CONTROL:
13269+ qh->ep_type = USB_ENDPOINT_XFER_CONTROL;
13270+ break;
13271+ case PIPE_BULK:
13272+ qh->ep_type = USB_ENDPOINT_XFER_BULK;
13273+ break;
13274+ case PIPE_ISOCHRONOUS:
13275+ qh->ep_type = USB_ENDPOINT_XFER_ISOC;
13276+ break;
13277+ case PIPE_INTERRUPT:
13278+ qh->ep_type = USB_ENDPOINT_XFER_INT;
13279+ break;
13280+ }
13281+
13282+ qh->ep_is_in = usb_pipein(urb->pipe) ? 1 : 0;
13283+
13284+ qh->data_toggle = DWC_OTG_HC_PID_DATA0;
13285+ qh->maxp = usb_maxpacket(urb->dev, urb->pipe, !(usb_pipein(urb->pipe)));
13286+ INIT_LIST_HEAD(&qh->qtd_list);
13287+ INIT_LIST_HEAD(&qh->qh_list_entry);
13288+ qh->channel = NULL;
13289+ qh->speed = urb->dev->speed;
13290+
13291+ /* FS/LS Enpoint on HS Hub
13292+ * NOT virtual root hub */
13293+ qh->do_split = 0;
13294+ if (((urb->dev->speed == USB_SPEED_LOW) ||
13295+ (urb->dev->speed == USB_SPEED_FULL)) &&
13296+ (urb->dev->tt) && (urb->dev->tt->hub) && (urb->dev->tt->hub->devnum != 1))
13297+ {
13298+ DWC_DEBUGPL(DBG_HCD, "QH init: EP %d: TT found at hub addr %d, for port %d\n",
13299+ usb_pipeendpoint(urb->pipe), urb->dev->tt->hub->devnum,
13300+ urb->dev->ttport);
13301+ qh->do_split = 1;
13302+ }
13303+
13304+ if (qh->ep_type == USB_ENDPOINT_XFER_INT ||
13305+ qh->ep_type == USB_ENDPOINT_XFER_ISOC) {
13306+ /* Compute scheduling parameters once and save them. */
13307+ hprt0_data_t hprt;
13308+
13309+ /** @todo Account for split transfers in the bus time. */
13310+ int bytecount = dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp);
13311+ qh->usecs = NS_TO_US(usb_calc_bus_time(urb->dev->speed,
13312+ usb_pipein(urb->pipe),
13313+ (qh->ep_type == USB_ENDPOINT_XFER_ISOC),
13314+ bytecount));
13315+
13316+ /* Start in a slightly future (micro)frame. */
13317+ qh->sched_frame = dwc_frame_num_inc(hcd->frame_number,
13318+ SCHEDULE_SLOP);
13319+ qh->interval = urb->interval;
13320+#if 0
13321+ /* Increase interrupt polling rate for debugging. */
13322+ if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
13323+ qh->interval = 8;
13324+ }
13325+#endif
13326+ hprt.d32 = dwc_read_reg32(hcd->core_if->host_if->hprt0);
13327+ if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
13328+ ((urb->dev->speed == USB_SPEED_LOW) ||
13329+ (urb->dev->speed == USB_SPEED_FULL))) {
13330+ qh->interval *= 8;
13331+ qh->sched_frame |= 0x7;
13332+ qh->start_split_frame = qh->sched_frame;
13333+ }
13334+
13335+ }
13336+
13337+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
13338+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", qh);
13339+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n",
13340+ urb->dev->devnum);
13341+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n",
13342+ usb_pipeendpoint(urb->pipe),
13343+ usb_pipein(urb->pipe) == USB_DIR_IN ? "IN" : "OUT");
13344+
13345+ switch(urb->dev->speed) {
13346+ case USB_SPEED_LOW:
13347+ speed = "low";
13348+ break;
13349+ case USB_SPEED_FULL:
13350+ speed = "full";
13351+ break;
13352+ case USB_SPEED_HIGH:
13353+ speed = "high";
13354+ break;
13355+ default:
13356+ speed = "?";
13357+ break;
13358+ }
13359+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n", speed);
13360+
13361+ switch (qh->ep_type) {
13362+ case USB_ENDPOINT_XFER_ISOC:
13363+ type = "isochronous";
13364+ break;
13365+ case USB_ENDPOINT_XFER_INT:
13366+ type = "interrupt";
13367+ break;
13368+ case USB_ENDPOINT_XFER_CONTROL:
13369+ type = "control";
13370+ break;
13371+ case USB_ENDPOINT_XFER_BULK:
13372+ type = "bulk";
13373+ break;
13374+ default:
13375+ type = "?";
13376+ break;
13377+ }
13378+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n",type);
13379+
13380+#ifdef DEBUG
13381+ if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
13382+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
13383+ qh->usecs);
13384+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
13385+ qh->interval);
13386+ }
13387+#endif
13388+
13389+ return;
13390+}
13391+
13392+/**
13393+ * Microframe scheduler
13394+ * track the total use in hcd->frame_usecs
13395+ * keep each qh use in qh->frame_usecs
13396+ * when surrendering the qh then donate the time back
13397+ */
13398+static const u16 max_uframe_usecs[] = { 100, 100, 100, 100, 100, 100, 30, 0 };
13399+
13400+/*
13401+ * called from dwc_otg_hcd.c:dwc_otg_hcd_init
13402+ */
13403+int init_hcd_usecs(dwc_otg_hcd_t *hcd)
13404+{
13405+ int i;
13406+
13407+ for (i = 0; i < 8; i++)
13408+ hcd->frame_usecs[i] = max_uframe_usecs[i];
13409+
13410+ return 0;
13411+}
13412+
13413+static int find_single_uframe(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
13414+{
13415+ int i;
13416+ u16 utime;
13417+ int t_left;
13418+ int ret;
13419+ int done;
13420+
13421+ ret = -1;
13422+ utime = qh->usecs;
13423+ t_left = utime;
13424+ i = 0;
13425+ done = 0;
13426+ while (done == 0) {
13427+ /* At the start hcd->frame_usecs[i] = max_uframe_usecs[i]; */
13428+ if (utime <= hcd->frame_usecs[i]) {
13429+ hcd->frame_usecs[i] -= utime;
13430+ qh->frame_usecs[i] += utime;
13431+ t_left -= utime;
13432+ ret = i;
13433+ done = 1;
13434+ return ret;
13435+ } else {
13436+ i++;
13437+ if (i == 8) {
13438+ done = 1;
13439+ ret = -1;
13440+ }
13441+ }
13442+ }
13443+ return ret;
13444+}
13445+
13446+/*
13447+ * use this for FS apps that can span multiple uframes
13448+ */
13449+static int find_multi_uframe(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
13450+{
13451+ int i;
13452+ int j;
13453+ u16 utime;
13454+ int t_left;
13455+ int ret;
13456+ int done;
13457+ u16 xtime;
13458+
13459+ ret = -1;
13460+ utime = qh->usecs;
13461+ t_left = utime;
13462+ i = 0;
13463+ done = 0;
13464+loop:
13465+ while (done == 0) {
13466+ if (hcd->frame_usecs[i] <= 0) {
13467+ i++;
13468+ if (i == 8) {
13469+ done = 1;
13470+ ret = -1;
13471+ }
13472+ goto loop;
13473+ }
13474+
13475+ /*
13476+ * We need n consequtive slots so use j as a start slot.
13477+ * j plus j+1 must be enough time (for now)
13478+ */
13479+ xtime = hcd->frame_usecs[i];
13480+ for (j = i + 1; j < 8; j++) {
13481+ /*
13482+ * if we add this frame remaining time to xtime we may
13483+ * be OK, if not we need to test j for a complete frame.
13484+ */
13485+ if ((xtime + hcd->frame_usecs[j]) < utime) {
13486+ if (hcd->frame_usecs[j] < max_uframe_usecs[j]) {
13487+ j = 8;
13488+ ret = -1;
13489+ continue;
13490+ }
13491+ }
13492+ if (xtime >= utime) {
13493+ ret = i;
13494+ j = 8; /* stop loop with a good value ret */
13495+ continue;
13496+ }
13497+ /* add the frame time to x time */
13498+ xtime += hcd->frame_usecs[j];
13499+ /* we must have a fully available next frame or break */
13500+ if ((xtime < utime) &&
13501+ (hcd->frame_usecs[j] == max_uframe_usecs[j])) {
13502+ ret = -1;
13503+ j = 8; /* stop loop with a bad value ret */
13504+ continue;
13505+ }
13506+ }
13507+ if (ret >= 0) {
13508+ t_left = utime;
13509+ for (j = i; (t_left > 0) && (j < 8); j++) {
13510+ t_left -= hcd->frame_usecs[j];
13511+ if (t_left <= 0) {
13512+ qh->frame_usecs[j] +=
13513+ hcd->frame_usecs[j] + t_left;
13514+ hcd->frame_usecs[j] = -t_left;
13515+ ret = i;
13516+ done = 1;
13517+ } else {
13518+ qh->frame_usecs[j] +=
13519+ hcd->frame_usecs[j];
13520+ hcd->frame_usecs[j] = 0;
13521+ }
13522+ }
13523+ } else {
13524+ i++;
13525+ if (i == 8) {
13526+ done = 1;
13527+ ret = -1;
13528+ }
13529+ }
13530+ }
13531+ return ret;
13532+}
13533+
13534+static int find_uframe(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
13535+{
13536+ int ret = -1;
13537+
13538+ if (qh->speed == USB_SPEED_HIGH)
13539+ /* if this is a hs transaction we need a full frame */
13540+ ret = find_single_uframe(hcd, qh);
13541+ else
13542+ /* FS transaction may need a sequence of frames */
13543+ ret = find_multi_uframe(hcd, qh);
13544+
13545+ return ret;
13546+}
13547+
13548+/**
13549+ * Checks that the max transfer size allowed in a host channel is large enough
13550+ * to handle the maximum data transfer in a single (micro)frame for a periodic
13551+ * transfer.
13552+ *
13553+ * @param hcd The HCD state structure for the DWC OTG controller.
13554+ * @param qh QH for a periodic endpoint.
13555+ *
13556+ * @return 0 if successful, negative error code otherwise.
13557+ */
13558+static int check_max_xfer_size(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
13559+{
13560+ int status;
13561+ uint32_t max_xfer_size;
13562+ uint32_t max_channel_xfer_size;
13563+
13564+ status = 0;
13565+
13566+ max_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp);
13567+ max_channel_xfer_size = hcd->core_if->core_params->max_transfer_size;
13568+
13569+ if (max_xfer_size > max_channel_xfer_size) {
13570+ DWC_NOTICE("%s: Periodic xfer length %d > "
13571+ "max xfer length for channel %d\n",
13572+ __func__, max_xfer_size, max_channel_xfer_size);
13573+ status = -ENOSPC;
13574+ }
13575+
13576+ return status;
13577+}
13578+
13579+/**
13580+ * Schedules an interrupt or isochronous transfer in the periodic schedule.
13581+ */
13582+static int schedule_periodic(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
13583+{
13584+ int status;
13585+ struct usb_bus *bus = hcd_to_bus(dwc_otg_hcd_to_hcd(hcd));
13586+ int frame;
13587+
13588+ status = find_uframe(hcd, qh);
13589+ frame = -1;
13590+ if (status == 0) {
13591+ frame = 7;
13592+ } else {
13593+ if (status > 0)
13594+ frame = status - 1;
13595+ }
13596+ /* Set the new frame up */
13597+ if (frame > -1) {
13598+ qh->sched_frame &= ~0x7;
13599+ qh->sched_frame |= (frame & 7);
13600+ }
13601+ if (status != -1)
13602+ status = 0;
13603+ if (status) {
13604+ pr_notice("%s: Insufficient periodic bandwidth for "
13605+ "periodic transfer.\n", __func__);
13606+ return status;
13607+ }
13608+ status = check_max_xfer_size(hcd, qh);
13609+ if (status) {
13610+ pr_notice("%s: Channel max transfer size too small "
13611+ "for periodic transfer.\n", __func__);
13612+ return status;
13613+ }
13614+ /* Always start in the inactive schedule. */
13615+ list_add_tail(&qh->qh_list_entry, &hcd->periodic_sched_inactive);
13616+
13617+ /* Update claimed usecs per (micro)frame. */
13618+ hcd->periodic_usecs += qh->usecs;
13619+
13620+ /*
13621+ * Update average periodic bandwidth claimed and # periodic reqs for
13622+ * usbfs.
13623+ */
13624+ bus->bandwidth_allocated += qh->usecs / qh->interval;
13625+
13626+ if (qh->ep_type == USB_ENDPOINT_XFER_INT)
13627+ bus->bandwidth_int_reqs++;
13628+ else
13629+ bus->bandwidth_isoc_reqs++;
13630+
13631+ return status;
13632+}
13633+
13634+/**
13635+ * This function adds a QH to either the non periodic or periodic schedule if
13636+ * it is not already in the schedule. If the QH is already in the schedule, no
13637+ * action is taken.
13638+ *
13639+ * @return 0 if successful, negative error code otherwise.
13640+ */
13641+int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
13642+{
13643+ //unsigned long flags;
13644+ int status = 0;
13645+
13646+#ifdef CONFIG_SMP
13647+ //the spinlock is locked before this function get called,
13648+ //but in case the lock is needed, the check function is preserved
13649+ //but in non-SMP mode, all spinlock is lockable.
13650+ //don't do the test in non-SMP mode
13651+
13652+ if(spin_trylock(&hcd->lock)) {
13653+ printk("%s: It is not supposed to be lockable!!\n",__func__);
13654+ BUG();
13655+ }
13656+#endif
13657+// SPIN_LOCK_IRQSAVE(&hcd->lock, flags)
13658+
13659+ if (!list_empty(&qh->qh_list_entry)) {
13660+ /* QH already in a schedule. */
13661+ goto done;
13662+ }
13663+
13664+ /* Add the new QH to the appropriate schedule */
13665+ if (dwc_qh_is_non_per(qh)) {
13666+ /* Always start in the inactive schedule. */
13667+ list_add_tail(&qh->qh_list_entry, &hcd->non_periodic_sched_inactive);
13668+ } else {
13669+ status = schedule_periodic(hcd, qh);
13670+ }
13671+
13672+ done:
13673+// SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags)
13674+
13675+ return status;
13676+}
13677+
13678+/**
13679+ * Removes an interrupt or isochronous transfer from the periodic schedule.
13680+ */
13681+static void deschedule_periodic(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
13682+{
13683+ struct usb_bus *bus = hcd_to_bus(dwc_otg_hcd_to_hcd(hcd));
13684+ int i;
13685+
13686+ list_del_init(&qh->qh_list_entry);
13687+ /* Update claimed usecs per (micro)frame. */
13688+ hcd->periodic_usecs -= qh->usecs;
13689+ for (i = 0; i < 8; i++) {
13690+ hcd->frame_usecs[i] += qh->frame_usecs[i];
13691+ qh->frame_usecs[i] = 0;
13692+ }
13693+ /*
13694+ * Update average periodic bandwidth claimed and # periodic reqs for
13695+ * usbfs.
13696+ */
13697+ bus->bandwidth_allocated -= qh->usecs / qh->interval;
13698+
13699+ if (qh->ep_type == USB_ENDPOINT_XFER_INT)
13700+ bus->bandwidth_int_reqs--;
13701+ else
13702+ bus->bandwidth_isoc_reqs--;
13703+}
13704+
13705+/**
13706+ * Removes a QH from either the non-periodic or periodic schedule. Memory is
13707+ * not freed.
13708+ *
13709+ * @param[in] hcd The HCD state structure.
13710+ * @param[in] qh QH to remove from schedule. */
13711+void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
13712+{
13713+ //unsigned long flags;
13714+
13715+#ifdef CONFIG_SMP
13716+ //the spinlock is locked before this function get called,
13717+ //but in case the lock is needed, the check function is preserved
13718+ //but in non-SMP mode, all spinlock is lockable.
13719+ //don't do the test in non-SMP mode
13720+
13721+ if(spin_trylock(&hcd->lock)) {
13722+ printk("%s: It is not supposed to be lockable!!\n",__func__);
13723+ BUG();
13724+ }
13725+#endif
13726+// SPIN_LOCK_IRQSAVE(&hcd->lock, flags);
13727+
13728+ if (list_empty(&qh->qh_list_entry)) {
13729+ /* QH is not in a schedule. */
13730+ goto done;
13731+ }
13732+
13733+ if (dwc_qh_is_non_per(qh)) {
13734+ if (hcd->non_periodic_qh_ptr == &qh->qh_list_entry) {
13735+ hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
13736+ }
13737+ list_del_init(&qh->qh_list_entry);
13738+ } else {
13739+ deschedule_periodic(hcd, qh);
13740+ }
13741+
13742+ done:
13743+// SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags);
13744+ return;
13745+}
13746+
13747+/**
13748+ * Deactivates a QH. For non-periodic QHs, removes the QH from the active
13749+ * non-periodic schedule. The QH is added to the inactive non-periodic
13750+ * schedule if any QTDs are still attached to the QH.
13751+ *
13752+ * For periodic QHs, the QH is removed from the periodic queued schedule. If
13753+ * there are any QTDs still attached to the QH, the QH is added to either the
13754+ * periodic inactive schedule or the periodic ready schedule and its next
13755+ * scheduled frame is calculated. The QH is placed in the ready schedule if
13756+ * the scheduled frame has been reached already. Otherwise it's placed in the
13757+ * inactive schedule. If there are no QTDs attached to the QH, the QH is
13758+ * completely removed from the periodic schedule.
13759+ */
13760+void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_next_periodic_split)
13761+{
13762+ unsigned long flags;
13763+ SPIN_LOCK_IRQSAVE(&hcd->lock, flags);
13764+
13765+ if (dwc_qh_is_non_per(qh)) {
13766+ dwc_otg_hcd_qh_remove(hcd, qh);
13767+ if (!list_empty(&qh->qtd_list)) {
13768+ /* Add back to inactive non-periodic schedule. */
13769+ dwc_otg_hcd_qh_add(hcd, qh);
13770+ }
13771+ } else {
13772+ uint16_t frame_number = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(hcd));
13773+
13774+ if (qh->do_split) {
13775+ /* Schedule the next continuing periodic split transfer */
13776+ if (sched_next_periodic_split) {
13777+
13778+ qh->sched_frame = frame_number;
13779+ if (dwc_frame_num_le(frame_number,
13780+ dwc_frame_num_inc(qh->start_split_frame, 1))) {
13781+ /*
13782+ * Allow one frame to elapse after start
13783+ * split microframe before scheduling
13784+ * complete split, but DONT if we are
13785+ * doing the next start split in the
13786+ * same frame for an ISOC out.
13787+ */
13788+ if ((qh->ep_type != USB_ENDPOINT_XFER_ISOC) || (qh->ep_is_in != 0)) {
13789+ qh->sched_frame = dwc_frame_num_inc(qh->sched_frame, 1);
13790+ }
13791+ }
13792+ } else {
13793+ qh->sched_frame = dwc_frame_num_inc(qh->start_split_frame,
13794+ qh->interval);
13795+ if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
13796+ qh->sched_frame = frame_number;
13797+ }
13798+ qh->sched_frame |= 0x7;
13799+ qh->start_split_frame = qh->sched_frame;
13800+ }
13801+ } else {
13802+ qh->sched_frame = dwc_frame_num_inc(qh->sched_frame, qh->interval);
13803+ if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
13804+ qh->sched_frame = frame_number;
13805+ }
13806+ }
13807+
13808+ if (list_empty(&qh->qtd_list)) {
13809+ dwc_otg_hcd_qh_remove(hcd, qh);
13810+ } else {
13811+ /*
13812+ * Remove from periodic_sched_queued and move to
13813+ * appropriate queue.
13814+ */
13815+ if (qh->sched_frame == frame_number) {
13816+ list_move(&qh->qh_list_entry,
13817+ &hcd->periodic_sched_ready);
13818+ } else {
13819+ list_move(&qh->qh_list_entry,
13820+ &hcd->periodic_sched_inactive);
13821+ }
13822+ }
13823+ }
13824+
13825+ SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags);
13826+}
13827+
13828+/**
13829+ * This function allocates and initializes a QTD.
13830+ *
13831+ * @param[in] urb The URB to create a QTD from. Each URB-QTD pair will end up
13832+ * pointing to each other so each pair should have a unique correlation.
13833+ *
13834+ * @return Returns pointer to the newly allocated QTD, or NULL on error. */
13835+dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *urb)
13836+{
13837+ dwc_otg_qtd_t *qtd;
13838+
13839+ qtd = dwc_otg_hcd_qtd_alloc ();
13840+ if (qtd == NULL) {
13841+ return NULL;
13842+ }
13843+
13844+ dwc_otg_hcd_qtd_init (qtd, urb);
13845+ return qtd;
13846+}
13847+
13848+/**
13849+ * Initializes a QTD structure.
13850+ *
13851+ * @param[in] qtd The QTD to initialize.
13852+ * @param[in] urb The URB to use for initialization. */
13853+void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *qtd, struct urb *urb)
13854+{
13855+ memset (qtd, 0, sizeof (dwc_otg_qtd_t));
13856+ qtd->urb = urb;
13857+ if (usb_pipecontrol(urb->pipe)) {
13858+ /*
13859+ * The only time the QTD data toggle is used is on the data
13860+ * phase of control transfers. This phase always starts with
13861+ * DATA1.
13862+ */
13863+ qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
13864+ qtd->control_phase = DWC_OTG_CONTROL_SETUP;
13865+ }
13866+
13867+ /* start split */
13868+ qtd->complete_split = 0;
13869+ qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
13870+ qtd->isoc_split_offset = 0;
13871+
13872+ /* Store the qtd ptr in the urb to reference what QTD. */
13873+ urb->hcpriv = qtd;
13874+ return;
13875+}
13876+
13877+/**
13878+ * This function adds a QTD to the QTD-list of a QH. It will find the correct
13879+ * QH to place the QTD into. If it does not find a QH, then it will create a
13880+ * new QH. If the QH to which the QTD is added is not currently scheduled, it
13881+ * is placed into the proper schedule based on its EP type.
13882+ *
13883+ * @param[in] qtd The QTD to add
13884+ * @param[in] dwc_otg_hcd The DWC HCD structure
13885+ *
13886+ * @return 0 if successful, negative error code otherwise.
13887+ */
13888+int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *qtd,
13889+ dwc_otg_hcd_t *dwc_otg_hcd)
13890+{
13891+ struct usb_host_endpoint *ep;
13892+ dwc_otg_qh_t *qh;
13893+ unsigned long flags;
13894+ int retval = 0;
13895+
13896+ struct urb *urb = qtd->urb;
13897+
13898+ SPIN_LOCK_IRQSAVE(&dwc_otg_hcd->lock, flags);
13899+
13900+ /*
13901+ * Get the QH which holds the QTD-list to insert to. Create QH if it
13902+ * doesn't exist.
13903+ */
13904+ ep = dwc_urb_to_endpoint(urb);
13905+ qh = (dwc_otg_qh_t *)ep->hcpriv;
13906+ if (qh == NULL) {
13907+ qh = dwc_otg_hcd_qh_create (dwc_otg_hcd, urb);
13908+ if (qh == NULL) {
13909+ goto done;
13910+ }
13911+ ep->hcpriv = qh;
13912+ }
13913+
13914+ retval = dwc_otg_hcd_qh_add(dwc_otg_hcd, qh);
13915+ if (retval == 0) {
13916+ list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list);
13917+ }
13918+
13919+ done:
13920+ SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
13921+
13922+ return retval;
13923+}
13924+
13925+#endif /* DWC_DEVICE_ONLY */
13926--- /dev/null
13927+++ b/drivers/usb/dwc/otg_pcd.c
13928@@ -0,0 +1,2502 @@
13929+/* ==========================================================================
13930+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $
13931+ * $Revision: #70 $
13932+ * $Date: 2008/10/14 $
13933+ * $Change: 1115682 $
13934+ *
13935+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
13936+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
13937+ * otherwise expressly agreed to in writing between Synopsys and you.
13938+ *
13939+ * The Software IS NOT an item of Licensed Software or Licensed Product under
13940+ * any End User Software License Agreement or Agreement for Licensed Product
13941+ * with Synopsys or any supplement thereto. You are permitted to use and
13942+ * redistribute this Software in source and binary forms, with or without
13943+ * modification, provided that redistributions of source code must retain this
13944+ * notice. You may not view, use, disclose, copy or distribute this file or
13945+ * any information contained herein except pursuant to this license grant from
13946+ * Synopsys. If you do not agree with this notice, including the disclaimer
13947+ * below, then you are not authorized to use the Software.
13948+ *
13949+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
13950+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
13951+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
13952+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
13953+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
13954+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
13955+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
13956+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
13957+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
13958+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
13959+ * DAMAGE.
13960+ * ========================================================================== */
13961+#ifndef DWC_HOST_ONLY
13962+
13963+/** @file
13964+ * This file implements the Peripheral Controller Driver.
13965+ *
13966+ * The Peripheral Controller Driver (PCD) is responsible for
13967+ * translating requests from the Function Driver into the appropriate
13968+ * actions on the DWC_otg controller. It isolates the Function Driver
13969+ * from the specifics of the controller by providing an API to the
13970+ * Function Driver.
13971+ *
13972+ * The Peripheral Controller Driver for Linux will implement the
13973+ * Gadget API, so that the existing Gadget drivers can be used.
13974+ * (Gadget Driver is the Linux terminology for a Function Driver.)
13975+ *
13976+ * The Linux Gadget API is defined in the header file
13977+ * <code><linux/usb_gadget.h></code>. The USB EP operations API is
13978+ * defined in the structure <code>usb_ep_ops</code> and the USB
13979+ * Controller API is defined in the structure
13980+ * <code>usb_gadget_ops</code>.
13981+ *
13982+ * An important function of the PCD is managing interrupts generated
13983+ * by the DWC_otg controller. The implementation of the DWC_otg device
13984+ * mode interrupt service routines is in dwc_otg_pcd_intr.c.
13985+ *
13986+ * @todo Add Device Mode test modes (Test J mode, Test K mode, etc).
13987+ * @todo Does it work when the request size is greater than DEPTSIZ
13988+ * transfer size
13989+ *
13990+ */
13991+
13992+
13993+#include <linux/kernel.h>
13994+#include <linux/module.h>
13995+#include <linux/moduleparam.h>
13996+#include <linux/init.h>
13997+#include <linux/device.h>
13998+#include <linux/platform_device.h>
13999+#include <linux/errno.h>
14000+#include <linux/list.h>
14001+#include <linux/interrupt.h>
14002+#include <linux/string.h>
14003+#include <linux/dma-mapping.h>
14004+#include <linux/version.h>
14005+
14006+#include <mach/irqs.h>
14007+#include <linux/usb/ch9.h>
14008+
14009+//#include <linux/usb_gadget.h>
14010+
14011+#include "otg_driver.h"
14012+#include "otg_pcd.h"
14013+
14014+
14015+
14016+/**
14017+ * Static PCD pointer for use in usb_gadget_register_driver and
14018+ * usb_gadget_unregister_driver. Initialized in dwc_otg_pcd_init.
14019+ */
14020+static dwc_otg_pcd_t *s_pcd = 0;
14021+
14022+
14023+/* Display the contents of the buffer */
14024+extern void dump_msg(const u8 *buf, unsigned int length);
14025+
14026+
14027+/**
14028+ * This function completes a request. It call's the request call back.
14029+ */
14030+void dwc_otg_request_done(dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_request_t *req,
14031+ int status)
14032+{
14033+ unsigned stopped = ep->stopped;
14034+
14035+ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, ep);
14036+ list_del_init(&req->queue);
14037+
14038+ if (req->req.status == -EINPROGRESS) {
14039+ req->req.status = status;
14040+ } else {
14041+ status = req->req.status;
14042+ }
14043+
14044+ /* don't modify queue heads during completion callback */
14045+ ep->stopped = 1;
14046+ SPIN_UNLOCK(&ep->pcd->lock);
14047+ req->req.complete(&ep->ep, &req->req);
14048+ SPIN_LOCK(&ep->pcd->lock);
14049+
14050+ if (ep->pcd->request_pending > 0) {
14051+ --ep->pcd->request_pending;
14052+ }
14053+
14054+ ep->stopped = stopped;
14055+}
14056+
14057+/**
14058+ * This function terminates all the requsts in the EP request queue.
14059+ */
14060+void dwc_otg_request_nuke(dwc_otg_pcd_ep_t *ep)
14061+{
14062+ dwc_otg_pcd_request_t *req;
14063+
14064+ ep->stopped = 1;
14065+
14066+ /* called with irqs blocked?? */
14067+ while (!list_empty(&ep->queue)) {
14068+ req = list_entry(ep->queue.next, dwc_otg_pcd_request_t,
14069+ queue);
14070+ dwc_otg_request_done(ep, req, -ESHUTDOWN);
14071+ }
14072+}
14073+
14074+/* USB Endpoint Operations */
14075+/*
14076+ * The following sections briefly describe the behavior of the Gadget
14077+ * API endpoint operations implemented in the DWC_otg driver
14078+ * software. Detailed descriptions of the generic behavior of each of
14079+ * these functions can be found in the Linux header file
14080+ * include/linux/usb_gadget.h.
14081+ *
14082+ * The Gadget API provides wrapper functions for each of the function
14083+ * pointers defined in usb_ep_ops. The Gadget Driver calls the wrapper
14084+ * function, which then calls the underlying PCD function. The
14085+ * following sections are named according to the wrapper
14086+ * functions. Within each section, the corresponding DWC_otg PCD
14087+ * function name is specified.
14088+ *
14089+ */
14090+
14091+/**
14092+ * This function assigns periodic Tx FIFO to an periodic EP
14093+ * in shared Tx FIFO mode
14094+ */
14095+static uint32_t assign_perio_tx_fifo(dwc_otg_core_if_t *core_if)
14096+{
14097+ uint32_t PerTxMsk = 1;
14098+ int i;
14099+ for(i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; ++i)
14100+ {
14101+ if((PerTxMsk & core_if->p_tx_msk) == 0) {
14102+ core_if->p_tx_msk |= PerTxMsk;
14103+ return i + 1;
14104+ }
14105+ PerTxMsk <<= 1;
14106+ }
14107+ return 0;
14108+}
14109+/**
14110+ * This function releases periodic Tx FIFO
14111+ * in shared Tx FIFO mode
14112+ */
14113+static void release_perio_tx_fifo(dwc_otg_core_if_t *core_if, uint32_t fifo_num)
14114+{
14115+ core_if->p_tx_msk = (core_if->p_tx_msk & (1 << (fifo_num - 1))) ^ core_if->p_tx_msk;
14116+}
14117+/**
14118+ * This function assigns periodic Tx FIFO to an periodic EP
14119+ * in shared Tx FIFO mode
14120+ */
14121+static uint32_t assign_tx_fifo(dwc_otg_core_if_t *core_if)
14122+{
14123+ uint32_t TxMsk = 1;
14124+ int i;
14125+
14126+ for(i = 0; i < core_if->hwcfg4.b.num_in_eps; ++i)
14127+ {
14128+ if((TxMsk & core_if->tx_msk) == 0) {
14129+ core_if->tx_msk |= TxMsk;
14130+ return i + 1;
14131+ }
14132+ TxMsk <<= 1;
14133+ }
14134+ return 0;
14135+}
14136+/**
14137+ * This function releases periodic Tx FIFO
14138+ * in shared Tx FIFO mode
14139+ */
14140+static void release_tx_fifo(dwc_otg_core_if_t *core_if, uint32_t fifo_num)
14141+{
14142+ core_if->tx_msk = (core_if->tx_msk & (1 << (fifo_num - 1))) ^ core_if->tx_msk;
14143+}
14144+
14145+/**
14146+ * This function is called by the Gadget Driver for each EP to be
14147+ * configured for the current configuration (SET_CONFIGURATION).
14148+ *
14149+ * This function initializes the dwc_otg_ep_t data structure, and then
14150+ * calls dwc_otg_ep_activate.
14151+ */
14152+static int dwc_otg_pcd_ep_enable(struct usb_ep *usb_ep,
14153+ const struct usb_endpoint_descriptor *ep_desc)
14154+{
14155+ dwc_otg_pcd_ep_t *ep = 0;
14156+ dwc_otg_pcd_t *pcd = 0;
14157+ unsigned long flags;
14158+
14159+ DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p)\n", __func__, usb_ep, ep_desc);
14160+
14161+ ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
14162+ if (!usb_ep || !ep_desc || ep->desc ||
14163+ ep_desc->bDescriptorType != USB_DT_ENDPOINT) {
14164+ DWC_WARN("%s, bad ep or descriptor\n", __func__);
14165+ return -EINVAL;
14166+ }
14167+ if (ep == &ep->pcd->ep0) {
14168+ DWC_WARN("%s, bad ep(0)\n", __func__);
14169+ return -EINVAL;
14170+ }
14171+
14172+ /* Check FIFO size? */
14173+ if (!ep_desc->wMaxPacketSize) {
14174+ DWC_WARN("%s, bad %s maxpacket\n", __func__, usb_ep->name);
14175+ return -ERANGE;
14176+ }
14177+
14178+ pcd = ep->pcd;
14179+ if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) {
14180+ DWC_WARN("%s, bogus device state\n", __func__);
14181+ return -ESHUTDOWN;
14182+ }
14183+
14184+ SPIN_LOCK_IRQSAVE(&pcd->lock, flags);
14185+
14186+ ep->desc = ep_desc;
14187+ ep->ep.maxpacket = le16_to_cpu (ep_desc->wMaxPacketSize);
14188+
14189+ /*
14190+ * Activate the EP
14191+ */
14192+ ep->stopped = 0;
14193+
14194+ ep->dwc_ep.is_in = (USB_DIR_IN & ep_desc->bEndpointAddress) != 0;
14195+ ep->dwc_ep.maxpacket = ep->ep.maxpacket;
14196+
14197+ ep->dwc_ep.type = ep_desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
14198+
14199+ if(ep->dwc_ep.is_in) {
14200+ if(!pcd->otg_dev->core_if->en_multiple_tx_fifo) {
14201+ ep->dwc_ep.tx_fifo_num = 0;
14202+
14203+ if (ep->dwc_ep.type == USB_ENDPOINT_XFER_ISOC) {
14204+ /*
14205+ * if ISOC EP then assign a Periodic Tx FIFO.
14206+ */
14207+ ep->dwc_ep.tx_fifo_num = assign_perio_tx_fifo(pcd->otg_dev->core_if);
14208+ }
14209+ } else {
14210+ /*
14211+ * if Dedicated FIFOs mode is on then assign a Tx FIFO.
14212+ */
14213+ ep->dwc_ep.tx_fifo_num = assign_tx_fifo(pcd->otg_dev->core_if);
14214+
14215+ }
14216+ }
14217+ /* Set initial data PID. */
14218+ if (ep->dwc_ep.type == USB_ENDPOINT_XFER_BULK) {
14219+ ep->dwc_ep.data_pid_start = 0;
14220+ }
14221+
14222+ DWC_DEBUGPL(DBG_PCD, "Activate %s-%s: type=%d, mps=%d desc=%p\n",
14223+ ep->ep.name, (ep->dwc_ep.is_in ?"IN":"OUT"),
14224+ ep->dwc_ep.type, ep->dwc_ep.maxpacket, ep->desc);
14225+
14226+ if(ep->dwc_ep.type != USB_ENDPOINT_XFER_ISOC) {
14227+ ep->dwc_ep.desc_addr = dwc_otg_ep_alloc_desc_chain(&ep->dwc_ep.dma_desc_addr, MAX_DMA_DESC_CNT);
14228+ }
14229+
14230+ dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
14231+ SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
14232+
14233+ return 0;
14234+}
14235+
14236+/**
14237+ * This function is called when an EP is disabled due to disconnect or
14238+ * change in configuration. Any pending requests will terminate with a
14239+ * status of -ESHUTDOWN.
14240+ *
14241+ * This function modifies the dwc_otg_ep_t data structure for this EP,
14242+ * and then calls dwc_otg_ep_deactivate.
14243+ */
14244+static int dwc_otg_pcd_ep_disable(struct usb_ep *usb_ep)
14245+{
14246+ dwc_otg_pcd_ep_t *ep;
14247+ dwc_otg_pcd_t *pcd = 0;
14248+ unsigned long flags;
14249+
14250+ DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, usb_ep);
14251+ ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
14252+ if (!usb_ep || !ep->desc) {
14253+ DWC_DEBUGPL(DBG_PCD, "%s, %s not enabled\n", __func__,
14254+ usb_ep ? ep->ep.name : NULL);
14255+ return -EINVAL;
14256+ }
14257+
14258+ SPIN_LOCK_IRQSAVE(&ep->pcd->lock, flags);
14259+
14260+ dwc_otg_request_nuke(ep);
14261+
14262+ dwc_otg_ep_deactivate(GET_CORE_IF(ep->pcd), &ep->dwc_ep);
14263+ ep->desc = 0;
14264+ ep->stopped = 1;
14265+
14266+ if(ep->dwc_ep.is_in) {
14267+ dwc_otg_flush_tx_fifo(GET_CORE_IF(ep->pcd), ep->dwc_ep.tx_fifo_num);
14268+ release_perio_tx_fifo(GET_CORE_IF(ep->pcd), ep->dwc_ep.tx_fifo_num);
14269+ release_tx_fifo(GET_CORE_IF(ep->pcd), ep->dwc_ep.tx_fifo_num);
14270+ }
14271+
14272+ /* Free DMA Descriptors */
14273+ pcd = ep->pcd;
14274+
14275+ SPIN_UNLOCK_IRQRESTORE(&ep->pcd->lock, flags);
14276+
14277+ if(ep->dwc_ep.type != USB_ENDPOINT_XFER_ISOC && ep->dwc_ep.desc_addr) {
14278+ dwc_otg_ep_free_desc_chain(ep->dwc_ep.desc_addr, ep->dwc_ep.dma_desc_addr, MAX_DMA_DESC_CNT);
14279+ }
14280+
14281+ DWC_DEBUGPL(DBG_PCD, "%s disabled\n", usb_ep->name);
14282+ return 0;
14283+}
14284+
14285+
14286+/**
14287+ * This function allocates a request object to use with the specified
14288+ * endpoint.
14289+ *
14290+ * @param ep The endpoint to be used with with the request
14291+ * @param gfp_flags the GFP_* flags to use.
14292+ */
14293+static struct usb_request *dwc_otg_pcd_alloc_request(struct usb_ep *ep,
14294+ gfp_t gfp_flags)
14295+{
14296+ dwc_otg_pcd_request_t *req;
14297+
14298+ DWC_DEBUGPL(DBG_PCDV,"%s(%p,%d)\n", __func__, ep, gfp_flags);
14299+ if (0 == ep) {
14300+ DWC_WARN("%s() %s\n", __func__, "Invalid EP!\n");
14301+ return 0;
14302+ }
14303+ req = kmalloc(sizeof(dwc_otg_pcd_request_t), gfp_flags);
14304+ if (0 == req) {
14305+ DWC_WARN("%s() %s\n", __func__,
14306+ "request allocation failed!\n");
14307+ return 0;
14308+ }
14309+ memset(req, 0, sizeof(dwc_otg_pcd_request_t));
14310+ req->req.dma = DMA_ADDR_INVALID;
14311+ INIT_LIST_HEAD(&req->queue);
14312+ return &req->req;
14313+}
14314+
14315+/**
14316+ * This function frees a request object.
14317+ *
14318+ * @param ep The endpoint associated with the request
14319+ * @param req The request being freed
14320+ */
14321+static void dwc_otg_pcd_free_request(struct usb_ep *ep,
14322+ struct usb_request *req)
14323+{
14324+ dwc_otg_pcd_request_t *request;
14325+ DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p)\n", __func__, ep, req);
14326+
14327+ if (0 == ep || 0 == req) {
14328+ DWC_WARN("%s() %s\n", __func__,
14329+ "Invalid ep or req argument!\n");
14330+ return;
14331+ }
14332+
14333+ request = container_of(req, dwc_otg_pcd_request_t, req);
14334+ kfree(request);
14335+}
14336+
14337+#if 0
14338+/**
14339+ * This function allocates an I/O buffer to be used for a transfer
14340+ * to/from the specified endpoint.
14341+ *
14342+ * @param usb_ep The endpoint to be used with with the request
14343+ * @param bytes The desired number of bytes for the buffer
14344+ * @param dma Pointer to the buffer's DMA address; must be valid
14345+ * @param gfp_flags the GFP_* flags to use.
14346+ * @return address of a new buffer or null is buffer could not be allocated.
14347+ */
14348+static void *dwc_otg_pcd_alloc_buffer(struct usb_ep *usb_ep, unsigned bytes,
14349+ dma_addr_t *dma,
14350+ gfp_t gfp_flags)
14351+{
14352+ void *buf;
14353+ dwc_otg_pcd_ep_t *ep;
14354+ dwc_otg_pcd_t *pcd = 0;
14355+
14356+ ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
14357+ pcd = ep->pcd;
14358+
14359+ DWC_DEBUGPL(DBG_PCDV,"%s(%p,%d,%p,%0x)\n", __func__, usb_ep, bytes,
14360+ dma, gfp_flags);
14361+
14362+ /* Check dword alignment */
14363+ if ((bytes & 0x3UL) != 0) {
14364+ DWC_WARN("%s() Buffer size is not a multiple of"
14365+ "DWORD size (%d)",__func__, bytes);
14366+ }
14367+
14368+ if (GET_CORE_IF(pcd)->dma_enable) {
14369+ buf = dma_alloc_coherent (NULL, bytes, dma, gfp_flags);
14370+ }
14371+ else {
14372+ buf = kmalloc(bytes, gfp_flags);
14373+ }
14374+
14375+ /* Check dword alignment */
14376+ if (((int)buf & 0x3UL) != 0) {
14377+ DWC_WARN("%s() Buffer is not DWORD aligned (%p)",
14378+ __func__, buf);
14379+ }
14380+
14381+ return buf;
14382+}
14383+
14384+/**
14385+ * This function frees an I/O buffer that was allocated by alloc_buffer.
14386+ *
14387+ * @param usb_ep the endpoint associated with the buffer
14388+ * @param buf address of the buffer
14389+ * @param dma The buffer's DMA address
14390+ * @param bytes The number of bytes of the buffer
14391+ */
14392+static void dwc_otg_pcd_free_buffer(struct usb_ep *usb_ep, void *buf,
14393+ dma_addr_t dma, unsigned bytes)
14394+{
14395+ dwc_otg_pcd_ep_t *ep;
14396+ dwc_otg_pcd_t *pcd = 0;
14397+
14398+ ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
14399+ pcd = ep->pcd;
14400+
14401+ DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p,%0x,%d)\n", __func__, ep, buf, dma, bytes);
14402+
14403+ if (GET_CORE_IF(pcd)->dma_enable) {
14404+ dma_free_coherent (NULL, bytes, buf, dma);
14405+ }
14406+ else {
14407+ kfree(buf);
14408+ }
14409+}
14410+#endif
14411+
14412+/**
14413+ * This function is used to submit an I/O Request to an EP.
14414+ *
14415+ * - When the request completes the request's completion callback
14416+ * is called to return the request to the driver.
14417+ * - An EP, except control EPs, may have multiple requests
14418+ * pending.
14419+ * - Once submitted the request cannot be examined or modified.
14420+ * - Each request is turned into one or more packets.
14421+ * - A BULK EP can queue any amount of data; the transfer is
14422+ * packetized.
14423+ * - Zero length Packets are specified with the request 'zero'
14424+ * flag.
14425+ */
14426+static int dwc_otg_pcd_ep_queue(struct usb_ep *usb_ep,
14427+ struct usb_request *usb_req,
14428+ gfp_t gfp_flags)
14429+{
14430+ int prevented = 0;
14431+ dwc_otg_pcd_request_t *req;
14432+ dwc_otg_pcd_ep_t *ep;
14433+ dwc_otg_pcd_t *pcd;
14434+ unsigned long flags = 0;
14435+
14436+ DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p,%d)\n",
14437+ __func__, usb_ep, usb_req, gfp_flags);
14438+
14439+ req = container_of(usb_req, dwc_otg_pcd_request_t, req);
14440+ if (!usb_req || !usb_req->complete || !usb_req->buf ||
14441+ !list_empty(&req->queue)) {
14442+ DWC_WARN("%s, bad params\n", __func__);
14443+ return -EINVAL;
14444+ }
14445+
14446+ ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
14447+ if (!usb_ep || (!ep->desc && ep->dwc_ep.num != 0)/* || ep->stopped != 0*/) {
14448+ DWC_WARN("%s, bad ep\n", __func__);
14449+ return -EINVAL;
14450+ }
14451+
14452+ pcd = ep->pcd;
14453+ if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) {
14454+ DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n", pcd->gadget.speed);
14455+ DWC_WARN("%s, bogus device state\n", __func__);
14456+ return -ESHUTDOWN;
14457+ }
14458+
14459+
14460+ DWC_DEBUGPL(DBG_PCD, "%s queue req %p, len %d buf %p\n",
14461+ usb_ep->name, usb_req, usb_req->length, usb_req->buf);
14462+
14463+ if (!GET_CORE_IF(pcd)->core_params->opt) {
14464+ if (ep->dwc_ep.num != 0) {
14465+ DWC_ERROR("%s queue req %p, len %d buf %p\n",
14466+ usb_ep->name, usb_req, usb_req->length, usb_req->buf);
14467+ }
14468+ }
14469+
14470+ SPIN_LOCK_IRQSAVE(&ep->pcd->lock, flags);
14471+
14472+#if defined(DEBUG) & defined(VERBOSE)
14473+ dump_msg(usb_req->buf, usb_req->length);
14474+#endif
14475+
14476+ usb_req->status = -EINPROGRESS;
14477+ usb_req->actual = 0;
14478+
14479+ /*
14480+ * For EP0 IN without premature status, zlp is required?
14481+ */
14482+ if (ep->dwc_ep.num == 0 && ep->dwc_ep.is_in) {
14483+ DWC_DEBUGPL(DBG_PCDV, "%s-OUT ZLP\n", usb_ep->name);
14484+ //_req->zero = 1;
14485+ }
14486+
14487+ /* Start the transfer */
14488+ if (list_empty(&ep->queue) && !ep->stopped) {
14489+ /* EP0 Transfer? */
14490+ if (ep->dwc_ep.num == 0) {
14491+ switch (pcd->ep0state) {
14492+ case EP0_IN_DATA_PHASE:
14493+ DWC_DEBUGPL(DBG_PCD,
14494+ "%s ep0: EP0_IN_DATA_PHASE\n",
14495+ __func__);
14496+ break;
14497+
14498+ case EP0_OUT_DATA_PHASE:
14499+ DWC_DEBUGPL(DBG_PCD,
14500+ "%s ep0: EP0_OUT_DATA_PHASE\n",
14501+ __func__);
14502+ if (pcd->request_config) {
14503+ /* Complete STATUS PHASE */
14504+ ep->dwc_ep.is_in = 1;
14505+ pcd->ep0state = EP0_IN_STATUS_PHASE;
14506+ }
14507+ break;
14508+
14509+ case EP0_IN_STATUS_PHASE:
14510+ DWC_DEBUGPL(DBG_PCD,
14511+ "%s ep0: EP0_IN_STATUS_PHASE\n",
14512+ __func__);
14513+ break;
14514+
14515+ default:
14516+ DWC_DEBUGPL(DBG_ANY, "ep0: odd state %d\n",
14517+ pcd->ep0state);
14518+ SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
14519+ return -EL2HLT;
14520+ }
14521+ ep->dwc_ep.dma_addr = usb_req->dma;
14522+ ep->dwc_ep.start_xfer_buff = usb_req->buf;
14523+ ep->dwc_ep.xfer_buff = usb_req->buf;
14524+ ep->dwc_ep.xfer_len = usb_req->length;
14525+ ep->dwc_ep.xfer_count = 0;
14526+ ep->dwc_ep.sent_zlp = 0;
14527+ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
14528+
14529+ if(usb_req->zero) {
14530+ if((ep->dwc_ep.xfer_len % ep->dwc_ep.maxpacket == 0)
14531+ && (ep->dwc_ep.xfer_len != 0)) {
14532+ ep->dwc_ep.sent_zlp = 1;
14533+ }
14534+
14535+ }
14536+
14537+ ep_check_and_patch_dma_addr(ep);
14538+ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep->dwc_ep);
14539+ }
14540+ else {
14541+
14542+ uint32_t max_transfer = GET_CORE_IF(ep->pcd)->core_params->max_transfer_size;
14543+
14544+ /* Setup and start the Transfer */
14545+ ep->dwc_ep.dma_addr = usb_req->dma;
14546+ ep->dwc_ep.start_xfer_buff = usb_req->buf;
14547+ ep->dwc_ep.xfer_buff = usb_req->buf;
14548+ ep->dwc_ep.sent_zlp = 0;
14549+ ep->dwc_ep.total_len = usb_req->length;
14550+ ep->dwc_ep.xfer_len = 0;
14551+ ep->dwc_ep.xfer_count = 0;
14552+
14553+ if(max_transfer > MAX_TRANSFER_SIZE) {
14554+ ep->dwc_ep.maxxfer = max_transfer - (max_transfer % ep->dwc_ep.maxpacket);
14555+ } else {
14556+ ep->dwc_ep.maxxfer = max_transfer;
14557+ }
14558+
14559+ if(usb_req->zero) {
14560+ if((ep->dwc_ep.total_len % ep->dwc_ep.maxpacket == 0)
14561+ && (ep->dwc_ep.total_len != 0)) {
14562+ ep->dwc_ep.sent_zlp = 1;
14563+ }
14564+
14565+ }
14566+
14567+ ep_check_and_patch_dma_addr(ep);
14568+ dwc_otg_ep_start_transfer(GET_CORE_IF(pcd), &ep->dwc_ep);
14569+ }
14570+ }
14571+
14572+ if ((req != 0) || prevented) {
14573+ ++pcd->request_pending;
14574+ list_add_tail(&req->queue, &ep->queue);
14575+ if (ep->dwc_ep.is_in && ep->stopped && !(GET_CORE_IF(pcd)->dma_enable)) {
14576+ /** @todo NGS Create a function for this. */
14577+ diepmsk_data_t diepmsk = { .d32 = 0};
14578+ diepmsk.b.intktxfemp = 1;
14579+ if(&GET_CORE_IF(pcd)->multiproc_int_enable) {
14580+ dwc_modify_reg32(&GET_CORE_IF(pcd)->dev_if->dev_global_regs->diepeachintmsk[ep->dwc_ep.num],
14581+ 0, diepmsk.d32);
14582+ } else {
14583+ dwc_modify_reg32(&GET_CORE_IF(pcd)->dev_if->dev_global_regs->diepmsk, 0, diepmsk.d32);
14584+ }
14585+ }
14586+ }
14587+
14588+ SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
14589+ return 0;
14590+}
14591+
14592+/**
14593+ * This function cancels an I/O request from an EP.
14594+ */
14595+static int dwc_otg_pcd_ep_dequeue(struct usb_ep *usb_ep,
14596+ struct usb_request *usb_req)
14597+{
14598+ dwc_otg_pcd_request_t *req;
14599+ dwc_otg_pcd_ep_t *ep;
14600+ dwc_otg_pcd_t *pcd;
14601+ unsigned long flags;
14602+
14603+ DWC_DEBUGPL(DBG_PCDV,"%s(%p,%p)\n", __func__, usb_ep, usb_req);
14604+
14605+ ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
14606+ if (!usb_ep || !usb_req || (!ep->desc && ep->dwc_ep.num != 0)) {
14607+ DWC_WARN("%s, bad argument\n", __func__);
14608+ return -EINVAL;
14609+ }
14610+ pcd = ep->pcd;
14611+ if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) {
14612+ DWC_WARN("%s, bogus device state\n", __func__);
14613+ return -ESHUTDOWN;
14614+ }
14615+
14616+ SPIN_LOCK_IRQSAVE(&pcd->lock, flags);
14617+ DWC_DEBUGPL(DBG_PCDV, "%s %s %s %p\n", __func__, usb_ep->name,
14618+ ep->dwc_ep.is_in ? "IN" : "OUT",
14619+ usb_req);
14620+
14621+ /* make sure it's actually queued on this endpoint */
14622+ list_for_each_entry(req, &ep->queue, queue)
14623+ {
14624+ if (&req->req == usb_req) {
14625+ break;
14626+ }
14627+ }
14628+
14629+ if (&req->req != usb_req) {
14630+ SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
14631+ return -EINVAL;
14632+ }
14633+
14634+ if (!list_empty(&req->queue)) {
14635+ dwc_otg_request_done(ep, req, -ECONNRESET);
14636+ }
14637+ else {
14638+ req = 0;
14639+ }
14640+
14641+ SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
14642+
14643+ return req ? 0 : -EOPNOTSUPP;
14644+}
14645+
14646+/**
14647+ * usb_ep_set_halt stalls an endpoint.
14648+ *
14649+ * usb_ep_clear_halt clears an endpoint halt and resets its data
14650+ * toggle.
14651+ *
14652+ * Both of these functions are implemented with the same underlying
14653+ * function. The behavior depends on the value argument.
14654+ *
14655+ * @param[in] usb_ep the Endpoint to halt or clear halt.
14656+ * @param[in] value
14657+ * - 0 means clear_halt.
14658+ * - 1 means set_halt,
14659+ * - 2 means clear stall lock flag.
14660+ * - 3 means set stall lock flag.
14661+ */
14662+static int dwc_otg_pcd_ep_set_halt(struct usb_ep *usb_ep, int value)
14663+{
14664+ int retval = 0;
14665+ unsigned long flags;
14666+ dwc_otg_pcd_ep_t *ep = 0;
14667+
14668+
14669+ DWC_DEBUGPL(DBG_PCD,"HALT %s %d\n", usb_ep->name, value);
14670+
14671+ ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
14672+
14673+ if (!usb_ep || (!ep->desc && ep != &ep->pcd->ep0) ||
14674+ ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
14675+ DWC_WARN("%s, bad ep\n", __func__);
14676+ return -EINVAL;
14677+ }
14678+
14679+ SPIN_LOCK_IRQSAVE(&ep->pcd->lock, flags);
14680+ if (!list_empty(&ep->queue)) {
14681+ DWC_WARN("%s() %s XFer In process\n", __func__, usb_ep->name);
14682+ retval = -EAGAIN;
14683+ }
14684+ else if (value == 0) {
14685+ dwc_otg_ep_clear_stall(ep->pcd->otg_dev->core_if,
14686+ &ep->dwc_ep);
14687+ }
14688+ else if(value == 1) {
14689+ if (ep->dwc_ep.is_in == 1 && ep->pcd->otg_dev->core_if->dma_desc_enable) {
14690+ dtxfsts_data_t txstatus;
14691+ fifosize_data_t txfifosize;
14692+
14693+ txfifosize.d32 = dwc_read_reg32(&ep->pcd->otg_dev->core_if->core_global_regs->dptxfsiz_dieptxf[ep->dwc_ep.tx_fifo_num]);
14694+ txstatus.d32 = dwc_read_reg32(&ep->pcd->otg_dev->core_if->dev_if->in_ep_regs[ep->dwc_ep.num]->dtxfsts);
14695+
14696+ if(txstatus.b.txfspcavail < txfifosize.b.depth) {
14697+ DWC_WARN("%s() %s Data In Tx Fifo\n", __func__, usb_ep->name);
14698+ retval = -EAGAIN;
14699+ }
14700+ else {
14701+ if (ep->dwc_ep.num == 0) {
14702+ ep->pcd->ep0state = EP0_STALL;
14703+ }
14704+
14705+ ep->stopped = 1;
14706+ dwc_otg_ep_set_stall(ep->pcd->otg_dev->core_if,
14707+ &ep->dwc_ep);
14708+ }
14709+ }
14710+ else {
14711+ if (ep->dwc_ep.num == 0) {
14712+ ep->pcd->ep0state = EP0_STALL;
14713+ }
14714+
14715+ ep->stopped = 1;
14716+ dwc_otg_ep_set_stall(ep->pcd->otg_dev->core_if,
14717+ &ep->dwc_ep);
14718+ }
14719+ }
14720+ else if (value == 2) {
14721+ ep->dwc_ep.stall_clear_flag = 0;
14722+ }
14723+ else if (value == 3) {
14724+ ep->dwc_ep.stall_clear_flag = 1;
14725+ }
14726+
14727+ SPIN_UNLOCK_IRQRESTORE(&ep->pcd->lock, flags);
14728+ return retval;
14729+}
14730+
14731+/**
14732+ * This function allocates a DMA Descriptor chain for the Endpoint
14733+ * buffer to be used for a transfer to/from the specified endpoint.
14734+ */
14735+dwc_otg_dma_desc_t* dwc_otg_ep_alloc_desc_chain(uint32_t * dma_desc_addr, uint32_t count)
14736+{
14737+
14738+ return dma_alloc_coherent(NULL, count * sizeof(dwc_otg_dma_desc_t), dma_desc_addr, GFP_KERNEL);
14739+}
14740+
14741+LIST_HEAD(tofree_list);
14742+DEFINE_SPINLOCK(tofree_list_lock);
14743+
14744+struct free_param {
14745+ struct list_head list;
14746+
14747+ void* addr;
14748+ dma_addr_t dma_addr;
14749+ uint32_t size;
14750+};
14751+void free_list_agent_fn(void *data){
14752+ struct list_head free_list;
14753+ struct free_param *cur,*next;
14754+
14755+ spin_lock(&tofree_list_lock);
14756+ list_add(&free_list,&tofree_list);
14757+ list_del_init(&tofree_list);
14758+ spin_unlock(&tofree_list_lock);
14759+
14760+ list_for_each_entry_safe(cur,next,&free_list,list){
14761+ if(cur==&free_list) break;
14762+ dma_free_coherent(NULL,cur->size,cur->addr,cur->dma_addr);
14763+ list_del(&cur->list);
14764+ kfree(cur);
14765+ }
14766+}
14767+DECLARE_WORK(free_list_agent,free_list_agent_fn);
14768+/**
14769+ * This function frees a DMA Descriptor chain that was allocated by ep_alloc_desc.
14770+ */
14771+void dwc_otg_ep_free_desc_chain(dwc_otg_dma_desc_t* desc_addr, uint32_t dma_desc_addr, uint32_t count)
14772+{
14773+ if(irqs_disabled()){
14774+ struct free_param* fp=kmalloc(sizeof(struct free_param),GFP_KERNEL);
14775+ fp->addr=desc_addr;
14776+ fp->dma_addr=dma_desc_addr;
14777+ fp->size=count*sizeof(dwc_otg_dma_desc_t);
14778+
14779+ spin_lock(&tofree_list_lock);
14780+ list_add(&fp->list,&tofree_list);
14781+ spin_unlock(&tofree_list_lock);
14782+
14783+ schedule_work(&free_list_agent);
14784+ return ;
14785+ }
14786+ dma_free_coherent(NULL, count * sizeof(dwc_otg_dma_desc_t), desc_addr, dma_desc_addr);
14787+}
14788+
14789+#ifdef DWC_EN_ISOC
14790+
14791+/**
14792+ * This function initializes a descriptor chain for Isochronous transfer
14793+ *
14794+ * @param core_if Programming view of DWC_otg controller.
14795+ * @param dwc_ep The EP to start the transfer on.
14796+ *
14797+ */
14798+void dwc_otg_iso_ep_start_ddma_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
14799+{
14800+
14801+ dsts_data_t dsts = { .d32 = 0};
14802+ depctl_data_t depctl = { .d32 = 0 };
14803+ volatile uint32_t *addr;
14804+ int i, j;
14805+
14806+ if(dwc_ep->is_in)
14807+ dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl / dwc_ep->bInterval;
14808+ else
14809+ dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / dwc_ep->bInterval;
14810+
14811+
14812+ /** Allocate descriptors for double buffering */
14813+ dwc_ep->iso_desc_addr = dwc_otg_ep_alloc_desc_chain(&dwc_ep->iso_dma_desc_addr,dwc_ep->desc_cnt*2);
14814+ if(dwc_ep->desc_addr) {
14815+ DWC_WARN("%s, can't allocate DMA descriptor chain\n", __func__);
14816+ return;
14817+ }
14818+
14819+ dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
14820+
14821+ /** ISO OUT EP */
14822+ if(dwc_ep->is_in == 0) {
14823+ desc_sts_data_t sts = { .d32 =0 };
14824+ dwc_otg_dma_desc_t* dma_desc = dwc_ep->iso_desc_addr;
14825+ dma_addr_t dma_ad;
14826+ uint32_t data_per_desc;
14827+ dwc_otg_dev_out_ep_regs_t *out_regs =
14828+ core_if->dev_if->out_ep_regs[dwc_ep->num];
14829+ int offset;
14830+
14831+ addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
14832+ dma_ad = (dma_addr_t)dwc_read_reg32(&(out_regs->doepdma));
14833+
14834+ /** Buffer 0 descriptors setup */
14835+ dma_ad = dwc_ep->dma_addr0;
14836+
14837+ sts.b_iso_out.bs = BS_HOST_READY;
14838+ sts.b_iso_out.rxsts = 0;
14839+ sts.b_iso_out.l = 0;
14840+ sts.b_iso_out.sp = 0;
14841+ sts.b_iso_out.ioc = 0;
14842+ sts.b_iso_out.pid = 0;
14843+ sts.b_iso_out.framenum = 0;
14844+
14845+ offset = 0;
14846+ for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm)
14847+ {
14848+
14849+ for(j = 0; j < dwc_ep->pkt_per_frm; ++j)
14850+ {
14851+ data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
14852+ dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
14853+
14854+ data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
14855+ sts.b_iso_out.rxbytes = data_per_desc;
14856+ writel((uint32_t)dma_ad, &dma_desc->buf);
14857+ writel(sts.d32, &dma_desc->status);
14858+
14859+ offset += data_per_desc;
14860+ dma_desc ++;
14861+ //(uint32_t)dma_ad += data_per_desc;
14862+ dma_ad = (uint32_t)dma_ad + data_per_desc;
14863+ }
14864+ }
14865+
14866+ for(j = 0; j < dwc_ep->pkt_per_frm - 1; ++j)
14867+ {
14868+ data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
14869+ dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
14870+ data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
14871+ sts.b_iso_out.rxbytes = data_per_desc;
14872+ writel((uint32_t)dma_ad, &dma_desc->buf);
14873+ writel(sts.d32, &dma_desc->status);
14874+
14875+ offset += data_per_desc;
14876+ dma_desc ++;
14877+ //(uint32_t)dma_ad += data_per_desc;
14878+ dma_ad = (uint32_t)dma_ad + data_per_desc;
14879+ }
14880+
14881+ sts.b_iso_out.ioc = 1;
14882+ data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
14883+ dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
14884+ data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
14885+ sts.b_iso_out.rxbytes = data_per_desc;
14886+
14887+ writel((uint32_t)dma_ad, &dma_desc->buf);
14888+ writel(sts.d32, &dma_desc->status);
14889+ dma_desc ++;
14890+
14891+ /** Buffer 1 descriptors setup */
14892+ sts.b_iso_out.ioc = 0;
14893+ dma_ad = dwc_ep->dma_addr1;
14894+
14895+ offset = 0;
14896+ for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm)
14897+ {
14898+ for(j = 0; j < dwc_ep->pkt_per_frm; ++j)
14899+ {
14900+ data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
14901+ dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
14902+ data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
14903+ sts.b_iso_out.rxbytes = data_per_desc;
14904+ writel((uint32_t)dma_ad, &dma_desc->buf);
14905+ writel(sts.d32, &dma_desc->status);
14906+
14907+ offset += data_per_desc;
14908+ dma_desc ++;
14909+ //(uint32_t)dma_ad += data_per_desc;
14910+ dma_ad = (uint32_t)dma_ad + data_per_desc;
14911+ }
14912+ }
14913+ for(j = 0; j < dwc_ep->pkt_per_frm - 1; ++j)
14914+ {
14915+ data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
14916+ dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
14917+ data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
14918+ sts.b_iso_out.rxbytes = data_per_desc;
14919+ writel((uint32_t)dma_ad, &dma_desc->buf);
14920+ writel(sts.d32, &dma_desc->status);
14921+
14922+ offset += data_per_desc;
14923+ dma_desc ++;
14924+ //(uint32_t)dma_ad += data_per_desc;
14925+ dma_ad = (uint32_t)dma_ad + data_per_desc;
14926+ }
14927+
14928+ sts.b_iso_out.ioc = 1;
14929+ sts.b_iso_out.l = 1;
14930+ data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
14931+ dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
14932+ data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
14933+ sts.b_iso_out.rxbytes = data_per_desc;
14934+
14935+ writel((uint32_t)dma_ad, &dma_desc->buf);
14936+ writel(sts.d32, &dma_desc->status);
14937+
14938+ dwc_ep->next_frame = 0;
14939+
14940+ /** Write dma_ad into DOEPDMA register */
14941+ dwc_write_reg32(&(out_regs->doepdma),(uint32_t)dwc_ep->iso_dma_desc_addr);
14942+
14943+ }
14944+ /** ISO IN EP */
14945+ else {
14946+ desc_sts_data_t sts = { .d32 =0 };
14947+ dwc_otg_dma_desc_t* dma_desc = dwc_ep->iso_desc_addr;
14948+ dma_addr_t dma_ad;
14949+ dwc_otg_dev_in_ep_regs_t *in_regs =
14950+ core_if->dev_if->in_ep_regs[dwc_ep->num];
14951+ unsigned int frmnumber;
14952+ fifosize_data_t txfifosize,rxfifosize;
14953+
14954+ txfifosize.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[dwc_ep->num]->dtxfsts);
14955+ rxfifosize.d32 = dwc_read_reg32(&core_if->core_global_regs->grxfsiz);
14956+
14957+
14958+ addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
14959+
14960+ dma_ad = dwc_ep->dma_addr0;
14961+
14962+ dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
14963+
14964+ sts.b_iso_in.bs = BS_HOST_READY;
14965+ sts.b_iso_in.txsts = 0;
14966+ sts.b_iso_in.sp = (dwc_ep->data_per_frame % dwc_ep->maxpacket)? 1 : 0;
14967+ sts.b_iso_in.ioc = 0;
14968+ sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
14969+
14970+
14971+ frmnumber = dwc_ep->next_frame;
14972+
14973+ sts.b_iso_in.framenum = frmnumber;
14974+ sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
14975+ sts.b_iso_in.l = 0;
14976+
14977+ /** Buffer 0 descriptors setup */
14978+ for(i = 0; i < dwc_ep->desc_cnt - 1; i++)
14979+ {
14980+ writel((uint32_t)dma_ad, &dma_desc->buf);
14981+ writel(sts.d32, &dma_desc->status);
14982+ dma_desc ++;
14983+
14984+ //(uint32_t)dma_ad += dwc_ep->data_per_frame;
14985+ dma_ad = (uint32_t)dma_ad + dwc_ep->data_per_frame;
14986+ sts.b_iso_in.framenum += dwc_ep->bInterval;
14987+ }
14988+
14989+ sts.b_iso_in.ioc = 1;
14990+ writel((uint32_t)dma_ad, &dma_desc->buf);
14991+ writel(sts.d32, &dma_desc->status);
14992+ ++dma_desc;
14993+
14994+ /** Buffer 1 descriptors setup */
14995+ sts.b_iso_in.ioc = 0;
14996+ dma_ad = dwc_ep->dma_addr1;
14997+
14998+ for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm)
14999+ {
15000+ writel((uint32_t)dma_ad, &dma_desc->buf);
15001+ writel(sts.d32, &dma_desc->status);
15002+ dma_desc ++;
15003+
15004+ //(uint32_t)dma_ad += dwc_ep->data_per_frame;
15005+ dma_ad = (uint32_t)dma_ad + dwc_ep->data_per_frame;
15006+ sts.b_iso_in.framenum += dwc_ep->bInterval;
15007+
15008+ sts.b_iso_in.ioc = 0;
15009+ }
15010+ sts.b_iso_in.ioc = 1;
15011+ sts.b_iso_in.l = 1;
15012+
15013+ writel((uint32_t)dma_ad, &dma_desc->buf);
15014+ writel(sts.d32, &dma_desc->status);
15015+
15016+ dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval;
15017+
15018+ /** Write dma_ad into diepdma register */
15019+ dwc_write_reg32(&(in_regs->diepdma),(uint32_t)dwc_ep->iso_dma_desc_addr);
15020+ }
15021+ /** Enable endpoint, clear nak */
15022+ depctl.d32 = 0;
15023+ depctl.b.epena = 1;
15024+ depctl.b.usbactep = 1;
15025+ depctl.b.cnak = 1;
15026+
15027+ dwc_modify_reg32(addr, depctl.d32,depctl.d32);
15028+ depctl.d32 = dwc_read_reg32(addr);
15029+}
15030+
15031+/**
15032+ * This function initializes a descriptor chain for Isochronous transfer
15033+ *
15034+ * @param core_if Programming view of DWC_otg controller.
15035+ * @param ep The EP to start the transfer on.
15036+ *
15037+ */
15038+
15039+void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
15040+{
15041+ depctl_data_t depctl = { .d32 = 0 };
15042+ volatile uint32_t *addr;
15043+
15044+
15045+ if(ep->is_in) {
15046+ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
15047+ } else {
15048+ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
15049+ }
15050+
15051+
15052+ if(core_if->dma_enable == 0 || core_if->dma_desc_enable!= 0) {
15053+ return;
15054+ } else {
15055+ deptsiz_data_t deptsiz = { .d32 = 0 };
15056+
15057+ ep->xfer_len = ep->data_per_frame * ep->buf_proc_intrvl / ep->bInterval;
15058+ ep->pkt_cnt = (ep->xfer_len - 1 + ep->maxpacket) /
15059+ ep->maxpacket;
15060+ ep->xfer_count = 0;
15061+ ep->xfer_buff = (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
15062+ ep->dma_addr = (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
15063+
15064+ if(ep->is_in) {
15065+ /* Program the transfer size and packet count
15066+ * as follows: xfersize = N * maxpacket +
15067+ * short_packet pktcnt = N + (short_packet
15068+ * exist ? 1 : 0)
15069+ */
15070+ deptsiz.b.mc = ep->pkt_per_frm;
15071+ deptsiz.b.xfersize = ep->xfer_len;
15072+ deptsiz.b.pktcnt =
15073+ (ep->xfer_len - 1 + ep->maxpacket) /
15074+ ep->maxpacket;
15075+ dwc_write_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz, deptsiz.d32);
15076+
15077+ /* Write the DMA register */
15078+ dwc_write_reg32 (&(core_if->dev_if->in_ep_regs[ep->num]->diepdma), (uint32_t)ep->dma_addr);
15079+
15080+ } else {
15081+ deptsiz.b.pktcnt =
15082+ (ep->xfer_len + (ep->maxpacket - 1)) /
15083+ ep->maxpacket;
15084+ deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
15085+
15086+ dwc_write_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doeptsiz, deptsiz.d32);
15087+
15088+ /* Write the DMA register */
15089+ dwc_write_reg32 (&(core_if->dev_if->out_ep_regs[ep->num]->doepdma), (uint32_t)ep->dma_addr);
15090+
15091+ }
15092+ /** Enable endpoint, clear nak */
15093+ depctl.d32 = 0;
15094+ dwc_modify_reg32(addr, depctl.d32,depctl.d32);
15095+
15096+ depctl.b.epena = 1;
15097+ depctl.b.cnak = 1;
15098+
15099+ dwc_modify_reg32(addr, depctl.d32,depctl.d32);
15100+ }
15101+}
15102+
15103+
15104+/**
15105+ * This function does the setup for a data transfer for an EP and
15106+ * starts the transfer. For an IN transfer, the packets will be
15107+ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
15108+ * the packets are unloaded from the Rx FIFO in the ISR. the ISR.
15109+ *
15110+ * @param core_if Programming view of DWC_otg controller.
15111+ * @param ep The EP to start the transfer on.
15112+ */
15113+
15114+void dwc_otg_iso_ep_start_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
15115+{
15116+ if(core_if->dma_enable) {
15117+ if(core_if->dma_desc_enable) {
15118+ if(ep->is_in) {
15119+ ep->desc_cnt = ep->pkt_cnt / ep->pkt_per_frm;
15120+ } else {
15121+ ep->desc_cnt = ep->pkt_cnt;
15122+ }
15123+ dwc_otg_iso_ep_start_ddma_transfer(core_if, ep);
15124+ } else {
15125+ if(core_if->pti_enh_enable) {
15126+ dwc_otg_iso_ep_start_buf_transfer(core_if, ep);
15127+ } else {
15128+ ep->cur_pkt_addr = (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
15129+ ep->cur_pkt_dma_addr = (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
15130+ dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
15131+ }
15132+ }
15133+ } else {
15134+ ep->cur_pkt_addr = (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
15135+ ep->cur_pkt_dma_addr = (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
15136+ dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
15137+ }
15138+}
15139+
15140+/**
15141+ * This function does the setup for a data transfer for an EP and
15142+ * starts the transfer. For an IN transfer, the packets will be
15143+ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
15144+ * the packets are unloaded from the Rx FIFO in the ISR. the ISR.
15145+ *
15146+ * @param core_if Programming view of DWC_otg controller.
15147+ * @param ep The EP to start the transfer on.
15148+ */
15149+
15150+void dwc_otg_iso_ep_stop_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
15151+{
15152+ depctl_data_t depctl = { .d32 = 0 };
15153+ volatile uint32_t *addr;
15154+
15155+ if(ep->is_in == 1) {
15156+ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
15157+ }
15158+ else {
15159+ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
15160+ }
15161+
15162+ /* disable the ep */
15163+ depctl.d32 = dwc_read_reg32(addr);
15164+
15165+ depctl.b.epdis = 1;
15166+ depctl.b.snak = 1;
15167+
15168+ dwc_write_reg32(addr, depctl.d32);
15169+
15170+ if(core_if->dma_desc_enable &&
15171+ ep->iso_desc_addr && ep->iso_dma_desc_addr) {
15172+ dwc_otg_ep_free_desc_chain(ep->iso_desc_addr,ep->iso_dma_desc_addr,ep->desc_cnt * 2);
15173+ }
15174+
15175+ /* reset varibales */
15176+ ep->dma_addr0 = 0;
15177+ ep->dma_addr1 = 0;
15178+ ep->xfer_buff0 = 0;
15179+ ep->xfer_buff1 = 0;
15180+ ep->data_per_frame = 0;
15181+ ep->data_pattern_frame = 0;
15182+ ep->sync_frame = 0;
15183+ ep->buf_proc_intrvl = 0;
15184+ ep->bInterval = 0;
15185+ ep->proc_buf_num = 0;
15186+ ep->pkt_per_frm = 0;
15187+ ep->pkt_per_frm = 0;
15188+ ep->desc_cnt = 0;
15189+ ep->iso_desc_addr = 0;
15190+ ep->iso_dma_desc_addr = 0;
15191+}
15192+
15193+
15194+/**
15195+ * This function is used to submit an ISOC Transfer Request to an EP.
15196+ *
15197+ * - Every time a sync period completes the request's completion callback
15198+ * is called to provide data to the gadget driver.
15199+ * - Once submitted the request cannot be modified.
15200+ * - Each request is turned into periodic data packets untill ISO
15201+ * Transfer is stopped..
15202+ */
15203+static int dwc_otg_pcd_iso_ep_start(struct usb_ep *usb_ep, struct usb_iso_request *req,
15204+ gfp_t gfp_flags)
15205+{
15206+ dwc_otg_pcd_ep_t *ep;
15207+ dwc_otg_pcd_t *pcd;
15208+ dwc_ep_t *dwc_ep;
15209+ unsigned long flags = 0;
15210+ int32_t frm_data;
15211+ dwc_otg_core_if_t *core_if;
15212+ dcfg_data_t dcfg;
15213+ dsts_data_t dsts;
15214+
15215+
15216+ if (!req || !req->process_buffer || !req->buf0 || !req->buf1) {
15217+ DWC_WARN("%s, bad params\n", __func__);
15218+ return -EINVAL;
15219+ }
15220+
15221+ ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
15222+
15223+ if (!usb_ep || !ep->desc || ep->dwc_ep.num == 0) {
15224+ DWC_WARN("%s, bad ep\n", __func__);
15225+ return -EINVAL;
15226+ }
15227+
15228+ pcd = ep->pcd;
15229+ core_if = GET_CORE_IF(pcd);
15230+
15231+ dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg);
15232+
15233+ if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) {
15234+ DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n", pcd->gadget.speed);
15235+ DWC_WARN("%s, bogus device state\n", __func__);
15236+ return -ESHUTDOWN;
15237+ }
15238+
15239+ SPIN_LOCK_IRQSAVE(&ep->pcd->lock, flags);
15240+
15241+ dwc_ep = &ep->dwc_ep;
15242+
15243+ if(ep->iso_req) {
15244+ DWC_WARN("%s, iso request in progress\n", __func__);
15245+ }
15246+ req->status = -EINPROGRESS;
15247+
15248+ dwc_ep->dma_addr0 = req->dma0;
15249+ dwc_ep->dma_addr1 = req->dma1;
15250+
15251+ dwc_ep->xfer_buff0 = req->buf0;
15252+ dwc_ep->xfer_buff1 = req->buf1;
15253+
15254+ ep->iso_req = req;
15255+
15256+ dwc_ep->data_per_frame = req->data_per_frame;
15257+
15258+ /** @todo - pattern data support is to be implemented in the future */
15259+ dwc_ep->data_pattern_frame = req->data_pattern_frame;
15260+ dwc_ep->sync_frame = req->sync_frame;
15261+
15262+ dwc_ep->buf_proc_intrvl = req->buf_proc_intrvl;
15263+
15264+ dwc_ep->bInterval = 1 << (ep->desc->bInterval - 1);
15265+
15266+ dwc_ep->proc_buf_num = 0;
15267+
15268+ dwc_ep->pkt_per_frm = 0;
15269+ frm_data = ep->dwc_ep.data_per_frame;
15270+ while(frm_data > 0) {
15271+ dwc_ep->pkt_per_frm++;
15272+ frm_data -= ep->dwc_ep.maxpacket;
15273+ }
15274+
15275+ dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
15276+
15277+ if(req->flags & USB_REQ_ISO_ASAP) {
15278+ dwc_ep->next_frame = dsts.b.soffn + 1;
15279+ if(dwc_ep->bInterval != 1){
15280+ dwc_ep->next_frame = dwc_ep->next_frame + (dwc_ep->bInterval - 1 - dwc_ep->next_frame % dwc_ep->bInterval);
15281+ }
15282+ } else {
15283+ dwc_ep->next_frame = req->start_frame;
15284+ }
15285+
15286+
15287+ if(!core_if->pti_enh_enable) {
15288+ dwc_ep->pkt_cnt = dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / dwc_ep->bInterval;
15289+ } else {
15290+ dwc_ep->pkt_cnt =
15291+ (dwc_ep->data_per_frame * (dwc_ep->buf_proc_intrvl / dwc_ep->bInterval)
15292+ - 1 + dwc_ep->maxpacket) / dwc_ep->maxpacket;
15293+ }
15294+
15295+ if(core_if->dma_desc_enable) {
15296+ dwc_ep->desc_cnt =
15297+ dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / dwc_ep->bInterval;
15298+ }
15299+
15300+ dwc_ep->pkt_info = kmalloc(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt, GFP_KERNEL);
15301+ if(!dwc_ep->pkt_info) {
15302+ return -ENOMEM;
15303+ }
15304+ if(core_if->pti_enh_enable) {
15305+ memset(dwc_ep->pkt_info, 0, sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
15306+ }
15307+
15308+ dwc_ep->cur_pkt = 0;
15309+
15310+ SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
15311+
15312+ dwc_otg_iso_ep_start_transfer(core_if, dwc_ep);
15313+
15314+ return 0;
15315+}
15316+
15317+/**
15318+ * This function stops ISO EP Periodic Data Transfer.
15319+ */
15320+static int dwc_otg_pcd_iso_ep_stop(struct usb_ep *usb_ep, struct usb_iso_request *req)
15321+{
15322+ dwc_otg_pcd_ep_t *ep;
15323+ dwc_otg_pcd_t *pcd;
15324+ dwc_ep_t *dwc_ep;
15325+ unsigned long flags;
15326+
15327+ ep = container_of(usb_ep, dwc_otg_pcd_ep_t, ep);
15328+
15329+ if (!usb_ep || !ep->desc || ep->dwc_ep.num == 0) {
15330+ DWC_WARN("%s, bad ep\n", __func__);
15331+ return -EINVAL;
15332+ }
15333+
15334+ pcd = ep->pcd;
15335+
15336+ if (!pcd->driver || pcd->gadget.speed == USB_SPEED_UNKNOWN) {
15337+ DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n", pcd->gadget.speed);
15338+ DWC_WARN("%s, bogus device state\n", __func__);
15339+ return -ESHUTDOWN;
15340+ }
15341+
15342+ dwc_ep = &ep->dwc_ep;
15343+
15344+ dwc_otg_iso_ep_stop_transfer(GET_CORE_IF(pcd), dwc_ep);
15345+
15346+ kfree(dwc_ep->pkt_info);
15347+
15348+ SPIN_LOCK_IRQSAVE(&pcd->lock, flags);
15349+
15350+ if(ep->iso_req != req) {
15351+ return -EINVAL;
15352+ }
15353+
15354+ req->status = -ECONNRESET;
15355+
15356+ SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
15357+
15358+
15359+ ep->iso_req = 0;
15360+
15361+ return 0;
15362+}
15363+
15364+/**
15365+ * This function is used for perodical data exchnage between PCD and gadget drivers.
15366+ * for Isochronous EPs
15367+ *
15368+ * - Every time a sync period completes this function is called to
15369+ * perform data exchange between PCD and gadget
15370+ */
15371+void dwc_otg_iso_buffer_done(dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_iso_request_t *req)
15372+{
15373+ int i;
15374+ struct usb_gadget_iso_packet_descriptor *iso_packet;
15375+ dwc_ep_t *dwc_ep;
15376+
15377+ dwc_ep = &ep->dwc_ep;
15378+
15379+ if(ep->iso_req->status == -ECONNRESET) {
15380+ DWC_PRINT("Device has already disconnected\n");
15381+ /*Device has been disconnected*/
15382+ return;
15383+ }
15384+
15385+ if(dwc_ep->proc_buf_num != 0) {
15386+ iso_packet = ep->iso_req->iso_packet_desc0;
15387+ }
15388+
15389+ else {
15390+ iso_packet = ep->iso_req->iso_packet_desc1;
15391+ }
15392+
15393+ /* Fill in ISOC packets descriptors & pass to gadget driver*/
15394+
15395+ for(i = 0; i < dwc_ep->pkt_cnt; ++i) {
15396+ iso_packet[i].status = dwc_ep->pkt_info[i].status;
15397+ iso_packet[i].offset = dwc_ep->pkt_info[i].offset;
15398+ iso_packet[i].actual_length = dwc_ep->pkt_info[i].length;
15399+ dwc_ep->pkt_info[i].status = 0;
15400+ dwc_ep->pkt_info[i].offset = 0;
15401+ dwc_ep->pkt_info[i].length = 0;
15402+ }
15403+
15404+ /* Call callback function to process data buffer */
15405+ ep->iso_req->status = 0;/* success */
15406+
15407+ SPIN_UNLOCK(&ep->pcd->lock);
15408+ ep->iso_req->process_buffer(&ep->ep, ep->iso_req);
15409+ SPIN_LOCK(&ep->pcd->lock);
15410+}
15411+
15412+
15413+static struct usb_iso_request *dwc_otg_pcd_alloc_iso_request(struct usb_ep *ep,int packets,
15414+ gfp_t gfp_flags)
15415+{
15416+ struct usb_iso_request *pReq = NULL;
15417+ uint32_t req_size;
15418+
15419+
15420+ req_size = sizeof(struct usb_iso_request);
15421+ req_size += (2 * packets * (sizeof(struct usb_gadget_iso_packet_descriptor)));
15422+
15423+
15424+ pReq = kmalloc(req_size, gfp_flags);
15425+ if (!pReq) {
15426+ DWC_WARN("%s, can't allocate Iso Request\n", __func__);
15427+ return 0;
15428+ }
15429+ pReq->iso_packet_desc0 = (void*) (pReq + 1);
15430+
15431+ pReq->iso_packet_desc1 = pReq->iso_packet_desc0 + packets;
15432+
15433+ return pReq;
15434+}
15435+
15436+static void dwc_otg_pcd_free_iso_request(struct usb_ep *ep, struct usb_iso_request *req)
15437+{
15438+ kfree(req);
15439+}
15440+
15441+static struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops =
15442+{
15443+ .ep_ops =
15444+ {
15445+ .enable = dwc_otg_pcd_ep_enable,
15446+ .disable = dwc_otg_pcd_ep_disable,
15447+
15448+ .alloc_request = dwc_otg_pcd_alloc_request,
15449+ .free_request = dwc_otg_pcd_free_request,
15450+
15451+ //.alloc_buffer = dwc_otg_pcd_alloc_buffer,
15452+ //.free_buffer = dwc_otg_pcd_free_buffer,
15453+
15454+ .queue = dwc_otg_pcd_ep_queue,
15455+ .dequeue = dwc_otg_pcd_ep_dequeue,
15456+
15457+ .set_halt = dwc_otg_pcd_ep_set_halt,
15458+ .fifo_status = 0,
15459+ .fifo_flush = 0,
15460+ },
15461+ .iso_ep_start = dwc_otg_pcd_iso_ep_start,
15462+ .iso_ep_stop = dwc_otg_pcd_iso_ep_stop,
15463+ .alloc_iso_request = dwc_otg_pcd_alloc_iso_request,
15464+ .free_iso_request = dwc_otg_pcd_free_iso_request,
15465+};
15466+
15467+#else
15468+
15469+
15470+static struct usb_ep_ops dwc_otg_pcd_ep_ops =
15471+{
15472+ .enable = dwc_otg_pcd_ep_enable,
15473+ .disable = dwc_otg_pcd_ep_disable,
15474+
15475+ .alloc_request = dwc_otg_pcd_alloc_request,
15476+ .free_request = dwc_otg_pcd_free_request,
15477+
15478+// .alloc_buffer = dwc_otg_pcd_alloc_buffer,
15479+// .free_buffer = dwc_otg_pcd_free_buffer,
15480+
15481+ .queue = dwc_otg_pcd_ep_queue,
15482+ .dequeue = dwc_otg_pcd_ep_dequeue,
15483+
15484+ .set_halt = dwc_otg_pcd_ep_set_halt,
15485+ .fifo_status = 0,
15486+ .fifo_flush = 0,
15487+
15488+
15489+};
15490+
15491+#endif /* DWC_EN_ISOC */
15492+/* Gadget Operations */
15493+/**
15494+ * The following gadget operations will be implemented in the DWC_otg
15495+ * PCD. Functions in the API that are not described below are not
15496+ * implemented.
15497+ *
15498+ * The Gadget API provides wrapper functions for each of the function
15499+ * pointers defined in usb_gadget_ops. The Gadget Driver calls the
15500+ * wrapper function, which then calls the underlying PCD function. The
15501+ * following sections are named according to the wrapper functions
15502+ * (except for ioctl, which doesn't have a wrapper function). Within
15503+ * each section, the corresponding DWC_otg PCD function name is
15504+ * specified.
15505+ *
15506+ */
15507+
15508+/**
15509+ *Gets the USB Frame number of the last SOF.
15510+ */
15511+static int dwc_otg_pcd_get_frame(struct usb_gadget *gadget)
15512+{
15513+ dwc_otg_pcd_t *pcd;
15514+
15515+ DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, gadget);
15516+
15517+ if (gadget == 0) {
15518+ return -ENODEV;
15519+ }
15520+ else {
15521+ pcd = container_of(gadget, dwc_otg_pcd_t, gadget);
15522+ dwc_otg_get_frame_number(GET_CORE_IF(pcd));
15523+ }
15524+
15525+ return 0;
15526+}
15527+
15528+void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t *pcd)
15529+{
15530+ uint32_t *addr = (uint32_t *)&(GET_CORE_IF(pcd)->core_global_regs->gotgctl);
15531+ gotgctl_data_t mem;
15532+ gotgctl_data_t val;
15533+
15534+ val.d32 = dwc_read_reg32(addr);
15535+ if (val.b.sesreq) {
15536+ DWC_ERROR("Session Request Already active!\n");
15537+ return;
15538+ }
15539+
15540+ DWC_NOTICE("Session Request Initated\n");
15541+ mem.d32 = dwc_read_reg32(addr);
15542+ mem.b.sesreq = 1;
15543+ dwc_write_reg32(addr, mem.d32);
15544+
15545+ /* Start the SRP timer */
15546+ dwc_otg_pcd_start_srp_timer(pcd);
15547+ return;
15548+}
15549+
15550+void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t *pcd, int set)
15551+{
15552+ dctl_data_t dctl = {.d32=0};
15553+ volatile uint32_t *addr = &(GET_CORE_IF(pcd)->dev_if->dev_global_regs->dctl);
15554+
15555+ if (dwc_otg_is_device_mode(GET_CORE_IF(pcd))) {
15556+ if (pcd->remote_wakeup_enable) {
15557+ if (set) {
15558+ dctl.b.rmtwkupsig = 1;
15559+ dwc_modify_reg32(addr, 0, dctl.d32);
15560+ DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
15561+ mdelay(1);
15562+ dwc_modify_reg32(addr, dctl.d32, 0);
15563+ DWC_DEBUGPL(DBG_PCD, "Clear Remote Wakeup\n");
15564+ }
15565+ else {
15566+ }
15567+ }
15568+ else {
15569+ DWC_DEBUGPL(DBG_PCD, "Remote Wakeup is disabled\n");
15570+ }
15571+ }
15572+ return;
15573+}
15574+
15575+/**
15576+ * Initiates Session Request Protocol (SRP) to wakeup the host if no
15577+ * session is in progress. If a session is already in progress, but
15578+ * the device is suspended, remote wakeup signaling is started.
15579+ *
15580+ */
15581+static int dwc_otg_pcd_wakeup(struct usb_gadget *gadget)
15582+{
15583+ unsigned long flags;
15584+ dwc_otg_pcd_t *pcd;
15585+ dsts_data_t dsts;
15586+ gotgctl_data_t gotgctl;
15587+
15588+ DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, gadget);
15589+
15590+ if (gadget == 0) {
15591+ return -ENODEV;
15592+ }
15593+ else {
15594+ pcd = container_of(gadget, dwc_otg_pcd_t, gadget);
15595+ }
15596+ SPIN_LOCK_IRQSAVE(&pcd->lock, flags);
15597+
15598+ /*
15599+ * This function starts the Protocol if no session is in progress. If
15600+ * a session is already in progress, but the device is suspended,
15601+ * remote wakeup signaling is started.
15602+ */
15603+
15604+ /* Check if valid session */
15605+ gotgctl.d32 = dwc_read_reg32(&(GET_CORE_IF(pcd)->core_global_regs->gotgctl));
15606+ if (gotgctl.b.bsesvld) {
15607+ /* Check if suspend state */
15608+ dsts.d32 = dwc_read_reg32(&(GET_CORE_IF(pcd)->dev_if->dev_global_regs->dsts));
15609+ if (dsts.b.suspsts) {
15610+ dwc_otg_pcd_remote_wakeup(pcd, 1);
15611+ }
15612+ }
15613+ else {
15614+ dwc_otg_pcd_initiate_srp(pcd);
15615+ }
15616+
15617+ SPIN_UNLOCK_IRQRESTORE(&pcd->lock, flags);
15618+ return 0;
15619+}
15620+
15621+static const struct usb_gadget_ops dwc_otg_pcd_ops =
15622+{
15623+ .get_frame = dwc_otg_pcd_get_frame,
15624+ .wakeup = dwc_otg_pcd_wakeup,
15625+ // current versions must always be self-powered
15626+};
15627+
15628+/**
15629+ * This function updates the otg values in the gadget structure.
15630+ */
15631+void dwc_otg_pcd_update_otg(dwc_otg_pcd_t *pcd, const unsigned reset)
15632+{
15633+
15634+ if (!pcd->gadget.is_otg)
15635+ return;
15636+
15637+ if (reset) {
15638+ pcd->b_hnp_enable = 0;
15639+ pcd->a_hnp_support = 0;
15640+ pcd->a_alt_hnp_support = 0;
15641+ }
15642+
15643+ pcd->gadget.b_hnp_enable = pcd->b_hnp_enable;
15644+ pcd->gadget.a_hnp_support = pcd->a_hnp_support;
15645+ pcd->gadget.a_alt_hnp_support = pcd->a_alt_hnp_support;
15646+}
15647+
15648+/**
15649+ * This function is the top level PCD interrupt handler.
15650+ */
15651+static irqreturn_t dwc_otg_pcd_irq(int irq, void *dev)
15652+{
15653+ dwc_otg_pcd_t *pcd = dev;
15654+ int32_t retval = IRQ_NONE;
15655+
15656+ retval = dwc_otg_pcd_handle_intr(pcd);
15657+ return IRQ_RETVAL(retval);
15658+}
15659+
15660+/**
15661+ * PCD Callback function for initializing the PCD when switching to
15662+ * device mode.
15663+ *
15664+ * @param p void pointer to the <code>dwc_otg_pcd_t</code>
15665+ */
15666+static int32_t dwc_otg_pcd_start_cb(void *p)
15667+{
15668+ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)p;
15669+
15670+ /*
15671+ * Initialized the Core for Device mode.
15672+ */
15673+ if (dwc_otg_is_device_mode(GET_CORE_IF(pcd))) {
15674+ dwc_otg_core_dev_init(GET_CORE_IF(pcd));
15675+ }
15676+ return 1;
15677+}
15678+
15679+/**
15680+ * PCD Callback function for stopping the PCD when switching to Host
15681+ * mode.
15682+ *
15683+ * @param p void pointer to the <code>dwc_otg_pcd_t</code>
15684+ */
15685+static int32_t dwc_otg_pcd_stop_cb(void *p)
15686+{
15687+ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)p;
15688+ extern void dwc_otg_pcd_stop(dwc_otg_pcd_t *_pcd);
15689+
15690+ dwc_otg_pcd_stop(pcd);
15691+ return 1;
15692+}
15693+
15694+
15695+/**
15696+ * PCD Callback function for notifying the PCD when resuming from
15697+ * suspend.
15698+ *
15699+ * @param p void pointer to the <code>dwc_otg_pcd_t</code>
15700+ */
15701+static int32_t dwc_otg_pcd_suspend_cb(void *p)
15702+{
15703+ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)p;
15704+
15705+ if (pcd->driver && pcd->driver->resume) {
15706+ SPIN_UNLOCK(&pcd->lock);
15707+ pcd->driver->suspend(&pcd->gadget);
15708+ SPIN_LOCK(&pcd->lock);
15709+ }
15710+
15711+ return 1;
15712+}
15713+
15714+
15715+/**
15716+ * PCD Callback function for notifying the PCD when resuming from
15717+ * suspend.
15718+ *
15719+ * @param p void pointer to the <code>dwc_otg_pcd_t</code>
15720+ */
15721+static int32_t dwc_otg_pcd_resume_cb(void *p)
15722+{
15723+ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)p;
15724+
15725+ if (pcd->driver && pcd->driver->resume) {
15726+ SPIN_UNLOCK(&pcd->lock);
15727+ pcd->driver->resume(&pcd->gadget);
15728+ SPIN_LOCK(&pcd->lock);
15729+ }
15730+
15731+ /* Stop the SRP timeout timer. */
15732+ if ((GET_CORE_IF(pcd)->core_params->phy_type != DWC_PHY_TYPE_PARAM_FS) ||
15733+ (!GET_CORE_IF(pcd)->core_params->i2c_enable)) {
15734+ if (GET_CORE_IF(pcd)->srp_timer_started) {
15735+ GET_CORE_IF(pcd)->srp_timer_started = 0;
15736+ del_timer(&pcd->srp_timer);
15737+ }
15738+ }
15739+ return 1;
15740+}
15741+
15742+
15743+/**
15744+ * PCD Callback structure for handling mode switching.
15745+ */
15746+static dwc_otg_cil_callbacks_t pcd_callbacks =
15747+{
15748+ .start = dwc_otg_pcd_start_cb,
15749+ .stop = dwc_otg_pcd_stop_cb,
15750+ .suspend = dwc_otg_pcd_suspend_cb,
15751+ .resume_wakeup = dwc_otg_pcd_resume_cb,
15752+ .p = 0, /* Set at registration */
15753+};
15754+
15755+/**
15756+ * This function is called when the SRP timer expires. The SRP should
15757+ * complete within 6 seconds.
15758+ */
15759+static void srp_timeout(unsigned long ptr)
15760+{
15761+ gotgctl_data_t gotgctl;
15762+ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *)ptr;
15763+ volatile uint32_t *addr = &core_if->core_global_regs->gotgctl;
15764+
15765+ gotgctl.d32 = dwc_read_reg32(addr);
15766+
15767+ core_if->srp_timer_started = 0;
15768+
15769+ if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
15770+ (core_if->core_params->i2c_enable)) {
15771+ DWC_PRINT("SRP Timeout\n");
15772+
15773+ if ((core_if->srp_success) &&
15774+ (gotgctl.b.bsesvld)) {
15775+ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
15776+ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
15777+ }
15778+
15779+ /* Clear Session Request */
15780+ gotgctl.d32 = 0;
15781+ gotgctl.b.sesreq = 1;
15782+ dwc_modify_reg32(&core_if->core_global_regs->gotgctl,
15783+ gotgctl.d32, 0);
15784+
15785+ core_if->srp_success = 0;
15786+ }
15787+ else {
15788+ DWC_ERROR("Device not connected/responding\n");
15789+ gotgctl.b.sesreq = 0;
15790+ dwc_write_reg32(addr, gotgctl.d32);
15791+ }
15792+ }
15793+ else if (gotgctl.b.sesreq) {
15794+ DWC_PRINT("SRP Timeout\n");
15795+
15796+ DWC_ERROR("Device not connected/responding\n");
15797+ gotgctl.b.sesreq = 0;
15798+ dwc_write_reg32(addr, gotgctl.d32);
15799+ }
15800+ else {
15801+ DWC_PRINT(" SRP GOTGCTL=%0x\n", gotgctl.d32);
15802+ }
15803+}
15804+
15805+/**
15806+ * Start the SRP timer to detect when the SRP does not complete within
15807+ * 6 seconds.
15808+ *
15809+ * @param pcd the pcd structure.
15810+ */
15811+void dwc_otg_pcd_start_srp_timer(dwc_otg_pcd_t *pcd)
15812+{
15813+ struct timer_list *srp_timer = &pcd->srp_timer;
15814+ GET_CORE_IF(pcd)->srp_timer_started = 1;
15815+ init_timer(srp_timer);
15816+ srp_timer->function = srp_timeout;
15817+ srp_timer->data = (unsigned long)GET_CORE_IF(pcd);
15818+ srp_timer->expires = jiffies + (HZ*6);
15819+ add_timer(srp_timer);
15820+}
15821+
15822+/**
15823+ * Tasklet
15824+ *
15825+ */
15826+extern void start_next_request(dwc_otg_pcd_ep_t *ep);
15827+
15828+static void start_xfer_tasklet_func (unsigned long data)
15829+{
15830+ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t*)data;
15831+ dwc_otg_core_if_t *core_if = pcd->otg_dev->core_if;
15832+
15833+ int i;
15834+ depctl_data_t diepctl;
15835+
15836+ DWC_DEBUGPL(DBG_PCDV, "Start xfer tasklet\n");
15837+
15838+ diepctl.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl);
15839+
15840+ if (pcd->ep0.queue_sof) {
15841+ pcd->ep0.queue_sof = 0;
15842+ start_next_request (&pcd->ep0);
15843+ // break;
15844+ }
15845+
15846+ for (i=0; i<core_if->dev_if->num_in_eps; i++)
15847+ {
15848+ depctl_data_t diepctl;
15849+ diepctl.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[i]->diepctl);
15850+
15851+ if (pcd->in_ep[i].queue_sof) {
15852+ pcd->in_ep[i].queue_sof = 0;
15853+ start_next_request (&pcd->in_ep[i]);
15854+ // break;
15855+ }
15856+ }
15857+
15858+ return;
15859+}
15860+
15861+
15862+
15863+
15864+
15865+
15866+
15867+static struct tasklet_struct start_xfer_tasklet = {
15868+ .next = NULL,
15869+ .state = 0,
15870+ .count = ATOMIC_INIT(0),
15871+ .func = start_xfer_tasklet_func,
15872+ .data = 0,
15873+};
15874+/**
15875+ * This function initialized the pcd Dp structures to there default
15876+ * state.
15877+ *
15878+ * @param pcd the pcd structure.
15879+ */
15880+void dwc_otg_pcd_reinit(dwc_otg_pcd_t *pcd)
15881+{
15882+ static const char * names[] =
15883+ {
15884+
15885+ "ep0",
15886+ "ep1in",
15887+ "ep2in",
15888+ "ep3in",
15889+ "ep4in",
15890+ "ep5in",
15891+ "ep6in",
15892+ "ep7in",
15893+ "ep8in",
15894+ "ep9in",
15895+ "ep10in",
15896+ "ep11in",
15897+ "ep12in",
15898+ "ep13in",
15899+ "ep14in",
15900+ "ep15in",
15901+ "ep1out",
15902+ "ep2out",
15903+ "ep3out",
15904+ "ep4out",
15905+ "ep5out",
15906+ "ep6out",
15907+ "ep7out",
15908+ "ep8out",
15909+ "ep9out",
15910+ "ep10out",
15911+ "ep11out",
15912+ "ep12out",
15913+ "ep13out",
15914+ "ep14out",
15915+ "ep15out"
15916+
15917+ };
15918+
15919+ int i;
15920+ int in_ep_cntr, out_ep_cntr;
15921+ uint32_t hwcfg1;
15922+ uint32_t num_in_eps = (GET_CORE_IF(pcd))->dev_if->num_in_eps;
15923+ uint32_t num_out_eps = (GET_CORE_IF(pcd))->dev_if->num_out_eps;
15924+ dwc_otg_pcd_ep_t *ep;
15925+
15926+ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd);
15927+
15928+ INIT_LIST_HEAD (&pcd->gadget.ep_list);
15929+ pcd->gadget.ep0 = &pcd->ep0.ep;
15930+ pcd->gadget.speed = USB_SPEED_UNKNOWN;
15931+
15932+ INIT_LIST_HEAD (&pcd->gadget.ep0->ep_list);
15933+
15934+ /**
15935+ * Initialize the EP0 structure.
15936+ */
15937+ ep = &pcd->ep0;
15938+
15939+ /* Init EP structure */
15940+ ep->desc = 0;
15941+ ep->pcd = pcd;
15942+ ep->stopped = 1;
15943+
15944+ /* Init DWC ep structure */
15945+ ep->dwc_ep.num = 0;
15946+ ep->dwc_ep.active = 0;
15947+ ep->dwc_ep.tx_fifo_num = 0;
15948+ /* Control until ep is actvated */
15949+ ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
15950+ ep->dwc_ep.maxpacket = MAX_PACKET_SIZE;
15951+ ep->dwc_ep.dma_addr = 0;
15952+ ep->dwc_ep.start_xfer_buff = 0;
15953+ ep->dwc_ep.xfer_buff = 0;
15954+ ep->dwc_ep.xfer_len = 0;
15955+ ep->dwc_ep.xfer_count = 0;
15956+ ep->dwc_ep.sent_zlp = 0;
15957+ ep->dwc_ep.total_len = 0;
15958+ ep->queue_sof = 0;
15959+ ep->dwc_ep.desc_addr = 0;
15960+ ep->dwc_ep.dma_desc_addr = 0;
15961+
15962+ ep->dwc_ep.aligned_buf=NULL;
15963+ ep->dwc_ep.aligned_buf_size=0;
15964+ ep->dwc_ep.aligned_dma_addr=0;
15965+
15966+
15967+ /* Init the usb_ep structure. */
15968+ ep->ep.name = names[0];
15969+ ep->ep.ops = (struct usb_ep_ops*)&dwc_otg_pcd_ep_ops;
15970+
15971+ /**
15972+ * @todo NGS: What should the max packet size be set to
15973+ * here? Before EP type is set?
15974+ */
15975+ ep->ep.maxpacket = MAX_PACKET_SIZE;
15976+
15977+ list_add_tail (&ep->ep.ep_list, &pcd->gadget.ep_list);
15978+
15979+ INIT_LIST_HEAD (&ep->queue);
15980+ /**
15981+ * Initialize the EP structures.
15982+ */
15983+ in_ep_cntr = 0;
15984+ hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 3;
15985+
15986+ for (i = 1; in_ep_cntr < num_in_eps; i++)
15987+ {
15988+ if((hwcfg1 & 0x1) == 0) {
15989+ dwc_otg_pcd_ep_t *ep = &pcd->in_ep[in_ep_cntr];
15990+ in_ep_cntr ++;
15991+
15992+ /* Init EP structure */
15993+ ep->desc = 0;
15994+ ep->pcd = pcd;
15995+ ep->stopped = 1;
15996+
15997+ /* Init DWC ep structure */
15998+ ep->dwc_ep.is_in = 1;
15999+ ep->dwc_ep.num = i;
16000+ ep->dwc_ep.active = 0;
16001+ ep->dwc_ep.tx_fifo_num = 0;
16002+
16003+ /* Control until ep is actvated */
16004+ ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
16005+ ep->dwc_ep.maxpacket = MAX_PACKET_SIZE;
16006+ ep->dwc_ep.dma_addr = 0;
16007+ ep->dwc_ep.start_xfer_buff = 0;
16008+ ep->dwc_ep.xfer_buff = 0;
16009+ ep->dwc_ep.xfer_len = 0;
16010+ ep->dwc_ep.xfer_count = 0;
16011+ ep->dwc_ep.sent_zlp = 0;
16012+ ep->dwc_ep.total_len = 0;
16013+ ep->queue_sof = 0;
16014+ ep->dwc_ep.desc_addr = 0;
16015+ ep->dwc_ep.dma_desc_addr = 0;
16016+
16017+ /* Init the usb_ep structure. */
16018+ ep->ep.name = names[i];
16019+ ep->ep.ops = (struct usb_ep_ops*)&dwc_otg_pcd_ep_ops;
16020+
16021+ /**
16022+ * @todo NGS: What should the max packet size be set to
16023+ * here? Before EP type is set?
16024+ */
16025+ ep->ep.maxpacket = MAX_PACKET_SIZE;
16026+
16027+ //add only even number ep as in
16028+ if((i%2)==1)
16029+ list_add_tail (&ep->ep.ep_list, &pcd->gadget.ep_list);
16030+
16031+ INIT_LIST_HEAD (&ep->queue);
16032+ }
16033+ hwcfg1 >>= 2;
16034+ }
16035+
16036+ out_ep_cntr = 0;
16037+ hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 2;
16038+
16039+ for (i = 1; out_ep_cntr < num_out_eps; i++)
16040+ {
16041+ if((hwcfg1 & 0x1) == 0) {
16042+ dwc_otg_pcd_ep_t *ep = &pcd->out_ep[out_ep_cntr];
16043+ out_ep_cntr++;
16044+
16045+ /* Init EP structure */
16046+ ep->desc = 0;
16047+ ep->pcd = pcd;
16048+ ep->stopped = 1;
16049+
16050+ /* Init DWC ep structure */
16051+ ep->dwc_ep.is_in = 0;
16052+ ep->dwc_ep.num = i;
16053+ ep->dwc_ep.active = 0;
16054+ ep->dwc_ep.tx_fifo_num = 0;
16055+ /* Control until ep is actvated */
16056+ ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
16057+ ep->dwc_ep.maxpacket = MAX_PACKET_SIZE;
16058+ ep->dwc_ep.dma_addr = 0;
16059+ ep->dwc_ep.start_xfer_buff = 0;
16060+ ep->dwc_ep.xfer_buff = 0;
16061+ ep->dwc_ep.xfer_len = 0;
16062+ ep->dwc_ep.xfer_count = 0;
16063+ ep->dwc_ep.sent_zlp = 0;
16064+ ep->dwc_ep.total_len = 0;
16065+ ep->queue_sof = 0;
16066+
16067+ /* Init the usb_ep structure. */
16068+ ep->ep.name = names[15 + i];
16069+ ep->ep.ops = (struct usb_ep_ops*)&dwc_otg_pcd_ep_ops;
16070+ /**
16071+ * @todo NGS: What should the max packet size be set to
16072+ * here? Before EP type is set?
16073+ */
16074+ ep->ep.maxpacket = MAX_PACKET_SIZE;
16075+
16076+ //add only odd number ep as out
16077+ if((i%2)==0)
16078+ list_add_tail (&ep->ep.ep_list, &pcd->gadget.ep_list);
16079+
16080+ INIT_LIST_HEAD (&ep->queue);
16081+ }
16082+ hwcfg1 >>= 2;
16083+ }
16084+
16085+ /* remove ep0 from the list. There is a ep0 pointer.*/
16086+ list_del_init (&pcd->ep0.ep.ep_list);
16087+
16088+ pcd->ep0state = EP0_DISCONNECT;
16089+ pcd->ep0.ep.maxpacket = MAX_EP0_SIZE;
16090+ pcd->ep0.dwc_ep.maxpacket = MAX_EP0_SIZE;
16091+ pcd->ep0.dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
16092+}
16093+
16094+/**
16095+ * This function releases the Gadget device.
16096+ * required by device_unregister().
16097+ *
16098+ * @todo Should this do something? Should it free the PCD?
16099+ */
16100+static void dwc_otg_pcd_gadget_release(struct device *dev)
16101+{
16102+ DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, dev);
16103+}
16104+
16105+
16106+
16107+/**
16108+ * This function initialized the PCD portion of the driver.
16109+ *
16110+ */
16111+u8 dev_id[]="gadget";
16112+int dwc_otg_pcd_init(struct platform_device *pdev)
16113+{
16114+ static char pcd_name[] = "dwc_otg_pcd";
16115+ dwc_otg_pcd_t *pcd;
16116+ dwc_otg_core_if_t* core_if;
16117+ dwc_otg_dev_if_t* dev_if;
16118+ dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev);
16119+ int retval = 0;
16120+
16121+
16122+ DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n",__func__, pdev);
16123+ /*
16124+ * Allocate PCD structure
16125+ */
16126+ pcd = kmalloc(sizeof(dwc_otg_pcd_t), GFP_KERNEL);
16127+
16128+ if (pcd == 0) {
16129+ return -ENOMEM;
16130+ }
16131+
16132+ memset(pcd, 0, sizeof(dwc_otg_pcd_t));
16133+ spin_lock_init(&pcd->lock);
16134+
16135+ otg_dev->pcd = pcd;
16136+ s_pcd = pcd;
16137+ pcd->gadget.name = pcd_name;
16138+
16139+ pcd->gadget.dev.init_name = dev_id;
16140+ pcd->otg_dev = platform_get_drvdata(pdev);
16141+
16142+ pcd->gadget.dev.parent = &pdev->dev;
16143+ pcd->gadget.dev.release = dwc_otg_pcd_gadget_release;
16144+ pcd->gadget.ops = &dwc_otg_pcd_ops;
16145+
16146+ core_if = GET_CORE_IF(pcd);
16147+ dev_if = core_if->dev_if;
16148+
16149+ if(core_if->hwcfg4.b.ded_fifo_en) {
16150+ DWC_PRINT("Dedicated Tx FIFOs mode\n");
16151+ }
16152+ else {
16153+ DWC_PRINT("Shared Tx FIFO mode\n");
16154+ }
16155+
16156+ /* If the module is set to FS or if the PHY_TYPE is FS then the gadget
16157+ * should not report as dual-speed capable. replace the following line
16158+ * with the block of code below it once the software is debugged for
16159+ * this. If is_dualspeed = 0 then the gadget driver should not report
16160+ * a device qualifier descriptor when queried. */
16161+ if ((GET_CORE_IF(pcd)->core_params->speed == DWC_SPEED_PARAM_FULL) ||
16162+ ((GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == 2) &&
16163+ (GET_CORE_IF(pcd)->hwcfg2.b.fs_phy_type == 1) &&
16164+ (GET_CORE_IF(pcd)->core_params->ulpi_fs_ls))) {
16165+ pcd->gadget.max_speed = USB_SPEED_FULL;
16166+ }
16167+ else {
16168+ pcd->gadget.max_speed = USB_SPEED_HIGH;
16169+ }
16170+
16171+ if ((otg_dev->core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE) ||
16172+ (otg_dev->core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST) ||
16173+ (otg_dev->core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
16174+ (otg_dev->core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
16175+ pcd->gadget.is_otg = 0;
16176+ }
16177+ else {
16178+ pcd->gadget.is_otg = 1;
16179+ }
16180+
16181+
16182+ pcd->driver = 0;
16183+ /* Register the gadget device */
16184+printk("%s: 1\n",__func__);
16185+ retval = device_register(&pcd->gadget.dev);
16186+ if (retval != 0) {
16187+ kfree (pcd);
16188+printk("%s: 2\n",__func__);
16189+ return retval;
16190+ }
16191+
16192+
16193+ /*
16194+ * Initialized the Core for Device mode.
16195+ */
16196+ if (dwc_otg_is_device_mode(core_if)) {
16197+ dwc_otg_core_dev_init(core_if);
16198+ }
16199+
16200+ /*
16201+ * Initialize EP structures
16202+ */
16203+ dwc_otg_pcd_reinit(pcd);
16204+
16205+ /*
16206+ * Register the PCD Callbacks.
16207+ */
16208+ dwc_otg_cil_register_pcd_callbacks(otg_dev->core_if, &pcd_callbacks,
16209+ pcd);
16210+ /*
16211+ * Setup interupt handler
16212+ */
16213+ DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n", otg_dev->irq);
16214+ retval = request_irq(otg_dev->irq, dwc_otg_pcd_irq,
16215+ IRQF_SHARED, pcd->gadget.name, pcd);
16216+ if (retval != 0) {
16217+ DWC_ERROR("request of irq%d failed\n", otg_dev->irq);
16218+ device_unregister(&pcd->gadget.dev);
16219+ kfree (pcd);
16220+ return -EBUSY;
16221+ }
16222+
16223+ /*
16224+ * Initialize the DMA buffer for SETUP packets
16225+ */
16226+ if (GET_CORE_IF(pcd)->dma_enable) {
16227+ pcd->setup_pkt = dma_alloc_coherent (NULL, sizeof (*pcd->setup_pkt) * 5, &pcd->setup_pkt_dma_handle, 0);
16228+ if (pcd->setup_pkt == 0) {
16229+ free_irq(otg_dev->irq, pcd);
16230+ device_unregister(&pcd->gadget.dev);
16231+ kfree (pcd);
16232+ return -ENOMEM;
16233+ }
16234+
16235+ pcd->status_buf = dma_alloc_coherent (NULL, sizeof (uint16_t), &pcd->status_buf_dma_handle, 0);
16236+ if (pcd->status_buf == 0) {
16237+ dma_free_coherent(NULL, sizeof(*pcd->setup_pkt), pcd->setup_pkt, pcd->setup_pkt_dma_handle);
16238+ free_irq(otg_dev->irq, pcd);
16239+ device_unregister(&pcd->gadget.dev);
16240+ kfree (pcd);
16241+ return -ENOMEM;
16242+ }
16243+
16244+ if (GET_CORE_IF(pcd)->dma_desc_enable) {
16245+ dev_if->setup_desc_addr[0] = dwc_otg_ep_alloc_desc_chain(&dev_if->dma_setup_desc_addr[0], 1);
16246+ dev_if->setup_desc_addr[1] = dwc_otg_ep_alloc_desc_chain(&dev_if->dma_setup_desc_addr[1], 1);
16247+ dev_if->in_desc_addr = dwc_otg_ep_alloc_desc_chain(&dev_if->dma_in_desc_addr, 1);
16248+ dev_if->out_desc_addr = dwc_otg_ep_alloc_desc_chain(&dev_if->dma_out_desc_addr, 1);
16249+
16250+ if(dev_if->setup_desc_addr[0] == 0
16251+ || dev_if->setup_desc_addr[1] == 0
16252+ || dev_if->in_desc_addr == 0
16253+ || dev_if->out_desc_addr == 0 ) {
16254+
16255+ if(dev_if->out_desc_addr)
16256+ dwc_otg_ep_free_desc_chain(dev_if->out_desc_addr, dev_if->dma_out_desc_addr, 1);
16257+ if(dev_if->in_desc_addr)
16258+ dwc_otg_ep_free_desc_chain(dev_if->in_desc_addr, dev_if->dma_in_desc_addr, 1);
16259+ if(dev_if->setup_desc_addr[1])
16260+ dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[1], dev_if->dma_setup_desc_addr[1], 1);
16261+ if(dev_if->setup_desc_addr[0])
16262+ dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[0], dev_if->dma_setup_desc_addr[0], 1);
16263+
16264+
16265+ dma_free_coherent(NULL, sizeof(*pcd->status_buf), pcd->status_buf, pcd->setup_pkt_dma_handle);
16266+ dma_free_coherent(NULL, sizeof(*pcd->setup_pkt), pcd->setup_pkt, pcd->setup_pkt_dma_handle);
16267+
16268+ free_irq(otg_dev->irq, pcd);
16269+ device_unregister(&pcd->gadget.dev);
16270+ kfree (pcd);
16271+
16272+ return -ENOMEM;
16273+ }
16274+ }
16275+ }
16276+ else {
16277+ pcd->setup_pkt = kmalloc (sizeof (*pcd->setup_pkt) * 5, GFP_KERNEL);
16278+ if (pcd->setup_pkt == 0) {
16279+ free_irq(otg_dev->irq, pcd);
16280+ device_unregister(&pcd->gadget.dev);
16281+ kfree (pcd);
16282+ return -ENOMEM;
16283+ }
16284+
16285+ pcd->status_buf = kmalloc (sizeof (uint16_t), GFP_KERNEL);
16286+ if (pcd->status_buf == 0) {
16287+ kfree(pcd->setup_pkt);
16288+ free_irq(otg_dev->irq, pcd);
16289+ device_unregister(&pcd->gadget.dev);
16290+ kfree (pcd);
16291+ return -ENOMEM;
16292+ }
16293+ }
16294+
16295+
16296+ /* Initialize tasklet */
16297+ start_xfer_tasklet.data = (unsigned long)pcd;
16298+ pcd->start_xfer_tasklet = &start_xfer_tasklet;
16299+
16300+ return 0;
16301+}
16302+
16303+/**
16304+ * Cleanup the PCD.
16305+ */
16306+void dwc_otg_pcd_remove(struct platform_device *pdev)
16307+{
16308+ dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev);
16309+ dwc_otg_pcd_t *pcd = otg_dev->pcd;
16310+ dwc_otg_dev_if_t* dev_if = GET_CORE_IF(pcd)->dev_if;
16311+
16312+ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pdev);
16313+
16314+ /*
16315+ * Free the IRQ
16316+ */
16317+ free_irq(otg_dev->irq, pcd);
16318+
16319+ /* start with the driver above us */
16320+ if (pcd->driver) {
16321+ /* should have been done already by driver model core */
16322+ DWC_WARN("driver '%s' is still registered\n",
16323+ pcd->driver->driver.name);
16324+ usb_gadget_unregister_driver(pcd->driver);
16325+ }
16326+ device_unregister(&pcd->gadget.dev);
16327+
16328+ if (GET_CORE_IF(pcd)->dma_enable) {
16329+ dma_free_coherent (NULL, sizeof (*pcd->setup_pkt) * 5, pcd->setup_pkt, pcd->setup_pkt_dma_handle);
16330+ dma_free_coherent (NULL, sizeof (uint16_t), pcd->status_buf, pcd->status_buf_dma_handle);
16331+ if (GET_CORE_IF(pcd)->dma_desc_enable) {
16332+ dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[0], dev_if->dma_setup_desc_addr[0], 1);
16333+ dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[1], dev_if->dma_setup_desc_addr[1], 1);
16334+ dwc_otg_ep_free_desc_chain(dev_if->in_desc_addr, dev_if->dma_in_desc_addr, 1);
16335+ dwc_otg_ep_free_desc_chain(dev_if->out_desc_addr, dev_if->dma_out_desc_addr, 1);
16336+ }
16337+ }
16338+ else {
16339+ kfree (pcd->setup_pkt);
16340+ kfree (pcd->status_buf);
16341+ }
16342+
16343+ kfree(pcd);
16344+ otg_dev->pcd = 0;
16345+}
16346+
16347+/**
16348+ * This function registers a gadget driver with the PCD.
16349+ *
16350+ * When a driver is successfully registered, it will receive control
16351+ * requests including set_configuration(), which enables non-control
16352+ * requests. then usb traffic follows until a disconnect is reported.
16353+ * then a host may connect again, or the driver might get unbound.
16354+ *
16355+ * @param driver The driver being registered
16356+ */
16357+int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
16358+ int (*bind)(struct usb_gadget *))
16359+{
16360+ int retval;
16361+
16362+ DWC_DEBUGPL(DBG_PCD, "registering gadget driver '%s'\n", driver->driver.name);
16363+
16364+ if (!driver || driver->max_speed == USB_SPEED_UNKNOWN ||
16365+ !bind ||
16366+ !driver->unbind ||
16367+ !driver->disconnect ||
16368+ !driver->setup) {
16369+ DWC_DEBUGPL(DBG_PCDV,"EINVAL\n");
16370+ return -EINVAL;
16371+ }
16372+ if (s_pcd == 0) {
16373+ DWC_DEBUGPL(DBG_PCDV,"ENODEV\n");
16374+ return -ENODEV;
16375+ }
16376+ if (s_pcd->driver != 0) {
16377+ DWC_DEBUGPL(DBG_PCDV,"EBUSY (%p)\n", s_pcd->driver);
16378+ return -EBUSY;
16379+ }
16380+
16381+ /* hook up the driver */
16382+ s_pcd->driver = driver;
16383+ s_pcd->gadget.dev.driver = &driver->driver;
16384+
16385+ DWC_DEBUGPL(DBG_PCD, "bind to driver %s\n", driver->driver.name);
16386+ retval = bind(&s_pcd->gadget);
16387+ if (retval) {
16388+ DWC_ERROR("bind to driver %s --> error %d\n",
16389+ driver->driver.name, retval);
16390+ s_pcd->driver = 0;
16391+ s_pcd->gadget.dev.driver = 0;
16392+ return retval;
16393+ }
16394+ DWC_DEBUGPL(DBG_ANY, "registered gadget driver '%s'\n",
16395+ driver->driver.name);
16396+ return 0;
16397+}
16398+
16399+EXPORT_SYMBOL(usb_gadget_probe_driver);
16400+
16401+/**
16402+ * This function unregisters a gadget driver
16403+ *
16404+ * @param driver The driver being unregistered
16405+ */
16406+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
16407+{
16408+ //DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, _driver);
16409+
16410+ if (s_pcd == 0) {
16411+ DWC_DEBUGPL(DBG_ANY, "%s Return(%d): s_pcd==0\n", __func__,
16412+ -ENODEV);
16413+ return -ENODEV;
16414+ }
16415+ if (driver == 0 || driver != s_pcd->driver) {
16416+ DWC_DEBUGPL(DBG_ANY, "%s Return(%d): driver?\n", __func__,
16417+ -EINVAL);
16418+ return -EINVAL;
16419+ }
16420+
16421+ driver->unbind(&s_pcd->gadget);
16422+ s_pcd->driver = 0;
16423+
16424+ DWC_DEBUGPL(DBG_ANY, "unregistered driver '%s'\n",
16425+ driver->driver.name);
16426+ return 0;
16427+}
16428+EXPORT_SYMBOL(usb_gadget_unregister_driver);
16429+
16430+#endif /* DWC_HOST_ONLY */
16431--- /dev/null
16432+++ b/drivers/usb/dwc/otg_pcd.h
16433@@ -0,0 +1,292 @@
16434+/* ==========================================================================
16435+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $
16436+ * $Revision: #36 $
16437+ * $Date: 2008/09/26 $
16438+ * $Change: 1103515 $
16439+ *
16440+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
16441+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
16442+ * otherwise expressly agreed to in writing between Synopsys and you.
16443+ *
16444+ * The Software IS NOT an item of Licensed Software or Licensed Product under
16445+ * any End User Software License Agreement or Agreement for Licensed Product
16446+ * with Synopsys or any supplement thereto. You are permitted to use and
16447+ * redistribute this Software in source and binary forms, with or without
16448+ * modification, provided that redistributions of source code must retain this
16449+ * notice. You may not view, use, disclose, copy or distribute this file or
16450+ * any information contained herein except pursuant to this license grant from
16451+ * Synopsys. If you do not agree with this notice, including the disclaimer
16452+ * below, then you are not authorized to use the Software.
16453+ *
16454+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
16455+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16456+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16457+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
16458+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
16459+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
16460+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
16461+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
16462+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
16463+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
16464+ * DAMAGE.
16465+ * ========================================================================== */
16466+#ifndef DWC_HOST_ONLY
16467+#if !defined(__DWC_PCD_H__)
16468+#define __DWC_PCD_H__
16469+
16470+#include <linux/types.h>
16471+#include <linux/list.h>
16472+#include <linux/errno.h>
16473+#include <linux/device.h>
16474+#include <linux/platform_device.h>
16475+
16476+#include <linux/usb/ch9.h>
16477+#include <linux/usb/gadget.h>
16478+
16479+#include <linux/interrupt.h>
16480+#include <linux/dma-mapping.h>
16481+
16482+struct dwc_otg_device;
16483+
16484+#include "otg_cil.h"
16485+
16486+/**
16487+ * @file
16488+ *
16489+ * This file contains the structures, constants, and interfaces for
16490+ * the Perpherial Contoller Driver (PCD).
16491+ *
16492+ * The Peripheral Controller Driver (PCD) for Linux will implement the
16493+ * Gadget API, so that the existing Gadget drivers can be used. For
16494+ * the Mass Storage Function driver the File-backed USB Storage Gadget
16495+ * (FBS) driver will be used. The FBS driver supports the
16496+ * Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only
16497+ * transports.
16498+ *
16499+ */
16500+
16501+/** Invalid DMA Address */
16502+#define DMA_ADDR_INVALID (~(dma_addr_t)0)
16503+/** Maxpacket size for EP0 */
16504+#define MAX_EP0_SIZE 64
16505+/** Maxpacket size for any EP */
16506+#define MAX_PACKET_SIZE 1024
16507+
16508+/** Max Transfer size for any EP */
16509+#define MAX_TRANSFER_SIZE 65535
16510+
16511+/** Max DMA Descriptor count for any EP */
16512+#define MAX_DMA_DESC_CNT 64
16513+
16514+/**
16515+ * Get the pointer to the core_if from the pcd pointer.
16516+ */
16517+#define GET_CORE_IF( _pcd ) (_pcd->otg_dev->core_if)
16518+
16519+/**
16520+ * States of EP0.
16521+ */
16522+typedef enum ep0_state
16523+{
16524+ EP0_DISCONNECT, /* no host */
16525+ EP0_IDLE,
16526+ EP0_IN_DATA_PHASE,
16527+ EP0_OUT_DATA_PHASE,
16528+ EP0_IN_STATUS_PHASE,
16529+ EP0_OUT_STATUS_PHASE,
16530+ EP0_STALL,
16531+} ep0state_e;
16532+
16533+/** Fordward declaration.*/
16534+struct dwc_otg_pcd;
16535+
16536+/** DWC_otg iso request structure.
16537+ *
16538+ */
16539+typedef struct usb_iso_request dwc_otg_pcd_iso_request_t;
16540+
16541+/** PCD EP structure.
16542+ * This structure describes an EP, there is an array of EPs in the PCD
16543+ * structure.
16544+ */
16545+typedef struct dwc_otg_pcd_ep
16546+{
16547+ /** USB EP data */
16548+ struct usb_ep ep;
16549+ /** USB EP Descriptor */
16550+ const struct usb_endpoint_descriptor *desc;
16551+
16552+ /** queue of dwc_otg_pcd_requests. */
16553+ struct list_head queue;
16554+ unsigned stopped : 1;
16555+ unsigned disabling : 1;
16556+ unsigned dma : 1;
16557+ unsigned queue_sof : 1;
16558+
16559+#ifdef DWC_EN_ISOC
16560+ /** DWC_otg Isochronous Transfer */
16561+ struct usb_iso_request* iso_req;
16562+#endif //DWC_EN_ISOC
16563+
16564+ /** DWC_otg ep data. */
16565+ dwc_ep_t dwc_ep;
16566+
16567+ /** Pointer to PCD */
16568+ struct dwc_otg_pcd *pcd;
16569+}dwc_otg_pcd_ep_t;
16570+
16571+
16572+
16573+/** DWC_otg PCD Structure.
16574+ * This structure encapsulates the data for the dwc_otg PCD.
16575+ */
16576+typedef struct dwc_otg_pcd
16577+{
16578+ /** USB gadget */
16579+ struct usb_gadget gadget;
16580+ /** USB gadget driver pointer*/
16581+ struct usb_gadget_driver *driver;
16582+ /** The DWC otg device pointer. */
16583+ struct dwc_otg_device *otg_dev;
16584+
16585+ /** State of EP0 */
16586+ ep0state_e ep0state;
16587+ /** EP0 Request is pending */
16588+ unsigned ep0_pending : 1;
16589+ /** Indicates when SET CONFIGURATION Request is in process */
16590+ unsigned request_config : 1;
16591+ /** The state of the Remote Wakeup Enable. */
16592+ unsigned remote_wakeup_enable : 1;
16593+ /** The state of the B-Device HNP Enable. */
16594+ unsigned b_hnp_enable : 1;
16595+ /** The state of A-Device HNP Support. */
16596+ unsigned a_hnp_support : 1;
16597+ /** The state of the A-Device Alt HNP support. */
16598+ unsigned a_alt_hnp_support : 1;
16599+ /** Count of pending Requests */
16600+ unsigned request_pending;
16601+
16602+ /** SETUP packet for EP0
16603+ * This structure is allocated as a DMA buffer on PCD initialization
16604+ * with enough space for up to 3 setup packets.
16605+ */
16606+ union
16607+ {
16608+ struct usb_ctrlrequest req;
16609+ uint32_t d32[2];
16610+ } *setup_pkt;
16611+
16612+ dma_addr_t setup_pkt_dma_handle;
16613+
16614+ /** 2-byte dma buffer used to return status from GET_STATUS */
16615+ uint16_t *status_buf;
16616+ dma_addr_t status_buf_dma_handle;
16617+
16618+ /** EP0 */
16619+ dwc_otg_pcd_ep_t ep0;
16620+
16621+ /** Array of IN EPs. */
16622+ dwc_otg_pcd_ep_t in_ep[ MAX_EPS_CHANNELS - 1];
16623+ /** Array of OUT EPs. */
16624+ dwc_otg_pcd_ep_t out_ep[ MAX_EPS_CHANNELS - 1];
16625+ /** number of valid EPs in the above array. */
16626+// unsigned num_eps : 4;
16627+ spinlock_t lock;
16628+ /** Timer for SRP. If it expires before SRP is successful
16629+ * clear the SRP. */
16630+ struct timer_list srp_timer;
16631+
16632+ /** Tasklet to defer starting of TEST mode transmissions until
16633+ * Status Phase has been completed.
16634+ */
16635+ struct tasklet_struct test_mode_tasklet;
16636+
16637+ /** Tasklet to delay starting of xfer in DMA mode */
16638+ struct tasklet_struct *start_xfer_tasklet;
16639+
16640+ /** The test mode to enter when the tasklet is executed. */
16641+ unsigned test_mode;
16642+
16643+} dwc_otg_pcd_t;
16644+
16645+
16646+/** DWC_otg request structure.
16647+ * This structure is a list of requests.
16648+ */
16649+typedef struct
16650+{
16651+ struct usb_request req; /**< USB Request. */
16652+ struct list_head queue; /**< queue of these requests. */
16653+} dwc_otg_pcd_request_t;
16654+
16655+
16656+extern int dwc_otg_pcd_init(struct platform_device *pdev);
16657+
16658+//extern void dwc_otg_pcd_remove( struct dwc_otg_device *_otg_dev );
16659+extern void dwc_otg_pcd_remove( struct platform_device *pdev );
16660+extern int32_t dwc_otg_pcd_handle_intr( dwc_otg_pcd_t *pcd );
16661+extern void dwc_otg_pcd_start_srp_timer(dwc_otg_pcd_t *pcd );
16662+
16663+extern void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t *pcd);
16664+extern void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t *pcd, int set);
16665+
16666+extern void dwc_otg_iso_buffer_done(dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_iso_request_t *req);
16667+extern void dwc_otg_request_done(dwc_otg_pcd_ep_t *_ep, dwc_otg_pcd_request_t *req,
16668+ int status);
16669+extern void dwc_otg_request_nuke(dwc_otg_pcd_ep_t *_ep);
16670+extern void dwc_otg_pcd_update_otg(dwc_otg_pcd_t *_pcd,
16671+ const unsigned reset);
16672+#ifndef VERBOSE
16673+#define VERIFY_PCD_DMA_ADDR(_addr_) BUG_ON(((_addr_)==DMA_ADDR_INVALID)||\
16674+ ((_addr_)==0)||\
16675+ ((_addr_)&0x3))
16676+#else
16677+#define VERIFY_PCD_DMA_ADDR(_addr_) {\
16678+ if(((_addr_)==DMA_ADDR_INVALID)||\
16679+ ((_addr_)==0)||\
16680+ ((_addr_)&0x3)) {\
16681+ printk("%s: Invalid DMA address "#_addr_"(%.8x)\n",__func__,_addr_);\
16682+ BUG();\
16683+ }\
16684+ }
16685+#endif
16686+
16687+
16688+static inline void ep_check_and_patch_dma_addr(dwc_otg_pcd_ep_t *ep){
16689+//void ep_check_and_patch_dma_addr(dwc_otg_pcd_ep_t *ep){
16690+ dwc_ep_t *dwc_ep=&ep->dwc_ep;
16691+
16692+DWC_DEBUGPL(DBG_PCDV,"%s: dwc_ep xfer_buf=%.8x, total_len=%d, dma_addr=%.8x\n",__func__,(u32)dwc_ep->xfer_buff,(dwc_ep->total_len),dwc_ep->dma_addr);
16693+ if (/*(core_if->dma_enable)&&*/(dwc_ep->dma_addr==DMA_ADDR_INVALID)) {
16694+ if((((u32)dwc_ep->xfer_buff)&0x3)==0){
16695+ dwc_ep->dma_addr=dma_map_single(NULL,(void *)(dwc_ep->start_xfer_buff),(dwc_ep->total_len), DMA_TO_DEVICE);
16696+DWC_DEBUGPL(DBG_PCDV," got dma_addr=%.8x\n",dwc_ep->dma_addr);
16697+ }else{
16698+DWC_DEBUGPL(DBG_PCDV," buf not aligned, use aligned_buf instead. xfer_buf=%.8x, total_len=%d, aligned_buf_size=%d\n",(u32)dwc_ep->xfer_buff,(dwc_ep->total_len),dwc_ep->aligned_buf_size);
16699+ if(dwc_ep->aligned_buf_size<dwc_ep->total_len){
16700+ if(dwc_ep->aligned_buf){
16701+//printk(" free buff dwc_ep aligned_buf_size=%d, aligned_buf(%.8x), aligned_dma_addr(%.8x));\n",dwc_ep->aligned_buf_size,dwc_ep->aligned_buf,dwc_ep->aligned_dma_addr);
16702+ //dma_free_coherent(NULL,dwc_ep->aligned_buf_size,dwc_ep->aligned_buf,dwc_ep->aligned_dma_addr);
16703+ kfree(dwc_ep->aligned_buf);
16704+ }
16705+ dwc_ep->aligned_buf_size=((1<<20)>(dwc_ep->total_len<<1))?(dwc_ep->total_len<<1):(1<<20);
16706+ //dwc_ep->aligned_buf = dma_alloc_coherent (NULL, dwc_ep->aligned_buf_size, &dwc_ep->aligned_dma_addr, GFP_KERNEL|GFP_DMA);
16707+ dwc_ep->aligned_buf=kmalloc(dwc_ep->aligned_buf_size,GFP_KERNEL|GFP_DMA|GFP_ATOMIC);
16708+ dwc_ep->aligned_dma_addr=dma_map_single(NULL,(void *)(dwc_ep->aligned_buf),(dwc_ep->aligned_buf_size),DMA_FROM_DEVICE);
16709+ if(!dwc_ep->aligned_buf){
16710+ DWC_ERROR("Cannot alloc required buffer!!\n");
16711+ BUG();
16712+ }
16713+DWC_DEBUGPL(DBG_PCDV," dwc_ep allocated aligned buf=%.8x, dma_addr=%.8x, size=%d(0x%x)\n", (u32)dwc_ep->aligned_buf, dwc_ep->aligned_dma_addr, dwc_ep->aligned_buf_size, dwc_ep->aligned_buf_size);
16714+ }
16715+ dwc_ep->dma_addr=dwc_ep->aligned_dma_addr;
16716+ if(dwc_ep->is_in) {
16717+ memcpy(dwc_ep->aligned_buf,dwc_ep->xfer_buff,dwc_ep->total_len);
16718+ dma_sync_single_for_device(NULL,dwc_ep->dma_addr,dwc_ep->total_len,DMA_TO_DEVICE);
16719+ }
16720+ }
16721+ }
16722+}
16723+
16724+#endif
16725+#endif /* DWC_HOST_ONLY */
16726--- /dev/null
16727+++ b/drivers/usb/dwc/otg_pcd_intr.c
16728@@ -0,0 +1,3682 @@
16729+/* ==========================================================================
16730+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_intr.c $
16731+ * $Revision: #83 $
16732+ * $Date: 2008/10/14 $
16733+ * $Change: 1115682 $
16734+ *
16735+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
16736+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
16737+ * otherwise expressly agreed to in writing between Synopsys and you.
16738+ *
16739+ * The Software IS NOT an item of Licensed Software or Licensed Product under
16740+ * any End User Software License Agreement or Agreement for Licensed Product
16741+ * with Synopsys or any supplement thereto. You are permitted to use and
16742+ * redistribute this Software in source and binary forms, with or without
16743+ * modification, provided that redistributions of source code must retain this
16744+ * notice. You may not view, use, disclose, copy or distribute this file or
16745+ * any information contained herein except pursuant to this license grant from
16746+ * Synopsys. If you do not agree with this notice, including the disclaimer
16747+ * below, then you are not authorized to use the Software.
16748+ *
16749+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
16750+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16751+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16752+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
16753+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
16754+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
16755+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
16756+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
16757+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
16758+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
16759+ * DAMAGE.
16760+ * ========================================================================== */
16761+#ifndef DWC_HOST_ONLY
16762+#include <linux/interrupt.h>
16763+#include <linux/dma-mapping.h>
16764+#include <linux/version.h>
16765+#include <linux/pci.h>
16766+
16767+#include "otg_driver.h"
16768+#include "otg_pcd.h"
16769+
16770+
16771+#define DEBUG_EP0
16772+
16773+
16774+/* request functions defined in "dwc_otg_pcd.c" */
16775+
16776+/** @file
16777+ * This file contains the implementation of the PCD Interrupt handlers.
16778+ *
16779+ * The PCD handles the device interrupts. Many conditions can cause a
16780+ * device interrupt. When an interrupt occurs, the device interrupt
16781+ * service routine determines the cause of the interrupt and
16782+ * dispatches handling to the appropriate function. These interrupt
16783+ * handling functions are described below.
16784+ * All interrupt registers are processed from LSB to MSB.
16785+ */
16786+
16787+
16788+/**
16789+ * This function prints the ep0 state for debug purposes.
16790+ */
16791+static inline void print_ep0_state(dwc_otg_pcd_t *pcd)
16792+{
16793+#ifdef DEBUG
16794+ char str[40];
16795+
16796+ switch (pcd->ep0state) {
16797+ case EP0_DISCONNECT:
16798+ strcpy(str, "EP0_DISCONNECT");
16799+ break;
16800+ case EP0_IDLE:
16801+ strcpy(str, "EP0_IDLE");
16802+ break;
16803+ case EP0_IN_DATA_PHASE:
16804+ strcpy(str, "EP0_IN_DATA_PHASE");
16805+ break;
16806+ case EP0_OUT_DATA_PHASE:
16807+ strcpy(str, "EP0_OUT_DATA_PHASE");
16808+ break;
16809+ case EP0_IN_STATUS_PHASE:
16810+ strcpy(str,"EP0_IN_STATUS_PHASE");
16811+ break;
16812+ case EP0_OUT_STATUS_PHASE:
16813+ strcpy(str,"EP0_OUT_STATUS_PHASE");
16814+ break;
16815+ case EP0_STALL:
16816+ strcpy(str,"EP0_STALL");
16817+ break;
16818+ default:
16819+ strcpy(str,"EP0_INVALID");
16820+ }
16821+
16822+ DWC_DEBUGPL(DBG_ANY, "%s(%d)\n", str, pcd->ep0state);
16823+#endif
16824+}
16825+
16826+/**
16827+ * This function returns pointer to in ep struct with number ep_num
16828+ */
16829+static inline dwc_otg_pcd_ep_t* get_in_ep(dwc_otg_pcd_t *pcd, uint32_t ep_num)
16830+{
16831+ int i;
16832+ int num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
16833+ if(ep_num == 0) {
16834+ return &pcd->ep0;
16835+ }
16836+ else {
16837+ for(i = 0; i < num_in_eps; ++i)
16838+ {
16839+ if(pcd->in_ep[i].dwc_ep.num == ep_num)
16840+ return &pcd->in_ep[i];
16841+ }
16842+ return 0;
16843+ }
16844+}
16845+/**
16846+ * This function returns pointer to out ep struct with number ep_num
16847+ */
16848+static inline dwc_otg_pcd_ep_t* get_out_ep(dwc_otg_pcd_t *pcd, uint32_t ep_num)
16849+{
16850+ int i;
16851+ int num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
16852+ if(ep_num == 0) {
16853+ return &pcd->ep0;
16854+ }
16855+ else {
16856+ for(i = 0; i < num_out_eps; ++i)
16857+ {
16858+ if(pcd->out_ep[i].dwc_ep.num == ep_num)
16859+ return &pcd->out_ep[i];
16860+ }
16861+ return 0;
16862+ }
16863+}
16864+/**
16865+ * This functions gets a pointer to an EP from the wIndex address
16866+ * value of the control request.
16867+ */
16868+static dwc_otg_pcd_ep_t *get_ep_by_addr (dwc_otg_pcd_t *pcd, u16 wIndex)
16869+{
16870+ dwc_otg_pcd_ep_t *ep;
16871+
16872+ if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
16873+ return &pcd->ep0;
16874+ list_for_each_entry(ep, &pcd->gadget.ep_list, ep.ep_list)
16875+ {
16876+ u8 bEndpointAddress;
16877+
16878+ if (!ep->desc)
16879+ continue;
16880+
16881+ bEndpointAddress = ep->desc->bEndpointAddress;
16882+ if((wIndex & (USB_DIR_IN | USB_ENDPOINT_NUMBER_MASK))
16883+ == (bEndpointAddress & (USB_DIR_IN | USB_ENDPOINT_NUMBER_MASK)))
16884+ return ep;
16885+ }
16886+ return NULL;
16887+}
16888+
16889+/**
16890+ * This function checks the EP request queue, if the queue is not
16891+ * empty the next request is started.
16892+ */
16893+void start_next_request(dwc_otg_pcd_ep_t *ep)
16894+{
16895+ dwc_otg_pcd_request_t *req = 0;
16896+ uint32_t max_transfer = GET_CORE_IF(ep->pcd)->core_params->max_transfer_size;
16897+ if (!list_empty(&ep->queue)) {
16898+ req = list_entry(ep->queue.next,
16899+ dwc_otg_pcd_request_t, queue);
16900+
16901+ /* Setup and start the Transfer */
16902+ ep->dwc_ep.dma_addr = req->req.dma;
16903+ ep->dwc_ep.start_xfer_buff = req->req.buf;
16904+ ep->dwc_ep.xfer_buff = req->req.buf;
16905+ ep->dwc_ep.sent_zlp = 0;
16906+ ep->dwc_ep.total_len = req->req.length;
16907+ ep->dwc_ep.xfer_len = 0;
16908+ ep->dwc_ep.xfer_count = 0;
16909+
16910+ if(max_transfer > MAX_TRANSFER_SIZE) {
16911+ ep->dwc_ep.maxxfer = max_transfer - (max_transfer % ep->dwc_ep.maxpacket);
16912+ } else {
16913+ ep->dwc_ep.maxxfer = max_transfer;
16914+ }
16915+
16916+ if(req->req.zero) {
16917+ if((ep->dwc_ep.total_len % ep->dwc_ep.maxpacket == 0)
16918+ && (ep->dwc_ep.total_len != 0)) {
16919+ ep->dwc_ep.sent_zlp = 1;
16920+ }
16921+
16922+ }
16923+ ep_check_and_patch_dma_addr(ep);
16924+ dwc_otg_ep_start_transfer(GET_CORE_IF(ep->pcd), &ep->dwc_ep);
16925+ }
16926+}
16927+
16928+/**
16929+ * This function handles the SOF Interrupts. At this time the SOF
16930+ * Interrupt is disabled.
16931+ */
16932+int32_t dwc_otg_pcd_handle_sof_intr(dwc_otg_pcd_t *pcd)
16933+{
16934+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
16935+
16936+ gintsts_data_t gintsts;
16937+
16938+ DWC_DEBUGPL(DBG_PCD, "SOF\n");
16939+
16940+ /* Clear interrupt */
16941+ gintsts.d32 = 0;
16942+ gintsts.b.sofintr = 1;
16943+ dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
16944+
16945+ return 1;
16946+}
16947+
16948+
16949+/**
16950+ * This function handles the Rx Status Queue Level Interrupt, which
16951+ * indicates that there is a least one packet in the Rx FIFO. The
16952+ * packets are moved from the FIFO to memory, where they will be
16953+ * processed when the Endpoint Interrupt Register indicates Transfer
16954+ * Complete or SETUP Phase Done.
16955+ *
16956+ * Repeat the following until the Rx Status Queue is empty:
16957+ * -# Read the Receive Status Pop Register (GRXSTSP) to get Packet
16958+ * info
16959+ * -# If Receive FIFO is empty then skip to step Clear the interrupt
16960+ * and exit
16961+ * -# If SETUP Packet call dwc_otg_read_setup_packet to copy the
16962+ * SETUP data to the buffer
16963+ * -# If OUT Data Packet call dwc_otg_read_packet to copy the data
16964+ * to the destination buffer
16965+ */
16966+int32_t dwc_otg_pcd_handle_rx_status_q_level_intr(dwc_otg_pcd_t *pcd)
16967+{
16968+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
16969+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
16970+ gintmsk_data_t gintmask = {.d32=0};
16971+ device_grxsts_data_t status;
16972+ dwc_otg_pcd_ep_t *ep;
16973+ gintsts_data_t gintsts;
16974+#ifdef DEBUG
16975+ static char *dpid_str[] ={ "D0", "D2", "D1", "MDATA" };
16976+#endif
16977+
16978+ //DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _pcd);
16979+ /* Disable the Rx Status Queue Level interrupt */
16980+ gintmask.b.rxstsqlvl= 1;
16981+ dwc_modify_reg32(&global_regs->gintmsk, gintmask.d32, 0);
16982+
16983+ /* Get the Status from the top of the FIFO */
16984+ status.d32 = dwc_read_reg32(&global_regs->grxstsp);
16985+
16986+ DWC_DEBUGPL(DBG_PCD, "EP:%d BCnt:%d DPID:%s "
16987+ "pktsts:%x Frame:%d(0x%0x)\n",
16988+ status.b.epnum, status.b.bcnt,
16989+ dpid_str[status.b.dpid],
16990+ status.b.pktsts, status.b.fn, status.b.fn);
16991+ /* Get pointer to EP structure */
16992+ ep = get_out_ep(pcd, status.b.epnum);
16993+
16994+ switch (status.b.pktsts) {
16995+ case DWC_DSTS_GOUT_NAK:
16996+ DWC_DEBUGPL(DBG_PCDV, "Global OUT NAK\n");
16997+ break;
16998+ case DWC_STS_DATA_UPDT:
16999+ DWC_DEBUGPL(DBG_PCDV, "OUT Data Packet\n");
17000+ if (status.b.bcnt && ep->dwc_ep.xfer_buff) {
17001+ /** @todo NGS Check for buffer overflow? */
17002+ dwc_otg_read_packet(core_if,
17003+ ep->dwc_ep.xfer_buff,
17004+ status.b.bcnt);
17005+ ep->dwc_ep.xfer_count += status.b.bcnt;
17006+ ep->dwc_ep.xfer_buff += status.b.bcnt;
17007+ }
17008+ break;
17009+ case DWC_STS_XFER_COMP:
17010+ DWC_DEBUGPL(DBG_PCDV, "OUT Complete\n");
17011+ break;
17012+ case DWC_DSTS_SETUP_COMP:
17013+#ifdef DEBUG_EP0
17014+ DWC_DEBUGPL(DBG_PCDV, "Setup Complete\n");
17015+#endif
17016+ break;
17017+case DWC_DSTS_SETUP_UPDT:
17018+ dwc_otg_read_setup_packet(core_if, pcd->setup_pkt->d32);
17019+#ifdef DEBUG_EP0
17020+ DWC_DEBUGPL(DBG_PCD,
17021+ "SETUP PKT: %02x.%02x v%04x i%04x l%04x\n",
17022+ pcd->setup_pkt->req.bRequestType,
17023+ pcd->setup_pkt->req.bRequest,
17024+ pcd->setup_pkt->req.wValue,
17025+ pcd->setup_pkt->req.wIndex,
17026+ pcd->setup_pkt->req.wLength);
17027+#endif
17028+ ep->dwc_ep.xfer_count += status.b.bcnt;
17029+ break;
17030+ default:
17031+ DWC_DEBUGPL(DBG_PCDV, "Invalid Packet Status (0x%0x)\n",
17032+ status.b.pktsts);
17033+ break;
17034+ }
17035+
17036+ /* Enable the Rx Status Queue Level interrupt */
17037+ dwc_modify_reg32(&global_regs->gintmsk, 0, gintmask.d32);
17038+ /* Clear interrupt */
17039+ gintsts.d32 = 0;
17040+ gintsts.b.rxstsqlvl = 1;
17041+ dwc_write_reg32 (&global_regs->gintsts, gintsts.d32);
17042+
17043+ //DWC_DEBUGPL(DBG_PCDV, "EXIT: %s\n", __func__);
17044+ return 1;
17045+}
17046+/**
17047+ * This function examines the Device IN Token Learning Queue to
17048+ * determine the EP number of the last IN token received. This
17049+ * implementation is for the Mass Storage device where there are only
17050+ * 2 IN EPs (Control-IN and BULK-IN).
17051+ *
17052+ * The EP numbers for the first six IN Tokens are in DTKNQR1 and there
17053+ * are 8 EP Numbers in each of the other possible DTKNQ Registers.
17054+ *
17055+ * @param core_if Programming view of DWC_otg controller.
17056+ *
17057+ */
17058+static inline int get_ep_of_last_in_token(dwc_otg_core_if_t *core_if)
17059+{
17060+ dwc_otg_device_global_regs_t *dev_global_regs =
17061+ core_if->dev_if->dev_global_regs;
17062+ const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;
17063+ /* Number of Token Queue Registers */
17064+ const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
17065+ dtknq1_data_t dtknqr1;
17066+ uint32_t in_tkn_epnums[4];
17067+ int ndx = 0;
17068+ int i = 0;
17069+ volatile uint32_t *addr = &dev_global_regs->dtknqr1;
17070+ int epnum = 0;
17071+
17072+ //DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);
17073+
17074+ /* Read the DTKNQ Registers */
17075+ for (i = 0; i < DTKNQ_REG_CNT; i++)
17076+ {
17077+ in_tkn_epnums[ i ] = dwc_read_reg32(addr);
17078+ DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i+1,
17079+ in_tkn_epnums[i]);
17080+ if (addr == &dev_global_regs->dvbusdis) {
17081+ addr = &dev_global_regs->dtknqr3_dthrctl;
17082+ }
17083+ else {
17084+ ++addr;
17085+ }
17086+ }
17087+
17088+ /* Copy the DTKNQR1 data to the bit field. */
17089+ dtknqr1.d32 = in_tkn_epnums[0];
17090+ /* Get the EP numbers */
17091+ in_tkn_epnums[0] = dtknqr1.b.epnums0_5;
17092+ ndx = dtknqr1.b.intknwptr - 1;
17093+
17094+ //DWC_DEBUGPL(DBG_PCDV,"ndx=%d\n",ndx);
17095+ if (ndx == -1) {
17096+ /** @todo Find a simpler way to calculate the max
17097+ * queue position.*/
17098+ int cnt = TOKEN_Q_DEPTH;
17099+ if (TOKEN_Q_DEPTH <= 6) {
17100+ cnt = TOKEN_Q_DEPTH - 1;
17101+ }
17102+ else if (TOKEN_Q_DEPTH <= 14) {
17103+ cnt = TOKEN_Q_DEPTH - 7;
17104+ }
17105+ else if (TOKEN_Q_DEPTH <= 22) {
17106+ cnt = TOKEN_Q_DEPTH - 15;
17107+ }
17108+ else {
17109+ cnt = TOKEN_Q_DEPTH - 23;
17110+ }
17111+ epnum = (in_tkn_epnums[ DTKNQ_REG_CNT - 1 ] >> (cnt * 4)) & 0xF;
17112+ }
17113+ else {
17114+ if (ndx <= 5) {
17115+ epnum = (in_tkn_epnums[0] >> (ndx * 4)) & 0xF;
17116+ }
17117+ else if (ndx <= 13) {
17118+ ndx -= 6;
17119+ epnum = (in_tkn_epnums[1] >> (ndx * 4)) & 0xF;
17120+ }
17121+ else if (ndx <= 21) {
17122+ ndx -= 14;
17123+ epnum = (in_tkn_epnums[2] >> (ndx * 4)) & 0xF;
17124+ }
17125+ else if (ndx <= 29) {
17126+ ndx -= 22;
17127+ epnum = (in_tkn_epnums[3] >> (ndx * 4)) & 0xF;
17128+ }
17129+ }
17130+ //DWC_DEBUGPL(DBG_PCD,"epnum=%d\n",epnum);
17131+ return epnum;
17132+}
17133+
17134+/**
17135+ * This interrupt occurs when the non-periodic Tx FIFO is half-empty.
17136+ * The active request is checked for the next packet to be loaded into
17137+ * the non-periodic Tx FIFO.
17138+ */
17139+int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr(dwc_otg_pcd_t *pcd)
17140+{
17141+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
17142+ dwc_otg_core_global_regs_t *global_regs =
17143+ core_if->core_global_regs;
17144+ dwc_otg_dev_in_ep_regs_t *ep_regs;
17145+ gnptxsts_data_t txstatus = {.d32 = 0};
17146+ gintsts_data_t gintsts;
17147+
17148+ int epnum = 0;
17149+ dwc_otg_pcd_ep_t *ep = 0;
17150+ uint32_t len = 0;
17151+ int dwords;
17152+
17153+ /* Get the epnum from the IN Token Learning Queue. */
17154+ epnum = get_ep_of_last_in_token(core_if);
17155+ ep = get_in_ep(pcd, epnum);
17156+
17157+ DWC_DEBUGPL(DBG_PCD, "NP TxFifo Empty: %s(%d) \n", ep->ep.name, epnum);
17158+ ep_regs = core_if->dev_if->in_ep_regs[epnum];
17159+
17160+ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
17161+ if (len > ep->dwc_ep.maxpacket) {
17162+ len = ep->dwc_ep.maxpacket;
17163+ }
17164+ dwords = (len + 3)/4;
17165+
17166+ /* While there is space in the queue and space in the FIFO and
17167+ * More data to tranfer, Write packets to the Tx FIFO */
17168+ txstatus.d32 = dwc_read_reg32(&global_regs->gnptxsts);
17169+ DWC_DEBUGPL(DBG_PCDV, "b4 GNPTXSTS=0x%08x\n",txstatus.d32);
17170+
17171+ while (txstatus.b.nptxqspcavail > 0 &&
17172+ txstatus.b.nptxfspcavail > dwords &&
17173+ ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len) {
17174+ /* Write the FIFO */
17175+ dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
17176+ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
17177+
17178+ if (len > ep->dwc_ep.maxpacket) {
17179+ len = ep->dwc_ep.maxpacket;
17180+ }
17181+
17182+ dwords = (len + 3)/4;
17183+ txstatus.d32 = dwc_read_reg32(&global_regs->gnptxsts);
17184+ DWC_DEBUGPL(DBG_PCDV,"GNPTXSTS=0x%08x\n",txstatus.d32);
17185+ }
17186+
17187+ DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n",
17188+ dwc_read_reg32(&global_regs->gnptxsts));
17189+
17190+ /* Clear interrupt */
17191+ gintsts.d32 = 0;
17192+ gintsts.b.nptxfempty = 1;
17193+ dwc_write_reg32 (&global_regs->gintsts, gintsts.d32);
17194+
17195+ return 1;
17196+}
17197+
17198+/**
17199+ * This function is called when dedicated Tx FIFO Empty interrupt occurs.
17200+ * The active request is checked for the next packet to be loaded into
17201+ * apropriate Tx FIFO.
17202+ */
17203+static int32_t write_empty_tx_fifo(dwc_otg_pcd_t *pcd, uint32_t epnum)
17204+{
17205+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
17206+ dwc_otg_dev_if_t* dev_if = core_if->dev_if;
17207+ dwc_otg_dev_in_ep_regs_t *ep_regs;
17208+ dtxfsts_data_t txstatus = {.d32 = 0};
17209+ dwc_otg_pcd_ep_t *ep = 0;
17210+ uint32_t len = 0;
17211+ int dwords;
17212+
17213+ ep = get_in_ep(pcd, epnum);
17214+
17215+ DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %s(%d) \n", ep->ep.name, epnum);
17216+
17217+ ep_regs = core_if->dev_if->in_ep_regs[epnum];
17218+
17219+ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
17220+
17221+ if (len > ep->dwc_ep.maxpacket) {
17222+ len = ep->dwc_ep.maxpacket;
17223+ }
17224+
17225+ dwords = (len + 3)/4;
17226+
17227+ /* While there is space in the queue and space in the FIFO and
17228+ * More data to tranfer, Write packets to the Tx FIFO */
17229+ txstatus.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts);
17230+ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n",epnum,txstatus.d32);
17231+
17232+ while (txstatus.b.txfspcavail > dwords &&
17233+ ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len &&
17234+ ep->dwc_ep.xfer_len != 0) {
17235+ /* Write the FIFO */
17236+ dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
17237+
17238+ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
17239+ if (len > ep->dwc_ep.maxpacket) {
17240+ len = ep->dwc_ep.maxpacket;
17241+ }
17242+
17243+ dwords = (len + 3)/4;
17244+ txstatus.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts);
17245+ DWC_DEBUGPL(DBG_PCDV,"dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
17246+ }
17247+
17248+ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n",epnum,dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts));
17249+
17250+ return 1;
17251+}
17252+
17253+/**
17254+ * This function is called when the Device is disconnected. It stops
17255+ * any active requests and informs the Gadget driver of the
17256+ * disconnect.
17257+ */
17258+void dwc_otg_pcd_stop(dwc_otg_pcd_t *pcd)
17259+{
17260+ int i, num_in_eps, num_out_eps;
17261+ dwc_otg_pcd_ep_t *ep;
17262+
17263+ gintmsk_data_t intr_mask = {.d32 = 0};
17264+
17265+ num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
17266+ num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
17267+
17268+ DWC_DEBUGPL(DBG_PCDV, "%s() \n", __func__);
17269+ /* don't disconnect drivers more than once */
17270+ if (pcd->ep0state == EP0_DISCONNECT) {
17271+ DWC_DEBUGPL(DBG_ANY, "%s() Already Disconnected\n", __func__);
17272+ return;
17273+ }
17274+ pcd->ep0state = EP0_DISCONNECT;
17275+
17276+ /* Reset the OTG state. */
17277+ dwc_otg_pcd_update_otg(pcd, 1);
17278+
17279+ /* Disable the NP Tx Fifo Empty Interrupt. */
17280+ intr_mask.b.nptxfempty = 1;
17281+ dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
17282+ intr_mask.d32, 0);
17283+
17284+ /* Flush the FIFOs */
17285+ /**@todo NGS Flush Periodic FIFOs */
17286+ dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), 0x10);
17287+ dwc_otg_flush_rx_fifo(GET_CORE_IF(pcd));
17288+
17289+ /* prevent new request submissions, kill any outstanding requests */
17290+ ep = &pcd->ep0;
17291+ dwc_otg_request_nuke(ep);
17292+ /* prevent new request submissions, kill any outstanding requests */
17293+ for (i = 0; i < num_in_eps; i++)
17294+ {
17295+ dwc_otg_pcd_ep_t *ep = &pcd->in_ep[i];
17296+ dwc_otg_request_nuke(ep);
17297+ }
17298+ /* prevent new request submissions, kill any outstanding requests */
17299+ for (i = 0; i < num_out_eps; i++)
17300+ {
17301+ dwc_otg_pcd_ep_t *ep = &pcd->out_ep[i];
17302+ dwc_otg_request_nuke(ep);
17303+ }
17304+
17305+ /* report disconnect; the driver is already quiesced */
17306+ if (pcd->driver && pcd->driver->disconnect) {
17307+ SPIN_UNLOCK(&pcd->lock);
17308+ pcd->driver->disconnect(&pcd->gadget);
17309+ SPIN_LOCK(&pcd->lock);
17310+ }
17311+}
17312+
17313+/**
17314+ * This interrupt indicates that ...
17315+ */
17316+int32_t dwc_otg_pcd_handle_i2c_intr(dwc_otg_pcd_t *pcd)
17317+{
17318+ gintmsk_data_t intr_mask = { .d32 = 0};
17319+ gintsts_data_t gintsts;
17320+
17321+ DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "i2cintr");
17322+ intr_mask.b.i2cintr = 1;
17323+ dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
17324+ intr_mask.d32, 0);
17325+
17326+ /* Clear interrupt */
17327+ gintsts.d32 = 0;
17328+ gintsts.b.i2cintr = 1;
17329+ dwc_write_reg32 (&GET_CORE_IF(pcd)->core_global_regs->gintsts,
17330+ gintsts.d32);
17331+ return 1;
17332+}
17333+
17334+
17335+/**
17336+ * This interrupt indicates that ...
17337+ */
17338+int32_t dwc_otg_pcd_handle_early_suspend_intr(dwc_otg_pcd_t *pcd)
17339+{
17340+ gintsts_data_t gintsts;
17341+#if defined(VERBOSE)
17342+ DWC_PRINT("Early Suspend Detected\n");
17343+#endif
17344+ /* Clear interrupt */
17345+ gintsts.d32 = 0;
17346+ gintsts.b.erlysuspend = 1;
17347+ dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
17348+ gintsts.d32);
17349+ return 1;
17350+}
17351+
17352+/**
17353+ * This function configures EPO to receive SETUP packets.
17354+ *
17355+ * @todo NGS: Update the comments from the HW FS.
17356+ *
17357+ * -# Program the following fields in the endpoint specific registers
17358+ * for Control OUT EP 0, in order to receive a setup packet
17359+ * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back
17360+ * setup packets)
17361+ * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back
17362+ * to back setup packets)
17363+ * - In DMA mode, DOEPDMA0 Register with a memory address to
17364+ * store any setup packets received
17365+ *
17366+ * @param core_if Programming view of DWC_otg controller.
17367+ * @param pcd Programming view of the PCD.
17368+ */
17369+static inline void ep0_out_start(dwc_otg_core_if_t *core_if, dwc_otg_pcd_t *pcd)
17370+{
17371+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
17372+ deptsiz0_data_t doeptsize0 = { .d32 = 0};
17373+ dwc_otg_dma_desc_t* dma_desc;
17374+ depctl_data_t doepctl = { .d32 = 0 };
17375+
17376+#ifdef VERBOSE
17377+ DWC_DEBUGPL(DBG_PCDV,"%s() doepctl0=%0x\n", __func__,
17378+ dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl));
17379+#endif
17380+
17381+ doeptsize0.b.supcnt = 3;
17382+ doeptsize0.b.pktcnt = 1;
17383+ doeptsize0.b.xfersize = 8*3;
17384+
17385+ if (core_if->dma_enable) {
17386+ if (!core_if->dma_desc_enable) {
17387+ /** put here as for Hermes mode deptisz register should not be written */
17388+ dwc_write_reg32(&dev_if->out_ep_regs[0]->doeptsiz,
17389+ doeptsize0.d32);
17390+
17391+ /** @todo dma needs to handle multiple setup packets (up to 3) */
17392+ VERIFY_PCD_DMA_ADDR(pcd->setup_pkt_dma_handle);
17393+
17394+ dwc_write_reg32(&dev_if->out_ep_regs[0]->doepdma,
17395+ pcd->setup_pkt_dma_handle);
17396+ } else {
17397+ dev_if->setup_desc_index = (dev_if->setup_desc_index + 1) & 1;
17398+ dma_desc = dev_if->setup_desc_addr[dev_if->setup_desc_index];
17399+
17400+ /** DMA Descriptor Setup */
17401+ dma_desc->status.b.bs = BS_HOST_BUSY;
17402+ dma_desc->status.b.l = 1;
17403+ dma_desc->status.b.ioc = 1;
17404+ dma_desc->status.b.bytes = pcd->ep0.dwc_ep.maxpacket;
17405+ dma_desc->buf = pcd->setup_pkt_dma_handle;
17406+ dma_desc->status.b.bs = BS_HOST_READY;
17407+
17408+ /** DOEPDMA0 Register write */
17409+ VERIFY_PCD_DMA_ADDR(dev_if->dma_setup_desc_addr[dev_if->setup_desc_index]);
17410+ dwc_write_reg32(&dev_if->out_ep_regs[0]->doepdma, dev_if->dma_setup_desc_addr[dev_if->setup_desc_index]);
17411+ }
17412+
17413+ } else {
17414+ /** put here as for Hermes mode deptisz register should not be written */
17415+ dwc_write_reg32(&dev_if->out_ep_regs[0]->doeptsiz,
17416+ doeptsize0.d32);
17417+ }
17418+
17419+ /** DOEPCTL0 Register write */
17420+ doepctl.b.epena = 1;
17421+ doepctl.b.cnak = 1;
17422+ dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
17423+
17424+#ifdef VERBOSE
17425+ DWC_DEBUGPL(DBG_PCDV,"doepctl0=%0x\n",
17426+ dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl));
17427+ DWC_DEBUGPL(DBG_PCDV,"diepctl0=%0x\n",
17428+ dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl));
17429+#endif
17430+}
17431+
17432+/**
17433+ * This interrupt occurs when a USB Reset is detected. When the USB
17434+ * Reset Interrupt occurs the device state is set to DEFAULT and the
17435+ * EP0 state is set to IDLE.
17436+ * -# Set the NAK bit for all OUT endpoints (DOEPCTLn.SNAK = 1)
17437+ * -# Unmask the following interrupt bits
17438+ * - DAINTMSK.INEP0 = 1 (Control 0 IN endpoint)
17439+ * - DAINTMSK.OUTEP0 = 1 (Control 0 OUT endpoint)
17440+ * - DOEPMSK.SETUP = 1
17441+ * - DOEPMSK.XferCompl = 1
17442+ * - DIEPMSK.XferCompl = 1
17443+ * - DIEPMSK.TimeOut = 1
17444+ * -# Program the following fields in the endpoint specific registers
17445+ * for Control OUT EP 0, in order to receive a setup packet
17446+ * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back
17447+ * setup packets)
17448+ * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back
17449+ * to back setup packets)
17450+ * - In DMA mode, DOEPDMA0 Register with a memory address to
17451+ * store any setup packets received
17452+ * At this point, all the required initialization, except for enabling
17453+ * the control 0 OUT endpoint is done, for receiving SETUP packets.
17454+ */
17455+int32_t dwc_otg_pcd_handle_usb_reset_intr(dwc_otg_pcd_t * pcd)
17456+{
17457+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
17458+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
17459+ depctl_data_t doepctl = { .d32 = 0};
17460+
17461+ daint_data_t daintmsk = { .d32 = 0};
17462+ doepmsk_data_t doepmsk = { .d32 = 0};
17463+ diepmsk_data_t diepmsk = { .d32 = 0};
17464+
17465+ dcfg_data_t dcfg = { .d32=0 };
17466+ grstctl_t resetctl = { .d32=0 };
17467+ dctl_data_t dctl = {.d32=0};
17468+ int i = 0;
17469+ gintsts_data_t gintsts;
17470+
17471+ DWC_PRINT("USB RESET\n");
17472+#ifdef DWC_EN_ISOC
17473+ for(i = 1;i < 16; ++i)
17474+ {
17475+ dwc_otg_pcd_ep_t *ep;
17476+ dwc_ep_t *dwc_ep;
17477+ ep = get_in_ep(pcd,i);
17478+ if(ep != 0){
17479+ dwc_ep = &ep->dwc_ep;
17480+ dwc_ep->next_frame = 0xffffffff;
17481+ }
17482+ }
17483+#endif /* DWC_EN_ISOC */
17484+
17485+ /* reset the HNP settings */
17486+ dwc_otg_pcd_update_otg(pcd, 1);
17487+
17488+ /* Clear the Remote Wakeup Signalling */
17489+ dctl.b.rmtwkupsig = 1;
17490+ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl,
17491+ dctl.d32, 0);
17492+
17493+ /* Set NAK for all OUT EPs */
17494+ doepctl.b.snak = 1;
17495+ for (i=0; i <= dev_if->num_out_eps; i++)
17496+ {
17497+ dwc_write_reg32(&dev_if->out_ep_regs[i]->doepctl,
17498+ doepctl.d32);
17499+ }
17500+
17501+ /* Flush the NP Tx FIFO */
17502+ dwc_otg_flush_tx_fifo(core_if, 0x10);
17503+ /* Flush the Learning Queue */
17504+ resetctl.b.intknqflsh = 1;
17505+ dwc_write_reg32(&core_if->core_global_regs->grstctl, resetctl.d32);
17506+
17507+ if(core_if->multiproc_int_enable) {
17508+ daintmsk.b.inep0 = 1;
17509+ daintmsk.b.outep0 = 1;
17510+ dwc_write_reg32(&dev_if->dev_global_regs->deachintmsk, daintmsk.d32);
17511+
17512+ doepmsk.b.setup = 1;
17513+ doepmsk.b.xfercompl = 1;
17514+ doepmsk.b.ahberr = 1;
17515+ doepmsk.b.epdisabled = 1;
17516+
17517+ if(core_if->dma_desc_enable) {
17518+ doepmsk.b.stsphsercvd = 1;
17519+ doepmsk.b.bna = 1;
17520+ }
17521+/*
17522+ doepmsk.b.babble = 1;
17523+ doepmsk.b.nyet = 1;
17524+
17525+ if(core_if->dma_enable) {
17526+ doepmsk.b.nak = 1;
17527+ }
17528+*/
17529+ dwc_write_reg32(&dev_if->dev_global_regs->doepeachintmsk[0], doepmsk.d32);
17530+
17531+ diepmsk.b.xfercompl = 1;
17532+ diepmsk.b.timeout = 1;
17533+ diepmsk.b.epdisabled = 1;
17534+ diepmsk.b.ahberr = 1;
17535+ diepmsk.b.intknepmis = 1;
17536+
17537+ if(core_if->dma_desc_enable) {
17538+ diepmsk.b.bna = 1;
17539+ }
17540+/*
17541+ if(core_if->dma_enable) {
17542+ diepmsk.b.nak = 1;
17543+ }
17544+*/
17545+ dwc_write_reg32(&dev_if->dev_global_regs->diepeachintmsk[0], diepmsk.d32);
17546+ } else{
17547+ daintmsk.b.inep0 = 1;
17548+ daintmsk.b.outep0 = 1;
17549+ dwc_write_reg32(&dev_if->dev_global_regs->daintmsk, daintmsk.d32);
17550+
17551+ doepmsk.b.setup = 1;
17552+ doepmsk.b.xfercompl = 1;
17553+ doepmsk.b.ahberr = 1;
17554+ doepmsk.b.epdisabled = 1;
17555+
17556+ if(core_if->dma_desc_enable) {
17557+ doepmsk.b.stsphsercvd = 1;
17558+ doepmsk.b.bna = 1;
17559+ }
17560+/*
17561+ doepmsk.b.babble = 1;
17562+ doepmsk.b.nyet = 1;
17563+ doepmsk.b.nak = 1;
17564+*/
17565+ dwc_write_reg32(&dev_if->dev_global_regs->doepmsk, doepmsk.d32);
17566+
17567+ diepmsk.b.xfercompl = 1;
17568+ diepmsk.b.timeout = 1;
17569+ diepmsk.b.epdisabled = 1;
17570+ diepmsk.b.ahberr = 1;
17571+ diepmsk.b.intknepmis = 1;
17572+
17573+ if(core_if->dma_desc_enable) {
17574+ diepmsk.b.bna = 1;
17575+ }
17576+
17577+// diepmsk.b.nak = 1;
17578+
17579+ dwc_write_reg32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32);
17580+ }
17581+
17582+ /* Reset Device Address */
17583+ dcfg.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dcfg);
17584+ dcfg.b.devaddr = 0;
17585+ dwc_write_reg32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
17586+
17587+ /* setup EP0 to receive SETUP packets */
17588+ ep0_out_start(core_if, pcd);
17589+
17590+ /* Clear interrupt */
17591+ gintsts.d32 = 0;
17592+ gintsts.b.usbreset = 1;
17593+ dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
17594+
17595+ return 1;
17596+}
17597+
17598+/**
17599+ * Get the device speed from the device status register and convert it
17600+ * to USB speed constant.
17601+ *
17602+ * @param core_if Programming view of DWC_otg controller.
17603+ */
17604+static int get_device_speed(dwc_otg_core_if_t *core_if)
17605+{
17606+ dsts_data_t dsts;
17607+ enum usb_device_speed speed = USB_SPEED_UNKNOWN;
17608+ dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
17609+
17610+ switch (dsts.b.enumspd) {
17611+ case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
17612+ speed = USB_SPEED_HIGH;
17613+ break;
17614+ case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
17615+ case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
17616+ speed = USB_SPEED_FULL;
17617+ break;
17618+
17619+ case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
17620+ speed = USB_SPEED_LOW;
17621+ break;
17622+ }
17623+
17624+ return speed;
17625+}
17626+
17627+/**
17628+ * Read the device status register and set the device speed in the
17629+ * data structure.
17630+ * Set up EP0 to receive SETUP packets by calling dwc_ep0_activate.
17631+ */
17632+int32_t dwc_otg_pcd_handle_enum_done_intr(dwc_otg_pcd_t *pcd)
17633+{
17634+ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
17635+ gintsts_data_t gintsts;
17636+ gusbcfg_data_t gusbcfg;
17637+ dwc_otg_core_global_regs_t *global_regs =
17638+ GET_CORE_IF(pcd)->core_global_regs;
17639+ uint8_t utmi16b, utmi8b;
17640+// DWC_DEBUGPL(DBG_PCD, "SPEED ENUM\n");
17641+ DWC_PRINT("SPEED ENUM\n");
17642+
17643+ if (GET_CORE_IF(pcd)->snpsid >= 0x4F54260A) {
17644+ utmi16b = 6;
17645+ utmi8b = 9;
17646+ } else {
17647+ utmi16b = 4;
17648+ utmi8b = 8;
17649+ }
17650+ dwc_otg_ep0_activate(GET_CORE_IF(pcd), &ep0->dwc_ep);
17651+
17652+#ifdef DEBUG_EP0
17653+ print_ep0_state(pcd);
17654+#endif
17655+
17656+ if (pcd->ep0state == EP0_DISCONNECT) {
17657+ pcd->ep0state = EP0_IDLE;
17658+ }
17659+ else if (pcd->ep0state == EP0_STALL) {
17660+ pcd->ep0state = EP0_IDLE;
17661+ }
17662+
17663+ pcd->ep0state = EP0_IDLE;
17664+
17665+ ep0->stopped = 0;
17666+
17667+ pcd->gadget.speed = get_device_speed(GET_CORE_IF(pcd));
17668+
17669+ /* Set USB turnaround time based on device speed and PHY interface. */
17670+ gusbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
17671+ if (pcd->gadget.speed == USB_SPEED_HIGH) {
17672+ if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == DWC_HWCFG2_HS_PHY_TYPE_ULPI) {
17673+ /* ULPI interface */
17674+ gusbcfg.b.usbtrdtim = 9;
17675+ }
17676+ if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == DWC_HWCFG2_HS_PHY_TYPE_UTMI) {
17677+ /* UTMI+ interface */
17678+ if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 0) {
17679+ gusbcfg.b.usbtrdtim = utmi8b;
17680+ }
17681+ else if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 1) {
17682+ gusbcfg.b.usbtrdtim = utmi16b;
17683+ }
17684+ else if (GET_CORE_IF(pcd)->core_params->phy_utmi_width == 8) {
17685+ gusbcfg.b.usbtrdtim = utmi8b;
17686+ }
17687+ else {
17688+ gusbcfg.b.usbtrdtim = utmi16b;
17689+ }
17690+ }
17691+ if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI) {
17692+ /* UTMI+ OR ULPI interface */
17693+ if (gusbcfg.b.ulpi_utmi_sel == 1) {
17694+ /* ULPI interface */
17695+ gusbcfg.b.usbtrdtim = 9;
17696+ }
17697+ else {
17698+ /* UTMI+ interface */
17699+ if (GET_CORE_IF(pcd)->core_params->phy_utmi_width == 16) {
17700+ gusbcfg.b.usbtrdtim = utmi16b;
17701+ }
17702+ else {
17703+ gusbcfg.b.usbtrdtim = utmi8b;
17704+ }
17705+ }
17706+ }
17707+ }
17708+ else {
17709+ /* Full or low speed */
17710+ gusbcfg.b.usbtrdtim = 9;
17711+ }
17712+ dwc_write_reg32(&global_regs->gusbcfg, gusbcfg.d32);
17713+
17714+ /* Clear interrupt */
17715+ gintsts.d32 = 0;
17716+ gintsts.b.enumdone = 1;
17717+ dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
17718+ gintsts.d32);
17719+ return 1;
17720+}
17721+
17722+/**
17723+ * This interrupt indicates that the ISO OUT Packet was dropped due to
17724+ * Rx FIFO full or Rx Status Queue Full. If this interrupt occurs
17725+ * read all the data from the Rx FIFO.
17726+ */
17727+int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(dwc_otg_pcd_t *pcd)
17728+{
17729+ gintmsk_data_t intr_mask = { .d32 = 0};
17730+ gintsts_data_t gintsts;
17731+
17732+ DWC_PRINT("INTERRUPT Handler not implemented for %s\n",
17733+ "ISOC Out Dropped");
17734+
17735+ intr_mask.b.isooutdrop = 1;
17736+ dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
17737+ intr_mask.d32, 0);
17738+
17739+ /* Clear interrupt */
17740+
17741+ gintsts.d32 = 0;
17742+ gintsts.b.isooutdrop = 1;
17743+ dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
17744+ gintsts.d32);
17745+
17746+ return 1;
17747+}
17748+
17749+/**
17750+ * This interrupt indicates the end of the portion of the micro-frame
17751+ * for periodic transactions. If there is a periodic transaction for
17752+ * the next frame, load the packets into the EP periodic Tx FIFO.
17753+ */
17754+int32_t dwc_otg_pcd_handle_end_periodic_frame_intr(dwc_otg_pcd_t *pcd)
17755+{
17756+ gintmsk_data_t intr_mask = { .d32 = 0};
17757+ gintsts_data_t gintsts;
17758+ DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "EOP");
17759+
17760+ intr_mask.b.eopframe = 1;
17761+ dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
17762+ intr_mask.d32, 0);
17763+
17764+ /* Clear interrupt */
17765+ gintsts.d32 = 0;
17766+ gintsts.b.eopframe = 1;
17767+ dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, gintsts.d32);
17768+
17769+ return 1;
17770+}
17771+
17772+/**
17773+ * This interrupt indicates that EP of the packet on the top of the
17774+ * non-periodic Tx FIFO does not match EP of the IN Token received.
17775+ *
17776+ * The "Device IN Token Queue" Registers are read to determine the
17777+ * order the IN Tokens have been received. The non-periodic Tx FIFO
17778+ * is flushed, so it can be reloaded in the order seen in the IN Token
17779+ * Queue.
17780+ */
17781+int32_t dwc_otg_pcd_handle_ep_mismatch_intr(dwc_otg_core_if_t *core_if)
17782+{
17783+ gintsts_data_t gintsts;
17784+ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
17785+
17786+ /* Clear interrupt */
17787+ gintsts.d32 = 0;
17788+ gintsts.b.epmismatch = 1;
17789+ dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32);
17790+
17791+ return 1;
17792+}
17793+
17794+/**
17795+ * This funcion stalls EP0.
17796+ */
17797+static inline void ep0_do_stall(dwc_otg_pcd_t *pcd, const int err_val)
17798+{
17799+ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
17800+ struct usb_ctrlrequest *ctrl = &pcd->setup_pkt->req;
17801+ DWC_WARN("req %02x.%02x protocol STALL; err %d\n",
17802+ ctrl->bRequestType, ctrl->bRequest, err_val);
17803+
17804+ ep0->dwc_ep.is_in = 1;
17805+ dwc_otg_ep_set_stall(pcd->otg_dev->core_if, &ep0->dwc_ep);
17806+ pcd->ep0.stopped = 1;
17807+ pcd->ep0state = EP0_IDLE;
17808+ ep0_out_start(GET_CORE_IF(pcd), pcd);
17809+}
17810+
17811+/**
17812+ * This functions delegates the setup command to the gadget driver.
17813+ */
17814+static inline void do_gadget_setup(dwc_otg_pcd_t *pcd,
17815+ struct usb_ctrlrequest * ctrl)
17816+{
17817+ int ret = 0;
17818+ if (pcd->driver && pcd->driver->setup) {
17819+ SPIN_UNLOCK(&pcd->lock);
17820+ ret = pcd->driver->setup(&pcd->gadget, ctrl);
17821+ SPIN_LOCK(&pcd->lock);
17822+ if (ret < 0) {
17823+ ep0_do_stall(pcd, ret);
17824+ }
17825+
17826+ /** @todo This is a g_file_storage gadget driver specific
17827+ * workaround: a DELAYED_STATUS result from the fsg_setup
17828+ * routine will result in the gadget queueing a EP0 IN status
17829+ * phase for a two-stage control transfer. Exactly the same as
17830+ * a SET_CONFIGURATION/SET_INTERFACE except that this is a class
17831+ * specific request. Need a generic way to know when the gadget
17832+ * driver will queue the status phase. Can we assume when we
17833+ * call the gadget driver setup() function that it will always
17834+ * queue and require the following flag? Need to look into
17835+ * this.
17836+ */
17837+
17838+ if (ret == 256 + 999) {
17839+ pcd->request_config = 1;
17840+ }
17841+ }
17842+}
17843+
17844+/**
17845+ * This function starts the Zero-Length Packet for the IN status phase
17846+ * of a 2 stage control transfer.
17847+ */
17848+static inline void do_setup_in_status_phase(dwc_otg_pcd_t *pcd)
17849+{
17850+ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
17851+ if (pcd->ep0state == EP0_STALL) {
17852+ return;
17853+ }
17854+
17855+ pcd->ep0state = EP0_IN_STATUS_PHASE;
17856+
17857+ /* Prepare for more SETUP Packets */
17858+ DWC_DEBUGPL(DBG_PCD, "EP0 IN ZLP\n");
17859+ ep0->dwc_ep.xfer_len = 0;
17860+ ep0->dwc_ep.xfer_count = 0;
17861+ ep0->dwc_ep.is_in = 1;
17862+ ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
17863+ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
17864+
17865+ /* Prepare for more SETUP Packets */
17866+// if(GET_CORE_IF(pcd)->dma_enable == 0) ep0_out_start(GET_CORE_IF(pcd), pcd);
17867+}
17868+
17869+/**
17870+ * This function starts the Zero-Length Packet for the OUT status phase
17871+ * of a 2 stage control transfer.
17872+ */
17873+static inline void do_setup_out_status_phase(dwc_otg_pcd_t *pcd)
17874+{
17875+ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
17876+ if (pcd->ep0state == EP0_STALL) {
17877+ DWC_DEBUGPL(DBG_PCD, "EP0 STALLED\n");
17878+ return;
17879+ }
17880+ pcd->ep0state = EP0_OUT_STATUS_PHASE;
17881+
17882+ DWC_DEBUGPL(DBG_PCD, "EP0 OUT ZLP\n");
17883+ ep0->dwc_ep.xfer_len = 0;
17884+ ep0->dwc_ep.xfer_count = 0;
17885+ ep0->dwc_ep.is_in = 0;
17886+ ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
17887+ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
17888+
17889+ /* Prepare for more SETUP Packets */
17890+ if(GET_CORE_IF(pcd)->dma_enable == 0) {
17891+ ep0_out_start(GET_CORE_IF(pcd), pcd);
17892+ }
17893+}
17894+
17895+/**
17896+ * Clear the EP halt (STALL) and if pending requests start the
17897+ * transfer.
17898+ */
17899+static inline void pcd_clear_halt(dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep)
17900+{
17901+ if(ep->dwc_ep.stall_clear_flag == 0)
17902+ dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
17903+
17904+ /* Reactive the EP */
17905+ dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
17906+ if (ep->stopped) {
17907+ ep->stopped = 0;
17908+ /* If there is a request in the EP queue start it */
17909+
17910+ /** @todo FIXME: this causes an EP mismatch in DMA mode.
17911+ * epmismatch not yet implemented. */
17912+
17913+ /*
17914+ * Above fixme is solved by implmenting a tasklet to call the
17915+ * start_next_request(), outside of interrupt context at some
17916+ * time after the current time, after a clear-halt setup packet.
17917+ * Still need to implement ep mismatch in the future if a gadget
17918+ * ever uses more than one endpoint at once
17919+ */
17920+ ep->queue_sof = 1;
17921+ tasklet_schedule (pcd->start_xfer_tasklet);
17922+ }
17923+ /* Start Control Status Phase */
17924+ do_setup_in_status_phase(pcd);
17925+}
17926+
17927+/**
17928+ * This function is called when the SET_FEATURE TEST_MODE Setup packet
17929+ * is sent from the host. The Device Control register is written with
17930+ * the Test Mode bits set to the specified Test Mode. This is done as
17931+ * a tasklet so that the "Status" phase of the control transfer
17932+ * completes before transmitting the TEST packets.
17933+ *
17934+ * @todo This has not been tested since the tasklet struct was put
17935+ * into the PCD struct!
17936+ *
17937+ */
17938+static void do_test_mode(unsigned long data)
17939+{
17940+ dctl_data_t dctl;
17941+ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *)data;
17942+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
17943+ int test_mode = pcd->test_mode;
17944+
17945+
17946+// DWC_WARN("%s() has not been tested since being rewritten!\n", __func__);
17947+
17948+ dctl.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dctl);
17949+ switch (test_mode) {
17950+ case 1: // TEST_J
17951+ dctl.b.tstctl = 1;
17952+ break;
17953+
17954+ case 2: // TEST_K
17955+ dctl.b.tstctl = 2;
17956+ break;
17957+
17958+ case 3: // TEST_SE0_NAK
17959+ dctl.b.tstctl = 3;
17960+ break;
17961+
17962+ case 4: // TEST_PACKET
17963+ dctl.b.tstctl = 4;
17964+ break;
17965+
17966+ case 5: // TEST_FORCE_ENABLE
17967+ dctl.b.tstctl = 5;
17968+ break;
17969+ }
17970+ dwc_write_reg32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
17971+}
17972+
17973+/**
17974+ * This function process the GET_STATUS Setup Commands.
17975+ */
17976+static inline void do_get_status(dwc_otg_pcd_t *pcd)
17977+{
17978+ struct usb_ctrlrequest ctrl = pcd->setup_pkt->req;
17979+ dwc_otg_pcd_ep_t *ep;
17980+ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
17981+ uint16_t *status = pcd->status_buf;
17982+
17983+#ifdef DEBUG_EP0
17984+ DWC_DEBUGPL(DBG_PCD,
17985+ "GET_STATUS %02x.%02x v%04x i%04x l%04x\n",
17986+ ctrl.bRequestType, ctrl.bRequest,
17987+ ctrl.wValue, ctrl.wIndex, ctrl.wLength);
17988+#endif
17989+
17990+ switch (ctrl.bRequestType & USB_RECIP_MASK) {
17991+ case USB_RECIP_DEVICE:
17992+ *status = 0x1; /* Self powered */
17993+ *status |= pcd->remote_wakeup_enable << 1;
17994+ break;
17995+
17996+ case USB_RECIP_INTERFACE:
17997+ *status = 0;
17998+ break;
17999+
18000+ case USB_RECIP_ENDPOINT:
18001+ ep = get_ep_by_addr(pcd, ctrl.wIndex);
18002+ if (ep == 0 || ctrl.wLength > 2) {
18003+ ep0_do_stall(pcd, -EOPNOTSUPP);
18004+ return;
18005+ }
18006+ /** @todo check for EP stall */
18007+ *status = ep->stopped;
18008+ break;
18009+ }
18010+ pcd->ep0_pending = 1;
18011+ ep0->dwc_ep.start_xfer_buff = (uint8_t *)status;
18012+ ep0->dwc_ep.xfer_buff = (uint8_t *)status;
18013+ ep0->dwc_ep.dma_addr = pcd->status_buf_dma_handle;
18014+ ep0->dwc_ep.xfer_len = 2;
18015+ ep0->dwc_ep.xfer_count = 0;
18016+ ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;
18017+ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
18018+}
18019+/**
18020+ * This function process the SET_FEATURE Setup Commands.
18021+ */
18022+static inline void do_set_feature(dwc_otg_pcd_t *pcd)
18023+{
18024+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
18025+ dwc_otg_core_global_regs_t *global_regs =
18026+ core_if->core_global_regs;
18027+ struct usb_ctrlrequest ctrl = pcd->setup_pkt->req;
18028+ dwc_otg_pcd_ep_t *ep = 0;
18029+ int32_t otg_cap_param = core_if->core_params->otg_cap;
18030+ gotgctl_data_t gotgctl = { .d32 = 0 };
18031+
18032+ DWC_DEBUGPL(DBG_PCD, "SET_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
18033+ ctrl.bRequestType, ctrl.bRequest,
18034+ ctrl.wValue, ctrl.wIndex, ctrl.wLength);
18035+ DWC_DEBUGPL(DBG_PCD,"otg_cap=%d\n", otg_cap_param);
18036+
18037+
18038+ switch (ctrl.bRequestType & USB_RECIP_MASK) {
18039+ case USB_RECIP_DEVICE:
18040+ switch (ctrl.wValue) {
18041+ case USB_DEVICE_REMOTE_WAKEUP:
18042+ pcd->remote_wakeup_enable = 1;
18043+ break;
18044+
18045+ case USB_DEVICE_TEST_MODE:
18046+ /* Setup the Test Mode tasklet to do the Test
18047+ * Packet generation after the SETUP Status
18048+ * phase has completed. */
18049+
18050+ /** @todo This has not been tested since the
18051+ * tasklet struct was put into the PCD
18052+ * struct! */
18053+ pcd->test_mode_tasklet.next = 0;
18054+ pcd->test_mode_tasklet.state = 0;
18055+ atomic_set(&pcd->test_mode_tasklet.count, 0);
18056+ pcd->test_mode_tasklet.func = do_test_mode;
18057+ pcd->test_mode_tasklet.data = (unsigned long)pcd;
18058+ pcd->test_mode = ctrl.wIndex >> 8;
18059+ tasklet_schedule(&pcd->test_mode_tasklet);
18060+ break;
18061+
18062+ case USB_DEVICE_B_HNP_ENABLE:
18063+ DWC_DEBUGPL(DBG_PCDV, "SET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
18064+
18065+ /* dev may initiate HNP */
18066+ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
18067+ pcd->b_hnp_enable = 1;
18068+ dwc_otg_pcd_update_otg(pcd, 0);
18069+ DWC_DEBUGPL(DBG_PCD, "Request B HNP\n");
18070+ /**@todo Is the gotgctl.devhnpen cleared
18071+ * by a USB Reset? */
18072+ gotgctl.b.devhnpen = 1;
18073+ gotgctl.b.hnpreq = 1;
18074+ dwc_write_reg32(&global_regs->gotgctl, gotgctl.d32);
18075+ }
18076+ else {
18077+ ep0_do_stall(pcd, -EOPNOTSUPP);
18078+ }
18079+ break;
18080+
18081+ case USB_DEVICE_A_HNP_SUPPORT:
18082+ /* RH port supports HNP */
18083+ DWC_DEBUGPL(DBG_PCDV, "SET_FEATURE: USB_DEVICE_A_HNP_SUPPORT\n");
18084+ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
18085+ pcd->a_hnp_support = 1;
18086+ dwc_otg_pcd_update_otg(pcd, 0);
18087+ }
18088+ else {
18089+ ep0_do_stall(pcd, -EOPNOTSUPP);
18090+ }
18091+ break;
18092+
18093+ case USB_DEVICE_A_ALT_HNP_SUPPORT:
18094+ /* other RH port does */
18095+ DWC_DEBUGPL(DBG_PCDV, "SET_FEATURE: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
18096+ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
18097+ pcd->a_alt_hnp_support = 1;
18098+ dwc_otg_pcd_update_otg(pcd, 0);
18099+ }
18100+ else {
18101+ ep0_do_stall(pcd, -EOPNOTSUPP);
18102+ }
18103+ break;
18104+ }
18105+ do_setup_in_status_phase(pcd);
18106+ break;
18107+
18108+ case USB_RECIP_INTERFACE:
18109+ do_gadget_setup(pcd, &ctrl);
18110+ break;
18111+
18112+ case USB_RECIP_ENDPOINT:
18113+ if (ctrl.wValue == USB_ENDPOINT_HALT) {
18114+ ep = get_ep_by_addr(pcd, ctrl.wIndex);
18115+ if (ep == 0) {
18116+ ep0_do_stall(pcd, -EOPNOTSUPP);
18117+ return;
18118+ }
18119+ ep->stopped = 1;
18120+ dwc_otg_ep_set_stall(core_if, &ep->dwc_ep);
18121+ }
18122+ do_setup_in_status_phase(pcd);
18123+ break;
18124+ }
18125+}
18126+
18127+/**
18128+ * This function process the CLEAR_FEATURE Setup Commands.
18129+ */
18130+static inline void do_clear_feature(dwc_otg_pcd_t *pcd)
18131+{
18132+ struct usb_ctrlrequest ctrl = pcd->setup_pkt->req;
18133+ dwc_otg_pcd_ep_t *ep = 0;
18134+
18135+ DWC_DEBUGPL(DBG_PCD,
18136+ "CLEAR_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
18137+ ctrl.bRequestType, ctrl.bRequest,
18138+ ctrl.wValue, ctrl.wIndex, ctrl.wLength);
18139+
18140+ switch (ctrl.bRequestType & USB_RECIP_MASK) {
18141+ case USB_RECIP_DEVICE:
18142+ switch (ctrl.wValue) {
18143+ case USB_DEVICE_REMOTE_WAKEUP:
18144+ pcd->remote_wakeup_enable = 0;
18145+ break;
18146+
18147+ case USB_DEVICE_TEST_MODE:
18148+ /** @todo Add CLEAR_FEATURE for TEST modes. */
18149+ break;
18150+ }
18151+ do_setup_in_status_phase(pcd);
18152+ break;
18153+
18154+ case USB_RECIP_ENDPOINT:
18155+ ep = get_ep_by_addr(pcd, ctrl.wIndex);
18156+ if (ep == 0) {
18157+ ep0_do_stall(pcd, -EOPNOTSUPP);
18158+ return;
18159+ }
18160+
18161+ pcd_clear_halt(pcd, ep);
18162+
18163+ break;
18164+ }
18165+}
18166+
18167+/**
18168+ * This function process the SET_ADDRESS Setup Commands.
18169+ */
18170+static inline void do_set_address(dwc_otg_pcd_t *pcd)
18171+{
18172+ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
18173+ struct usb_ctrlrequest ctrl = pcd->setup_pkt->req;
18174+
18175+ if (ctrl.bRequestType == USB_RECIP_DEVICE) {
18176+ dcfg_data_t dcfg = {.d32=0};
18177+
18178+#ifdef DEBUG_EP0
18179+// DWC_DEBUGPL(DBG_PCDV, "SET_ADDRESS:%d\n", ctrl.wValue);
18180+#endif
18181+ dcfg.b.devaddr = ctrl.wValue;
18182+ dwc_modify_reg32(&dev_if->dev_global_regs->dcfg, 0, dcfg.d32);
18183+ do_setup_in_status_phase(pcd);
18184+ }
18185+}
18186+
18187+/**
18188+ * This function processes SETUP commands. In Linux, the USB Command
18189+ * processing is done in two places - the first being the PCD and the
18190+ * second in the Gadget Driver (for example, the File-Backed Storage
18191+ * Gadget Driver).
18192+ *
18193+ * <table>
18194+ * <tr><td>Command </td><td>Driver </td><td>Description</td></tr>
18195+ *
18196+ * <tr><td>GET_STATUS </td><td>PCD </td><td>Command is processed as
18197+ * defined in chapter 9 of the USB 2.0 Specification chapter 9
18198+ * </td></tr>
18199+ *
18200+ * <tr><td>CLEAR_FEATURE </td><td>PCD </td><td>The Device and Endpoint
18201+ * requests are the ENDPOINT_HALT feature is procesed, all others the
18202+ * interface requests are ignored.</td></tr>
18203+ *
18204+ * <tr><td>SET_FEATURE </td><td>PCD </td><td>The Device and Endpoint
18205+ * requests are processed by the PCD. Interface requests are passed
18206+ * to the Gadget Driver.</td></tr>
18207+ *
18208+ * <tr><td>SET_ADDRESS </td><td>PCD </td><td>Program the DCFG reg,
18209+ * with device address received </td></tr>
18210+ *
18211+ * <tr><td>GET_DESCRIPTOR </td><td>Gadget Driver </td><td>Return the
18212+ * requested descriptor</td></tr>
18213+ *
18214+ * <tr><td>SET_DESCRIPTOR </td><td>Gadget Driver </td><td>Optional -
18215+ * not implemented by any of the existing Gadget Drivers.</td></tr>
18216+ *
18217+ * <tr><td>SET_CONFIGURATION </td><td>Gadget Driver </td><td>Disable
18218+ * all EPs and enable EPs for new configuration.</td></tr>
18219+ *
18220+ * <tr><td>GET_CONFIGURATION </td><td>Gadget Driver </td><td>Return
18221+ * the current configuration</td></tr>
18222+ *
18223+ * <tr><td>SET_INTERFACE </td><td>Gadget Driver </td><td>Disable all
18224+ * EPs and enable EPs for new configuration.</td></tr>
18225+ *
18226+ * <tr><td>GET_INTERFACE </td><td>Gadget Driver </td><td>Return the
18227+ * current interface.</td></tr>
18228+ *
18229+ * <tr><td>SYNC_FRAME </td><td>PCD </td><td>Display debug
18230+ * message.</td></tr>
18231+ * </table>
18232+ *
18233+ * When the SETUP Phase Done interrupt occurs, the PCD SETUP commands are
18234+ * processed by pcd_setup. Calling the Function Driver's setup function from
18235+ * pcd_setup processes the gadget SETUP commands.
18236+ */
18237+static inline void pcd_setup(dwc_otg_pcd_t *pcd)
18238+{
18239+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
18240+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
18241+ struct usb_ctrlrequest ctrl = pcd->setup_pkt->req;
18242+ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
18243+
18244+ deptsiz0_data_t doeptsize0 = { .d32 = 0};
18245+
18246+#ifdef DEBUG_EP0
18247+ DWC_DEBUGPL(DBG_PCD, "SETUP %02x.%02x v%04x i%04x l%04x\n",
18248+ ctrl.bRequestType, ctrl.bRequest,
18249+ ctrl.wValue, ctrl.wIndex, ctrl.wLength);
18250+#endif
18251+
18252+ doeptsize0.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doeptsiz);
18253+
18254+ /** @todo handle > 1 setup packet , assert error for now */
18255+
18256+ if (core_if->dma_enable && core_if->dma_desc_enable == 0 && (doeptsize0.b.supcnt < 2)) {
18257+ DWC_ERROR ("\n\n----------- CANNOT handle > 1 setup packet in DMA mode\n\n");
18258+ }
18259+
18260+ /* Clean up the request queue */
18261+ dwc_otg_request_nuke(ep0);
18262+ ep0->stopped = 0;
18263+
18264+ if (ctrl.bRequestType & USB_DIR_IN) {
18265+ ep0->dwc_ep.is_in = 1;
18266+ pcd->ep0state = EP0_IN_DATA_PHASE;
18267+ }
18268+ else {
18269+ ep0->dwc_ep.is_in = 0;
18270+ pcd->ep0state = EP0_OUT_DATA_PHASE;
18271+ }
18272+
18273+ if(ctrl.wLength == 0) {
18274+ ep0->dwc_ep.is_in = 1;
18275+ pcd->ep0state = EP0_IN_STATUS_PHASE;
18276+ }
18277+
18278+ if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD) {
18279+ /* handle non-standard (class/vendor) requests in the gadget driver */
18280+ do_gadget_setup(pcd, &ctrl);
18281+ return;
18282+ }
18283+
18284+ /** @todo NGS: Handle bad setup packet? */
18285+
18286+///////////////////////////////////////////
18287+//// --- Standard Request handling --- ////
18288+
18289+ switch (ctrl.bRequest) {
18290+ case USB_REQ_GET_STATUS:
18291+ do_get_status(pcd);
18292+ break;
18293+
18294+ case USB_REQ_CLEAR_FEATURE:
18295+ do_clear_feature(pcd);
18296+ break;
18297+
18298+ case USB_REQ_SET_FEATURE:
18299+ do_set_feature(pcd);
18300+ break;
18301+
18302+ case USB_REQ_SET_ADDRESS:
18303+ do_set_address(pcd);
18304+ break;
18305+
18306+ case USB_REQ_SET_INTERFACE:
18307+ case USB_REQ_SET_CONFIGURATION:
18308+// _pcd->request_config = 1; /* Configuration changed */
18309+ do_gadget_setup(pcd, &ctrl);
18310+ break;
18311+
18312+ case USB_REQ_SYNCH_FRAME:
18313+ do_gadget_setup(pcd, &ctrl);
18314+ break;
18315+
18316+ default:
18317+ /* Call the Gadget Driver's setup functions */
18318+ do_gadget_setup(pcd, &ctrl);
18319+ break;
18320+ }
18321+}
18322+
18323+/**
18324+ * This function completes the ep0 control transfer.
18325+ */
18326+static int32_t ep0_complete_request(dwc_otg_pcd_ep_t *ep)
18327+{
18328+ dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
18329+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
18330+ dwc_otg_dev_in_ep_regs_t *in_ep_regs =
18331+ dev_if->in_ep_regs[ep->dwc_ep.num];
18332+#ifdef DEBUG_EP0
18333+ dwc_otg_dev_out_ep_regs_t *out_ep_regs =
18334+ dev_if->out_ep_regs[ep->dwc_ep.num];
18335+#endif
18336+ deptsiz0_data_t deptsiz;
18337+ desc_sts_data_t desc_sts;
18338+ dwc_otg_pcd_request_t *req;
18339+ int is_last = 0;
18340+ dwc_otg_pcd_t *pcd = ep->pcd;
18341+
18342+ //DWC_DEBUGPL(DBG_PCDV, "%s() %s\n", __func__, _ep->ep.name);
18343+
18344+ if (pcd->ep0_pending && list_empty(&ep->queue)) {
18345+ if (ep->dwc_ep.is_in) {
18346+#ifdef DEBUG_EP0
18347+ DWC_DEBUGPL(DBG_PCDV, "Do setup OUT status phase\n");
18348+#endif
18349+ do_setup_out_status_phase(pcd);
18350+ }
18351+ else {
18352+#ifdef DEBUG_EP0
18353+ DWC_DEBUGPL(DBG_PCDV, "Do setup IN status phase\n");
18354+#endif
18355+ do_setup_in_status_phase(pcd);
18356+ }
18357+ pcd->ep0_pending = 0;
18358+ return 1;
18359+ }
18360+
18361+ if (list_empty(&ep->queue)) {
18362+ return 0;
18363+ }
18364+ req = list_entry(ep->queue.next, dwc_otg_pcd_request_t, queue);
18365+
18366+
18367+ if (pcd->ep0state == EP0_OUT_STATUS_PHASE || pcd->ep0state == EP0_IN_STATUS_PHASE) {
18368+ is_last = 1;
18369+ }
18370+ else if (ep->dwc_ep.is_in) {
18371+ deptsiz.d32 = dwc_read_reg32(&in_ep_regs->dieptsiz);
18372+ if(core_if->dma_desc_enable != 0)
18373+ desc_sts.d32 = readl(dev_if->in_desc_addr);
18374+#ifdef DEBUG_EP0
18375+ DWC_DEBUGPL(DBG_PCDV, "%s len=%d xfersize=%d pktcnt=%d\n",
18376+ ep->ep.name, ep->dwc_ep.xfer_len,
18377+ deptsiz.b.xfersize, deptsiz.b.pktcnt);
18378+#endif
18379+
18380+ if (((core_if->dma_desc_enable == 0) && (deptsiz.b.xfersize == 0)) ||
18381+ ((core_if->dma_desc_enable != 0) && (desc_sts.b.bytes == 0))) {
18382+ req->req.actual = ep->dwc_ep.xfer_count;
18383+ /* Is a Zero Len Packet needed? */
18384+ if (req->req.zero) {
18385+#ifdef DEBUG_EP0
18386+ DWC_DEBUGPL(DBG_PCD, "Setup Rx ZLP\n");
18387+#endif
18388+ req->req.zero = 0;
18389+ }
18390+ do_setup_out_status_phase(pcd);
18391+ }
18392+ }
18393+ else {
18394+ /* ep0-OUT */
18395+#ifdef DEBUG_EP0
18396+ deptsiz.d32 = dwc_read_reg32(&out_ep_regs->doeptsiz);
18397+ DWC_DEBUGPL(DBG_PCDV, "%s len=%d xsize=%d pktcnt=%d\n",
18398+ ep->ep.name, ep->dwc_ep.xfer_len,
18399+ deptsiz.b.xfersize,
18400+ deptsiz.b.pktcnt);
18401+#endif
18402+ req->req.actual = ep->dwc_ep.xfer_count;
18403+ /* Is a Zero Len Packet needed? */
18404+ if (req->req.zero) {
18405+#ifdef DEBUG_EP0
18406+ DWC_DEBUGPL(DBG_PCDV, "Setup Tx ZLP\n");
18407+#endif
18408+ req->req.zero = 0;
18409+ }
18410+ if(core_if->dma_desc_enable == 0)
18411+ do_setup_in_status_phase(pcd);
18412+ }
18413+
18414+ /* Complete the request */
18415+ if (is_last) {
18416+ dwc_otg_request_done(ep, req, 0);
18417+ ep->dwc_ep.start_xfer_buff = 0;
18418+ ep->dwc_ep.xfer_buff = 0;
18419+ ep->dwc_ep.xfer_len = 0;
18420+ return 1;
18421+ }
18422+ return 0;
18423+}
18424+
18425+inline void aligned_buf_patch_on_buf_dma_oep_completion(dwc_otg_pcd_ep_t *ep, uint32_t byte_count)
18426+{
18427+ dwc_ep_t *dwc_ep = &ep->dwc_ep;
18428+ if(byte_count && dwc_ep->aligned_buf &&
18429+ dwc_ep->dma_addr>=dwc_ep->aligned_dma_addr &&
18430+ dwc_ep->dma_addr<=(dwc_ep->aligned_dma_addr+dwc_ep->aligned_buf_size))\
18431+ {
18432+ //aligned buf used, apply complete patch
18433+ u32 offset=(dwc_ep->dma_addr-dwc_ep->aligned_dma_addr);
18434+ memcpy(dwc_ep->start_xfer_buff+offset, dwc_ep->aligned_buf+offset, byte_count);
18435+ }
18436+}
18437+
18438+/**
18439+ * This function completes the request for the EP. If there are
18440+ * additional requests for the EP in the queue they will be started.
18441+ */
18442+static void complete_ep(dwc_otg_pcd_ep_t *ep)
18443+{
18444+ dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
18445+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
18446+ dwc_otg_dev_in_ep_regs_t *in_ep_regs =
18447+ dev_if->in_ep_regs[ep->dwc_ep.num];
18448+ deptsiz_data_t deptsiz;
18449+ desc_sts_data_t desc_sts;
18450+ dwc_otg_pcd_request_t *req = 0;
18451+ dwc_otg_dma_desc_t* dma_desc;
18452+ uint32_t byte_count = 0;
18453+ int is_last = 0;
18454+ int i;
18455+
18456+ DWC_DEBUGPL(DBG_PCDV,"%s() %s-%s\n", __func__, ep->ep.name,
18457+ (ep->dwc_ep.is_in?"IN":"OUT"));
18458+
18459+ /* Get any pending requests */
18460+ if (!list_empty(&ep->queue)) {
18461+ req = list_entry(ep->queue.next, dwc_otg_pcd_request_t,
18462+ queue);
18463+ if (!req) {
18464+ printk("complete_ep 0x%p, req = NULL!\n", ep);
18465+ return;
18466+ }
18467+ }
18468+ else {
18469+ printk("complete_ep 0x%p, ep->queue empty!\n", ep);
18470+ return;
18471+ }
18472+ DWC_DEBUGPL(DBG_PCD, "Requests %d\n", ep->pcd->request_pending);
18473+
18474+ if (ep->dwc_ep.is_in) {
18475+ deptsiz.d32 = dwc_read_reg32(&in_ep_regs->dieptsiz);
18476+
18477+ if (core_if->dma_enable) {
18478+ //dma_unmap_single(NULL,ep->dwc_ep.dma_addr,ep->dwc_ep.xfer_count,DMA_NONE);
18479+ if(core_if->dma_desc_enable == 0) {
18480+ //dma_unmap_single(NULL,ep->dwc_ep.dma_addr,ep->dwc_ep.xfer_count,DMA_NONE);
18481+ if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) {
18482+ byte_count = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
18483+DWC_DEBUGPL(DBG_PCDV,"byte_count(%.8x) = (ep->dwc_ep.xfer_len(%.8x) - ep->dwc_ep.xfer_count(%.8x)\n", byte_count ,ep->dwc_ep.xfer_len , ep->dwc_ep.xfer_count );
18484+
18485+ ep->dwc_ep.xfer_buff += byte_count;
18486+ ep->dwc_ep.dma_addr += byte_count;
18487+ ep->dwc_ep.xfer_count += byte_count;
18488+
18489+ DWC_DEBUGPL(DBG_PCDV, "%s len=%d xfersize=%d pktcnt=%d\n",
18490+ ep->ep.name, ep->dwc_ep.xfer_len,
18491+ deptsiz.b.xfersize, deptsiz.b.pktcnt);
18492+
18493+ if(ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
18494+ //dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
18495+printk("Warning: transfer ended, but specified len is not accomplished!! ep->total_len=%.x,ep->dwc_ep.sent_zlp=%d, byte_count(%.8x) = (ep->dwc_ep.xfer_len(%.8x) - ep->dwc_ep.xfer_count(%.8x) - deptsiz.b.xfersize(%.8x)\n", ep->dwc_ep.total_len, ep->dwc_ep.sent_zlp, byte_count ,ep->dwc_ep.xfer_len , ep->dwc_ep.xfer_count , deptsiz.b.xfersize);
18496+ } else if(ep->dwc_ep.sent_zlp) {
18497+ /*
18498+ * This fragment of code should initiate 0
18499+ * length trasfer in case if it is queued
18500+ * a trasfer with size divisible to EPs max
18501+ * packet size and with usb_request zero field
18502+ * is set, which means that after data is transfered,
18503+ * it is also should be transfered
18504+ * a 0 length packet at the end. For Slave and
18505+ * Buffer DMA modes in this case SW has
18506+ * to initiate 2 transfers one with transfer size,
18507+ * and the second with 0 size. For Desriptor
18508+ * DMA mode SW is able to initiate a transfer,
18509+ * which will handle all the packets including
18510+ * the last 0 legth.
18511+ */
18512+ ep->dwc_ep.sent_zlp = 0;
18513+ dwc_otg_ep_start_zl_transfer(core_if, &ep->dwc_ep);
18514+ } else {
18515+ is_last = 1;
18516+ }
18517+ } else {
18518+ DWC_WARN("Incomplete transfer (%s-%s [siz=%d pkt=%d])\n",
18519+ ep->ep.name, (ep->dwc_ep.is_in?"IN":"OUT"),
18520+ deptsiz.b.xfersize, deptsiz.b.pktcnt);
18521+ }
18522+ } else {
18523+
18524+ dma_desc = ep->dwc_ep.desc_addr;
18525+ byte_count = 0;
18526+ ep->dwc_ep.sent_zlp = 0;
18527+
18528+ for(i = 0; i < ep->dwc_ep.desc_cnt; ++i) {
18529+ desc_sts.d32 = readl(dma_desc);
18530+ byte_count += desc_sts.b.bytes;
18531+ dma_desc++;
18532+ }
18533+
18534+ if(byte_count == 0) {
18535+ ep->dwc_ep.xfer_count = ep->dwc_ep.total_len;
18536+ is_last = 1;
18537+ } else {
18538+ DWC_WARN("Incomplete transfer\n");
18539+ }
18540+ }
18541+ } else {
18542+ if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) {
18543+ /* Check if the whole transfer was completed,
18544+ * if no, setup transfer for next portion of data
18545+ */
18546+ DWC_DEBUGPL(DBG_PCDV, "%s len=%d xfersize=%d pktcnt=%d\n",
18547+ ep->ep.name, ep->dwc_ep.xfer_len,
18548+ deptsiz.b.xfersize, deptsiz.b.pktcnt);
18549+ if(ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
18550+ //dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
18551+printk("Warning: transfer ended, but specified len is not accomplished!! ep->total_len=%.x,ep->dwc_ep.sent_zlp=%d, ep->dwc_ep.xfer_len(%.8x) \n", ep->dwc_ep.total_len, ep->dwc_ep.sent_zlp, ep->dwc_ep.xfer_len );
18552+ } else if(ep->dwc_ep.sent_zlp) {
18553+ /*
18554+ * This fragment of code should initiate 0
18555+ * length trasfer in case if it is queued
18556+ * a trasfer with size divisible to EPs max
18557+ * packet size and with usb_request zero field
18558+ * is set, which means that after data is transfered,
18559+ * it is also should be transfered
18560+ * a 0 length packet at the end. For Slave and
18561+ * Buffer DMA modes in this case SW has
18562+ * to initiate 2 transfers one with transfer size,
18563+ * and the second with 0 size. For Desriptor
18564+ * DMA mode SW is able to initiate a transfer,
18565+ * which will handle all the packets including
18566+ * the last 0 legth.
18567+ */
18568+ ep->dwc_ep.sent_zlp = 0;
18569+ dwc_otg_ep_start_zl_transfer(core_if, &ep->dwc_ep);
18570+ } else {
18571+ is_last = 1;
18572+ }
18573+ }
18574+ else {
18575+ DWC_WARN("Incomplete transfer (%s-%s [siz=%d pkt=%d])\n",
18576+ ep->ep.name, (ep->dwc_ep.is_in?"IN":"OUT"),
18577+ deptsiz.b.xfersize, deptsiz.b.pktcnt);
18578+ }
18579+ }
18580+ } else {
18581+ dwc_otg_dev_out_ep_regs_t *out_ep_regs =
18582+ dev_if->out_ep_regs[ep->dwc_ep.num];
18583+ desc_sts.d32 = 0;
18584+ if(core_if->dma_enable) {
18585+ //dma_unmap_single(NULL,ep->dwc_ep.dma_addr,ep->dwc_ep.xfer_count,DMA_FROM_DEVICE);
18586+ if(core_if->dma_desc_enable) {
18587+ DWC_WARN("\n\n%s: we need a cache invalidation here!!\n\n",__func__);
18588+ dma_desc = ep->dwc_ep.desc_addr;
18589+ byte_count = 0;
18590+ ep->dwc_ep.sent_zlp = 0;
18591+ for(i = 0; i < ep->dwc_ep.desc_cnt; ++i) {
18592+ desc_sts.d32 = readl(dma_desc);
18593+ byte_count += desc_sts.b.bytes;
18594+ dma_desc++;
18595+ }
18596+
18597+ ep->dwc_ep.xfer_count = ep->dwc_ep.total_len
18598+ - byte_count + ((4 - (ep->dwc_ep.total_len & 0x3)) & 0x3);
18599+
18600+ //todo: invalidate cache & aligned buf patch on completion
18601+ //
18602+
18603+ is_last = 1;
18604+ } else {
18605+ deptsiz.d32 = 0;
18606+ deptsiz.d32 = dwc_read_reg32(&out_ep_regs->doeptsiz);
18607+
18608+ byte_count = (ep->dwc_ep.xfer_len -
18609+ ep->dwc_ep.xfer_count - deptsiz.b.xfersize);
18610+
18611+// dma_sync_single_for_device(NULL,ep->dwc_ep.dma_addr,byte_count,DMA_FROM_DEVICE);
18612+
18613+DWC_DEBUGPL(DBG_PCDV,"ep->total_len=%.x,ep->dwc_ep.sent_zlp=%d, byte_count(%.8x) = (ep->dwc_ep.xfer_len(%.8x) - ep->dwc_ep.xfer_count(%.8x) - deptsiz.b.xfersize(%.8x)\n", ep->dwc_ep.total_len, ep->dwc_ep.sent_zlp, byte_count ,ep->dwc_ep.xfer_len , ep->dwc_ep.xfer_count , deptsiz.b.xfersize);
18614+ //todo: invalidate cache & aligned buf patch on completion
18615+ dma_sync_single_for_device(NULL,ep->dwc_ep.dma_addr,byte_count,DMA_FROM_DEVICE);
18616+ aligned_buf_patch_on_buf_dma_oep_completion(ep,byte_count);
18617+
18618+ ep->dwc_ep.xfer_buff += byte_count;
18619+ ep->dwc_ep.dma_addr += byte_count;
18620+ ep->dwc_ep.xfer_count += byte_count;
18621+
18622+ /* Check if the whole transfer was completed,
18623+ * if no, setup transfer for next portion of data
18624+ */
18625+ if(ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
18626+ //dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
18627+printk("Warning: transfer ended, but specified len is not accomplished!! ep->total_len=%.x,ep->dwc_ep.sent_zlp=%d, byte_count(%.8x) = (ep->dwc_ep.xfer_len(%.8x) - ep->dwc_ep.xfer_count(%.8x) - deptsiz.b.xfersize(%.8x)\n", ep->dwc_ep.total_len, ep->dwc_ep.sent_zlp, byte_count ,ep->dwc_ep.xfer_len , ep->dwc_ep.xfer_count , deptsiz.b.xfersize);
18628+ }
18629+ else if(ep->dwc_ep.sent_zlp) {
18630+ /*
18631+ * This fragment of code should initiate 0
18632+ * length trasfer in case if it is queued
18633+ * a trasfer with size divisible to EPs max
18634+ * packet size and with usb_request zero field
18635+ * is set, which means that after data is transfered,
18636+ * it is also should be transfered
18637+ * a 0 length packet at the end. For Slave and
18638+ * Buffer DMA modes in this case SW has
18639+ * to initiate 2 transfers one with transfer size,
18640+ * and the second with 0 size. For Desriptor
18641+ * DMA mode SW is able to initiate a transfer,
18642+ * which will handle all the packets including
18643+ * the last 0 legth.
18644+ */
18645+ ep->dwc_ep.sent_zlp = 0;
18646+ dwc_otg_ep_start_zl_transfer(core_if, &ep->dwc_ep);
18647+ } else {
18648+ is_last = 1;
18649+ }
18650+ }
18651+ } else {
18652+ /* Check if the whole transfer was completed,
18653+ * if no, setup transfer for next portion of data
18654+ */
18655+ if(ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
18656+ //dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
18657+printk("Warning: transfer ended, but specified len is not accomplished!! ep->total_len=%.x,ep->dwc_ep.sent_zlp=%d, ep->dwc_ep.xfer_len(%.8x) \n", ep->dwc_ep.total_len, ep->dwc_ep.sent_zlp, ep->dwc_ep.xfer_len );
18658+ }
18659+ else if(ep->dwc_ep.sent_zlp) {
18660+ /*
18661+ * This fragment of code should initiate 0
18662+ * length trasfer in case if it is queued
18663+ * a trasfer with size divisible to EPs max
18664+ * packet size and with usb_request zero field
18665+ * is set, which means that after data is transfered,
18666+ * it is also should be transfered
18667+ * a 0 length packet at the end. For Slave and
18668+ * Buffer DMA modes in this case SW has
18669+ * to initiate 2 transfers one with transfer size,
18670+ * and the second with 0 size. For Desriptor
18671+ * DMA mode SW is able to initiate a transfer,
18672+ * which will handle all the packets including
18673+ * the last 0 legth.
18674+ */
18675+ ep->dwc_ep.sent_zlp = 0;
18676+ dwc_otg_ep_start_zl_transfer(core_if, &ep->dwc_ep);
18677+ } else {
18678+ is_last = 1;
18679+ }
18680+ }
18681+
18682+#ifdef DEBUG
18683+
18684+ DWC_DEBUGPL(DBG_PCDV, "addr %p, %s len=%d cnt=%d xsize=%d pktcnt=%d\n",
18685+ &out_ep_regs->doeptsiz, ep->ep.name, ep->dwc_ep.xfer_len,
18686+ ep->dwc_ep.xfer_count,
18687+ deptsiz.b.xfersize,
18688+ deptsiz.b.pktcnt);
18689+#endif
18690+ }
18691+
18692+ /* Complete the request */
18693+ if (is_last) {
18694+ req->req.actual = ep->dwc_ep.xfer_count;
18695+
18696+ dwc_otg_request_done(ep, req, 0);
18697+
18698+ ep->dwc_ep.start_xfer_buff = 0;
18699+ ep->dwc_ep.xfer_buff = 0;
18700+ ep->dwc_ep.xfer_len = 0;
18701+
18702+ /* If there is a request in the queue start it.*/
18703+ start_next_request(ep);
18704+ }
18705+}
18706+
18707+
18708+#ifdef DWC_EN_ISOC
18709+
18710+/**
18711+ * This function BNA interrupt for Isochronous EPs
18712+ *
18713+ */
18714+static void dwc_otg_pcd_handle_iso_bna(dwc_otg_pcd_ep_t *ep)
18715+{
18716+ dwc_ep_t *dwc_ep = &ep->dwc_ep;
18717+ volatile uint32_t *addr;
18718+ depctl_data_t depctl = {.d32 = 0};
18719+ dwc_otg_pcd_t *pcd = ep->pcd;
18720+ dwc_otg_dma_desc_t *dma_desc;
18721+ int i;
18722+
18723+ dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * (dwc_ep->proc_buf_num);
18724+
18725+ if(dwc_ep->is_in) {
18726+ desc_sts_data_t sts = {.d32 = 0};
18727+ for(i = 0;i < dwc_ep->desc_cnt; ++i, ++dma_desc)
18728+ {
18729+ sts.d32 = readl(&dma_desc->status);
18730+ sts.b_iso_in.bs = BS_HOST_READY;
18731+ writel(sts.d32,&dma_desc->status);
18732+ }
18733+ }
18734+ else {
18735+ desc_sts_data_t sts = {.d32 = 0};
18736+ for(i = 0;i < dwc_ep->desc_cnt; ++i, ++dma_desc)
18737+ {
18738+ sts.d32 = readl(&dma_desc->status);
18739+ sts.b_iso_out.bs = BS_HOST_READY;
18740+ writel(sts.d32,&dma_desc->status);
18741+ }
18742+ }
18743+
18744+ if(dwc_ep->is_in == 0){
18745+ addr = &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
18746+ }
18747+ else{
18748+ addr = &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
18749+ }
18750+ depctl.b.epena = 1;
18751+ dwc_modify_reg32(addr,depctl.d32,depctl.d32);
18752+}
18753+
18754+/**
18755+ * This function sets latest iso packet information(non-PTI mode)
18756+ *
18757+ * @param core_if Programming view of DWC_otg controller.
18758+ * @param ep The EP to start the transfer on.
18759+ *
18760+ */
18761+void set_current_pkt_info(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
18762+{
18763+ deptsiz_data_t deptsiz = { .d32 = 0 };
18764+ dma_addr_t dma_addr;
18765+ uint32_t offset;
18766+
18767+ if(ep->proc_buf_num)
18768+ dma_addr = ep->dma_addr1;
18769+ else
18770+ dma_addr = ep->dma_addr0;
18771+
18772+ if(ep->is_in) {
18773+ deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz);
18774+ offset = ep->data_per_frame;
18775+ } else {
18776+ deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doeptsiz);
18777+ offset = ep->data_per_frame + (0x4 & (0x4 - (ep->data_per_frame & 0x3)));
18778+ }
18779+
18780+ if(!deptsiz.b.xfersize) {
18781+ ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
18782+ ep->pkt_info[ep->cur_pkt].offset = ep->cur_pkt_dma_addr - dma_addr;
18783+ ep->pkt_info[ep->cur_pkt].status = 0;
18784+ } else {
18785+ ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
18786+ ep->pkt_info[ep->cur_pkt].offset = ep->cur_pkt_dma_addr - dma_addr;
18787+ ep->pkt_info[ep->cur_pkt].status = -ENODATA;
18788+ }
18789+ ep->cur_pkt_addr += offset;
18790+ ep->cur_pkt_dma_addr += offset;
18791+ ep->cur_pkt++;
18792+}
18793+
18794+/**
18795+ * This function sets latest iso packet information(DDMA mode)
18796+ *
18797+ * @param core_if Programming view of DWC_otg controller.
18798+ * @param dwc_ep The EP to start the transfer on.
18799+ *
18800+ */
18801+static void set_ddma_iso_pkts_info(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
18802+{
18803+ dwc_otg_dma_desc_t* dma_desc;
18804+ desc_sts_data_t sts = {.d32 = 0};
18805+ iso_pkt_info_t *iso_packet;
18806+ uint32_t data_per_desc;
18807+ uint32_t offset;
18808+ int i, j;
18809+
18810+ iso_packet = dwc_ep->pkt_info;
18811+
18812+ /** Reinit closed DMA Descriptors*/
18813+ /** ISO OUT EP */
18814+ if(dwc_ep->is_in == 0) {
18815+ dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
18816+ offset = 0;
18817+
18818+ for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm)
18819+ {
18820+ for(j = 0; j < dwc_ep->pkt_per_frm; ++j)
18821+ {
18822+ data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
18823+ dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
18824+ data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
18825+
18826+ sts.d32 = readl(&dma_desc->status);
18827+
18828+ /* Write status in iso_packet_decsriptor */
18829+ iso_packet->status = sts.b_iso_out.rxsts + (sts.b_iso_out.bs^BS_DMA_DONE);
18830+ if(iso_packet->status) {
18831+ iso_packet->status = -ENODATA;
18832+ }
18833+
18834+ /* Received data length */
18835+ if(!sts.b_iso_out.rxbytes){
18836+ iso_packet->length = data_per_desc - sts.b_iso_out.rxbytes;
18837+ } else {
18838+ iso_packet->length = data_per_desc - sts.b_iso_out.rxbytes +
18839+ (4 - dwc_ep->data_per_frame % 4);
18840+ }
18841+
18842+ iso_packet->offset = offset;
18843+
18844+ offset += data_per_desc;
18845+ dma_desc ++;
18846+ iso_packet ++;
18847+ }
18848+ }
18849+
18850+ for(j = 0; j < dwc_ep->pkt_per_frm - 1; ++j)
18851+ {
18852+ data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
18853+ dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
18854+ data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
18855+
18856+ sts.d32 = readl(&dma_desc->status);
18857+
18858+ /* Write status in iso_packet_decsriptor */
18859+ iso_packet->status = sts.b_iso_out.rxsts + (sts.b_iso_out.bs^BS_DMA_DONE);
18860+ if(iso_packet->status) {
18861+ iso_packet->status = -ENODATA;
18862+ }
18863+
18864+ /* Received data length */
18865+ iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
18866+
18867+ iso_packet->offset = offset;
18868+
18869+ offset += data_per_desc;
18870+ iso_packet++;
18871+ dma_desc++;
18872+ }
18873+
18874+ sts.d32 = readl(&dma_desc->status);
18875+
18876+ /* Write status in iso_packet_decsriptor */
18877+ iso_packet->status = sts.b_iso_out.rxsts + (sts.b_iso_out.bs^BS_DMA_DONE);
18878+ if(iso_packet->status) {
18879+ iso_packet->status = -ENODATA;
18880+ }
18881+ /* Received data length */
18882+ if(!sts.b_iso_out.rxbytes){
18883+ iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
18884+ } else {
18885+ iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_out.rxbytes +
18886+ (4 - dwc_ep->data_per_frame % 4);
18887+ }
18888+
18889+ iso_packet->offset = offset;
18890+ }
18891+ else /** ISO IN EP */
18892+ {
18893+ dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
18894+
18895+ for(i = 0; i < dwc_ep->desc_cnt - 1; i++)
18896+ {
18897+ sts.d32 = readl(&dma_desc->status);
18898+
18899+ /* Write status in iso packet descriptor */
18900+ iso_packet->status = sts.b_iso_in.txsts + (sts.b_iso_in.bs^BS_DMA_DONE);
18901+ if(iso_packet->status != 0) {
18902+ iso_packet->status = -ENODATA;
18903+
18904+ }
18905+ /* Bytes has been transfered */
18906+ iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
18907+
18908+ dma_desc ++;
18909+ iso_packet++;
18910+ }
18911+
18912+ sts.d32 = readl(&dma_desc->status);
18913+ while(sts.b_iso_in.bs == BS_DMA_BUSY) {
18914+ sts.d32 = readl(&dma_desc->status);
18915+ }
18916+
18917+ /* Write status in iso packet descriptor ??? do be done with ERROR codes*/
18918+ iso_packet->status = sts.b_iso_in.txsts + (sts.b_iso_in.bs^BS_DMA_DONE);
18919+ if(iso_packet->status != 0) {
18920+ iso_packet->status = -ENODATA;
18921+ }
18922+
18923+ /* Bytes has been transfered */
18924+ iso_packet->length = dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
18925+ }
18926+}
18927+
18928+/**
18929+ * This function reinitialize DMA Descriptors for Isochronous transfer
18930+ *
18931+ * @param core_if Programming view of DWC_otg controller.
18932+ * @param dwc_ep The EP to start the transfer on.
18933+ *
18934+ */
18935+static void reinit_ddma_iso_xfer(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
18936+{
18937+ int i, j;
18938+ dwc_otg_dma_desc_t* dma_desc;
18939+ dma_addr_t dma_ad;
18940+ volatile uint32_t *addr;
18941+ desc_sts_data_t sts = { .d32 =0 };
18942+ uint32_t data_per_desc;
18943+
18944+ if(dwc_ep->is_in == 0) {
18945+ addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
18946+ }
18947+ else {
18948+ addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
18949+ }
18950+
18951+
18952+ if(dwc_ep->proc_buf_num == 0) {
18953+ /** Buffer 0 descriptors setup */
18954+ dma_ad = dwc_ep->dma_addr0;
18955+ }
18956+ else {
18957+ /** Buffer 1 descriptors setup */
18958+ dma_ad = dwc_ep->dma_addr1;
18959+ }
18960+
18961+ /** Reinit closed DMA Descriptors*/
18962+ /** ISO OUT EP */
18963+ if(dwc_ep->is_in == 0) {
18964+ dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
18965+
18966+ sts.b_iso_out.bs = BS_HOST_READY;
18967+ sts.b_iso_out.rxsts = 0;
18968+ sts.b_iso_out.l = 0;
18969+ sts.b_iso_out.sp = 0;
18970+ sts.b_iso_out.ioc = 0;
18971+ sts.b_iso_out.pid = 0;
18972+ sts.b_iso_out.framenum = 0;
18973+
18974+ for(i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; i+= dwc_ep->pkt_per_frm)
18975+ {
18976+ for(j = 0; j < dwc_ep->pkt_per_frm; ++j)
18977+ {
18978+ data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
18979+ dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
18980+ data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
18981+ sts.b_iso_out.rxbytes = data_per_desc;
18982+ writel((uint32_t)dma_ad, &dma_desc->buf);
18983+ writel(sts.d32, &dma_desc->status);
18984+
18985+ //(uint32_t)dma_ad += data_per_desc;
18986+ dma_ad = (uint32_t)dma_ad + data_per_desc;
18987+ dma_desc ++;
18988+ }
18989+ }
18990+
18991+ for(j = 0; j < dwc_ep->pkt_per_frm - 1; ++j)
18992+ {
18993+
18994+ data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
18995+ dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
18996+ data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
18997+ sts.b_iso_out.rxbytes = data_per_desc;
18998+
18999+ writel((uint32_t)dma_ad, &dma_desc->buf);
19000+ writel(sts.d32, &dma_desc->status);
19001+
19002+ dma_desc++;
19003+ //(uint32_t)dma_ad += data_per_desc;
19004+ dma_ad = (uint32_t)dma_ad + data_per_desc;
19005+ }
19006+
19007+ sts.b_iso_out.ioc = 1;
19008+ sts.b_iso_out.l = dwc_ep->proc_buf_num;
19009+
19010+ data_per_desc = ((j + 1) * dwc_ep->maxpacket > dwc_ep->data_per_frame) ?
19011+ dwc_ep->data_per_frame - j * dwc_ep->maxpacket : dwc_ep->maxpacket;
19012+ data_per_desc += (data_per_desc % 4) ? (4 - data_per_desc % 4):0;
19013+ sts.b_iso_out.rxbytes = data_per_desc;
19014+
19015+ writel((uint32_t)dma_ad, &dma_desc->buf);
19016+ writel(sts.d32, &dma_desc->status);
19017+ }
19018+ else /** ISO IN EP */
19019+ {
19020+ dma_desc = dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
19021+
19022+ sts.b_iso_in.bs = BS_HOST_READY;
19023+ sts.b_iso_in.txsts = 0;
19024+ sts.b_iso_in.sp = 0;
19025+ sts.b_iso_in.ioc = 0;
19026+ sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
19027+ sts.b_iso_in.framenum = dwc_ep->next_frame;
19028+ sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
19029+ sts.b_iso_in.l = 0;
19030+
19031+ for(i = 0; i < dwc_ep->desc_cnt - 1; i++)
19032+ {
19033+ writel((uint32_t)dma_ad, &dma_desc->buf);
19034+ writel(sts.d32, &dma_desc->status);
19035+
19036+ sts.b_iso_in.framenum += dwc_ep->bInterval;
19037+ //(uint32_t)dma_ad += dwc_ep->data_per_frame;
19038+ dma_ad = (uint32_t)dma_ad + dwc_ep->data_per_frame;
19039+ dma_desc ++;
19040+ }
19041+
19042+ sts.b_iso_in.ioc = 1;
19043+ sts.b_iso_in.l = dwc_ep->proc_buf_num;
19044+
19045+ writel((uint32_t)dma_ad, &dma_desc->buf);
19046+ writel(sts.d32, &dma_desc->status);
19047+
19048+ dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval * 1;
19049+ }
19050+ dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
19051+}
19052+
19053+
19054+/**
19055+ * This function is to handle Iso EP transfer complete interrupt
19056+ * in case Iso out packet was dropped
19057+ *
19058+ * @param core_if Programming view of DWC_otg controller.
19059+ * @param dwc_ep The EP for wihich transfer complete was asserted
19060+ *
19061+ */
19062+static uint32_t handle_iso_out_pkt_dropped(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
19063+{
19064+ uint32_t dma_addr;
19065+ uint32_t drp_pkt;
19066+ uint32_t drp_pkt_cnt;
19067+ deptsiz_data_t deptsiz = { .d32 = 0 };
19068+ depctl_data_t depctl = { .d32 = 0 };
19069+ int i;
19070+
19071+ deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz);
19072+
19073+ drp_pkt = dwc_ep->pkt_cnt - deptsiz.b.pktcnt;
19074+ drp_pkt_cnt = dwc_ep->pkt_per_frm - (drp_pkt % dwc_ep->pkt_per_frm);
19075+
19076+ /* Setting dropped packets status */
19077+ for(i = 0; i < drp_pkt_cnt; ++i) {
19078+ dwc_ep->pkt_info[drp_pkt].status = -ENODATA;
19079+ drp_pkt ++;
19080+ deptsiz.b.pktcnt--;
19081+ }
19082+
19083+
19084+ if(deptsiz.b.pktcnt > 0) {
19085+ deptsiz.b.xfersize = dwc_ep->xfer_len - (dwc_ep->pkt_cnt - deptsiz.b.pktcnt) * dwc_ep->maxpacket;
19086+ } else {
19087+ deptsiz.b.xfersize = 0;
19088+ deptsiz.b.pktcnt = 0;
19089+ }
19090+
19091+ dwc_write_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz, deptsiz.d32);
19092+
19093+ if(deptsiz.b.pktcnt > 0) {
19094+ if(dwc_ep->proc_buf_num) {
19095+ dma_addr = dwc_ep->dma_addr1 + dwc_ep->xfer_len - deptsiz.b.xfersize;
19096+ } else {
19097+ dma_addr = dwc_ep->dma_addr0 + dwc_ep->xfer_len - deptsiz.b.xfersize;;
19098+ }
19099+
19100+ VERIFY_PCD_DMA_ADDR(dma_addr);
19101+ dwc_write_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepdma, dma_addr);
19102+
19103+ /** Re-enable endpoint, clear nak */
19104+ depctl.d32 = 0;
19105+ depctl.b.epena = 1;
19106+ depctl.b.cnak = 1;
19107+
19108+ dwc_modify_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl,
19109+ depctl.d32,depctl.d32);
19110+ return 0;
19111+ } else {
19112+ return 1;
19113+ }
19114+}
19115+
19116+/**
19117+ * This function sets iso packets information(PTI mode)
19118+ *
19119+ * @param core_if Programming view of DWC_otg controller.
19120+ * @param ep The EP to start the transfer on.
19121+ *
19122+ */
19123+static uint32_t set_iso_pkts_info(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
19124+{
19125+ int i, j;
19126+ dma_addr_t dma_ad;
19127+ iso_pkt_info_t *packet_info = ep->pkt_info;
19128+ uint32_t offset;
19129+ uint32_t frame_data;
19130+ deptsiz_data_t deptsiz;
19131+
19132+ if(ep->proc_buf_num == 0) {
19133+ /** Buffer 0 descriptors setup */
19134+ dma_ad = ep->dma_addr0;
19135+ }
19136+ else {
19137+ /** Buffer 1 descriptors setup */
19138+ dma_ad = ep->dma_addr1;
19139+ }
19140+
19141+ if(ep->is_in) {
19142+ deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz);
19143+ } else {
19144+ deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]->doeptsiz);
19145+ }
19146+
19147+ if(!deptsiz.b.xfersize) {
19148+ offset = 0;
19149+ for(i = 0; i < ep->pkt_cnt; i += ep->pkt_per_frm)
19150+ {
19151+ frame_data = ep->data_per_frame;
19152+ for(j = 0; j < ep->pkt_per_frm; ++j) {
19153+
19154+ /* Packet status - is not set as initially
19155+ * it is set to 0 and if packet was sent
19156+ successfully, status field will remain 0*/
19157+
19158+ /* Bytes has been transfered */
19159+ packet_info->length = (ep->maxpacket < frame_data) ?
19160+ ep->maxpacket : frame_data;
19161+
19162+ /* Received packet offset */
19163+ packet_info->offset = offset;
19164+ offset += packet_info->length;
19165+ frame_data -= packet_info->length;
19166+
19167+ packet_info ++;
19168+ }
19169+ }
19170+ return 1;
19171+ } else {
19172+ /* This is a workaround for in case of Transfer Complete with
19173+ * PktDrpSts interrupts merging - in this case Transfer complete
19174+ * interrupt for Isoc Out Endpoint is asserted without PktDrpSts
19175+ * set and with DOEPTSIZ register non zero. Investigations showed,
19176+ * that this happens when Out packet is dropped, but because of
19177+ * interrupts merging during first interrupt handling PktDrpSts
19178+ * bit is cleared and for next merged interrupts it is not reset.
19179+ * In this case SW hadles the interrupt as if PktDrpSts bit is set.
19180+ */
19181+ if(ep->is_in) {
19182+ return 1;
19183+ } else {
19184+ return handle_iso_out_pkt_dropped(core_if, ep);
19185+ }
19186+ }
19187+}
19188+
19189+/**
19190+ * This function is to handle Iso EP transfer complete interrupt
19191+ *
19192+ * @param ep The EP for which transfer complete was asserted
19193+ *
19194+ */
19195+static void complete_iso_ep(dwc_otg_pcd_ep_t *ep)
19196+{
19197+ dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
19198+ dwc_ep_t *dwc_ep = &ep->dwc_ep;
19199+ uint8_t is_last = 0;
19200+
19201+ if(core_if->dma_enable) {
19202+ if(core_if->dma_desc_enable) {
19203+ set_ddma_iso_pkts_info(core_if, dwc_ep);
19204+ reinit_ddma_iso_xfer(core_if, dwc_ep);
19205+ is_last = 1;
19206+ } else {
19207+ if(core_if->pti_enh_enable) {
19208+ if(set_iso_pkts_info(core_if, dwc_ep)) {
19209+ dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
19210+ dwc_otg_iso_ep_start_buf_transfer(core_if, dwc_ep);
19211+ is_last = 1;
19212+ }
19213+ } else {
19214+ set_current_pkt_info(core_if, dwc_ep);
19215+ if(dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
19216+ is_last = 1;
19217+ dwc_ep->cur_pkt = 0;
19218+ dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
19219+ if(dwc_ep->proc_buf_num) {
19220+ dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
19221+ dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
19222+ } else {
19223+ dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
19224+ dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
19225+ }
19226+ }
19227+ dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep);
19228+ }
19229+ }
19230+ } else {
19231+ set_current_pkt_info(core_if, dwc_ep);
19232+ if(dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
19233+ is_last = 1;
19234+ dwc_ep->cur_pkt = 0;
19235+ dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
19236+ if(dwc_ep->proc_buf_num) {
19237+ dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
19238+ dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
19239+ } else {
19240+ dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
19241+ dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
19242+ }
19243+ }
19244+ dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep);
19245+ }
19246+ if(is_last)
19247+ dwc_otg_iso_buffer_done(ep, ep->iso_req);
19248+}
19249+
19250+#endif //DWC_EN_ISOC
19251+
19252+
19253+/**
19254+ * This function handles EP0 Control transfers.
19255+ *
19256+ * The state of the control tranfers are tracked in
19257+ * <code>ep0state</code>.
19258+ */
19259+static void handle_ep0(dwc_otg_pcd_t *pcd)
19260+{
19261+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
19262+ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
19263+ desc_sts_data_t desc_sts;
19264+ deptsiz0_data_t deptsiz;
19265+ uint32_t byte_count;
19266+
19267+#ifdef DEBUG_EP0
19268+ DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
19269+ print_ep0_state(pcd);
19270+#endif
19271+
19272+ switch (pcd->ep0state) {
19273+ case EP0_DISCONNECT:
19274+ break;
19275+
19276+ case EP0_IDLE:
19277+ pcd->request_config = 0;
19278+
19279+ pcd_setup(pcd);
19280+ break;
19281+
19282+ case EP0_IN_DATA_PHASE:
19283+#ifdef DEBUG_EP0
19284+ DWC_DEBUGPL(DBG_PCD, "DATA_IN EP%d-%s: type=%d, mps=%d\n",
19285+ ep0->dwc_ep.num, (ep0->dwc_ep.is_in ?"IN":"OUT"),
19286+ ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
19287+#endif
19288+
19289+ if (core_if->dma_enable != 0) {
19290+ /*
19291+ * For EP0 we can only program 1 packet at a time so we
19292+ * need to do the make calculations after each complete.
19293+ * Call write_packet to make the calculations, as in
19294+ * slave mode, and use those values to determine if we
19295+ * can complete.
19296+ */
19297+ if(core_if->dma_desc_enable == 0) {
19298+ deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[0]->dieptsiz);
19299+ byte_count = ep0->dwc_ep.xfer_len - deptsiz.b.xfersize;
19300+ }
19301+ else {
19302+ desc_sts.d32 = readl(core_if->dev_if->in_desc_addr);
19303+ byte_count = ep0->dwc_ep.xfer_len - desc_sts.b.bytes;
19304+ }
19305+
19306+ ep0->dwc_ep.xfer_count += byte_count;
19307+ ep0->dwc_ep.xfer_buff += byte_count;
19308+ ep0->dwc_ep.dma_addr += byte_count;
19309+ }
19310+ if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
19311+ dwc_otg_ep0_continue_transfer (GET_CORE_IF(pcd), &ep0->dwc_ep);
19312+ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
19313+ }
19314+ else if(ep0->dwc_ep.sent_zlp) {
19315+ dwc_otg_ep0_continue_transfer (GET_CORE_IF(pcd), &ep0->dwc_ep);
19316+ ep0->dwc_ep.sent_zlp = 0;
19317+ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
19318+ }
19319+ else {
19320+ ep0_complete_request(ep0);
19321+ DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
19322+ }
19323+ break;
19324+ case EP0_OUT_DATA_PHASE:
19325+#ifdef DEBUG_EP0
19326+ DWC_DEBUGPL(DBG_PCD, "DATA_OUT EP%d-%s: type=%d, mps=%d\n",
19327+ ep0->dwc_ep.num, (ep0->dwc_ep.is_in ?"IN":"OUT"),
19328+ ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
19329+#endif
19330+ if (core_if->dma_enable != 0) {
19331+ if(core_if->dma_desc_enable == 0) {
19332+ deptsiz.d32 = dwc_read_reg32(&core_if->dev_if->out_ep_regs[0]->doeptsiz);
19333+ byte_count = ep0->dwc_ep.maxpacket - deptsiz.b.xfersize;
19334+
19335+ //todo: invalidate cache & aligned buf patch on completion
19336+ dma_sync_single_for_device(NULL,ep0->dwc_ep.dma_addr,byte_count,DMA_FROM_DEVICE);
19337+ aligned_buf_patch_on_buf_dma_oep_completion(ep0,byte_count);
19338+ }
19339+ else {
19340+ desc_sts.d32 = readl(core_if->dev_if->out_desc_addr);
19341+ byte_count = ep0->dwc_ep.maxpacket - desc_sts.b.bytes;
19342+
19343+ //todo: invalidate cache & aligned buf patch on completion
19344+ //
19345+
19346+ }
19347+ ep0->dwc_ep.xfer_count += byte_count;
19348+ ep0->dwc_ep.xfer_buff += byte_count;
19349+ ep0->dwc_ep.dma_addr += byte_count;
19350+ }
19351+ if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
19352+ dwc_otg_ep0_continue_transfer (GET_CORE_IF(pcd), &ep0->dwc_ep);
19353+ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
19354+ }
19355+ else if(ep0->dwc_ep.sent_zlp) {
19356+ dwc_otg_ep0_continue_transfer (GET_CORE_IF(pcd), &ep0->dwc_ep);
19357+ ep0->dwc_ep.sent_zlp = 0;
19358+ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
19359+ }
19360+ else {
19361+ ep0_complete_request(ep0);
19362+ DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
19363+ }
19364+ break;
19365+
19366+ case EP0_IN_STATUS_PHASE:
19367+ case EP0_OUT_STATUS_PHASE:
19368+ DWC_DEBUGPL(DBG_PCD, "CASE: EP0_STATUS\n");
19369+ ep0_complete_request(ep0);
19370+ pcd->ep0state = EP0_IDLE;
19371+ ep0->stopped = 1;
19372+ ep0->dwc_ep.is_in = 0; /* OUT for next SETUP */
19373+
19374+ /* Prepare for more SETUP Packets */
19375+ if(core_if->dma_enable) {
19376+ ep0_out_start(core_if, pcd);
19377+ }
19378+ break;
19379+
19380+ case EP0_STALL:
19381+ DWC_ERROR("EP0 STALLed, should not get here pcd_setup()\n");
19382+ break;
19383+ }
19384+#ifdef DEBUG_EP0
19385+ print_ep0_state(pcd);
19386+#endif
19387+}
19388+
19389+
19390+/**
19391+ * Restart transfer
19392+ */
19393+static void restart_transfer(dwc_otg_pcd_t *pcd, const uint32_t epnum)
19394+{
19395+ dwc_otg_core_if_t *core_if;
19396+ dwc_otg_dev_if_t *dev_if;
19397+ deptsiz_data_t dieptsiz = {.d32=0};
19398+ dwc_otg_pcd_ep_t *ep;
19399+
19400+ ep = get_in_ep(pcd, epnum);
19401+
19402+#ifdef DWC_EN_ISOC
19403+ if(ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
19404+ return;
19405+ }
19406+#endif /* DWC_EN_ISOC */
19407+
19408+ core_if = GET_CORE_IF(pcd);
19409+ dev_if = core_if->dev_if;
19410+
19411+ dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dieptsiz);
19412+
19413+ DWC_DEBUGPL(DBG_PCD,"xfer_buff=%p xfer_count=%0x xfer_len=%0x"
19414+ " stopped=%d\n", ep->dwc_ep.xfer_buff,
19415+ ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len ,
19416+ ep->stopped);
19417+ /*
19418+ * If xfersize is 0 and pktcnt in not 0, resend the last packet.
19419+ */
19420+ if (dieptsiz.b.pktcnt && dieptsiz.b.xfersize == 0 &&
19421+ ep->dwc_ep.start_xfer_buff != 0) {
19422+ if (ep->dwc_ep.total_len <= ep->dwc_ep.maxpacket) {
19423+ ep->dwc_ep.xfer_count = 0;
19424+ ep->dwc_ep.xfer_buff = ep->dwc_ep.start_xfer_buff;
19425+ ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
19426+ }
19427+ else {
19428+ ep->dwc_ep.xfer_count -= ep->dwc_ep.maxpacket;
19429+ /* convert packet size to dwords. */
19430+ ep->dwc_ep.xfer_buff -= ep->dwc_ep.maxpacket;
19431+ ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
19432+ }
19433+ ep->stopped = 0;
19434+ DWC_DEBUGPL(DBG_PCD,"xfer_buff=%p xfer_count=%0x "
19435+ "xfer_len=%0x stopped=%d\n",
19436+ ep->dwc_ep.xfer_buff,
19437+ ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len ,
19438+ ep->stopped
19439+ );
19440+ if (epnum == 0) {
19441+ dwc_otg_ep0_start_transfer(core_if, &ep->dwc_ep);
19442+ }
19443+ else {
19444+ dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
19445+ }
19446+ }
19447+}
19448+
19449+
19450+/**
19451+ * handle the IN EP disable interrupt.
19452+ */
19453+static inline void handle_in_ep_disable_intr(dwc_otg_pcd_t *pcd,
19454+ const uint32_t epnum)
19455+{
19456+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
19457+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
19458+ deptsiz_data_t dieptsiz = {.d32=0};
19459+ dctl_data_t dctl = {.d32=0};
19460+ dwc_otg_pcd_ep_t *ep;
19461+ dwc_ep_t *dwc_ep;
19462+
19463+ ep = get_in_ep(pcd, epnum);
19464+ dwc_ep = &ep->dwc_ep;
19465+
19466+ if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
19467+ dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
19468+ return;
19469+ }
19470+
19471+ DWC_DEBUGPL(DBG_PCD,"diepctl%d=%0x\n", epnum,
19472+ dwc_read_reg32(&dev_if->in_ep_regs[epnum]->diepctl));
19473+ dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dieptsiz);
19474+
19475+ DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
19476+ dieptsiz.b.pktcnt,
19477+ dieptsiz.b.xfersize);
19478+
19479+ if (ep->stopped) {
19480+ /* Flush the Tx FIFO */
19481+ dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
19482+ /* Clear the Global IN NP NAK */
19483+ dctl.d32 = 0;
19484+ dctl.b.cgnpinnak = 1;
19485+ dwc_modify_reg32(&dev_if->dev_global_regs->dctl,
19486+ dctl.d32, 0);
19487+ /* Restart the transaction */
19488+ if (dieptsiz.b.pktcnt != 0 ||
19489+ dieptsiz.b.xfersize != 0) {
19490+ restart_transfer(pcd, epnum);
19491+ }
19492+ }
19493+ else {
19494+ /* Restart the transaction */
19495+ if (dieptsiz.b.pktcnt != 0 ||
19496+ dieptsiz.b.xfersize != 0) {
19497+ restart_transfer(pcd, epnum);
19498+ }
19499+ DWC_DEBUGPL(DBG_ANY, "STOPPED!!!\n");
19500+ }
19501+}
19502+
19503+/**
19504+ * Handler for the IN EP timeout handshake interrupt.
19505+ */
19506+static inline void handle_in_ep_timeout_intr(dwc_otg_pcd_t *pcd,
19507+ const uint32_t epnum)
19508+{
19509+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
19510+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
19511+
19512+#ifdef DEBUG
19513+ deptsiz_data_t dieptsiz = {.d32=0};
19514+ uint32_t num = 0;
19515+#endif
19516+ dctl_data_t dctl = {.d32=0};
19517+ dwc_otg_pcd_ep_t *ep;
19518+
19519+ gintmsk_data_t intr_mask = {.d32 = 0};
19520+
19521+ ep = get_in_ep(pcd, epnum);
19522+
19523+ /* Disable the NP Tx Fifo Empty Interrrupt */
19524+ if (!core_if->dma_enable) {
19525+ intr_mask.b.nptxfempty = 1;
19526+ dwc_modify_reg32(&core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
19527+ }
19528+ /** @todo NGS Check EP type.
19529+ * Implement for Periodic EPs */
19530+ /*
19531+ * Non-periodic EP
19532+ */
19533+ /* Enable the Global IN NAK Effective Interrupt */
19534+ intr_mask.b.ginnakeff = 1;
19535+ dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
19536+ 0, intr_mask.d32);
19537+
19538+ /* Set Global IN NAK */
19539+ dctl.b.sgnpinnak = 1;
19540+ dwc_modify_reg32(&dev_if->dev_global_regs->dctl,
19541+ dctl.d32, dctl.d32);
19542+
19543+ ep->stopped = 1;
19544+
19545+#ifdef DEBUG
19546+ dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[num]->dieptsiz);
19547+ DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
19548+ dieptsiz.b.pktcnt,
19549+ dieptsiz.b.xfersize);
19550+#endif
19551+
19552+#ifdef DISABLE_PERIODIC_EP
19553+ /*
19554+ * Set the NAK bit for this EP to
19555+ * start the disable process.
19556+ */
19557+ diepctl.d32 = 0;
19558+ diepctl.b.snak = 1;
19559+ dwc_modify_reg32(&dev_if->in_ep_regs[num]->diepctl, diepctl.d32, diepctl.d32);
19560+ ep->disabling = 1;
19561+ ep->stopped = 1;
19562+#endif
19563+}
19564+
19565+/**
19566+ * Handler for the IN EP NAK interrupt.
19567+ */
19568+static inline int32_t handle_in_ep_nak_intr(dwc_otg_pcd_t *pcd,
19569+ const uint32_t epnum)
19570+{
19571+ /** @todo implement ISR */
19572+ dwc_otg_core_if_t* core_if;
19573+ diepmsk_data_t intr_mask = { .d32 = 0};
19574+
19575+ DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "IN EP NAK");
19576+ core_if = GET_CORE_IF(pcd);
19577+ intr_mask.b.nak = 1;
19578+
19579+ if(core_if->multiproc_int_enable) {
19580+ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->diepeachintmsk[epnum],
19581+ intr_mask.d32, 0);
19582+ } else {
19583+ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->diepmsk,
19584+ intr_mask.d32, 0);
19585+ }
19586+
19587+ return 1;
19588+}
19589+
19590+/**
19591+ * Handler for the OUT EP Babble interrupt.
19592+ */
19593+static inline int32_t handle_out_ep_babble_intr(dwc_otg_pcd_t *pcd,
19594+ const uint32_t epnum)
19595+{
19596+ /** @todo implement ISR */
19597+ dwc_otg_core_if_t* core_if;
19598+ doepmsk_data_t intr_mask = { .d32 = 0};
19599+
19600+ DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "OUT EP Babble");
19601+ core_if = GET_CORE_IF(pcd);
19602+ intr_mask.b.babble = 1;
19603+
19604+ if(core_if->multiproc_int_enable) {
19605+ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepeachintmsk[epnum],
19606+ intr_mask.d32, 0);
19607+ } else {
19608+ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk,
19609+ intr_mask.d32, 0);
19610+ }
19611+
19612+ return 1;
19613+}
19614+
19615+/**
19616+ * Handler for the OUT EP NAK interrupt.
19617+ */
19618+static inline int32_t handle_out_ep_nak_intr(dwc_otg_pcd_t *pcd,
19619+ const uint32_t epnum)
19620+{
19621+ /** @todo implement ISR */
19622+ dwc_otg_core_if_t* core_if;
19623+ doepmsk_data_t intr_mask = { .d32 = 0};
19624+
19625+ DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "OUT EP NAK");
19626+ core_if = GET_CORE_IF(pcd);
19627+ intr_mask.b.nak = 1;
19628+
19629+ if(core_if->multiproc_int_enable) {
19630+ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepeachintmsk[epnum],
19631+ intr_mask.d32, 0);
19632+ } else {
19633+ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk,
19634+ intr_mask.d32, 0);
19635+ }
19636+
19637+ return 1;
19638+}
19639+
19640+/**
19641+ * Handler for the OUT EP NYET interrupt.
19642+ */
19643+static inline int32_t handle_out_ep_nyet_intr(dwc_otg_pcd_t *pcd,
19644+ const uint32_t epnum)
19645+{
19646+ /** @todo implement ISR */
19647+ dwc_otg_core_if_t* core_if;
19648+ doepmsk_data_t intr_mask = { .d32 = 0};
19649+
19650+ DWC_PRINT("INTERRUPT Handler not implemented for %s\n", "OUT EP NYET");
19651+ core_if = GET_CORE_IF(pcd);
19652+ intr_mask.b.nyet = 1;
19653+
19654+ if(core_if->multiproc_int_enable) {
19655+ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepeachintmsk[epnum],
19656+ intr_mask.d32, 0);
19657+ } else {
19658+ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk,
19659+ intr_mask.d32, 0);
19660+ }
19661+
19662+ return 1;
19663+}
19664+
19665+/**
19666+ * This interrupt indicates that an IN EP has a pending Interrupt.
19667+ * The sequence for handling the IN EP interrupt is shown below:
19668+ * -# Read the Device All Endpoint Interrupt register
19669+ * -# Repeat the following for each IN EP interrupt bit set (from
19670+ * LSB to MSB).
19671+ * -# Read the Device Endpoint Interrupt (DIEPINTn) register
19672+ * -# If "Transfer Complete" call the request complete function
19673+ * -# If "Endpoint Disabled" complete the EP disable procedure.
19674+ * -# If "AHB Error Interrupt" log error
19675+ * -# If "Time-out Handshake" log error
19676+ * -# If "IN Token Received when TxFIFO Empty" write packet to Tx
19677+ * FIFO.
19678+ * -# If "IN Token EP Mismatch" (disable, this is handled by EP
19679+ * Mismatch Interrupt)
19680+ */
19681+static int32_t dwc_otg_pcd_handle_in_ep_intr(dwc_otg_pcd_t *pcd)
19682+{
19683+#define CLEAR_IN_EP_INTR(__core_if,__epnum,__intr) \
19684+do { \
19685+ diepint_data_t diepint = {.d32=0}; \
19686+ diepint.b.__intr = 1; \
19687+ dwc_write_reg32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \
19688+ diepint.d32); \
19689+} while (0)
19690+
19691+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
19692+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
19693+ diepint_data_t diepint = {.d32=0};
19694+ dctl_data_t dctl = {.d32=0};
19695+ depctl_data_t depctl = {.d32=0};
19696+ uint32_t ep_intr;
19697+ uint32_t epnum = 0;
19698+ dwc_otg_pcd_ep_t *ep;
19699+ dwc_ep_t *dwc_ep;
19700+ gintmsk_data_t intr_mask = {.d32 = 0};
19701+
19702+ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd);
19703+
19704+ /* Read in the device interrupt bits */
19705+ ep_intr = dwc_otg_read_dev_all_in_ep_intr(core_if);
19706+
19707+ /* Service the Device IN interrupts for each endpoint */
19708+ while(ep_intr) {
19709+ if (ep_intr&0x1) {
19710+ uint32_t empty_msk;
19711+ /* Get EP pointer */
19712+ ep = get_in_ep(pcd, epnum);
19713+ dwc_ep = &ep->dwc_ep;
19714+
19715+ depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->diepctl);
19716+ empty_msk = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk);
19717+
19718+ DWC_DEBUGPL(DBG_PCDV,
19719+ "IN EP INTERRUPT - %d\nepmty_msk - %8x diepctl - %8x\n",
19720+ epnum,
19721+ empty_msk,
19722+ depctl.d32);
19723+
19724+ DWC_DEBUGPL(DBG_PCD,
19725+ "EP%d-%s: type=%d, mps=%d\n",
19726+ dwc_ep->num, (dwc_ep->is_in ?"IN":"OUT"),
19727+ dwc_ep->type, dwc_ep->maxpacket);
19728+
19729+ diepint.d32 = dwc_otg_read_dev_in_ep_intr(core_if, dwc_ep);
19730+
19731+ DWC_DEBUGPL(DBG_PCDV, "EP %d Interrupt Register - 0x%x\n", epnum, diepint.d32);
19732+ /* Transfer complete */
19733+ if (diepint.b.xfercompl) {
19734+ /* Disable the NP Tx FIFO Empty
19735+ * Interrrupt */
19736+ if(core_if->en_multiple_tx_fifo == 0) {
19737+ intr_mask.b.nptxfempty = 1;
19738+ dwc_modify_reg32(&core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
19739+ }
19740+ else {
19741+ /* Disable the Tx FIFO Empty Interrupt for this EP */
19742+ uint32_t fifoemptymsk = 0x1 << dwc_ep->num;
19743+ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
19744+ fifoemptymsk, 0);
19745+ }
19746+ /* Clear the bit in DIEPINTn for this interrupt */
19747+ CLEAR_IN_EP_INTR(core_if,epnum,xfercompl);
19748+
19749+ /* Complete the transfer */
19750+ if (epnum == 0) {
19751+ handle_ep0(pcd);
19752+ }
19753+#ifdef DWC_EN_ISOC
19754+ else if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
19755+ if(!ep->stopped)
19756+ complete_iso_ep(ep);
19757+ }
19758+#endif //DWC_EN_ISOC
19759+ else {
19760+
19761+ complete_ep(ep);
19762+ }
19763+ }
19764+ /* Endpoint disable */
19765+ if (diepint.b.epdisabled) {
19766+ DWC_DEBUGPL(DBG_ANY,"EP%d IN disabled\n", epnum);
19767+ handle_in_ep_disable_intr(pcd, epnum);
19768+
19769+ /* Clear the bit in DIEPINTn for this interrupt */
19770+ CLEAR_IN_EP_INTR(core_if,epnum,epdisabled);
19771+ }
19772+ /* AHB Error */
19773+ if (diepint.b.ahberr) {
19774+ DWC_DEBUGPL(DBG_ANY,"EP%d IN AHB Error\n", epnum);
19775+ /* Clear the bit in DIEPINTn for this interrupt */
19776+ CLEAR_IN_EP_INTR(core_if,epnum,ahberr);
19777+ }
19778+ /* TimeOUT Handshake (non-ISOC IN EPs) */
19779+ if (diepint.b.timeout) {
19780+ DWC_DEBUGPL(DBG_ANY,"EP%d IN Time-out\n", epnum);
19781+ handle_in_ep_timeout_intr(pcd, epnum);
19782+
19783+ CLEAR_IN_EP_INTR(core_if,epnum,timeout);
19784+ }
19785+ /** IN Token received with TxF Empty */
19786+ if (diepint.b.intktxfemp) {
19787+ DWC_DEBUGPL(DBG_ANY,"EP%d IN TKN TxFifo Empty\n",
19788+ epnum);
19789+ if (!ep->stopped && epnum != 0) {
19790+
19791+ diepmsk_data_t diepmsk = { .d32 = 0};
19792+ diepmsk.b.intktxfemp = 1;
19793+
19794+ if(core_if->multiproc_int_enable) {
19795+ dwc_modify_reg32(&dev_if->dev_global_regs->diepeachintmsk[epnum],
19796+ diepmsk.d32, 0);
19797+ } else {
19798+ dwc_modify_reg32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32, 0);
19799+ }
19800+ start_next_request(ep);
19801+ }
19802+ else if(core_if->dma_desc_enable && epnum == 0 &&
19803+ pcd->ep0state == EP0_OUT_STATUS_PHASE) {
19804+ // EP0 IN set STALL
19805+ depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->diepctl);
19806+
19807+ /* set the disable and stall bits */
19808+ if (depctl.b.epena) {
19809+ depctl.b.epdis = 1;
19810+ }
19811+ depctl.b.stall = 1;
19812+ dwc_write_reg32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32);
19813+ }
19814+ CLEAR_IN_EP_INTR(core_if,epnum,intktxfemp);
19815+ }
19816+ /** IN Token Received with EP mismatch */
19817+ if (diepint.b.intknepmis) {
19818+ DWC_DEBUGPL(DBG_ANY,"EP%d IN TKN EP Mismatch\n", epnum);
19819+ CLEAR_IN_EP_INTR(core_if,epnum,intknepmis);
19820+ }
19821+ /** IN Endpoint NAK Effective */
19822+ if (diepint.b.inepnakeff) {
19823+ DWC_DEBUGPL(DBG_ANY,"EP%d IN EP NAK Effective\n", epnum);
19824+ /* Periodic EP */
19825+ if (ep->disabling) {
19826+ depctl.d32 = 0;
19827+ depctl.b.snak = 1;
19828+ depctl.b.epdis = 1;
19829+ dwc_modify_reg32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32, depctl.d32);
19830+ }
19831+ CLEAR_IN_EP_INTR(core_if,epnum,inepnakeff);
19832+
19833+ }
19834+
19835+ /** IN EP Tx FIFO Empty Intr */
19836+ if (diepint.b.emptyintr) {
19837+ DWC_DEBUGPL(DBG_ANY,"EP%d Tx FIFO Empty Intr \n", epnum);
19838+ write_empty_tx_fifo(pcd, epnum);
19839+
19840+ CLEAR_IN_EP_INTR(core_if,epnum,emptyintr);
19841+ }
19842+
19843+ /** IN EP BNA Intr */
19844+ if (diepint.b.bna) {
19845+ CLEAR_IN_EP_INTR(core_if,epnum,bna);
19846+ if(core_if->dma_desc_enable) {
19847+#ifdef DWC_EN_ISOC
19848+ if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
19849+ /*
19850+ * This checking is performed to prevent first "false" BNA
19851+ * handling occuring right after reconnect
19852+ */
19853+ if(dwc_ep->next_frame != 0xffffffff)
19854+ dwc_otg_pcd_handle_iso_bna(ep);
19855+ }
19856+ else
19857+#endif //DWC_EN_ISOC
19858+ {
19859+ dctl.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dctl);
19860+
19861+ /* If Global Continue on BNA is disabled - disable EP */
19862+ if(!dctl.b.gcontbna) {
19863+ depctl.d32 = 0;
19864+ depctl.b.snak = 1;
19865+ depctl.b.epdis = 1;
19866+ dwc_modify_reg32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32, depctl.d32);
19867+ } else {
19868+ start_next_request(ep);
19869+ }
19870+ }
19871+ }
19872+ }
19873+ /* NAK Interrutp */
19874+ if (diepint.b.nak) {
19875+ DWC_DEBUGPL(DBG_ANY,"EP%d IN NAK Interrupt\n", epnum);
19876+ handle_in_ep_nak_intr(pcd, epnum);
19877+
19878+ CLEAR_IN_EP_INTR(core_if,epnum,nak);
19879+ }
19880+ }
19881+ epnum++;
19882+ ep_intr >>=1;
19883+ }
19884+
19885+ return 1;
19886+#undef CLEAR_IN_EP_INTR
19887+}
19888+
19889+/**
19890+ * This interrupt indicates that an OUT EP has a pending Interrupt.
19891+ * The sequence for handling the OUT EP interrupt is shown below:
19892+ * -# Read the Device All Endpoint Interrupt register
19893+ * -# Repeat the following for each OUT EP interrupt bit set (from
19894+ * LSB to MSB).
19895+ * -# Read the Device Endpoint Interrupt (DOEPINTn) register
19896+ * -# If "Transfer Complete" call the request complete function
19897+ * -# If "Endpoint Disabled" complete the EP disable procedure.
19898+ * -# If "AHB Error Interrupt" log error
19899+ * -# If "Setup Phase Done" process Setup Packet (See Standard USB
19900+ * Command Processing)
19901+ */
19902+static int32_t dwc_otg_pcd_handle_out_ep_intr(dwc_otg_pcd_t *pcd)
19903+{
19904+#define CLEAR_OUT_EP_INTR(__core_if,__epnum,__intr) \
19905+do { \
19906+ doepint_data_t doepint = {.d32=0}; \
19907+ doepint.b.__intr = 1; \
19908+ dwc_write_reg32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \
19909+ doepint.d32); \
19910+} while (0)
19911+
19912+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
19913+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
19914+ uint32_t ep_intr;
19915+ doepint_data_t doepint = {.d32=0};
19916+ dctl_data_t dctl = {.d32=0};
19917+ depctl_data_t doepctl = {.d32=0};
19918+ uint32_t epnum = 0;
19919+ dwc_otg_pcd_ep_t *ep;
19920+ dwc_ep_t *dwc_ep;
19921+
19922+ DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
19923+
19924+ /* Read in the device interrupt bits */
19925+ ep_intr = dwc_otg_read_dev_all_out_ep_intr(core_if);
19926+
19927+ while(ep_intr) {
19928+ if (ep_intr&0x1) {
19929+ /* Get EP pointer */
19930+ ep = get_out_ep(pcd, epnum);
19931+ dwc_ep = &ep->dwc_ep;
19932+
19933+#ifdef VERBOSE
19934+ DWC_DEBUGPL(DBG_PCDV,
19935+ "EP%d-%s: type=%d, mps=%d\n",
19936+ dwc_ep->num, (dwc_ep->is_in ?"IN":"OUT"),
19937+ dwc_ep->type, dwc_ep->maxpacket);
19938+#endif
19939+ doepint.d32 = dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep);
19940+
19941+ /* Transfer complete */
19942+ if (doepint.b.xfercompl) {
19943+ if (epnum == 0) {
19944+ /* Clear the bit in DOEPINTn for this interrupt */
19945+ CLEAR_OUT_EP_INTR(core_if,epnum,xfercompl);
19946+ if(core_if->dma_desc_enable == 0 || pcd->ep0state != EP0_IDLE)
19947+ handle_ep0(pcd);
19948+#ifdef DWC_EN_ISOC
19949+ } else if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
19950+ if (doepint.b.pktdrpsts == 0) {
19951+ /* Clear the bit in DOEPINTn for this interrupt */
19952+ CLEAR_OUT_EP_INTR(core_if,epnum,xfercompl);
19953+ complete_iso_ep(ep);
19954+ } else {
19955+ doepint_data_t doepint = {.d32=0};
19956+ doepint.b.xfercompl = 1;
19957+ doepint.b.pktdrpsts = 1;
19958+ dwc_write_reg32(&core_if->dev_if->out_ep_regs[epnum]->doepint,
19959+ doepint.d32);
19960+ if(handle_iso_out_pkt_dropped(core_if,dwc_ep)) {
19961+ complete_iso_ep(ep);
19962+ }
19963+ }
19964+#endif //DWC_EN_ISOC
19965+ } else {
19966+ /* Clear the bit in DOEPINTn for this interrupt */
19967+ CLEAR_OUT_EP_INTR(core_if,epnum,xfercompl);
19968+ complete_ep(ep);
19969+ }
19970+
19971+ }
19972+
19973+ /* Endpoint disable */
19974+ if (doepint.b.epdisabled) {
19975+ /* Clear the bit in DOEPINTn for this interrupt */
19976+ CLEAR_OUT_EP_INTR(core_if,epnum,epdisabled);
19977+ }
19978+ /* AHB Error */
19979+ if (doepint.b.ahberr) {
19980+ DWC_DEBUGPL(DBG_PCD,"EP%d OUT AHB Error\n", epnum);
19981+ DWC_DEBUGPL(DBG_PCD,"EP DMA REG %d \n", core_if->dev_if->out_ep_regs[epnum]->doepdma);
19982+ CLEAR_OUT_EP_INTR(core_if,epnum,ahberr);
19983+ }
19984+ /* Setup Phase Done (contorl EPs) */
19985+ if (doepint.b.setup) {
19986+#ifdef DEBUG_EP0
19987+ DWC_DEBUGPL(DBG_PCD,"EP%d SETUP Done\n",
19988+ epnum);
19989+#endif
19990+ CLEAR_OUT_EP_INTR(core_if,epnum,setup);
19991+ handle_ep0(pcd);
19992+ }
19993+
19994+ /** OUT EP BNA Intr */
19995+ if (doepint.b.bna) {
19996+ CLEAR_OUT_EP_INTR(core_if,epnum,bna);
19997+ if(core_if->dma_desc_enable) {
19998+#ifdef DWC_EN_ISOC
19999+ if(dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
20000+ /*
20001+ * This checking is performed to prevent first "false" BNA
20002+ * handling occuring right after reconnect
20003+ */
20004+ if(dwc_ep->next_frame != 0xffffffff)
20005+ dwc_otg_pcd_handle_iso_bna(ep);
20006+ }
20007+ else
20008+#endif //DWC_EN_ISOC
20009+ {
20010+ dctl.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dctl);
20011+
20012+ /* If Global Continue on BNA is disabled - disable EP*/
20013+ if(!dctl.b.gcontbna) {
20014+ doepctl.d32 = 0;
20015+ doepctl.b.snak = 1;
20016+ doepctl.b.epdis = 1;
20017+ dwc_modify_reg32(&dev_if->out_ep_regs[epnum]->doepctl, doepctl.d32, doepctl.d32);
20018+ } else {
20019+ start_next_request(ep);
20020+ }
20021+ }
20022+ }
20023+ }
20024+ if (doepint.b.stsphsercvd) {
20025+ CLEAR_OUT_EP_INTR(core_if,epnum,stsphsercvd);
20026+ if(core_if->dma_desc_enable) {
20027+ do_setup_in_status_phase(pcd);
20028+ }
20029+ }
20030+ /* Babble Interrutp */
20031+ if (doepint.b.babble) {
20032+ DWC_DEBUGPL(DBG_ANY,"EP%d OUT Babble\n", epnum);
20033+ handle_out_ep_babble_intr(pcd, epnum);
20034+
20035+ CLEAR_OUT_EP_INTR(core_if,epnum,babble);
20036+ }
20037+ /* NAK Interrutp */
20038+ if (doepint.b.nak) {
20039+ DWC_DEBUGPL(DBG_ANY,"EP%d OUT NAK\n", epnum);
20040+ handle_out_ep_nak_intr(pcd, epnum);
20041+
20042+ CLEAR_OUT_EP_INTR(core_if,epnum,nak);
20043+ }
20044+ /* NYET Interrutp */
20045+ if (doepint.b.nyet) {
20046+ DWC_DEBUGPL(DBG_ANY,"EP%d OUT NYET\n", epnum);
20047+ handle_out_ep_nyet_intr(pcd, epnum);
20048+
20049+ CLEAR_OUT_EP_INTR(core_if,epnum,nyet);
20050+ }
20051+ }
20052+
20053+ epnum++;
20054+ ep_intr >>=1;
20055+ }
20056+
20057+ return 1;
20058+
20059+#undef CLEAR_OUT_EP_INTR
20060+}
20061+
20062+
20063+/**
20064+ * Incomplete ISO IN Transfer Interrupt.
20065+ * This interrupt indicates one of the following conditions occurred
20066+ * while transmitting an ISOC transaction.
20067+ * - Corrupted IN Token for ISOC EP.
20068+ * - Packet not complete in FIFO.
20069+ * The follow actions will be taken:
20070+ * -# Determine the EP
20071+ * -# Set incomplete flag in dwc_ep structure
20072+ * -# Disable EP; when "Endpoint Disabled" interrupt is received
20073+ * Flush FIFO
20074+ */
20075+int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr(dwc_otg_pcd_t *pcd)
20076+{
20077+ gintsts_data_t gintsts;
20078+
20079+
20080+#ifdef DWC_EN_ISOC
20081+ dwc_otg_dev_if_t *dev_if;
20082+ deptsiz_data_t deptsiz = { .d32 = 0};
20083+ depctl_data_t depctl = { .d32 = 0};
20084+ dsts_data_t dsts = { .d32 = 0};
20085+ dwc_ep_t *dwc_ep;
20086+ int i;
20087+
20088+ dev_if = GET_CORE_IF(pcd)->dev_if;
20089+
20090+ for(i = 1; i <= dev_if->num_in_eps; ++i) {
20091+ dwc_ep = &pcd->in_ep[i].dwc_ep;
20092+ if(dwc_ep->active &&
20093+ dwc_ep->type == USB_ENDPOINT_XFER_ISOC)
20094+ {
20095+ deptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->dieptsiz);
20096+ depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl);
20097+
20098+ if(depctl.b.epdis && deptsiz.d32) {
20099+ set_current_pkt_info(GET_CORE_IF(pcd), dwc_ep);
20100+ if(dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
20101+ dwc_ep->cur_pkt = 0;
20102+ dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
20103+
20104+ if(dwc_ep->proc_buf_num) {
20105+ dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
20106+ dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
20107+ } else {
20108+ dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
20109+ dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
20110+ }
20111+ }
20112+
20113+ dsts.d32 = dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if->dev_global_regs->dsts);
20114+ dwc_ep->next_frame = dsts.b.soffn;
20115+
20116+ dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF(pcd), dwc_ep);
20117+ }
20118+ }
20119+ }
20120+
20121+#else
20122+ gintmsk_data_t intr_mask = { .d32 = 0};
20123+ DWC_PRINT("INTERRUPT Handler not implemented for %s\n",
20124+ "IN ISOC Incomplete");
20125+
20126+ intr_mask.b.incomplisoin = 1;
20127+ dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
20128+ intr_mask.d32, 0);
20129+#endif //DWC_EN_ISOC
20130+
20131+ /* Clear interrupt */
20132+ gintsts.d32 = 0;
20133+ gintsts.b.incomplisoin = 1;
20134+ dwc_write_reg32 (&GET_CORE_IF(pcd)->core_global_regs->gintsts,
20135+ gintsts.d32);
20136+
20137+ return 1;
20138+}
20139+
20140+/**
20141+ * Incomplete ISO OUT Transfer Interrupt.
20142+ *
20143+ * This interrupt indicates that the core has dropped an ISO OUT
20144+ * packet. The following conditions can be the cause:
20145+ * - FIFO Full, the entire packet would not fit in the FIFO.
20146+ * - CRC Error
20147+ * - Corrupted Token
20148+ * The follow actions will be taken:
20149+ * -# Determine the EP
20150+ * -# Set incomplete flag in dwc_ep structure
20151+ * -# Read any data from the FIFO
20152+ * -# Disable EP. when "Endpoint Disabled" interrupt is received
20153+ * re-enable EP.
20154+ */
20155+int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr(dwc_otg_pcd_t *pcd)
20156+{
20157+ /* @todo implement ISR */
20158+ gintsts_data_t gintsts;
20159+
20160+#ifdef DWC_EN_ISOC
20161+ dwc_otg_dev_if_t *dev_if;
20162+ deptsiz_data_t deptsiz = { .d32 = 0};
20163+ depctl_data_t depctl = { .d32 = 0};
20164+ dsts_data_t dsts = { .d32 = 0};
20165+ dwc_ep_t *dwc_ep;
20166+ int i;
20167+
20168+ dev_if = GET_CORE_IF(pcd)->dev_if;
20169+
20170+ for(i = 1; i <= dev_if->num_out_eps; ++i) {
20171+ dwc_ep = &pcd->in_ep[i].dwc_ep;
20172+ if(pcd->out_ep[i].dwc_ep.active &&
20173+ pcd->out_ep[i].dwc_ep.type == USB_ENDPOINT_XFER_ISOC)
20174+ {
20175+ deptsiz.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doeptsiz);
20176+ depctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl);
20177+
20178+ if(depctl.b.epdis && deptsiz.d32) {
20179+ set_current_pkt_info(GET_CORE_IF(pcd), &pcd->out_ep[i].dwc_ep);
20180+ if(dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
20181+ dwc_ep->cur_pkt = 0;
20182+ dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
20183+
20184+ if(dwc_ep->proc_buf_num) {
20185+ dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
20186+ dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
20187+ } else {
20188+ dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
20189+ dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
20190+ }
20191+ }
20192+
20193+ dsts.d32 = dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if->dev_global_regs->dsts);
20194+ dwc_ep->next_frame = dsts.b.soffn;
20195+
20196+ dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF(pcd), dwc_ep);
20197+ }
20198+ }
20199+ }
20200+#else
20201+ /** @todo implement ISR */
20202+ gintmsk_data_t intr_mask = { .d32 = 0};
20203+
20204+ DWC_PRINT("INTERRUPT Handler not implemented for %s\n",
20205+ "OUT ISOC Incomplete");
20206+
20207+ intr_mask.b.incomplisoout = 1;
20208+ dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
20209+ intr_mask.d32, 0);
20210+
20211+#endif // DWC_EN_ISOC
20212+
20213+ /* Clear interrupt */
20214+ gintsts.d32 = 0;
20215+ gintsts.b.incomplisoout = 1;
20216+ dwc_write_reg32 (&GET_CORE_IF(pcd)->core_global_regs->gintsts,
20217+ gintsts.d32);
20218+
20219+ return 1;
20220+}
20221+
20222+/**
20223+ * This function handles the Global IN NAK Effective interrupt.
20224+ *
20225+ */
20226+int32_t dwc_otg_pcd_handle_in_nak_effective(dwc_otg_pcd_t *pcd)
20227+{
20228+ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
20229+ depctl_data_t diepctl = { .d32 = 0};
20230+ depctl_data_t diepctl_rd = { .d32 = 0};
20231+ gintmsk_data_t intr_mask = { .d32 = 0};
20232+ gintsts_data_t gintsts;
20233+ int i;
20234+
20235+ DWC_DEBUGPL(DBG_PCD, "Global IN NAK Effective\n");
20236+
20237+ /* Disable all active IN EPs */
20238+ diepctl.b.epdis = 1;
20239+ diepctl.b.snak = 1;
20240+
20241+ for (i=0; i <= dev_if->num_in_eps; i++)
20242+ {
20243+ diepctl_rd.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl);
20244+ if (diepctl_rd.b.epena) {
20245+ dwc_write_reg32(&dev_if->in_ep_regs[i]->diepctl,
20246+ diepctl.d32);
20247+ }
20248+ }
20249+ /* Disable the Global IN NAK Effective Interrupt */
20250+ intr_mask.b.ginnakeff = 1;
20251+ dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
20252+ intr_mask.d32, 0);
20253+
20254+ /* Clear interrupt */
20255+ gintsts.d32 = 0;
20256+ gintsts.b.ginnakeff = 1;
20257+ dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
20258+ gintsts.d32);
20259+
20260+ return 1;
20261+}
20262+
20263+/**
20264+ * OUT NAK Effective.
20265+ *
20266+ */
20267+int32_t dwc_otg_pcd_handle_out_nak_effective(dwc_otg_pcd_t *pcd)
20268+{
20269+ gintmsk_data_t intr_mask = { .d32 = 0};
20270+ gintsts_data_t gintsts;
20271+
20272+ DWC_PRINT("INTERRUPT Handler not implemented for %s\n",
20273+ "Global IN NAK Effective\n");
20274+ /* Disable the Global IN NAK Effective Interrupt */
20275+ intr_mask.b.goutnakeff = 1;
20276+ dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
20277+ intr_mask.d32, 0);
20278+
20279+ /* Clear interrupt */
20280+ gintsts.d32 = 0;
20281+ gintsts.b.goutnakeff = 1;
20282+ dwc_write_reg32 (&GET_CORE_IF(pcd)->core_global_regs->gintsts,
20283+ gintsts.d32);
20284+
20285+ return 1;
20286+}
20287+
20288+
20289+/**
20290+ * PCD interrupt handler.
20291+ *
20292+ * The PCD handles the device interrupts. Many conditions can cause a
20293+ * device interrupt. When an interrupt occurs, the device interrupt
20294+ * service routine determines the cause of the interrupt and
20295+ * dispatches handling to the appropriate function. These interrupt
20296+ * handling functions are described below.
20297+ *
20298+ * All interrupt registers are processed from LSB to MSB.
20299+ *
20300+ */
20301+int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t *pcd)
20302+{
20303+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
20304+#ifdef VERBOSE
20305+ dwc_otg_core_global_regs_t *global_regs =
20306+ core_if->core_global_regs;
20307+#endif
20308+ gintsts_data_t gintr_status;
20309+ int32_t retval = 0;
20310+
20311+
20312+#ifdef VERBOSE
20313+ DWC_DEBUGPL(DBG_ANY, "%s() gintsts=%08x gintmsk=%08x\n",
20314+ __func__,
20315+ dwc_read_reg32(&global_regs->gintsts),
20316+ dwc_read_reg32(&global_regs->gintmsk));
20317+#endif
20318+
20319+ if (dwc_otg_is_device_mode(core_if)) {
20320+ SPIN_LOCK(&pcd->lock);
20321+#ifdef VERBOSE
20322+ DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%08x gintmsk=%08x\n",
20323+ __func__,
20324+ dwc_read_reg32(&global_regs->gintsts),
20325+ dwc_read_reg32(&global_regs->gintmsk));
20326+#endif
20327+
20328+ gintr_status.d32 = dwc_otg_read_core_intr(core_if);
20329+/*
20330+ if (!gintr_status.d32) {
20331+ SPIN_UNLOCK(&pcd->lock);
20332+ return 0;
20333+ }
20334+*/
20335+ DWC_DEBUGPL(DBG_PCDV, "%s: gintsts&gintmsk=%08x\n",
20336+ __func__, gintr_status.d32);
20337+
20338+ if (gintr_status.b.sofintr) {
20339+ retval |= dwc_otg_pcd_handle_sof_intr(pcd);
20340+ }
20341+ if (gintr_status.b.rxstsqlvl) {
20342+ retval |= dwc_otg_pcd_handle_rx_status_q_level_intr(pcd);
20343+ }
20344+ if (gintr_status.b.nptxfempty) {
20345+ retval |= dwc_otg_pcd_handle_np_tx_fifo_empty_intr(pcd);
20346+ }
20347+ if (gintr_status.b.ginnakeff) {
20348+ retval |= dwc_otg_pcd_handle_in_nak_effective(pcd);
20349+ }
20350+ if (gintr_status.b.goutnakeff) {
20351+ retval |= dwc_otg_pcd_handle_out_nak_effective(pcd);
20352+ }
20353+ if (gintr_status.b.i2cintr) {
20354+ retval |= dwc_otg_pcd_handle_i2c_intr(pcd);
20355+ }
20356+ if (gintr_status.b.erlysuspend) {
20357+ retval |= dwc_otg_pcd_handle_early_suspend_intr(pcd);
20358+ }
20359+ if (gintr_status.b.usbreset) {
20360+ retval |= dwc_otg_pcd_handle_usb_reset_intr(pcd);
20361+ }
20362+ if (gintr_status.b.enumdone) {
20363+ retval |= dwc_otg_pcd_handle_enum_done_intr(pcd);
20364+ }
20365+ if (gintr_status.b.isooutdrop) {
20366+ retval |= dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(pcd);
20367+ }
20368+ if (gintr_status.b.eopframe) {
20369+ retval |= dwc_otg_pcd_handle_end_periodic_frame_intr(pcd);
20370+ }
20371+ if (gintr_status.b.epmismatch) {
20372+ retval |= dwc_otg_pcd_handle_ep_mismatch_intr(core_if);
20373+ }
20374+ if (gintr_status.b.inepint) {
20375+ if(!core_if->multiproc_int_enable) {
20376+ retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
20377+ }
20378+ }
20379+ if (gintr_status.b.outepintr) {
20380+ if(!core_if->multiproc_int_enable) {
20381+ retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
20382+ }
20383+ }
20384+ if (gintr_status.b.incomplisoin) {
20385+ retval |= dwc_otg_pcd_handle_incomplete_isoc_in_intr(pcd);
20386+ }
20387+ if (gintr_status.b.incomplisoout) {
20388+ retval |= dwc_otg_pcd_handle_incomplete_isoc_out_intr(pcd);
20389+ }
20390+
20391+ /* In MPI mode De vice Endpoints intterrupts are asserted
20392+ * without setting outepintr and inepint bits set, so these
20393+ * Interrupt handlers are called without checking these bit-fields
20394+ */
20395+ if(core_if->multiproc_int_enable) {
20396+ retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
20397+ retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
20398+ }
20399+#ifdef VERBOSE
20400+ DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%0x\n", __func__,
20401+ dwc_read_reg32(&global_regs->gintsts));
20402+#endif
20403+ SPIN_UNLOCK(&pcd->lock);
20404+ }
20405+ S3C2410X_CLEAR_EINTPEND();
20406+
20407+ return retval;
20408+}
20409+
20410+#endif /* DWC_HOST_ONLY */
20411--- /dev/null
20412+++ b/drivers/usb/dwc/otg_plat.h
20413@@ -0,0 +1,266 @@
20414+/* ==========================================================================
20415+ * $File: //dwh/usb_iip/dev/software/otg/linux/platform/dwc_otg_plat.h $
20416+ * $Revision: #23 $
20417+ * $Date: 2008/07/15 $
20418+ * $Change: 1064915 $
20419+ *
20420+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
20421+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
20422+ * otherwise expressly agreed to in writing between Synopsys and you.
20423+ *
20424+ * The Software IS NOT an item of Licensed Software or Licensed Product under
20425+ * any End User Software License Agreement or Agreement for Licensed Product
20426+ * with Synopsys or any supplement thereto. You are permitted to use and
20427+ * redistribute this Software in source and binary forms, with or without
20428+ * modification, provided that redistributions of source code must retain this
20429+ * notice. You may not view, use, disclose, copy or distribute this file or
20430+ * any information contained herein except pursuant to this license grant from
20431+ * Synopsys. If you do not agree with this notice, including the disclaimer
20432+ * below, then you are not authorized to use the Software.
20433+ *
20434+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
20435+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20436+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20437+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
20438+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20439+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
20440+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
20441+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
20442+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
20443+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
20444+ * DAMAGE.
20445+ * ========================================================================== */
20446+
20447+#if !defined(__DWC_OTG_PLAT_H__)
20448+#define __DWC_OTG_PLAT_H__
20449+
20450+#include <linux/types.h>
20451+#include <linux/slab.h>
20452+#include <linux/list.h>
20453+#include <linux/delay.h>
20454+#include <asm/io.h>
20455+
20456+/* Changed all readl and writel to __raw_readl, __raw_writel */
20457+
20458+/**
20459+ * @file
20460+ *
20461+ * This file contains the Platform Specific constants, interfaces
20462+ * (functions and macros) for Linux.
20463+ *
20464+ */
20465+//#if !defined(__LINUX_ARM_ARCH__)
20466+//#error "The contents of this file is Linux specific!!!"
20467+//#endif
20468+
20469+/**
20470+ * Reads the content of a register.
20471+ *
20472+ * @param reg address of register to read.
20473+ * @return contents of the register.
20474+ *
20475+
20476+ * Usage:<br>
20477+ * <code>uint32_t dev_ctl = dwc_read_reg32(&dev_regs->dctl);</code>
20478+ */
20479+static __inline__ uint32_t dwc_read_reg32( volatile uint32_t *reg)
20480+{
20481+ return __raw_readl(reg);
20482+ // return readl(reg);
20483+};
20484+
20485+/**
20486+ * Writes a register with a 32 bit value.
20487+ *
20488+ * @param reg address of register to read.
20489+ * @param value to write to _reg.
20490+ *
20491+ * Usage:<br>
20492+ * <code>dwc_write_reg32(&dev_regs->dctl, 0); </code>
20493+ */
20494+static __inline__ void dwc_write_reg32( volatile uint32_t *reg, const uint32_t value)
20495+{
20496+ // writel( value, reg );
20497+ __raw_writel(value, reg);
20498+
20499+};
20500+
20501+/**
20502+ * This function modifies bit values in a register. Using the
20503+ * algorithm: (reg_contents & ~clear_mask) | set_mask.
20504+ *
20505+ * @param reg address of register to read.
20506+ * @param clear_mask bit mask to be cleared.
20507+ * @param set_mask bit mask to be set.
20508+ *
20509+ * Usage:<br>
20510+ * <code> // Clear the SOF Interrupt Mask bit and <br>
20511+ * // set the OTG Interrupt mask bit, leaving all others as they were.
20512+ * dwc_modify_reg32(&dev_regs->gintmsk, DWC_SOF_INT, DWC_OTG_INT);</code>
20513+ */
20514+static __inline__
20515+ void dwc_modify_reg32( volatile uint32_t *reg, const uint32_t clear_mask, const uint32_t set_mask)
20516+{
20517+ // writel( (readl(reg) & ~clear_mask) | set_mask, reg );
20518+ __raw_writel( (__raw_readl(reg) & ~clear_mask) | set_mask, reg );
20519+};
20520+
20521+
20522+/**
20523+ * Wrapper for the OS micro-second delay function.
20524+ * @param[in] usecs Microseconds of delay
20525+ */
20526+static __inline__ void UDELAY( const uint32_t usecs )
20527+{
20528+ udelay( usecs );
20529+}
20530+
20531+/**
20532+ * Wrapper for the OS milli-second delay function.
20533+ * @param[in] msecs milliseconds of delay
20534+ */
20535+static __inline__ void MDELAY( const uint32_t msecs )
20536+{
20537+ mdelay( msecs );
20538+}
20539+
20540+/**
20541+ * Wrapper for the Linux spin_lock. On the ARM (Integrator)
20542+ * spin_lock() is a nop.
20543+ *
20544+ * @param lock Pointer to the spinlock.
20545+ */
20546+static __inline__ void SPIN_LOCK( spinlock_t *lock )
20547+{
20548+ spin_lock(lock);
20549+}
20550+
20551+/**
20552+ * Wrapper for the Linux spin_unlock. On the ARM (Integrator)
20553+ * spin_lock() is a nop.
20554+ *
20555+ * @param lock Pointer to the spinlock.
20556+ */
20557+static __inline__ void SPIN_UNLOCK( spinlock_t *lock )
20558+{
20559+ spin_unlock(lock);
20560+}
20561+
20562+/**
20563+ * Wrapper (macro) for the Linux spin_lock_irqsave. On the ARM
20564+ * (Integrator) spin_lock() is a nop.
20565+ *
20566+ * @param l Pointer to the spinlock.
20567+ * @param f unsigned long for irq flags storage.
20568+ */
20569+#define SPIN_LOCK_IRQSAVE( l, f ) spin_lock_irqsave(l,f);
20570+
20571+/**
20572+ * Wrapper (macro) for the Linux spin_unlock_irqrestore. On the ARM
20573+ * (Integrator) spin_lock() is a nop.
20574+ *
20575+ * @param l Pointer to the spinlock.
20576+ * @param f unsigned long for irq flags storage.
20577+ */
20578+#define SPIN_UNLOCK_IRQRESTORE( l,f ) spin_unlock_irqrestore(l,f);
20579+
20580+/*
20581+ * Debugging support vanishes in non-debug builds.
20582+ */
20583+
20584+
20585+/**
20586+ * The Debug Level bit-mask variable.
20587+ */
20588+extern uint32_t g_dbg_lvl;
20589+/**
20590+ * Set the Debug Level variable.
20591+ */
20592+static inline uint32_t SET_DEBUG_LEVEL( const uint32_t new )
20593+{
20594+ uint32_t old = g_dbg_lvl;
20595+ g_dbg_lvl = new;
20596+ return old;
20597+}
20598+
20599+/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */
20600+#define DBG_CIL (0x2)
20601+/** When debug level has the DBG_CILV bit set, display CIL Verbose debug
20602+ * messages */
20603+#define DBG_CILV (0x20)
20604+/** When debug level has the DBG_PCD bit set, display PCD (Device) debug
20605+ * messages */
20606+#define DBG_PCD (0x4)
20607+/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug
20608+ * messages */
20609+#define DBG_PCDV (0x40)
20610+/** When debug level has the DBG_HCD bit set, display Host debug messages */
20611+#define DBG_HCD (0x8)
20612+/** When debug level has the DBG_HCDV bit set, display Verbose Host debug
20613+ * messages */
20614+#define DBG_HCDV (0x80)
20615+/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host
20616+ * mode. */
20617+#define DBG_HCD_URB (0x800)
20618+
20619+/** When debug level has any bit set, display debug messages */
20620+#define DBG_ANY (0xFF)
20621+
20622+/** All debug messages off */
20623+#define DBG_OFF 0
20624+
20625+/** Prefix string for DWC_DEBUG print macros. */
20626+#define USB_DWC "DWC_otg: "
20627+
20628+/**
20629+ * Print a debug message when the Global debug level variable contains
20630+ * the bit defined in <code>lvl</code>.
20631+ *
20632+ * @param[in] lvl - Debug level, use one of the DBG_ constants above.
20633+ * @param[in] x - like printf
20634+ *
20635+ * Example:<p>
20636+ * <code>
20637+ * DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr);
20638+ * </code>
20639+ * <br>
20640+ * results in:<br>
20641+ * <code>
20642+ * usb-DWC_otg: dwc_otg_cil_init(ca867000)
20643+ * </code>
20644+ */
20645+#ifdef DEBUG
20646+
20647+# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)printk( KERN_DEBUG USB_DWC x ); }while(0)
20648+# define DWC_DEBUGP(x...) DWC_DEBUGPL(DBG_ANY, x )
20649+
20650+# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl)
20651+
20652+#else
20653+
20654+# define DWC_DEBUGPL(lvl, x...) do{}while(0)
20655+# define DWC_DEBUGP(x...)
20656+
20657+# define CHK_DEBUG_LEVEL(level) (0)
20658+
20659+#endif /*DEBUG*/
20660+
20661+/**
20662+ * Print an Error message.
20663+ */
20664+#define DWC_ERROR(x...) printk( KERN_ERR USB_DWC x )
20665+/**
20666+ * Print a Warning message.
20667+ */
20668+#define DWC_WARN(x...) printk( KERN_WARNING USB_DWC x )
20669+/**
20670+ * Print a notice (normal but significant message).
20671+ */
20672+#define DWC_NOTICE(x...) printk( KERN_NOTICE USB_DWC x )
20673+/**
20674+ * Basic message printing.
20675+ */
20676+#define DWC_PRINT(x...) printk( KERN_INFO USB_DWC x )
20677+
20678+#endif
20679+
20680--- /dev/null
20681+++ b/drivers/usb/dwc/otg_regs.h
20682@@ -0,0 +1,2059 @@
20683+/* ==========================================================================
20684+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $
20685+ * $Revision: #72 $
20686+ * $Date: 2008/09/19 $
20687+ * $Change: 1099526 $
20688+ *
20689+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
20690+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
20691+ * otherwise expressly agreed to in writing between Synopsys and you.
20692+ *
20693+ * The Software IS NOT an item of Licensed Software or Licensed Product under
20694+ * any End User Software License Agreement or Agreement for Licensed Product
20695+ * with Synopsys or any supplement thereto. You are permitted to use and
20696+ * redistribute this Software in source and binary forms, with or without
20697+ * modification, provided that redistributions of source code must retain this
20698+ * notice. You may not view, use, disclose, copy or distribute this file or
20699+ * any information contained herein except pursuant to this license grant from
20700+ * Synopsys. If you do not agree with this notice, including the disclaimer
20701+ * below, then you are not authorized to use the Software.
20702+ *
20703+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
20704+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20705+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20706+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
20707+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20708+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
20709+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
20710+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
20711+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
20712+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
20713+ * DAMAGE.
20714+ * ========================================================================== */
20715+
20716+#ifndef __DWC_OTG_REGS_H__
20717+#define __DWC_OTG_REGS_H__
20718+
20719+/**
20720+ * @file
20721+ *
20722+ * This file contains the data structures for accessing the DWC_otg core registers.
20723+ *
20724+ * The application interfaces with the HS OTG core by reading from and
20725+ * writing to the Control and Status Register (CSR) space through the
20726+ * AHB Slave interface. These registers are 32 bits wide, and the
20727+ * addresses are 32-bit-block aligned.
20728+ * CSRs are classified as follows:
20729+ * - Core Global Registers
20730+ * - Device Mode Registers
20731+ * - Device Global Registers
20732+ * - Device Endpoint Specific Registers
20733+ * - Host Mode Registers
20734+ * - Host Global Registers
20735+ * - Host Port CSRs
20736+ * - Host Channel Specific Registers
20737+ *
20738+ * Only the Core Global registers can be accessed in both Device and
20739+ * Host modes. When the HS OTG core is operating in one mode, either
20740+ * Device or Host, the application must not access registers from the
20741+ * other mode. When the core switches from one mode to another, the
20742+ * registers in the new mode of operation must be reprogrammed as they
20743+ * would be after a power-on reset.
20744+ */
20745+
20746+/** Maximum number of Periodic FIFOs */
20747+#define MAX_PERIO_FIFOS 15
20748+/** Maximum number of Transmit FIFOs */
20749+#define MAX_TX_FIFOS 15
20750+
20751+/** Maximum number of Endpoints/HostChannels */
20752+#define MAX_EPS_CHANNELS 16
20753+
20754+/****************************************************************************/
20755+/** DWC_otg Core registers .
20756+ * The dwc_otg_core_global_regs structure defines the size
20757+ * and relative field offsets for the Core Global registers.
20758+ */
20759+typedef struct dwc_otg_core_global_regs
20760+{
20761+ /** OTG Control and Status Register. <i>Offset: 000h</i> */
20762+ volatile uint32_t gotgctl;
20763+ /** OTG Interrupt Register. <i>Offset: 004h</i> */
20764+ volatile uint32_t gotgint;
20765+ /**Core AHB Configuration Register. <i>Offset: 008h</i> */
20766+ volatile uint32_t gahbcfg;
20767+
20768+#define DWC_GLBINTRMASK 0x0001
20769+#define DWC_DMAENABLE 0x0020
20770+#define DWC_NPTXEMPTYLVL_EMPTY 0x0080
20771+#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000
20772+#define DWC_PTXEMPTYLVL_EMPTY 0x0100
20773+#define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000
20774+
20775+ /**Core USB Configuration Register. <i>Offset: 00Ch</i> */
20776+ volatile uint32_t gusbcfg;
20777+ /**Core Reset Register. <i>Offset: 010h</i> */
20778+ volatile uint32_t grstctl;
20779+ /**Core Interrupt Register. <i>Offset: 014h</i> */
20780+ volatile uint32_t gintsts;
20781+ /**Core Interrupt Mask Register. <i>Offset: 018h</i> */
20782+ volatile uint32_t gintmsk;
20783+ /**Receive Status Queue Read Register (Read Only). <i>Offset: 01Ch</i> */
20784+ volatile uint32_t grxstsr;
20785+ /**Receive Status Queue Read & POP Register (Read Only). <i>Offset: 020h</i>*/
20786+ volatile uint32_t grxstsp;
20787+ /**Receive FIFO Size Register. <i>Offset: 024h</i> */
20788+ volatile uint32_t grxfsiz;
20789+ /**Non Periodic Transmit FIFO Size Register. <i>Offset: 028h</i> */
20790+ volatile uint32_t gnptxfsiz;
20791+ /**Non Periodic Transmit FIFO/Queue Status Register (Read
20792+ * Only). <i>Offset: 02Ch</i> */
20793+ volatile uint32_t gnptxsts;
20794+ /**I2C Access Register. <i>Offset: 030h</i> */
20795+ volatile uint32_t gi2cctl;
20796+ /**PHY Vendor Control Register. <i>Offset: 034h</i> */
20797+ volatile uint32_t gpvndctl;
20798+ /**General Purpose Input/Output Register. <i>Offset: 038h</i> */
20799+ volatile uint32_t ggpio;
20800+ /**User ID Register. <i>Offset: 03Ch</i> */
20801+ volatile uint32_t guid;
20802+ /**Synopsys ID Register (Read Only). <i>Offset: 040h</i> */
20803+ volatile uint32_t gsnpsid;
20804+ /**User HW Config1 Register (Read Only). <i>Offset: 044h</i> */
20805+ volatile uint32_t ghwcfg1;
20806+ /**User HW Config2 Register (Read Only). <i>Offset: 048h</i> */
20807+ volatile uint32_t ghwcfg2;
20808+#define DWC_SLAVE_ONLY_ARCH 0
20809+#define DWC_EXT_DMA_ARCH 1
20810+#define DWC_INT_DMA_ARCH 2
20811+
20812+#define DWC_MODE_HNP_SRP_CAPABLE 0
20813+#define DWC_MODE_SRP_ONLY_CAPABLE 1
20814+#define DWC_MODE_NO_HNP_SRP_CAPABLE 2
20815+#define DWC_MODE_SRP_CAPABLE_DEVICE 3
20816+#define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4
20817+#define DWC_MODE_SRP_CAPABLE_HOST 5
20818+#define DWC_MODE_NO_SRP_CAPABLE_HOST 6
20819+
20820+ /**User HW Config3 Register (Read Only). <i>Offset: 04Ch</i> */
20821+ volatile uint32_t ghwcfg3;
20822+ /**User HW Config4 Register (Read Only). <i>Offset: 050h</i>*/
20823+ volatile uint32_t ghwcfg4;
20824+ /** Reserved <i>Offset: 054h-0FFh</i> */
20825+ volatile uint32_t reserved[43];
20826+ /** Host Periodic Transmit FIFO Size Register. <i>Offset: 100h</i> */
20827+ volatile uint32_t hptxfsiz;
20828+ /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled,
20829+ otherwise Device Transmit FIFO#n Register.
20830+ * <i>Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15).</i> */
20831+ volatile uint32_t dptxfsiz_dieptxf[15];
20832+} dwc_otg_core_global_regs_t;
20833+
20834+/**
20835+ * This union represents the bit fields of the Core OTG Control
20836+ * and Status Register (GOTGCTL). Set the bits using the bit
20837+ * fields then write the <i>d32</i> value to the register.
20838+ */
20839+typedef union gotgctl_data
20840+{
20841+ /** raw register data */
20842+ uint32_t d32;
20843+ /** register bits */
20844+ struct
20845+ {
20846+ unsigned sesreqscs : 1;
20847+ unsigned sesreq : 1;
20848+ unsigned reserved2_7 : 6;
20849+ unsigned hstnegscs : 1;
20850+ unsigned hnpreq : 1;
20851+ unsigned hstsethnpen : 1;
20852+ unsigned devhnpen : 1;
20853+ unsigned reserved12_15 : 4;
20854+ unsigned conidsts : 1;
20855+ unsigned reserved17 : 1;
20856+ unsigned asesvld : 1;
20857+ unsigned bsesvld : 1;
20858+ unsigned currmod : 1;
20859+ unsigned reserved21_31 : 11;
20860+ } b;
20861+} gotgctl_data_t;
20862+
20863+/**
20864+ * This union represents the bit fields of the Core OTG Interrupt Register
20865+ * (GOTGINT). Set/clear the bits using the bit fields then write the <i>d32</i>
20866+ * value to the register.
20867+ */
20868+typedef union gotgint_data
20869+{
20870+ /** raw register data */
20871+ uint32_t d32;
20872+ /** register bits */
20873+ struct
20874+ {
20875+ /** Current Mode */
20876+ unsigned reserved0_1 : 2;
20877+
20878+ /** Session End Detected */
20879+ unsigned sesenddet : 1;
20880+
20881+ unsigned reserved3_7 : 5;
20882+
20883+ /** Session Request Success Status Change */
20884+ unsigned sesreqsucstschng : 1;
20885+ /** Host Negotiation Success Status Change */
20886+ unsigned hstnegsucstschng : 1;
20887+
20888+ unsigned reserver10_16 : 7;
20889+
20890+ /** Host Negotiation Detected */
20891+ unsigned hstnegdet : 1;
20892+ /** A-Device Timeout Change */
20893+ unsigned adevtoutchng : 1;
20894+ /** Debounce Done */
20895+ unsigned debdone : 1;
20896+
20897+ unsigned reserved31_20 : 12;
20898+
20899+ } b;
20900+} gotgint_data_t;
20901+
20902+
20903+/**
20904+ * This union represents the bit fields of the Core AHB Configuration
20905+ * Register (GAHBCFG). Set/clear the bits using the bit fields then
20906+ * write the <i>d32</i> value to the register.
20907+ */
20908+typedef union gahbcfg_data
20909+{
20910+ /** raw register data */
20911+ uint32_t d32;
20912+ /** register bits */
20913+ struct
20914+ {
20915+ unsigned glblintrmsk : 1;
20916+#define DWC_GAHBCFG_GLBINT_ENABLE 1
20917+
20918+ unsigned hburstlen : 4;
20919+#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0
20920+#define DWC_GAHBCFG_INT_DMA_BURST_INCR 1
20921+#define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3
20922+#define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5
20923+#define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7
20924+
20925+ unsigned dmaenable : 1;
20926+#define DWC_GAHBCFG_DMAENABLE 1
20927+ unsigned reserved : 1;
20928+ unsigned nptxfemplvl_txfemplvl : 1;
20929+ unsigned ptxfemplvl : 1;
20930+#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1
20931+#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
20932+ unsigned reserved9_31 : 23;
20933+ } b;
20934+} gahbcfg_data_t;
20935+
20936+/**
20937+ * This union represents the bit fields of the Core USB Configuration
20938+ * Register (GUSBCFG). Set the bits using the bit fields then write
20939+ * the <i>d32</i> value to the register.
20940+ */
20941+typedef union gusbcfg_data
20942+{
20943+ /** raw register data */
20944+ uint32_t d32;
20945+ /** register bits */
20946+ struct
20947+ {
20948+ unsigned toutcal : 3;
20949+ unsigned phyif : 1;
20950+ unsigned ulpi_utmi_sel : 1;
20951+ unsigned fsintf : 1;
20952+ unsigned physel : 1;
20953+ unsigned ddrsel : 1;
20954+ unsigned srpcap : 1;
20955+ unsigned hnpcap : 1;
20956+ unsigned usbtrdtim : 4;
20957+ unsigned nptxfrwnden : 1;
20958+ unsigned phylpwrclksel : 1;
20959+ unsigned otgutmifssel : 1;
20960+ unsigned ulpi_fsls : 1;
20961+ unsigned ulpi_auto_res : 1;
20962+ unsigned ulpi_clk_sus_m : 1;
20963+ unsigned ulpi_ext_vbus_drv : 1;
20964+ unsigned ulpi_int_vbus_indicator : 1;
20965+ unsigned term_sel_dl_pulse : 1;
20966+ unsigned reserved23_27 : 5;
20967+ unsigned tx_end_delay : 1;
20968+ unsigned reserved29_31 : 3;
20969+ } b;
20970+} gusbcfg_data_t;
20971+
20972+/**
20973+ * This union represents the bit fields of the Core Reset Register
20974+ * (GRSTCTL). Set/clear the bits using the bit fields then write the
20975+ * <i>d32</i> value to the register.
20976+ */
20977+typedef union grstctl_data
20978+{
20979+ /** raw register data */
20980+ uint32_t d32;
20981+ /** register bits */
20982+ struct
20983+ {
20984+ /** Core Soft Reset (CSftRst) (Device and Host)
20985+ *
20986+ * The application can flush the control logic in the
20987+ * entire core using this bit. This bit resets the
20988+ * pipelines in the AHB Clock domain as well as the
20989+ * PHY Clock domain.
20990+ *
20991+ * The state machines are reset to an IDLE state, the
20992+ * control bits in the CSRs are cleared, all the
20993+ * transmit FIFOs and the receive FIFO are flushed.
20994+ *
20995+ * The status mask bits that control the generation of
20996+ * the interrupt, are cleared, to clear the
20997+ * interrupt. The interrupt status bits are not
20998+ * cleared, so the application can get the status of
20999+ * any events that occurred in the core after it has
21000+ * set this bit.
21001+ *
21002+ * Any transactions on the AHB are terminated as soon
21003+ * as possible following the protocol. Any
21004+ * transactions on the USB are terminated immediately.
21005+ *
21006+ * The configuration settings in the CSRs are
21007+ * unchanged, so the software doesn't have to
21008+ * reprogram these registers (Device
21009+ * Configuration/Host Configuration/Core System
21010+ * Configuration/Core PHY Configuration).
21011+ *
21012+ * The application can write to this bit, any time it
21013+ * wants to reset the core. This is a self clearing
21014+ * bit and the core clears this bit after all the
21015+ * necessary logic is reset in the core, which may
21016+ * take several clocks, depending on the current state
21017+ * of the core.
21018+ */
21019+ unsigned csftrst : 1;
21020+ /** Hclk Soft Reset
21021+ *
21022+ * The application uses this bit to reset the control logic in
21023+ * the AHB clock domain. Only AHB clock domain pipelines are
21024+ * reset.
21025+ */
21026+ unsigned hsftrst : 1;
21027+ /** Host Frame Counter Reset (Host Only)<br>
21028+ *
21029+ * The application can reset the (micro)frame number
21030+ * counter inside the core, using this bit. When the
21031+ * (micro)frame counter is reset, the subsequent SOF
21032+ * sent out by the core, will have a (micro)frame
21033+ * number of 0.
21034+ */
21035+ unsigned hstfrm : 1;
21036+ /** In Token Sequence Learning Queue Flush
21037+ * (INTknQFlsh) (Device Only)
21038+ */
21039+ unsigned intknqflsh : 1;
21040+ /** RxFIFO Flush (RxFFlsh) (Device and Host)
21041+ *
21042+ * The application can flush the entire Receive FIFO
21043+ * using this bit. <p>The application must first
21044+ * ensure that the core is not in the middle of a
21045+ * transaction. <p>The application should write into
21046+ * this bit, only after making sure that neither the
21047+ * DMA engine is reading from the RxFIFO nor the MAC
21048+ * is writing the data in to the FIFO. <p>The
21049+ * application should wait until the bit is cleared
21050+ * before performing any other operations. This bit
21051+ * will takes 8 clocks (slowest of PHY or AHB clock)
21052+ * to clear.
21053+ */
21054+ unsigned rxfflsh : 1;
21055+ /** TxFIFO Flush (TxFFlsh) (Device and Host).
21056+ *
21057+ * This bit is used to selectively flush a single or
21058+ * all transmit FIFOs. The application must first
21059+ * ensure that the core is not in the middle of a
21060+ * transaction. <p>The application should write into
21061+ * this bit, only after making sure that neither the
21062+ * DMA engine is writing into the TxFIFO nor the MAC
21063+ * is reading the data out of the FIFO. <p>The
21064+ * application should wait until the core clears this
21065+ * bit, before performing any operations. This bit
21066+ * will takes 8 clocks (slowest of PHY or AHB clock)
21067+ * to clear.
21068+ */
21069+ unsigned txfflsh : 1;
21070+ /** TxFIFO Number (TxFNum) (Device and Host).
21071+ *
21072+ * This is the FIFO number which needs to be flushed,
21073+ * using the TxFIFO Flush bit. This field should not
21074+ * be changed until the TxFIFO Flush bit is cleared by
21075+ * the core.
21076+ * - 0x0 : Non Periodic TxFIFO Flush
21077+ * - 0x1 : Periodic TxFIFO #1 Flush in device mode
21078+ * or Periodic TxFIFO in host mode
21079+ * - 0x2 : Periodic TxFIFO #2 Flush in device mode.
21080+ * - ...
21081+ * - 0xF : Periodic TxFIFO #15 Flush in device mode
21082+ * - 0x10: Flush all the Transmit NonPeriodic and
21083+ * Transmit Periodic FIFOs in the core
21084+ */
21085+ unsigned txfnum : 5;
21086+ /** Reserved */
21087+ unsigned reserved11_29 : 19;
21088+ /** DMA Request Signal. Indicated DMA request is in
21089+ * probress. Used for debug purpose. */
21090+ unsigned dmareq : 1;
21091+ /** AHB Master Idle. Indicates the AHB Master State
21092+ * Machine is in IDLE condition. */
21093+ unsigned ahbidle : 1;
21094+ } b;
21095+} grstctl_t;
21096+
21097+
21098+/**
21099+ * This union represents the bit fields of the Core Interrupt Mask
21100+ * Register (GINTMSK). Set/clear the bits using the bit fields then
21101+ * write the <i>d32</i> value to the register.
21102+ */
21103+typedef union gintmsk_data
21104+{
21105+ /** raw register data */
21106+ uint32_t d32;
21107+ /** register bits */
21108+ struct
21109+ {
21110+ unsigned reserved0 : 1;
21111+ unsigned modemismatch : 1;
21112+ unsigned otgintr : 1;
21113+ unsigned sofintr : 1;
21114+ unsigned rxstsqlvl : 1;
21115+ unsigned nptxfempty : 1;
21116+ unsigned ginnakeff : 1;
21117+ unsigned goutnakeff : 1;
21118+ unsigned reserved8 : 1;
21119+ unsigned i2cintr : 1;
21120+ unsigned erlysuspend : 1;
21121+ unsigned usbsuspend : 1;
21122+ unsigned usbreset : 1;
21123+ unsigned enumdone : 1;
21124+ unsigned isooutdrop : 1;
21125+ unsigned eopframe : 1;
21126+ unsigned reserved16 : 1;
21127+ unsigned epmismatch : 1;
21128+ unsigned inepintr : 1;
21129+ unsigned outepintr : 1;
21130+ unsigned incomplisoin : 1;
21131+ unsigned incomplisoout : 1;
21132+ unsigned reserved22_23 : 2;
21133+ unsigned portintr : 1;
21134+ unsigned hcintr : 1;
21135+ unsigned ptxfempty : 1;
21136+ unsigned reserved27 : 1;
21137+ unsigned conidstschng : 1;
21138+ unsigned disconnect : 1;
21139+ unsigned sessreqintr : 1;
21140+ unsigned wkupintr : 1;
21141+ } b;
21142+} gintmsk_data_t;
21143+/**
21144+ * This union represents the bit fields of the Core Interrupt Register
21145+ * (GINTSTS). Set/clear the bits using the bit fields then write the
21146+ * <i>d32</i> value to the register.
21147+ */
21148+typedef union gintsts_data
21149+{
21150+ /** raw register data */
21151+ uint32_t d32;
21152+#define DWC_SOF_INTR_MASK 0x0008
21153+ /** register bits */
21154+ struct
21155+ {
21156+#define DWC_HOST_MODE 1
21157+ unsigned curmode : 1;
21158+ unsigned modemismatch : 1;
21159+ unsigned otgintr : 1;
21160+ unsigned sofintr : 1;
21161+ unsigned rxstsqlvl : 1;
21162+ unsigned nptxfempty : 1;
21163+ unsigned ginnakeff : 1;
21164+ unsigned goutnakeff : 1;
21165+ unsigned reserved8 : 1;
21166+ unsigned i2cintr : 1;
21167+ unsigned erlysuspend : 1;
21168+ unsigned usbsuspend : 1;
21169+ unsigned usbreset : 1;
21170+ unsigned enumdone : 1;
21171+ unsigned isooutdrop : 1;
21172+ unsigned eopframe : 1;
21173+ unsigned intokenrx : 1;
21174+ unsigned epmismatch : 1;
21175+ unsigned inepint: 1;
21176+ unsigned outepintr : 1;
21177+ unsigned incomplisoin : 1;
21178+ unsigned incomplisoout : 1;
21179+ unsigned reserved22_23 : 2;
21180+ unsigned portintr : 1;
21181+ unsigned hcintr : 1;
21182+ unsigned ptxfempty : 1;
21183+ unsigned reserved27 : 1;
21184+ unsigned conidstschng : 1;
21185+ unsigned disconnect : 1;
21186+ unsigned sessreqintr : 1;
21187+ unsigned wkupintr : 1;
21188+ } b;
21189+} gintsts_data_t;
21190+
21191+
21192+/**
21193+ * This union represents the bit fields in the Device Receive Status Read and
21194+ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
21195+ * element then read out the bits using the <i>b</i>it elements.
21196+ */
21197+typedef union device_grxsts_data
21198+{
21199+ /** raw register data */
21200+ uint32_t d32;
21201+ /** register bits */
21202+ struct
21203+ {
21204+ unsigned epnum : 4;
21205+ unsigned bcnt : 11;
21206+ unsigned dpid : 2;
21207+#define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet
21208+#define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete
21209+
21210+#define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK
21211+#define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete
21212+#define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet
21213+ unsigned pktsts : 4;
21214+ unsigned fn : 4;
21215+ unsigned reserved : 7;
21216+ } b;
21217+} device_grxsts_data_t;
21218+
21219+/**
21220+ * This union represents the bit fields in the Host Receive Status Read and
21221+ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
21222+ * element then read out the bits using the <i>b</i>it elements.
21223+ */
21224+typedef union host_grxsts_data
21225+{
21226+ /** raw register data */
21227+ uint32_t d32;
21228+ /** register bits */
21229+ struct
21230+ {
21231+ unsigned chnum : 4;
21232+ unsigned bcnt : 11;
21233+ unsigned dpid : 2;
21234+ unsigned pktsts : 4;
21235+#define DWC_GRXSTS_PKTSTS_IN 0x2
21236+#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3
21237+#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5
21238+#define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7
21239+ unsigned reserved : 11;
21240+ } b;
21241+} host_grxsts_data_t;
21242+
21243+/**
21244+ * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ,
21245+ * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the <i>d32</i> element then
21246+ * read out the bits using the <i>b</i>it elements.
21247+ */
21248+typedef union fifosize_data
21249+{
21250+ /** raw register data */
21251+ uint32_t d32;
21252+ /** register bits */
21253+ struct
21254+ {
21255+ unsigned startaddr : 16;
21256+ unsigned depth : 16;
21257+ } b;
21258+} fifosize_data_t;
21259+
21260+/**
21261+ * This union represents the bit fields in the Non-Periodic Transmit
21262+ * FIFO/Queue Status Register (GNPTXSTS). Read the register into the
21263+ * <i>d32</i> element then read out the bits using the <i>b</i>it
21264+ * elements.
21265+ */
21266+typedef union gnptxsts_data
21267+{
21268+ /** raw register data */
21269+ uint32_t d32;
21270+ /** register bits */
21271+ struct
21272+ {
21273+ unsigned nptxfspcavail : 16;
21274+ unsigned nptxqspcavail : 8;
21275+ /** Top of the Non-Periodic Transmit Request Queue
21276+ * - bit 24 - Terminate (Last entry for the selected
21277+ * channel/EP)
21278+ * - bits 26:25 - Token Type
21279+ * - 2'b00 - IN/OUT
21280+ * - 2'b01 - Zero Length OUT
21281+ * - 2'b10 - PING/Complete Split
21282+ * - 2'b11 - Channel Halt
21283+ * - bits 30:27 - Channel/EP Number
21284+ */
21285+ unsigned nptxqtop_terminate : 1;
21286+ unsigned nptxqtop_token : 2;
21287+ unsigned nptxqtop_chnep : 4;
21288+ unsigned reserved : 1;
21289+ } b;
21290+} gnptxsts_data_t;
21291+
21292+/**
21293+ * This union represents the bit fields in the Transmit
21294+ * FIFO Status Register (DTXFSTS). Read the register into the
21295+ * <i>d32</i> element then read out the bits using the <i>b</i>it
21296+ * elements.
21297+ */
21298+typedef union dtxfsts_data
21299+{
21300+ /** raw register data */
21301+ uint32_t d32;
21302+ /** register bits */
21303+ struct
21304+ {
21305+ unsigned txfspcavail : 16;
21306+ unsigned reserved : 16;
21307+ } b;
21308+} dtxfsts_data_t;
21309+
21310+/**
21311+ * This union represents the bit fields in the I2C Control Register
21312+ * (I2CCTL). Read the register into the <i>d32</i> element then read out the
21313+ * bits using the <i>b</i>it elements.
21314+ */
21315+typedef union gi2cctl_data
21316+{
21317+ /** raw register data */
21318+ uint32_t d32;
21319+ /** register bits */
21320+ struct
21321+ {
21322+ unsigned rwdata : 8;
21323+ unsigned regaddr : 8;
21324+ unsigned addr : 7;
21325+ unsigned i2cen : 1;
21326+ unsigned ack : 1;
21327+ unsigned i2csuspctl : 1;
21328+ unsigned i2cdevaddr : 2;
21329+ unsigned reserved : 2;
21330+ unsigned rw : 1;
21331+ unsigned bsydne : 1;
21332+ } b;
21333+} gi2cctl_data_t;
21334+
21335+/**
21336+ * This union represents the bit fields in the User HW Config1
21337+ * Register. Read the register into the <i>d32</i> element then read
21338+ * out the bits using the <i>b</i>it elements.
21339+ */
21340+typedef union hwcfg1_data
21341+{
21342+ /** raw register data */
21343+ uint32_t d32;
21344+ /** register bits */
21345+ struct
21346+ {
21347+ unsigned ep_dir0 : 2;
21348+ unsigned ep_dir1 : 2;
21349+ unsigned ep_dir2 : 2;
21350+ unsigned ep_dir3 : 2;
21351+ unsigned ep_dir4 : 2;
21352+ unsigned ep_dir5 : 2;
21353+ unsigned ep_dir6 : 2;
21354+ unsigned ep_dir7 : 2;
21355+ unsigned ep_dir8 : 2;
21356+ unsigned ep_dir9 : 2;
21357+ unsigned ep_dir10 : 2;
21358+ unsigned ep_dir11 : 2;
21359+ unsigned ep_dir12 : 2;
21360+ unsigned ep_dir13 : 2;
21361+ unsigned ep_dir14 : 2;
21362+ unsigned ep_dir15 : 2;
21363+ } b;
21364+} hwcfg1_data_t;
21365+
21366+/**
21367+ * This union represents the bit fields in the User HW Config2
21368+ * Register. Read the register into the <i>d32</i> element then read
21369+ * out the bits using the <i>b</i>it elements.
21370+ */
21371+typedef union hwcfg2_data
21372+{
21373+ /** raw register data */
21374+ uint32_t d32;
21375+ /** register bits */
21376+ struct
21377+ {
21378+ /* GHWCFG2 */
21379+ unsigned op_mode : 3;
21380+#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0
21381+#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
21382+#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
21383+#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
21384+#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
21385+#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
21386+#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
21387+
21388+ unsigned architecture : 2;
21389+ unsigned point2point : 1;
21390+ unsigned hs_phy_type : 2;
21391+#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
21392+#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1
21393+#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2
21394+#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
21395+
21396+ unsigned fs_phy_type : 2;
21397+ unsigned num_dev_ep : 4;
21398+ unsigned num_host_chan : 4;
21399+ unsigned perio_ep_supported : 1;
21400+ unsigned dynamic_fifo : 1;
21401+ unsigned multi_proc_int : 1;
21402+ unsigned reserved21 : 1;
21403+ unsigned nonperio_tx_q_depth : 2;
21404+ unsigned host_perio_tx_q_depth : 2;
21405+ unsigned dev_token_q_depth : 5;
21406+ unsigned reserved31 : 1;
21407+ } b;
21408+} hwcfg2_data_t;
21409+
21410+/**
21411+ * This union represents the bit fields in the User HW Config3
21412+ * Register. Read the register into the <i>d32</i> element then read
21413+ * out the bits using the <i>b</i>it elements.
21414+ */
21415+typedef union hwcfg3_data
21416+{
21417+ /** raw register data */
21418+ uint32_t d32;
21419+ /** register bits */
21420+ struct
21421+ {
21422+ /* GHWCFG3 */
21423+ unsigned xfer_size_cntr_width : 4;
21424+ unsigned packet_size_cntr_width : 3;
21425+ unsigned otg_func : 1;
21426+ unsigned i2c : 1;
21427+ unsigned vendor_ctrl_if : 1;
21428+ unsigned optional_features : 1;
21429+ unsigned synch_reset_type : 1;
21430+ unsigned ahb_phy_clock_synch : 1;
21431+ unsigned reserved15_13 : 3;
21432+ unsigned dfifo_depth : 16;
21433+ } b;
21434+} hwcfg3_data_t;
21435+
21436+/**
21437+ * This union represents the bit fields in the User HW Config4
21438+ * Register. Read the register into the <i>d32</i> element then read
21439+ * out the bits using the <i>b</i>it elements.
21440+ */
21441+typedef union hwcfg4_data
21442+{
21443+ /** raw register data */
21444+ uint32_t d32;
21445+ /** register bits */
21446+ struct
21447+ {
21448+ unsigned num_dev_perio_in_ep : 4;
21449+ unsigned power_optimiz : 1;
21450+ unsigned min_ahb_freq : 9;
21451+ unsigned utmi_phy_data_width : 2;
21452+ unsigned num_dev_mode_ctrl_ep : 4;
21453+ unsigned iddig_filt_en : 1;
21454+ unsigned vbus_valid_filt_en : 1;
21455+ unsigned a_valid_filt_en : 1;
21456+ unsigned b_valid_filt_en : 1;
21457+ unsigned session_end_filt_en : 1;
21458+ unsigned ded_fifo_en : 1;
21459+ unsigned num_in_eps : 4;
21460+ unsigned desc_dma : 1;
21461+ unsigned desc_dma_dyn : 1;
21462+ } b;
21463+} hwcfg4_data_t;
21464+
21465+////////////////////////////////////////////
21466+// Device Registers
21467+/**
21468+ * Device Global Registers. <i>Offsets 800h-BFFh</i>
21469+ *
21470+ * The following structures define the size and relative field offsets
21471+ * for the Device Mode Registers.
21472+ *
21473+ * <i>These registers are visible only in Device mode and must not be
21474+ * accessed in Host mode, as the results are unknown.</i>
21475+ */
21476+typedef struct dwc_otg_dev_global_regs
21477+{
21478+ /** Device Configuration Register. <i>Offset 800h</i> */
21479+ volatile uint32_t dcfg;
21480+ /** Device Control Register. <i>Offset: 804h</i> */
21481+ volatile uint32_t dctl;
21482+ /** Device Status Register (Read Only). <i>Offset: 808h</i> */
21483+ volatile uint32_t dsts;
21484+ /** Reserved. <i>Offset: 80Ch</i> */
21485+ uint32_t unused;
21486+ /** Device IN Endpoint Common Interrupt Mask
21487+ * Register. <i>Offset: 810h</i> */
21488+ volatile uint32_t diepmsk;
21489+ /** Device OUT Endpoint Common Interrupt Mask
21490+ * Register. <i>Offset: 814h</i> */
21491+ volatile uint32_t doepmsk;
21492+ /** Device All Endpoints Interrupt Register. <i>Offset: 818h</i> */
21493+ volatile uint32_t daint;
21494+ /** Device All Endpoints Interrupt Mask Register. <i>Offset:
21495+ * 81Ch</i> */
21496+ volatile uint32_t daintmsk;
21497+ /** Device IN Token Queue Read Register-1 (Read Only).
21498+ * <i>Offset: 820h</i> */
21499+ volatile uint32_t dtknqr1;
21500+ /** Device IN Token Queue Read Register-2 (Read Only).
21501+ * <i>Offset: 824h</i> */
21502+ volatile uint32_t dtknqr2;
21503+ /** Device VBUS discharge Register. <i>Offset: 828h</i> */
21504+ volatile uint32_t dvbusdis;
21505+ /** Device VBUS Pulse Register. <i>Offset: 82Ch</i> */
21506+ volatile uint32_t dvbuspulse;
21507+ /** Device IN Token Queue Read Register-3 (Read Only). /
21508+ * Device Thresholding control register (Read/Write)
21509+ * <i>Offset: 830h</i> */
21510+ volatile uint32_t dtknqr3_dthrctl;
21511+ /** Device IN Token Queue Read Register-4 (Read Only). /
21512+ * Device IN EPs empty Inr. Mask Register (Read/Write)
21513+ * <i>Offset: 834h</i> */
21514+ volatile uint32_t dtknqr4_fifoemptymsk;
21515+ /** Device Each Endpoint Interrupt Register (Read Only). /
21516+ * <i>Offset: 838h</i> */
21517+ volatile uint32_t deachint;
21518+ /** Device Each Endpoint Interrupt mask Register (Read/Write). /
21519+ * <i>Offset: 83Ch</i> */
21520+ volatile uint32_t deachintmsk;
21521+ /** Device Each In Endpoint Interrupt mask Register (Read/Write). /
21522+ * <i>Offset: 840h</i> */
21523+ volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS];
21524+ /** Device Each Out Endpoint Interrupt mask Register (Read/Write). /
21525+ * <i>Offset: 880h</i> */
21526+ volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS];
21527+} dwc_otg_device_global_regs_t;
21528+
21529+/**
21530+ * This union represents the bit fields in the Device Configuration
21531+ * Register. Read the register into the <i>d32</i> member then
21532+ * set/clear the bits using the <i>b</i>it elements. Write the
21533+ * <i>d32</i> member to the dcfg register.
21534+ */
21535+typedef union dcfg_data
21536+{
21537+ /** raw register data */
21538+ uint32_t d32;
21539+ /** register bits */
21540+ struct
21541+ {
21542+ /** Device Speed */
21543+ unsigned devspd : 2;
21544+ /** Non Zero Length Status OUT Handshake */
21545+ unsigned nzstsouthshk : 1;
21546+#define DWC_DCFG_SEND_STALL 1
21547+
21548+ unsigned reserved3 : 1;
21549+ /** Device Addresses */
21550+ unsigned devaddr : 7;
21551+ /** Periodic Frame Interval */
21552+ unsigned perfrint : 2;
21553+#define DWC_DCFG_FRAME_INTERVAL_80 0
21554+#define DWC_DCFG_FRAME_INTERVAL_85 1
21555+#define DWC_DCFG_FRAME_INTERVAL_90 2
21556+#define DWC_DCFG_FRAME_INTERVAL_95 3
21557+
21558+ unsigned reserved13_17 : 5;
21559+ /** In Endpoint Mis-match count */
21560+ unsigned epmscnt : 5;
21561+ /** Enable Descriptor DMA in Device mode */
21562+ unsigned descdma : 1;
21563+ } b;
21564+} dcfg_data_t;
21565+
21566+/**
21567+ * This union represents the bit fields in the Device Control
21568+ * Register. Read the register into the <i>d32</i> member then
21569+ * set/clear the bits using the <i>b</i>it elements.
21570+ */
21571+typedef union dctl_data
21572+{
21573+ /** raw register data */
21574+ uint32_t d32;
21575+ /** register bits */
21576+ struct
21577+ {
21578+ /** Remote Wakeup */
21579+ unsigned rmtwkupsig : 1;
21580+ /** Soft Disconnect */
21581+ unsigned sftdiscon : 1;
21582+ /** Global Non-Periodic IN NAK Status */
21583+ unsigned gnpinnaksts : 1;
21584+ /** Global OUT NAK Status */
21585+ unsigned goutnaksts : 1;
21586+ /** Test Control */
21587+ unsigned tstctl : 3;
21588+ /** Set Global Non-Periodic IN NAK */
21589+ unsigned sgnpinnak : 1;
21590+ /** Clear Global Non-Periodic IN NAK */
21591+ unsigned cgnpinnak : 1;
21592+ /** Set Global OUT NAK */
21593+ unsigned sgoutnak : 1;
21594+ /** Clear Global OUT NAK */
21595+ unsigned cgoutnak : 1;
21596+
21597+ /** Power-On Programming Done */
21598+ unsigned pwronprgdone : 1;
21599+ /** Global Continue on BNA */
21600+ unsigned gcontbna : 1;
21601+ /** Global Multi Count */
21602+ unsigned gmc : 2;
21603+ /** Ignore Frame Number for ISOC EPs */
21604+ unsigned ifrmnum : 1;
21605+ /** NAK on Babble */
21606+ unsigned nakonbble : 1;
21607+
21608+ unsigned reserved16_31 : 16;
21609+ } b;
21610+} dctl_data_t;
21611+
21612+/**
21613+ * This union represents the bit fields in the Device Status
21614+ * Register. Read the register into the <i>d32</i> member then
21615+ * set/clear the bits using the <i>b</i>it elements.
21616+ */
21617+typedef union dsts_data
21618+{
21619+ /** raw register data */
21620+ uint32_t d32;
21621+ /** register bits */
21622+ struct
21623+ {
21624+ /** Suspend Status */
21625+ unsigned suspsts : 1;
21626+ /** Enumerated Speed */
21627+ unsigned enumspd : 2;
21628+#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
21629+#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
21630+#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2
21631+#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3
21632+ /** Erratic Error */
21633+ unsigned errticerr : 1;
21634+ unsigned reserved4_7: 4;
21635+ /** Frame or Microframe Number of the received SOF */
21636+ unsigned soffn : 14;
21637+ unsigned reserved22_31 : 10;
21638+ } b;
21639+} dsts_data_t;
21640+
21641+
21642+/**
21643+ * This union represents the bit fields in the Device IN EP Interrupt
21644+ * Register and the Device IN EP Common Mask Register.
21645+ *
21646+ * - Read the register into the <i>d32</i> member then set/clear the
21647+ * bits using the <i>b</i>it elements.
21648+ */
21649+typedef union diepint_data
21650+{
21651+ /** raw register data */
21652+ uint32_t d32;
21653+ /** register bits */
21654+ struct
21655+ {
21656+ /** Transfer complete mask */
21657+ unsigned xfercompl : 1;
21658+ /** Endpoint disable mask */
21659+ unsigned epdisabled : 1;
21660+ /** AHB Error mask */
21661+ unsigned ahberr : 1;
21662+ /** TimeOUT Handshake mask (non-ISOC EPs) */
21663+ unsigned timeout : 1;
21664+ /** IN Token received with TxF Empty mask */
21665+ unsigned intktxfemp : 1;
21666+ /** IN Token Received with EP mismatch mask */
21667+ unsigned intknepmis : 1;
21668+ /** IN Endpoint HAK Effective mask */
21669+ unsigned inepnakeff : 1;
21670+ /** IN Endpoint HAK Effective mask */
21671+ unsigned emptyintr : 1;
21672+ unsigned txfifoundrn : 1;
21673+
21674+ /** BNA Interrupt mask */
21675+ unsigned bna : 1;
21676+ unsigned reserved10_12 : 3;
21677+ /** BNA Interrupt mask */
21678+ unsigned nak : 1;
21679+ unsigned reserved14_31 : 18;
21680+ } b;
21681+} diepint_data_t;
21682+
21683+/**
21684+ * This union represents the bit fields in the Device IN EP
21685+ * Common/Dedicated Interrupt Mask Register.
21686+ */
21687+typedef union diepint_data diepmsk_data_t;
21688+
21689+/**
21690+ * This union represents the bit fields in the Device OUT EP Interrupt
21691+ * Registerand Device OUT EP Common Interrupt Mask Register.
21692+ *
21693+ * - Read the register into the <i>d32</i> member then set/clear the
21694+ * bits using the <i>b</i>it elements.
21695+ */
21696+typedef union doepint_data
21697+{
21698+ /** raw register data */
21699+ uint32_t d32;
21700+ /** register bits */
21701+ struct
21702+ {
21703+ /** Transfer complete */
21704+ unsigned xfercompl : 1;
21705+ /** Endpoint disable */
21706+ unsigned epdisabled : 1;
21707+ /** AHB Error */
21708+ unsigned ahberr : 1;
21709+ /** Setup Phase Done (contorl EPs) */
21710+ unsigned setup : 1;
21711+ /** OUT Token Received when Endpoint Disabled */
21712+ unsigned outtknepdis : 1;
21713+ unsigned stsphsercvd : 1;
21714+ /** Back-to-Back SETUP Packets Received */
21715+ unsigned back2backsetup : 1;
21716+ unsigned reserved7 : 1;
21717+ /** OUT packet Error */
21718+ unsigned outpkterr : 1;
21719+ /** BNA Interrupt */
21720+ unsigned bna : 1;
21721+ unsigned reserved10 : 1;
21722+ /** Packet Drop Status */
21723+ unsigned pktdrpsts : 1;
21724+ /** Babble Interrupt */
21725+ unsigned babble : 1;
21726+ /** NAK Interrupt */
21727+ unsigned nak : 1;
21728+ /** NYET Interrupt */
21729+ unsigned nyet : 1;
21730+
21731+ unsigned reserved15_31 : 17;
21732+ } b;
21733+} doepint_data_t;
21734+
21735+/**
21736+ * This union represents the bit fields in the Device OUT EP
21737+ * Common/Dedicated Interrupt Mask Register.
21738+ */
21739+typedef union doepint_data doepmsk_data_t;
21740+
21741+/**
21742+ * This union represents the bit fields in the Device All EP Interrupt
21743+ * and Mask Registers.
21744+ * - Read the register into the <i>d32</i> member then set/clear the
21745+ * bits using the <i>b</i>it elements.
21746+ */
21747+typedef union daint_data
21748+{
21749+ /** raw register data */
21750+ uint32_t d32;
21751+ /** register bits */
21752+ struct
21753+ {
21754+ /** IN Endpoint bits */
21755+ unsigned in : 16;
21756+ /** OUT Endpoint bits */
21757+ unsigned out : 16;
21758+ } ep;
21759+ struct
21760+ {
21761+ /** IN Endpoint bits */
21762+ unsigned inep0 : 1;
21763+ unsigned inep1 : 1;
21764+ unsigned inep2 : 1;
21765+ unsigned inep3 : 1;
21766+ unsigned inep4 : 1;
21767+ unsigned inep5 : 1;
21768+ unsigned inep6 : 1;
21769+ unsigned inep7 : 1;
21770+ unsigned inep8 : 1;
21771+ unsigned inep9 : 1;
21772+ unsigned inep10 : 1;
21773+ unsigned inep11 : 1;
21774+ unsigned inep12 : 1;
21775+ unsigned inep13 : 1;
21776+ unsigned inep14 : 1;
21777+ unsigned inep15 : 1;
21778+ /** OUT Endpoint bits */
21779+ unsigned outep0 : 1;
21780+ unsigned outep1 : 1;
21781+ unsigned outep2 : 1;
21782+ unsigned outep3 : 1;
21783+ unsigned outep4 : 1;
21784+ unsigned outep5 : 1;
21785+ unsigned outep6 : 1;
21786+ unsigned outep7 : 1;
21787+ unsigned outep8 : 1;
21788+ unsigned outep9 : 1;
21789+ unsigned outep10 : 1;
21790+ unsigned outep11 : 1;
21791+ unsigned outep12 : 1;
21792+ unsigned outep13 : 1;
21793+ unsigned outep14 : 1;
21794+ unsigned outep15 : 1;
21795+ } b;
21796+} daint_data_t;
21797+
21798+/**
21799+ * This union represents the bit fields in the Device IN Token Queue
21800+ * Read Registers.
21801+ * - Read the register into the <i>d32</i> member.
21802+ * - READ-ONLY Register
21803+ */
21804+typedef union dtknq1_data
21805+{
21806+ /** raw register data */
21807+ uint32_t d32;
21808+ /** register bits */
21809+ struct
21810+ {
21811+ /** In Token Queue Write Pointer */
21812+ unsigned intknwptr : 5;
21813+ /** Reserved */
21814+ unsigned reserved05_06 : 2;
21815+ /** write pointer has wrapped. */
21816+ unsigned wrap_bit : 1;
21817+ /** EP Numbers of IN Tokens 0 ... 4 */
21818+ unsigned epnums0_5 : 24;
21819+ }b;
21820+} dtknq1_data_t;
21821+
21822+/**
21823+ * This union represents Threshold control Register
21824+ * - Read and write the register into the <i>d32</i> member.
21825+ * - READ-WRITABLE Register
21826+ */
21827+typedef union dthrctl_data
21828+{
21829+ /** raw register data */
21830+ uint32_t d32;
21831+ /** register bits */
21832+ struct
21833+ {
21834+ /** non ISO Tx Thr. Enable */
21835+ unsigned non_iso_thr_en : 1;
21836+ /** ISO Tx Thr. Enable */
21837+ unsigned iso_thr_en : 1;
21838+ /** Tx Thr. Length */
21839+ unsigned tx_thr_len : 9;
21840+ /** Reserved */
21841+ unsigned reserved11_15 : 5;
21842+ /** Rx Thr. Enable */
21843+ unsigned rx_thr_en : 1;
21844+ /** Rx Thr. Length */
21845+ unsigned rx_thr_len : 9;
21846+ /** Reserved */
21847+ unsigned reserved26_31 : 6;
21848+ }b;
21849+} dthrctl_data_t;
21850+
21851+
21852+/**
21853+ * Device Logical IN Endpoint-Specific Registers. <i>Offsets
21854+ * 900h-AFCh</i>
21855+ *
21856+ * There will be one set of endpoint registers per logical endpoint
21857+ * implemented.
21858+ *
21859+ * <i>These registers are visible only in Device mode and must not be
21860+ * accessed in Host mode, as the results are unknown.</i>
21861+ */
21862+typedef struct dwc_otg_dev_in_ep_regs
21863+{
21864+ /** Device IN Endpoint Control Register. <i>Offset:900h +
21865+ * (ep_num * 20h) + 00h</i> */
21866+ volatile uint32_t diepctl;
21867+ /** Reserved. <i>Offset:900h + (ep_num * 20h) + 04h</i> */
21868+ uint32_t reserved04;
21869+ /** Device IN Endpoint Interrupt Register. <i>Offset:900h +
21870+ * (ep_num * 20h) + 08h</i> */
21871+ volatile uint32_t diepint;
21872+ /** Reserved. <i>Offset:900h + (ep_num * 20h) + 0Ch</i> */
21873+ uint32_t reserved0C;
21874+ /** Device IN Endpoint Transfer Size
21875+ * Register. <i>Offset:900h + (ep_num * 20h) + 10h</i> */
21876+ volatile uint32_t dieptsiz;
21877+ /** Device IN Endpoint DMA Address Register. <i>Offset:900h +
21878+ * (ep_num * 20h) + 14h</i> */
21879+ volatile uint32_t diepdma;
21880+ /** Device IN Endpoint Transmit FIFO Status Register. <i>Offset:900h +
21881+ * (ep_num * 20h) + 18h</i> */
21882+ volatile uint32_t dtxfsts;
21883+ /** Device IN Endpoint DMA Buffer Register. <i>Offset:900h +
21884+ * (ep_num * 20h) + 1Ch</i> */
21885+ volatile uint32_t diepdmab;
21886+} dwc_otg_dev_in_ep_regs_t;
21887+
21888+/**
21889+ * Device Logical OUT Endpoint-Specific Registers. <i>Offsets:
21890+ * B00h-CFCh</i>
21891+ *
21892+ * There will be one set of endpoint registers per logical endpoint
21893+ * implemented.
21894+ *
21895+ * <i>These registers are visible only in Device mode and must not be
21896+ * accessed in Host mode, as the results are unknown.</i>
21897+ */
21898+typedef struct dwc_otg_dev_out_ep_regs
21899+{
21900+ /** Device OUT Endpoint Control Register. <i>Offset:B00h +
21901+ * (ep_num * 20h) + 00h</i> */
21902+ volatile uint32_t doepctl;
21903+ /** Device OUT Endpoint Frame number Register. <i>Offset:
21904+ * B00h + (ep_num * 20h) + 04h</i> */
21905+ volatile uint32_t doepfn;
21906+ /** Device OUT Endpoint Interrupt Register. <i>Offset:B00h +
21907+ * (ep_num * 20h) + 08h</i> */
21908+ volatile uint32_t doepint;
21909+ /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 0Ch</i> */
21910+ uint32_t reserved0C;
21911+ /** Device OUT Endpoint Transfer Size Register. <i>Offset:
21912+ * B00h + (ep_num * 20h) + 10h</i> */
21913+ volatile uint32_t doeptsiz;
21914+ /** Device OUT Endpoint DMA Address Register. <i>Offset:B00h
21915+ * + (ep_num * 20h) + 14h</i> */
21916+ volatile uint32_t doepdma;
21917+ /** Reserved. <i>Offset:B00h + * (ep_num * 20h) + 1Ch</i> */
21918+ uint32_t unused;
21919+ /** Device OUT Endpoint DMA Buffer Register. <i>Offset:B00h
21920+ * + (ep_num * 20h) + 1Ch</i> */
21921+ uint32_t doepdmab;
21922+} dwc_otg_dev_out_ep_regs_t;
21923+
21924+/**
21925+ * This union represents the bit fields in the Device EP Control
21926+ * Register. Read the register into the <i>d32</i> member then
21927+ * set/clear the bits using the <i>b</i>it elements.
21928+ */
21929+typedef union depctl_data
21930+{
21931+ /** raw register data */
21932+ uint32_t d32;
21933+ /** register bits */
21934+ struct
21935+ {
21936+ /** Maximum Packet Size
21937+ * IN/OUT EPn
21938+ * IN/OUT EP0 - 2 bits
21939+ * 2'b00: 64 Bytes
21940+ * 2'b01: 32
21941+ * 2'b10: 16
21942+ * 2'b11: 8 */
21943+ unsigned mps : 11;
21944+#define DWC_DEP0CTL_MPS_64 0
21945+#define DWC_DEP0CTL_MPS_32 1
21946+#define DWC_DEP0CTL_MPS_16 2
21947+#define DWC_DEP0CTL_MPS_8 3
21948+
21949+ /** Next Endpoint
21950+ * IN EPn/IN EP0
21951+ * OUT EPn/OUT EP0 - reserved */
21952+ unsigned nextep : 4;
21953+
21954+ /** USB Active Endpoint */
21955+ unsigned usbactep : 1;
21956+
21957+ /** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
21958+ * This field contains the PID of the packet going to
21959+ * be received or transmitted on this endpoint. The
21960+ * application should program the PID of the first
21961+ * packet going to be received or transmitted on this
21962+ * endpoint , after the endpoint is
21963+ * activated. Application use the SetD1PID and
21964+ * SetD0PID fields of this register to program either
21965+ * D0 or D1 PID.
21966+ *
21967+ * The encoding for this field is
21968+ * - 0: D0
21969+ * - 1: D1
21970+ */
21971+ unsigned dpid : 1;
21972+
21973+ /** NAK Status */
21974+ unsigned naksts : 1;
21975+
21976+ /** Endpoint Type
21977+ * 2'b00: Control
21978+ * 2'b01: Isochronous
21979+ * 2'b10: Bulk
21980+ * 2'b11: Interrupt */
21981+ unsigned eptype : 2;
21982+
21983+ /** Snoop Mode
21984+ * OUT EPn/OUT EP0
21985+ * IN EPn/IN EP0 - reserved */
21986+ unsigned snp : 1;
21987+
21988+ /** Stall Handshake */
21989+ unsigned stall : 1;
21990+
21991+ /** Tx Fifo Number
21992+ * IN EPn/IN EP0
21993+ * OUT EPn/OUT EP0 - reserved */
21994+ unsigned txfnum : 4;
21995+
21996+ /** Clear NAK */
21997+ unsigned cnak : 1;
21998+ /** Set NAK */
21999+ unsigned snak : 1;
22000+ /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
22001+ * Writing to this field sets the Endpoint DPID (DPID)
22002+ * field in this register to DATA0. Set Even
22003+ * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
22004+ * Writing to this field sets the Even/Odd
22005+ * (micro)frame (EO_FrNum) field to even (micro)
22006+ * frame.
22007+ */
22008+ unsigned setd0pid : 1;
22009+ /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
22010+ * Writing to this field sets the Endpoint DPID (DPID)
22011+ * field in this register to DATA1 Set Odd
22012+ * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
22013+ * Writing to this field sets the Even/Odd
22014+ * (micro)frame (EO_FrNum) field to odd (micro) frame.
22015+ */
22016+ unsigned setd1pid : 1;
22017+ /** Endpoint Disable */
22018+ unsigned epdis : 1;
22019+ /** Endpoint Enable */
22020+ unsigned epena : 1;
22021+ } b;
22022+} depctl_data_t;
22023+
22024+/**
22025+ * This union represents the bit fields in the Device EP Transfer
22026+ * Size Register. Read the register into the <i>d32</i> member then
22027+ * set/clear the bits using the <i>b</i>it elements.
22028+ */
22029+typedef union deptsiz_data
22030+{
22031+ /** raw register data */
22032+ uint32_t d32;
22033+ /** register bits */
22034+ struct {
22035+ /** Transfer size */
22036+ unsigned xfersize : 19;
22037+ /** Packet Count */
22038+ unsigned pktcnt : 10;
22039+ /** Multi Count - Periodic IN endpoints */
22040+ unsigned mc : 2;
22041+ unsigned reserved : 1;
22042+ } b;
22043+} deptsiz_data_t;
22044+
22045+/**
22046+ * This union represents the bit fields in the Device EP 0 Transfer
22047+ * Size Register. Read the register into the <i>d32</i> member then
22048+ * set/clear the bits using the <i>b</i>it elements.
22049+ */
22050+typedef union deptsiz0_data
22051+{
22052+ /** raw register data */
22053+ uint32_t d32;
22054+ /** register bits */
22055+ struct {
22056+ /** Transfer size */
22057+ unsigned xfersize : 7;
22058+ /** Reserved */
22059+ unsigned reserved7_18 : 12;
22060+ /** Packet Count */
22061+ unsigned pktcnt : 1;
22062+ /** Reserved */
22063+ unsigned reserved20_28 : 9;
22064+ /**Setup Packet Count (DOEPTSIZ0 Only) */
22065+ unsigned supcnt : 2;
22066+ unsigned reserved31;
22067+ } b;
22068+} deptsiz0_data_t;
22069+
22070+
22071+/////////////////////////////////////////////////
22072+// DMA Descriptor Specific Structures
22073+//
22074+
22075+/** Buffer status definitions */
22076+
22077+#define BS_HOST_READY 0x0
22078+#define BS_DMA_BUSY 0x1
22079+#define BS_DMA_DONE 0x2
22080+#define BS_HOST_BUSY 0x3
22081+
22082+/** Receive/Transmit status definitions */
22083+
22084+#define RTS_SUCCESS 0x0
22085+#define RTS_BUFFLUSH 0x1
22086+#define RTS_RESERVED 0x2
22087+#define RTS_BUFERR 0x3
22088+
22089+
22090+/**
22091+ * This union represents the bit fields in the DMA Descriptor
22092+ * status quadlet. Read the quadlet into the <i>d32</i> member then
22093+ * set/clear the bits using the <i>b</i>it, <i>b_iso_out</i> and
22094+ * <i>b_iso_in</i> elements.
22095+ */
22096+typedef union desc_sts_data
22097+{
22098+ /** raw register data */
22099+ uint32_t d32;
22100+ /** quadlet bits */
22101+ struct {
22102+ /** Received number of bytes */
22103+ unsigned bytes : 16;
22104+
22105+ unsigned reserved16_22 : 7;
22106+ /** Multiple Transfer - only for OUT EPs */
22107+ unsigned mtrf : 1;
22108+ /** Setup Packet received - only for OUT EPs */
22109+ unsigned sr : 1;
22110+ /** Interrupt On Complete */
22111+ unsigned ioc : 1;
22112+ /** Short Packet */
22113+ unsigned sp : 1;
22114+ /** Last */
22115+ unsigned l : 1;
22116+ /** Receive Status */
22117+ unsigned sts : 2;
22118+ /** Buffer Status */
22119+ unsigned bs : 2;
22120+ } b;
22121+
22122+#ifdef DWC_EN_ISOC
22123+ /** iso out quadlet bits */
22124+ struct {
22125+ /** Received number of bytes */
22126+ unsigned rxbytes : 11;
22127+
22128+ unsigned reserved11 : 1;
22129+ /** Frame Number */
22130+ unsigned framenum : 11;
22131+ /** Received ISO Data PID */
22132+ unsigned pid : 2;
22133+ /** Interrupt On Complete */
22134+ unsigned ioc : 1;
22135+ /** Short Packet */
22136+ unsigned sp : 1;
22137+ /** Last */
22138+ unsigned l : 1;
22139+ /** Receive Status */
22140+ unsigned rxsts : 2;
22141+ /** Buffer Status */
22142+ unsigned bs : 2;
22143+ } b_iso_out;
22144+
22145+ /** iso in quadlet bits */
22146+ struct {
22147+ /** Transmited number of bytes */
22148+ unsigned txbytes : 12;
22149+ /** Frame Number */
22150+ unsigned framenum : 11;
22151+ /** Transmited ISO Data PID */
22152+ unsigned pid : 2;
22153+ /** Interrupt On Complete */
22154+ unsigned ioc : 1;
22155+ /** Short Packet */
22156+ unsigned sp : 1;
22157+ /** Last */
22158+ unsigned l : 1;
22159+ /** Transmit Status */
22160+ unsigned txsts : 2;
22161+ /** Buffer Status */
22162+ unsigned bs : 2;
22163+ } b_iso_in;
22164+#endif //DWC_EN_ISOC
22165+} desc_sts_data_t;
22166+
22167+/**
22168+ * DMA Descriptor structure
22169+ *
22170+ * DMA Descriptor structure contains two quadlets:
22171+ * Status quadlet and Data buffer pointer.
22172+ */
22173+typedef struct dwc_otg_dma_desc
22174+{
22175+ /** DMA Descriptor status quadlet */
22176+ desc_sts_data_t status;
22177+ /** DMA Descriptor data buffer pointer */
22178+ dma_addr_t buf;
22179+} dwc_otg_dma_desc_t;
22180+
22181+/**
22182+ * The dwc_otg_dev_if structure contains information needed to manage
22183+ * the DWC_otg controller acting in device mode. It represents the
22184+ * programming view of the device-specific aspects of the controller.
22185+ */
22186+typedef struct dwc_otg_dev_if
22187+{
22188+ /** Pointer to device Global registers.
22189+ * Device Global Registers starting at offset 800h
22190+ */
22191+ dwc_otg_device_global_regs_t *dev_global_regs;
22192+#define DWC_DEV_GLOBAL_REG_OFFSET 0x800
22193+
22194+ /**
22195+ * Device Logical IN Endpoint-Specific Registers 900h-AFCh
22196+ */
22197+ dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS];
22198+#define DWC_DEV_IN_EP_REG_OFFSET 0x900
22199+#define DWC_EP_REG_OFFSET 0x20
22200+
22201+ /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */
22202+ dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS];
22203+#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00
22204+
22205+ /* Device configuration information*/
22206+ uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */
22207+ uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */
22208+ uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/
22209+
22210+ /** Size of periodic FIFOs (Bytes) */
22211+ uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS];
22212+
22213+ /** Size of Tx FIFOs (Bytes) */
22214+ uint16_t tx_fifo_size[MAX_TX_FIFOS];
22215+
22216+ /** Thresholding enable flags and length varaiables **/
22217+ uint16_t rx_thr_en;
22218+ uint16_t iso_tx_thr_en;
22219+ uint16_t non_iso_tx_thr_en;
22220+
22221+ uint16_t rx_thr_length;
22222+ uint16_t tx_thr_length;
22223+
22224+ /**
22225+ * Pointers to the DMA Descriptors for EP0 Control
22226+ * transfers (virtual and physical)
22227+ */
22228+ /** 2 descriptors for SETUP packets */
22229+ uint32_t dma_setup_desc_addr[2];
22230+ dwc_otg_dma_desc_t* setup_desc_addr[2];
22231+
22232+ /** Pointer to Descriptor with latest SETUP packet */
22233+ dwc_otg_dma_desc_t* psetup;
22234+
22235+ /** Index of current SETUP handler descriptor */
22236+ uint32_t setup_desc_index;
22237+
22238+ /** Descriptor for Data In or Status In phases */
22239+ uint32_t dma_in_desc_addr;
22240+ dwc_otg_dma_desc_t* in_desc_addr;;
22241+
22242+ /** Descriptor for Data Out or Status Out phases */
22243+ uint32_t dma_out_desc_addr;
22244+ dwc_otg_dma_desc_t* out_desc_addr;
22245+} dwc_otg_dev_if_t;
22246+
22247+
22248+
22249+
22250+/////////////////////////////////////////////////
22251+// Host Mode Register Structures
22252+//
22253+/**
22254+ * The Host Global Registers structure defines the size and relative
22255+ * field offsets for the Host Mode Global Registers. Host Global
22256+ * Registers offsets 400h-7FFh.
22257+*/
22258+typedef struct dwc_otg_host_global_regs
22259+{
22260+ /** Host Configuration Register. <i>Offset: 400h</i> */
22261+ volatile uint32_t hcfg;
22262+ /** Host Frame Interval Register. <i>Offset: 404h</i> */
22263+ volatile uint32_t hfir;
22264+ /** Host Frame Number / Frame Remaining Register. <i>Offset: 408h</i> */
22265+ volatile uint32_t hfnum;
22266+ /** Reserved. <i>Offset: 40Ch</i> */
22267+ uint32_t reserved40C;
22268+ /** Host Periodic Transmit FIFO/ Queue Status Register. <i>Offset: 410h</i> */
22269+ volatile uint32_t hptxsts;
22270+ /** Host All Channels Interrupt Register. <i>Offset: 414h</i> */
22271+ volatile uint32_t haint;
22272+ /** Host All Channels Interrupt Mask Register. <i>Offset: 418h</i> */
22273+ volatile uint32_t haintmsk;
22274+} dwc_otg_host_global_regs_t;
22275+
22276+/**
22277+ * This union represents the bit fields in the Host Configuration Register.
22278+ * Read the register into the <i>d32</i> member then set/clear the bits using
22279+ * the <i>b</i>it elements. Write the <i>d32</i> member to the hcfg register.
22280+ */
22281+typedef union hcfg_data
22282+{
22283+ /** raw register data */
22284+ uint32_t d32;
22285+
22286+ /** register bits */
22287+ struct
22288+ {
22289+ /** FS/LS Phy Clock Select */
22290+ unsigned fslspclksel : 2;
22291+#define DWC_HCFG_30_60_MHZ 0
22292+#define DWC_HCFG_48_MHZ 1
22293+#define DWC_HCFG_6_MHZ 2
22294+
22295+ /** FS/LS Only Support */
22296+ unsigned fslssupp : 1;
22297+ } b;
22298+} hcfg_data_t;
22299+
22300+/**
22301+ * This union represents the bit fields in the Host Frame Remaing/Number
22302+ * Register.
22303+ */
22304+typedef union hfir_data
22305+{
22306+ /** raw register data */
22307+ uint32_t d32;
22308+
22309+ /** register bits */
22310+ struct
22311+ {
22312+ unsigned frint : 16;
22313+ unsigned reserved : 16;
22314+ } b;
22315+} hfir_data_t;
22316+
22317+/**
22318+ * This union represents the bit fields in the Host Frame Remaing/Number
22319+ * Register.
22320+ */
22321+typedef union hfnum_data
22322+{
22323+ /** raw register data */
22324+ uint32_t d32;
22325+
22326+ /** register bits */
22327+ struct
22328+ {
22329+ unsigned frnum : 16;
22330+#define DWC_HFNUM_MAX_FRNUM 0x3FFF
22331+ unsigned frrem : 16;
22332+ } b;
22333+} hfnum_data_t;
22334+
22335+typedef union hptxsts_data
22336+{
22337+ /** raw register data */
22338+ uint32_t d32;
22339+
22340+ /** register bits */
22341+ struct
22342+ {
22343+ unsigned ptxfspcavail : 16;
22344+ unsigned ptxqspcavail : 8;
22345+ /** Top of the Periodic Transmit Request Queue
22346+ * - bit 24 - Terminate (last entry for the selected channel)
22347+ * - bits 26:25 - Token Type
22348+ * - 2'b00 - Zero length
22349+ * - 2'b01 - Ping
22350+ * - 2'b10 - Disable
22351+ * - bits 30:27 - Channel Number
22352+ * - bit 31 - Odd/even microframe
22353+ */
22354+ unsigned ptxqtop_terminate : 1;
22355+ unsigned ptxqtop_token : 2;
22356+ unsigned ptxqtop_chnum : 4;
22357+ unsigned ptxqtop_odd : 1;
22358+ } b;
22359+} hptxsts_data_t;
22360+
22361+/**
22362+ * This union represents the bit fields in the Host Port Control and Status
22363+ * Register. Read the register into the <i>d32</i> member then set/clear the
22364+ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
22365+ * hprt0 register.
22366+ */
22367+typedef union hprt0_data
22368+{
22369+ /** raw register data */
22370+ uint32_t d32;
22371+ /** register bits */
22372+ struct
22373+ {
22374+ unsigned prtconnsts : 1;
22375+ unsigned prtconndet : 1;
22376+ unsigned prtena : 1;
22377+ unsigned prtenchng : 1;
22378+ unsigned prtovrcurract : 1;
22379+ unsigned prtovrcurrchng : 1;
22380+ unsigned prtres : 1;
22381+ unsigned prtsusp : 1;
22382+ unsigned prtrst : 1;
22383+ unsigned reserved9 : 1;
22384+ unsigned prtlnsts : 2;
22385+ unsigned prtpwr : 1;
22386+ unsigned prttstctl : 4;
22387+ unsigned prtspd : 2;
22388+#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0
22389+#define DWC_HPRT0_PRTSPD_FULL_SPEED 1
22390+#define DWC_HPRT0_PRTSPD_LOW_SPEED 2
22391+ unsigned reserved19_31 : 13;
22392+ } b;
22393+} hprt0_data_t;
22394+
22395+/**
22396+ * This union represents the bit fields in the Host All Interrupt
22397+ * Register.
22398+ */
22399+typedef union haint_data
22400+{
22401+ /** raw register data */
22402+ uint32_t d32;
22403+ /** register bits */
22404+ struct
22405+ {
22406+ unsigned ch0 : 1;
22407+ unsigned ch1 : 1;
22408+ unsigned ch2 : 1;
22409+ unsigned ch3 : 1;
22410+ unsigned ch4 : 1;
22411+ unsigned ch5 : 1;
22412+ unsigned ch6 : 1;
22413+ unsigned ch7 : 1;
22414+ unsigned ch8 : 1;
22415+ unsigned ch9 : 1;
22416+ unsigned ch10 : 1;
22417+ unsigned ch11 : 1;
22418+ unsigned ch12 : 1;
22419+ unsigned ch13 : 1;
22420+ unsigned ch14 : 1;
22421+ unsigned ch15 : 1;
22422+ unsigned reserved : 16;
22423+ } b;
22424+
22425+ struct
22426+ {
22427+ unsigned chint : 16;
22428+ unsigned reserved : 16;
22429+ } b2;
22430+} haint_data_t;
22431+
22432+/**
22433+ * This union represents the bit fields in the Host All Interrupt
22434+ * Register.
22435+ */
22436+typedef union haintmsk_data
22437+{
22438+ /** raw register data */
22439+ uint32_t d32;
22440+ /** register bits */
22441+ struct
22442+ {
22443+ unsigned ch0 : 1;
22444+ unsigned ch1 : 1;
22445+ unsigned ch2 : 1;
22446+ unsigned ch3 : 1;
22447+ unsigned ch4 : 1;
22448+ unsigned ch5 : 1;
22449+ unsigned ch6 : 1;
22450+ unsigned ch7 : 1;
22451+ unsigned ch8 : 1;
22452+ unsigned ch9 : 1;
22453+ unsigned ch10 : 1;
22454+ unsigned ch11 : 1;
22455+ unsigned ch12 : 1;
22456+ unsigned ch13 : 1;
22457+ unsigned ch14 : 1;
22458+ unsigned ch15 : 1;
22459+ unsigned reserved : 16;
22460+ } b;
22461+
22462+ struct
22463+ {
22464+ unsigned chint : 16;
22465+ unsigned reserved : 16;
22466+ } b2;
22467+} haintmsk_data_t;
22468+
22469+/**
22470+ * Host Channel Specific Registers. <i>500h-5FCh</i>
22471+ */
22472+typedef struct dwc_otg_hc_regs
22473+{
22474+ /** Host Channel 0 Characteristic Register. <i>Offset: 500h + (chan_num * 20h) + 00h</i> */
22475+ volatile uint32_t hcchar;
22476+ /** Host Channel 0 Split Control Register. <i>Offset: 500h + (chan_num * 20h) + 04h</i> */
22477+ volatile uint32_t hcsplt;
22478+ /** Host Channel 0 Interrupt Register. <i>Offset: 500h + (chan_num * 20h) + 08h</i> */
22479+ volatile uint32_t hcint;
22480+ /** Host Channel 0 Interrupt Mask Register. <i>Offset: 500h + (chan_num * 20h) + 0Ch</i> */
22481+ volatile uint32_t hcintmsk;
22482+ /** Host Channel 0 Transfer Size Register. <i>Offset: 500h + (chan_num * 20h) + 10h</i> */
22483+ volatile uint32_t hctsiz;
22484+ /** Host Channel 0 DMA Address Register. <i>Offset: 500h + (chan_num * 20h) + 14h</i> */
22485+ volatile uint32_t hcdma;
22486+ /** Reserved. <i>Offset: 500h + (chan_num * 20h) + 18h - 500h + (chan_num * 20h) + 1Ch</i> */
22487+ uint32_t reserved[2];
22488+} dwc_otg_hc_regs_t;
22489+
22490+/**
22491+ * This union represents the bit fields in the Host Channel Characteristics
22492+ * Register. Read the register into the <i>d32</i> member then set/clear the
22493+ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
22494+ * hcchar register.
22495+ */
22496+typedef union hcchar_data
22497+{
22498+ /** raw register data */
22499+ uint32_t d32;
22500+
22501+ /** register bits */
22502+ struct
22503+ {
22504+ /** Maximum packet size in bytes */
22505+ unsigned mps : 11;
22506+
22507+ /** Endpoint number */
22508+ unsigned epnum : 4;
22509+
22510+ /** 0: OUT, 1: IN */
22511+ unsigned epdir : 1;
22512+
22513+ unsigned reserved : 1;
22514+
22515+ /** 0: Full/high speed device, 1: Low speed device */
22516+ unsigned lspddev : 1;
22517+
22518+ /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */
22519+ unsigned eptype : 2;
22520+
22521+ /** Packets per frame for periodic transfers. 0 is reserved. */
22522+ unsigned multicnt : 2;
22523+
22524+ /** Device address */
22525+ unsigned devaddr : 7;
22526+
22527+ /**
22528+ * Frame to transmit periodic transaction.
22529+ * 0: even, 1: odd
22530+ */
22531+ unsigned oddfrm : 1;
22532+
22533+ /** Channel disable */
22534+ unsigned chdis : 1;
22535+
22536+ /** Channel enable */
22537+ unsigned chen : 1;
22538+ } b;
22539+} hcchar_data_t;
22540+
22541+typedef union hcsplt_data
22542+{
22543+ /** raw register data */
22544+ uint32_t d32;
22545+
22546+ /** register bits */
22547+ struct
22548+ {
22549+ /** Port Address */
22550+ unsigned prtaddr : 7;
22551+
22552+ /** Hub Address */
22553+ unsigned hubaddr : 7;
22554+
22555+ /** Transaction Position */
22556+ unsigned xactpos : 2;
22557+#define DWC_HCSPLIT_XACTPOS_MID 0
22558+#define DWC_HCSPLIT_XACTPOS_END 1
22559+#define DWC_HCSPLIT_XACTPOS_BEGIN 2
22560+#define DWC_HCSPLIT_XACTPOS_ALL 3
22561+
22562+ /** Do Complete Split */
22563+ unsigned compsplt : 1;
22564+
22565+ /** Reserved */
22566+ unsigned reserved : 14;
22567+
22568+ /** Split Enble */
22569+ unsigned spltena : 1;
22570+ } b;
22571+} hcsplt_data_t;
22572+
22573+
22574+/**
22575+ * This union represents the bit fields in the Host All Interrupt
22576+ * Register.
22577+ */
22578+typedef union hcint_data
22579+{
22580+ /** raw register data */
22581+ uint32_t d32;
22582+ /** register bits */
22583+ struct
22584+ {
22585+ /** Transfer Complete */
22586+ unsigned xfercomp : 1;
22587+ /** Channel Halted */
22588+ unsigned chhltd : 1;
22589+ /** AHB Error */
22590+ unsigned ahberr : 1;
22591+ /** STALL Response Received */
22592+ unsigned stall : 1;
22593+ /** NAK Response Received */
22594+ unsigned nak : 1;
22595+ /** ACK Response Received */
22596+ unsigned ack : 1;
22597+ /** NYET Response Received */
22598+ unsigned nyet : 1;
22599+ /** Transaction Err */
22600+ unsigned xacterr : 1;
22601+ /** Babble Error */
22602+ unsigned bblerr : 1;
22603+ /** Frame Overrun */
22604+ unsigned frmovrun : 1;
22605+ /** Data Toggle Error */
22606+ unsigned datatglerr : 1;
22607+ /** Reserved */
22608+ unsigned reserved : 21;
22609+ } b;
22610+} hcint_data_t;
22611+
22612+/**
22613+ * This union represents the bit fields in the Host Channel Transfer Size
22614+ * Register. Read the register into the <i>d32</i> member then set/clear the
22615+ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
22616+ * hcchar register.
22617+ */
22618+typedef union hctsiz_data
22619+{
22620+ /** raw register data */
22621+ uint32_t d32;
22622+
22623+ /** register bits */
22624+ struct
22625+ {
22626+ /** Total transfer size in bytes */
22627+ unsigned xfersize : 19;
22628+
22629+ /** Data packets to transfer */
22630+ unsigned pktcnt : 10;
22631+
22632+ /**
22633+ * Packet ID for next data packet
22634+ * 0: DATA0
22635+ * 1: DATA2
22636+ * 2: DATA1
22637+ * 3: MDATA (non-Control), SETUP (Control)
22638+ */
22639+ unsigned pid : 2;
22640+#define DWC_HCTSIZ_DATA0 0
22641+#define DWC_HCTSIZ_DATA1 2
22642+#define DWC_HCTSIZ_DATA2 1
22643+#define DWC_HCTSIZ_MDATA 3
22644+#define DWC_HCTSIZ_SETUP 3
22645+
22646+ /** Do PING protocol when 1 */
22647+ unsigned dopng : 1;
22648+ } b;
22649+} hctsiz_data_t;
22650+
22651+/**
22652+ * This union represents the bit fields in the Host Channel Interrupt Mask
22653+ * Register. Read the register into the <i>d32</i> member then set/clear the
22654+ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
22655+ * hcintmsk register.
22656+ */
22657+typedef union hcintmsk_data
22658+{
22659+ /** raw register data */
22660+ uint32_t d32;
22661+
22662+ /** register bits */
22663+ struct
22664+ {
22665+ unsigned xfercompl : 1;
22666+ unsigned chhltd : 1;
22667+ unsigned ahberr : 1;
22668+ unsigned stall : 1;
22669+ unsigned nak : 1;
22670+ unsigned ack : 1;
22671+ unsigned nyet : 1;
22672+ unsigned xacterr : 1;
22673+ unsigned bblerr : 1;
22674+ unsigned frmovrun : 1;
22675+ unsigned datatglerr : 1;
22676+ unsigned reserved : 21;
22677+ } b;
22678+} hcintmsk_data_t;
22679+
22680+/** OTG Host Interface Structure.
22681+ *
22682+ * The OTG Host Interface Structure structure contains information
22683+ * needed to manage the DWC_otg controller acting in host mode. It
22684+ * represents the programming view of the host-specific aspects of the
22685+ * controller.
22686+ */
22687+typedef struct dwc_otg_host_if
22688+{
22689+ /** Host Global Registers starting at offset 400h.*/
22690+ dwc_otg_host_global_regs_t *host_global_regs;
22691+#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400
22692+
22693+ /** Host Port 0 Control and Status Register */
22694+ volatile uint32_t *hprt0;
22695+#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440
22696+
22697+ /** Host Channel Specific Registers at offsets 500h-5FCh. */
22698+ dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS];
22699+#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500
22700+#define DWC_OTG_CHAN_REGS_OFFSET 0x20
22701+
22702+
22703+ /* Host configuration information */
22704+ /** Number of Host Channels (range: 1-16) */
22705+ uint8_t num_host_channels;
22706+ /** Periodic EPs supported (0: no, 1: yes) */
22707+ uint8_t perio_eps_supported;
22708+ /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */
22709+ uint16_t perio_tx_fifo_size;
22710+} dwc_otg_host_if_t;
22711+
22712+
22713+/**
22714+ * This union represents the bit fields in the Power and Clock Gating Control
22715+ * Register. Read the register into the <i>d32</i> member then set/clear the
22716+ * bits using the <i>b</i>it elements.
22717+ */
22718+typedef union pcgcctl_data
22719+{
22720+ /** raw register data */
22721+ uint32_t d32;
22722+
22723+ /** register bits */
22724+ struct
22725+ {
22726+ /** Stop Pclk */
22727+ unsigned stoppclk : 1;
22728+ /** Gate Hclk */
22729+ unsigned gatehclk : 1;
22730+ /** Power Clamp */
22731+ unsigned pwrclmp : 1;
22732+ /** Reset Power Down Modules */
22733+ unsigned rstpdwnmodule : 1;
22734+ /** PHY Suspended */
22735+ unsigned physuspended : 1;
22736+ unsigned reserved : 27;
22737+ } b;
22738+} pcgcctl_data_t;
22739+
22740+
22741+#endif
22742--- a/drivers/usb/core/urb.c
22743+++ b/drivers/usb/core/urb.c
22744@@ -17,7 +17,11 @@ static void urb_destroy(struct kref *kre
22745 
22746     if (urb->transfer_flags & URB_FREE_BUFFER)
22747         kfree(urb->transfer_buffer);
22748-
22749+ if (urb->aligned_transfer_buffer) {
22750+ kfree(urb->aligned_transfer_buffer);
22751+ urb->aligned_transfer_buffer = 0;
22752+ urb->aligned_transfer_dma = 0;
22753+ }
22754     kfree(urb);
22755 }
22756 
22757--- a/include/linux/usb.h
22758+++ b/include/linux/usb.h
22759@@ -1234,6 +1234,9 @@ struct urb {
22760     unsigned int transfer_flags; /* (in) URB_SHORT_NOT_OK | ...*/
22761     void *transfer_buffer; /* (in) associated data buffer */
22762     dma_addr_t transfer_dma; /* (in) dma addr for transfer_buffer */
22763+ void *aligned_transfer_buffer; /* (in) associeated data buffer */
22764+ dma_addr_t aligned_transfer_dma;/* (in) dma addr for transfer_buffer */
22765+ u32 aligned_transfer_buffer_length; /* (in) data buffer length */
22766     struct scatterlist *sg; /* (in) scatter gather buffer list */
22767     int num_mapped_sgs; /* (internal) mapped sg entries */
22768     int num_sgs; /* (in) number of entries in the sg list */
22769--- a/drivers/usb/gadget/Kconfig
22770+++ b/drivers/usb/gadget/Kconfig
22771@@ -125,6 +125,7 @@ config USB_GADGET_STORAGE_NUM_BUFFERS
22772 #
22773 choice
22774     prompt "USB Peripheral Controller"
22775+ depends on !USB_DWC_OTG
22776     help
22777        A USB device uses a controller to talk to its host.
22778        Systems should have only one such upstream link.
22779@@ -616,7 +617,7 @@ config USB_ETH
22780     help
22781       This driver implements Ethernet style communication, in one of
22782       several ways:
22783-
22784+
22785        - The "Communication Device Class" (CDC) Ethernet Control Model.
22786          That protocol is often avoided with pure Ethernet adapters, in
22787          favor of simpler vendor-specific hardware, but is widely
22788@@ -656,7 +657,7 @@ config USB_ETH_RNDIS
22789        If you say "y" here, the Ethernet gadget driver will try to provide
22790        a second device configuration, supporting RNDIS to talk to such
22791        Microsoft USB hosts.
22792-
22793+
22794        To make MS-Windows work with this, use Documentation/usb/linux.inf
22795        as the "driver info file". For versions of MS-Windows older than
22796        XP, you'll need to download drivers from Microsoft's website; a URL
22797--- a/drivers/usb/gadget/Makefile
22798+++ b/drivers/usb/gadget/Makefile
22799@@ -3,7 +3,7 @@
22800 #
22801 ccflags-$(CONFIG_USB_GADGET_DEBUG) := -DDEBUG
22802 
22803-obj-$(CONFIG_USB_GADGET) += udc-core.o
22804+#obj-$(CONFIG_USB_GADGET) += udc-core.o
22805 obj-$(CONFIG_USB_DUMMY_HCD) += dummy_hcd.o
22806 obj-$(CONFIG_USB_NET2272) += net2272.o
22807 obj-$(CONFIG_USB_NET2280) += net2280.o
22808

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