Root/target/linux/cns3xxx/patches-3.3/300-laguna_support.patch

1--- /dev/null
2+++ b/arch/arm/mach-cns3xxx/laguna.c
3@@ -0,0 +1,936 @@
4+/*
5+ * Gateworks Corporation Laguna Platform
6+ *
7+ * Copyright 2000 Deep Blue Solutions Ltd
8+ * Copyright 2008 ARM Limited
9+ * Copyright 2008 Cavium Networks
10+ * Scott Shu
11+ * Copyright 2010 MontaVista Software, LLC.
12+ * Anton Vorontsov <avorontsov@mvista.com>
13+ * Copyright 2011 Gateworks Corporation
14+ * Chris Lang <clang@gateworks.com>
15+ * Copyright 2012 Gateworks Corporation
16+ * Tim Harvey <tharvey@gateworks.com>
17+ *
18+ * This file is free software; you can redistribute it and/or modify
19+ * it under the terms of the GNU General Public License, Version 2, as
20+ * published by the Free Software Foundation.
21+ */
22+
23+#include <linux/init.h>
24+#include <linux/kernel.h>
25+#include <linux/compiler.h>
26+#include <linux/io.h>
27+#include <linux/gpio.h>
28+#include <linux/dma-mapping.h>
29+#include <linux/serial_core.h>
30+#include <linux/serial_8250.h>
31+#include <linux/platform_device.h>
32+#include <linux/mtd/mtd.h>
33+#include <linux/mtd/physmap.h>
34+#include <linux/mtd/partitions.h>
35+#include <linux/leds.h>
36+#include <linux/i2c.h>
37+#include <linux/i2c/at24.h>
38+#include <linux/i2c/pca953x.h>
39+#include <linux/spi/spi.h>
40+#include <linux/spi/flash.h>
41+#include <linux/if_ether.h>
42+#include <asm/setup.h>
43+#include <asm/mach-types.h>
44+#include <asm/mach/arch.h>
45+#include <asm/mach/map.h>
46+#include <asm/mach/time.h>
47+#include <mach/cns3xxx.h>
48+#include <mach/irqs.h>
49+#include <mach/platform.h>
50+#include <mach/pm.h>
51+#include <asm/hardware/gic.h>
52+#include "core.h"
53+#include "devices.h"
54+
55+#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
56+
57+// Config 1 Bitmap
58+#define ETH0_LOAD BIT(0)
59+#define ETH1_LOAD BIT(1)
60+#define ETH2_LOAD BIT(2)
61+#define SATA0_LOAD BIT(3)
62+#define SATA1_LOAD BIT(4)
63+#define PCM_LOAD BIT(5)
64+#define I2S_LOAD BIT(6)
65+#define SPI0_LOAD BIT(7)
66+#define SPI1_LOAD BIT(8)
67+#define PCIE0_LOAD BIT(9)
68+#define PCIE1_LOAD BIT(10)
69+#define USB0_LOAD BIT(11)
70+#define USB1_LOAD BIT(12)
71+#define USB1_ROUTE BIT(13)
72+#define SD_LOAD BIT(14)
73+#define UART0_LOAD BIT(15)
74+#define UART1_LOAD BIT(16)
75+#define UART2_LOAD BIT(17)
76+#define MPCI0_LOAD BIT(18)
77+#define MPCI1_LOAD BIT(19)
78+#define MPCI2_LOAD BIT(20)
79+#define MPCI3_LOAD BIT(21)
80+#define FP_BUT_LOAD BIT(22)
81+#define FP_BUT_HEADER_LOAD BIT(23)
82+#define FP_LED_LOAD BIT(24)
83+#define FP_LED_HEADER_LOAD BIT(25)
84+#define FP_TAMPER_LOAD BIT(26)
85+#define HEADER_33V_LOAD BIT(27)
86+#define SATA_POWER_LOAD BIT(28)
87+#define FP_POWER_LOAD BIT(29)
88+#define GPIO_HEADER_LOAD BIT(30)
89+#define GSP_BAT_LOAD BIT(31)
90+
91+// Config 2 Bitmap
92+#define FAN_LOAD BIT(0)
93+#define SPI_FLASH_LOAD BIT(1)
94+#define NOR_FLASH_LOAD BIT(2)
95+#define GPS_LOAD BIT(3)
96+#define SUPPLY_5V_LOAD BIT(6)
97+#define SUPPLY_33V_LOAD BIT(7)
98+
99+struct laguna_board_info {
100+ char model[16];
101+ u32 config_bitmap;
102+ u32 config2_bitmap;
103+ u8 nor_flash_size;
104+ u8 spi_flash_size;
105+};
106+
107+static struct laguna_board_info laguna_info __initdata;
108+
109+/*
110+ * NOR Flash
111+ */
112+static struct mtd_partition laguna_nor_partitions[] = {
113+ {
114+ .name = "uboot",
115+ .size = SZ_256K,
116+ .offset = 0,
117+ .mask_flags = MTD_WRITEABLE,
118+ }, {
119+ .name = "params",
120+ .size = SZ_128K,
121+ .offset = SZ_256K,
122+ }, {
123+ .name = "kernel",
124+ .size = SZ_2M,
125+ .offset = SZ_256K + SZ_128K,
126+ }, {
127+ .name = "rootfs",
128+ .size = SZ_16M - SZ_256K - SZ_128K - SZ_2M,
129+ .offset = SZ_256K + SZ_128K + SZ_2M,
130+ },
131+};
132+
133+static struct physmap_flash_data laguna_nor_pdata = {
134+ .width = 2,
135+ .parts = laguna_nor_partitions,
136+ .nr_parts = ARRAY_SIZE(laguna_nor_partitions),
137+};
138+
139+static struct resource laguna_nor_res = {
140+ .start = CNS3XXX_FLASH_BASE,
141+ .end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
142+ .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
143+};
144+
145+static struct platform_device laguna_nor_pdev = {
146+ .name = "physmap-flash",
147+ .id = 0,
148+ .resource = &laguna_nor_res,
149+ .num_resources = 1,
150+ .dev = {
151+ .platform_data = &laguna_nor_pdata,
152+ },
153+};
154+
155+/*
156+ * SPI
157+ */
158+static struct mtd_partition laguna_spi_partitions[] = {
159+ {
160+ .name = "uboot",
161+ .size = SZ_256K,
162+ .offset = 0,
163+ .mask_flags = MTD_WRITEABLE,
164+ }, {
165+ .name = "params",
166+ .size = SZ_256K,
167+ .offset = SZ_256K,
168+ }, {
169+ .name = "kernel",
170+ .size = SZ_1M + SZ_512K,
171+ .offset = SZ_512K,
172+ }, {
173+ .name = "rootfs",
174+ .size = SZ_16M - SZ_2M,
175+ .offset = SZ_2M,
176+ },
177+};
178+
179+static struct flash_platform_data laguna_spi_pdata = {
180+ .parts = laguna_spi_partitions,
181+ .nr_parts = ARRAY_SIZE(laguna_spi_partitions),
182+};
183+
184+static struct spi_board_info __initdata laguna_spi_devices[] = {
185+ {
186+ .modalias = "m25p80",
187+ .platform_data = &laguna_spi_pdata,
188+ .max_speed_hz = 50000000,
189+ .bus_num = 1,
190+ .chip_select = 0,
191+ },
192+};
193+
194+static struct platform_device laguna_spi_controller = {
195+ .name = "cns3xxx_spi",
196+};
197+
198+/*
199+ * LED's
200+ */
201+static struct gpio_led laguna_gpio_leds[] = {
202+ {
203+ .name = "user1", /* Green Led */
204+ .gpio = 115,
205+ .active_low = 1,
206+ },{
207+ .name = "user2", /* Red Led */
208+ .gpio = 114,
209+ .active_low = 1,
210+ },{
211+ .name = "pwr1", /* Green Led */
212+ .gpio = 116,
213+ .active_low = 1,
214+ },{
215+ .name = "pwr2", /* Yellow Led */
216+ .gpio = 117,
217+ .active_low = 1,
218+ },{
219+ .name = "txd1", /* Green Led */
220+ .gpio = 118,
221+ .active_low = 1,
222+ },{
223+ .name = "txd2", /* Yellow Led */
224+ .gpio = 119,
225+ .active_low = 1,
226+ },{
227+ .name = "rxd1", /* Green Led */
228+ .gpio = 120,
229+ .active_low = 1,
230+ },{
231+ .name = "rxd2", /* Yellow Led */
232+ .gpio = 121,
233+ .active_low = 1,
234+ },{
235+ .name = "ser1", /* Green Led */
236+ .gpio = 122,
237+ .active_low = 1,
238+ },{
239+ .name = "ser2", /* Yellow Led */
240+ .gpio = 123,
241+ .active_low = 1,
242+ },{
243+ .name = "enet1", /* Green Led */
244+ .gpio = 124,
245+ .active_low = 1,
246+ },{
247+ .name = "enet2", /* Yellow Led */
248+ .gpio = 125,
249+ .active_low = 1,
250+ },{
251+ .name = "sig1_1", /* Green Led */
252+ .gpio = 126,
253+ .active_low = 1,
254+ },{
255+ .name = "sig1_2", /* Yellow Led */
256+ .gpio = 127,
257+ .active_low = 1,
258+ },{
259+ .name = "sig2_1", /* Green Led */
260+ .gpio = 128,
261+ .active_low = 1,
262+ },{
263+ .name = "sig2_2", /* Yellow Led */
264+ .gpio = 129,
265+ .active_low = 1,
266+ },{
267+ .name = "sig3_1", /* Green Led */
268+ .gpio = 130,
269+ .active_low = 1,
270+ },{
271+ .name = "sig3_2", /* Yellow Led */
272+ .gpio = 131,
273+ .active_low = 1,
274+ },{
275+ .name = "net1", /*Green Led */
276+ .gpio = 109,
277+ .active_low = 1,
278+ },{
279+ .name = "net2", /* Red Led */
280+ .gpio = 110,
281+ .active_low = 1,
282+ },{
283+ .name = "mod1", /* Green Led */
284+ .gpio = 111,
285+ .active_low = 1,
286+ },{
287+ .name = "mod2", /* Red Led */
288+ .gpio = 112,
289+ .active_low = 1,
290+ },
291+};
292+
293+static struct gpio_led_platform_data laguna_gpio_leds_data = {
294+ .num_leds = 22,
295+ .leds = laguna_gpio_leds,
296+};
297+
298+static struct platform_device laguna_gpio_leds_device = {
299+ .name = "leds-gpio",
300+ .id = -1,
301+ .dev.platform_data = &laguna_gpio_leds_data,
302+};
303+
304+/*
305+ * Ethernet
306+ */
307+static struct cns3xxx_plat_info laguna_net_data = {
308+ .ports = 0,
309+ .phy = {
310+ 0,
311+ 1,
312+ 2,
313+ },
314+};
315+
316+static struct platform_device laguna_net_device = {
317+ .name = "cns3xxx_eth",
318+ .id = 0,
319+ .dev.platform_data = &laguna_net_data,
320+};
321+
322+/*
323+ * UART
324+ */
325+static void __init laguna_early_serial_setup(void)
326+{
327+#ifdef CONFIG_SERIAL_8250_CONSOLE
328+ static struct uart_port laguna_serial_port = {
329+ .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
330+ .mapbase = CNS3XXX_UART0_BASE,
331+ .irq = IRQ_CNS3XXX_UART0,
332+ .iotype = UPIO_MEM,
333+ .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
334+ .regshift = 2,
335+ .uartclk = 24000000,
336+ .line = 0,
337+ .type = PORT_16550A,
338+ .fifosize = 16,
339+ };
340+
341+ early_serial_setup(&laguna_serial_port);
342+#endif
343+}
344+
345+static struct resource laguna_uart_resources[] = {
346+ {
347+ .start = CNS3XXX_UART0_BASE,
348+ .end = CNS3XXX_UART0_BASE + SZ_4K - 1,
349+ .flags = IORESOURCE_MEM
350+ },{
351+ .start = CNS3XXX_UART2_BASE,
352+ .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
353+ .flags = IORESOURCE_MEM
354+ },{
355+ .start = CNS3XXX_UART2_BASE,
356+ .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
357+ .flags = IORESOURCE_MEM
358+ },
359+};
360+
361+static struct plat_serial8250_port laguna_uart_data[] = {
362+ {
363+ .membase = (char*) (CNS3XXX_UART0_BASE_VIRT),
364+ .mapbase = (CNS3XXX_UART0_BASE),
365+ .irq = IRQ_CNS3XXX_UART0,
366+ .iotype = UPIO_MEM,
367+ .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
368+ .regshift = 2,
369+ .uartclk = 24000000,
370+ .type = PORT_16550A,
371+ },{
372+ .membase = (char*) (CNS3XXX_UART1_BASE_VIRT),
373+ .mapbase = (CNS3XXX_UART1_BASE),
374+ .irq = IRQ_CNS3XXX_UART1,
375+ .iotype = UPIO_MEM,
376+ .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
377+ .regshift = 2,
378+ .uartclk = 24000000,
379+ .type = PORT_16550A,
380+ },{
381+ .membase = (char*) (CNS3XXX_UART2_BASE_VIRT),
382+ .mapbase = (CNS3XXX_UART2_BASE),
383+ .irq = IRQ_CNS3XXX_UART2,
384+ .iotype = UPIO_MEM,
385+ .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
386+ .regshift = 2,
387+ .uartclk = 24000000,
388+ .type = PORT_16550A,
389+ },
390+ { },
391+};
392+
393+static struct platform_device laguna_uart = {
394+ .name = "serial8250",
395+ .id = PLAT8250_DEV_PLATFORM,
396+ .dev.platform_data = laguna_uart_data,
397+ .num_resources = 3,
398+ .resource = laguna_uart_resources
399+};
400+
401+/*
402+ * USB
403+ */
404+static struct resource cns3xxx_usb_ehci_resources[] = {
405+ [0] = {
406+ .start = CNS3XXX_USB_BASE,
407+ .end = CNS3XXX_USB_BASE + SZ_16M - 1,
408+ .flags = IORESOURCE_MEM,
409+ },
410+ [1] = {
411+ .start = IRQ_CNS3XXX_USB_EHCI,
412+ .flags = IORESOURCE_IRQ,
413+ },
414+};
415+
416+static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
417+
418+static struct platform_device cns3xxx_usb_ehci_device = {
419+ .name = "cns3xxx-ehci",
420+ .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
421+ .resource = cns3xxx_usb_ehci_resources,
422+ .dev = {
423+ .dma_mask = &cns3xxx_usb_ehci_dma_mask,
424+ .coherent_dma_mask = DMA_BIT_MASK(32),
425+ },
426+};
427+
428+static struct resource cns3xxx_usb_ohci_resources[] = {
429+ [0] = {
430+ .start = CNS3XXX_USB_OHCI_BASE,
431+ .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
432+ .flags = IORESOURCE_MEM,
433+ },
434+ [1] = {
435+ .start = IRQ_CNS3XXX_USB_OHCI,
436+ .flags = IORESOURCE_IRQ,
437+ },
438+};
439+
440+static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
441+
442+static struct platform_device cns3xxx_usb_ohci_device = {
443+ .name = "cns3xxx-ohci",
444+ .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
445+ .resource = cns3xxx_usb_ohci_resources,
446+ .dev = {
447+ .dma_mask = &cns3xxx_usb_ohci_dma_mask,
448+ .coherent_dma_mask = DMA_BIT_MASK(32),
449+ },
450+};
451+
452+static struct resource cns3xxx_usb_otg_resources[] = {
453+ [0] = {
454+ .start = CNS3XXX_USBOTG_BASE,
455+ .end = CNS3XXX_USBOTG_BASE + SZ_16M - 1,
456+ .flags = IORESOURCE_MEM,
457+ },
458+ [1] = {
459+ .start = IRQ_CNS3XXX_USB_OTG,
460+ .flags = IORESOURCE_IRQ,
461+ },
462+};
463+
464+static u64 cns3xxx_usb_otg_dma_mask = DMA_BIT_MASK(32);
465+
466+static struct platform_device cns3xxx_usb_otg_device = {
467+ .name = "dwc_otg",
468+ .num_resources = ARRAY_SIZE(cns3xxx_usb_otg_resources),
469+ .resource = cns3xxx_usb_otg_resources,
470+ .dev = {
471+ .dma_mask = &cns3xxx_usb_otg_dma_mask,
472+ .coherent_dma_mask = DMA_BIT_MASK(32),
473+ },
474+};
475+
476+/*
477+ * I2C
478+ */
479+static struct resource laguna_i2c_resource[] = {
480+ {
481+ .start = CNS3XXX_SSP_BASE + 0x20,
482+ .end = 0x7100003f,
483+ .flags = IORESOURCE_MEM,
484+ },{
485+ .start = IRQ_CNS3XXX_I2C,
486+ .flags = IORESOURCE_IRQ,
487+ },
488+};
489+
490+static struct platform_device laguna_i2c_controller = {
491+ .name = "cns3xxx-i2c",
492+ .num_resources = 2,
493+ .resource = laguna_i2c_resource,
494+};
495+
496+static struct memory_accessor *at24_mem_acc;
497+
498+static void at24_setup(struct memory_accessor *mem_acc, void *context)
499+{
500+ char buf[16];
501+
502+ at24_mem_acc = mem_acc;
503+
504+ /* Read MAC addresses */
505+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x100, 6) == 6)
506+ memcpy(&laguna_net_data.hwaddr[0], buf, ETH_ALEN);
507+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x106, 6) == 6)
508+ memcpy(&laguna_net_data.hwaddr[1], buf, ETH_ALEN);
509+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x10C, 6) == 6)
510+ memcpy(&laguna_net_data.hwaddr[2], buf, ETH_ALEN);
511+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x112, 6) == 6)
512+ memcpy(&laguna_net_data.hwaddr[3], buf, ETH_ALEN);
513+
514+ /* Read out Model Information */
515+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x130, 16) == 16)
516+ memcpy(&laguna_info.model, buf, 16);
517+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x140, 1) == 1)
518+ memcpy(&laguna_info.nor_flash_size, buf, 1);
519+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x141, 1) == 1)
520+ memcpy(&laguna_info.spi_flash_size, buf, 1);
521+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x142, 4) == 4)
522+ memcpy(&laguna_info.config_bitmap, buf, 4);
523+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x146, 4) == 4)
524+ memcpy(&laguna_info.config2_bitmap, buf, 4);
525+};
526+
527+static struct at24_platform_data laguna_eeprom_info = {
528+ .byte_len = 1024,
529+ .page_size = 16,
530+ .flags = AT24_FLAG_READONLY,
531+ .setup = at24_setup,
532+};
533+
534+static struct pca953x_platform_data laguna_pca_data = {
535+ .gpio_base = 100,
536+ .irq_base = -1,
537+};
538+
539+static struct pca953x_platform_data laguna_pca2_data = {
540+ .gpio_base = 116,
541+ .irq_base = -1,
542+};
543+
544+static struct i2c_board_info __initdata laguna_i2c_devices[] = {
545+ {
546+ I2C_BOARD_INFO("pca9555", 0x23),
547+ .platform_data = &laguna_pca_data,
548+ },{
549+ I2C_BOARD_INFO("pca9555", 0x27),
550+ .platform_data = &laguna_pca2_data,
551+ },{
552+ I2C_BOARD_INFO("gsp", 0x29),
553+ },{
554+ I2C_BOARD_INFO ("24c08",0x50),
555+ .platform_data = &laguna_eeprom_info,
556+ },{
557+ I2C_BOARD_INFO("ds1672", 0x68),
558+ },
559+};
560+
561+/*
562+ * Watchdog
563+ */
564+
565+static struct resource laguna_watchdog_resources[] = {
566+ [0] = {
567+ .start = CNS3XXX_TC11MP_TWD_BASE + 0x100, // CPU0 watchdog
568+ .end = CNS3XXX_TC11MP_TWD_BASE + SZ_4K - 1,
569+ .flags = IORESOURCE_MEM,
570+ },
571+ [1] = {
572+ .start = IRQ_LOCALWDOG,
573+ .end = IRQ_LOCALWDOG,
574+ .flags = IORESOURCE_IRQ,
575+ }
576+};
577+
578+static struct platform_device laguna_watchdog = {
579+ .name = "mpcore_wdt",
580+ .id = -1,
581+ .num_resources = ARRAY_SIZE(laguna_watchdog_resources),
582+ .resource = laguna_watchdog_resources,
583+};
584+
585+/*
586+ * GPIO
587+ */
588+static struct platform_device laguna_gpio_dev = {
589+ .name = "GPIODEV",
590+ .id = -1,
591+};
592+
593+static struct gpio laguna_gpio_gw2391[] = {
594+ { 0, GPIOF_IN , "*GPS_PPS" },
595+ { 1, GPIOF_IN , "*GSC_IRQ#" },
596+ { 2, GPIOF_IN , "*USB_FAULT#" },
597+ { 5, GPIOF_OUT_INIT_LOW , "*USB0_PCI_SEL" },
598+ { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
599+ { 7, GPIOF_OUT_INIT_LOW , "*USB1_PCI_SEL" },
600+ { 8, GPIOF_OUT_INIT_HIGH, "*PERST#" },
601+ { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN#" },
602+ { 100, GPIOF_IN , "*USER_PB#" },
603+ { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
604+ { 108, GPIOF_IN , "DIO0" },
605+ { 109, GPIOF_IN , "DIO1" },
606+ { 110, GPIOF_IN , "DIO2" },
607+ { 111, GPIOF_IN , "DIO3" },
608+ { 112, GPIOF_IN , "DIO4" },
609+};
610+
611+static struct gpio laguna_gpio_gw2388[] = {
612+ { 0, GPIOF_IN , "*GPS_PPS" },
613+ { 1, GPIOF_IN , "*GSC_IRQ#" },
614+ { 3, GPIOF_IN , "*USB_FAULT#" },
615+ { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
616+ { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
617+ { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
618+ { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
619+ { 100, GPIOF_OUT_INIT_HIGH, "*USER_PB#" },
620+ { 108, GPIOF_IN , "DIO0" },
621+ { 109, GPIOF_IN , "DIO1" },
622+ { 110, GPIOF_IN , "DIO2" },
623+ { 111, GPIOF_IN , "DIO3" },
624+ { 112, GPIOF_IN , "DIO4" },
625+};
626+
627+static struct gpio laguna_gpio_gw2387[] = {
628+ { 0, GPIOF_IN , "*GPS_PPS" },
629+ { 1, GPIOF_IN , "*GSC_IRQ#" },
630+ { 2, GPIOF_IN , "*USB_FAULT#" },
631+ { 5, GPIOF_OUT_INIT_LOW , "*USB_PCI_SEL" },
632+ { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
633+ { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
634+ { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
635+ { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
636+ { 100, GPIOF_IN , "*USER_PB#" },
637+ { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
638+ { 108, GPIOF_IN , "DIO0" },
639+ { 109, GPIOF_IN , "DIO1" },
640+ { 110, GPIOF_IN , "DIO2" },
641+ { 111, GPIOF_IN , "DIO3" },
642+ { 112, GPIOF_IN , "DIO4" },
643+ { 113, GPIOF_IN , "DIO5" },
644+};
645+
646+static struct gpio laguna_gpio_gw2384[] = {
647+ { 0, GPIOF_IN , "*GSC_IRQ#" },
648+ { 1, GPIOF_OUT_INIT_HIGH, "*USB_HST_VBUS_EN" },
649+ { 2, GPIOF_IN , "*USB_HST_FAULT#" },
650+ { 5, GPIOF_IN , "*USB_OTG_FAULT#" },
651+ { 6, GPIOF_OUT_INIT_LOW , "*USB_HST_PCI_SEL" },
652+ { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
653+ { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
654+ { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
655+ { 12, GPIOF_OUT_INIT_LOW , "J10_DIOLED0" },
656+ { 13, GPIOF_OUT_INIT_HIGH, "*I2CMUX_RST#" },
657+ { 14, GPIOF_OUT_INIT_LOW , "J10_DIOLED1" },
658+ { 15, GPIOF_OUT_INIT_LOW , "J10_DIOLED2" },
659+ { 100, GPIOF_IN , "*USER_PB#" },
660+ { 103, GPIOF_OUT_INIT_HIGH, "V5_EN" },
661+ { 108, GPIOF_IN , "J9_DIOGSC0" },
662+};
663+
664+static struct gpio laguna_gpio_gw2383[] = {
665+ { 0, GPIOF_IN , "*GPS_PPS" },
666+ { 1, GPIOF_IN , "*GSC_IRQ#" },
667+ { 2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" },
668+ { 3, GPIOF_IN , "GPIO0" },
669+ { 8, GPIOF_IN , "GPIO1" },
670+ { 100, GPIOF_IN , "DIO0" },
671+ { 101, GPIOF_IN , "DIO1" },
672+};
673+
674+static struct gpio laguna_gpio_gw2382[] = {
675+ { 0, GPIOF_IN , "*GPS_PPS" },
676+ { 1, GPIOF_IN , "*GSC_IRQ#" },
677+ { 2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" },
678+ { 3, GPIOF_IN , "GPIO0" },
679+ { 4, GPIOF_IN , "GPIO1" },
680+ { 9, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
681+ { 10, GPIOF_OUT_INIT_HIGH, "*USB_PCI_SEL#" },
682+ { 100, GPIOF_IN , "DIO0" },
683+ { 101, GPIOF_IN , "DIO1" },
684+};
685+
686+static struct gpio laguna_gpio_gw2380[] = {
687+ { 0, GPIOF_IN , "*GPS_PPS" },
688+ { 1, GPIOF_IN , "*GSC_IRQ#" },
689+ { 3, GPIOF_IN , "GPIO0" },
690+ { 8, GPIOF_IN , "GPIO1" },
691+ { 100, GPIOF_IN , "DIO0" },
692+ { 101, GPIOF_IN , "DIO1" },
693+ { 102, GPIOF_IN , "DIO2" },
694+ { 103, GPIOF_IN , "DIO3" },
695+};
696+
697+/*
698+ * Initialization
699+ */
700+static void __init laguna_init(void)
701+{
702+ cns3xxx_l2x0_init();
703+
704+ platform_device_register(&laguna_watchdog);
705+
706+ platform_device_register(&laguna_i2c_controller);
707+
708+ i2c_register_board_info(0, ARRAY_AND_SIZE(laguna_i2c_devices));
709+
710+ pm_power_off = cns3xxx_power_off;
711+}
712+
713+static struct map_desc laguna_io_desc[] __initdata = {
714+ {
715+ .virtual = CNS3XXX_UART0_BASE_VIRT,
716+ .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE),
717+ .length = SZ_4K,
718+ .type = MT_DEVICE,
719+ },{
720+ .virtual = CNS3XXX_UART1_BASE_VIRT,
721+ .pfn = __phys_to_pfn(CNS3XXX_UART1_BASE),
722+ .length = SZ_4K,
723+ .type = MT_DEVICE,
724+ },{
725+ .virtual = CNS3XXX_UART2_BASE_VIRT,
726+ .pfn = __phys_to_pfn(CNS3XXX_UART2_BASE),
727+ .length = SZ_4K,
728+ .type = MT_DEVICE,
729+ },
730+};
731+
732+static void __init laguna_map_io(void)
733+{
734+ cns3xxx_common_init();
735+ cns3xxx_pcie_iotable_init(0x3);
736+ iotable_init(ARRAY_AND_SIZE(laguna_io_desc));
737+ laguna_early_serial_setup();
738+}
739+
740+static int laguna_register_gpio(struct gpio *array, size_t num)
741+{
742+ int i, err, ret;
743+
744+ ret = 0;
745+ for (i = 0; i < num; i++, array++) {
746+ const char *label = array->label;
747+ if (label[0] == '*')
748+ label++;
749+ err = gpio_request_one(array->gpio, array->flags, label);
750+ if (err)
751+ ret = err;
752+ else {
753+ err = gpio_export(array->gpio, array->label[0] != '*');
754+ }
755+ }
756+ return ret;
757+}
758+
759+static int __init laguna_model_setup(void)
760+{
761+ u32 __iomem *mem;
762+ u32 reg;
763+ u8 pcie_bitmap = 0;
764+
765+ printk("Running on Gateworks Laguna %s\n", laguna_info.model);
766+
767+ if (strncmp(laguna_info.model, "GW", 2) == 0) {
768+ if (laguna_info.config_bitmap & ETH0_LOAD)
769+ laguna_net_data.ports |= BIT(0);
770+ if (laguna_info.config_bitmap & ETH1_LOAD)
771+ laguna_net_data.ports |= BIT(1);
772+ if (laguna_info.config_bitmap & ETH2_LOAD)
773+ laguna_net_data.ports |= BIT(2);
774+ if (laguna_net_data.ports)
775+ platform_device_register(&laguna_net_device);
776+
777+ if ((laguna_info.config_bitmap & SATA0_LOAD) ||
778+ (laguna_info.config_bitmap & SATA1_LOAD))
779+ cns3xxx_ahci_init();
780+
781+ if (laguna_info.config_bitmap & (PCIE0_LOAD))
782+ pcie_bitmap |= 0x1;
783+
784+ if (laguna_info.config_bitmap & (PCIE1_LOAD))
785+ pcie_bitmap |= 0x2;
786+
787+ cns3xxx_pcie_init(pcie_bitmap);
788+
789+ if (laguna_info.config_bitmap & (USB0_LOAD)) {
790+ cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
791+
792+ /* DRVVBUS pins share with GPIOA */
793+ mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0014);
794+ reg = __raw_readl(mem);
795+ reg |= 0x8;
796+ __raw_writel(reg, mem);
797+
798+ /* Enable OTG */
799+ mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0808);
800+ reg = __raw_readl(mem);
801+ reg &= ~(1 << 10);
802+ __raw_writel(reg, mem);
803+
804+ platform_device_register(&cns3xxx_usb_otg_device);
805+ }
806+
807+ if (laguna_info.config_bitmap & (USB1_LOAD)) {
808+ platform_device_register(&cns3xxx_usb_ehci_device);
809+ platform_device_register(&cns3xxx_usb_ohci_device);
810+ }
811+
812+ if (laguna_info.config_bitmap & (SD_LOAD))
813+ cns3xxx_sdhci_init();
814+
815+ if (laguna_info.config_bitmap & (UART0_LOAD))
816+ laguna_uart.num_resources = 1;
817+ if (laguna_info.config_bitmap & (UART1_LOAD))
818+ laguna_uart.num_resources = 2;
819+ if (laguna_info.config_bitmap & (UART2_LOAD))
820+ laguna_uart.num_resources = 3;
821+ platform_device_register(&laguna_uart);
822+
823+ if (laguna_info.config2_bitmap & (NOR_FLASH_LOAD)) {
824+ switch (laguna_info.nor_flash_size) {
825+ case 1:
826+ laguna_nor_partitions[3].size = SZ_8M - SZ_256K - SZ_128K - SZ_2M;
827+ laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_8M - 1;
828+ break;
829+ case 2:
830+ laguna_nor_partitions[3].size = SZ_16M - SZ_256K - SZ_128K - SZ_2M;
831+ laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_16M - 1;
832+ break;
833+ case 3:
834+ laguna_nor_partitions[3].size = SZ_32M - SZ_256K - SZ_128K - SZ_2M;
835+ laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_32M - 1;
836+ break;
837+ case 4:
838+ laguna_nor_partitions[3].size = SZ_64M - SZ_256K - SZ_128K - SZ_2M;
839+ laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_64M - 1;
840+ break;
841+ case 5:
842+ laguna_nor_partitions[3].size = SZ_128M - SZ_256K - SZ_128K - SZ_2M;
843+ laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_128M - 1;
844+ break;
845+ }
846+ platform_device_register(&laguna_nor_pdev);
847+ }
848+
849+ if (laguna_info.config2_bitmap & (SPI_FLASH_LOAD)) {
850+ switch (laguna_info.spi_flash_size) {
851+ case 1:
852+ laguna_spi_partitions[3].size = SZ_4M - SZ_2M;
853+ break;
854+ case 2:
855+ laguna_spi_partitions[3].size = SZ_8M - SZ_2M;
856+ break;
857+ case 3:
858+ laguna_spi_partitions[3].size = SZ_16M - SZ_2M;
859+ break;
860+ case 4:
861+ laguna_spi_partitions[3].size = SZ_32M - SZ_2M;
862+ break;
863+ case 5:
864+ laguna_spi_partitions[3].size = SZ_64M - SZ_2M;
865+ break;
866+ }
867+ spi_register_board_info(ARRAY_AND_SIZE(laguna_spi_devices));
868+ }
869+
870+ if ((laguna_info.config_bitmap & SPI0_LOAD) ||
871+ (laguna_info.config_bitmap & SPI1_LOAD))
872+ platform_device_register(&laguna_spi_controller);
873+
874+ /*
875+ * Do any model specific setup not known by the bitmap by matching
876+ * the first 6 characters of the model name
877+ */
878+
879+ if ( (strncmp(laguna_info.model, "GW2388", 6) == 0)
880+ || (strncmp(laguna_info.model, "GW2389", 6) == 0) )
881+ {
882+ // configure GPIO's
883+ laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2388));
884+ // configure LED's
885+ laguna_gpio_leds_data.num_leds = 2;
886+ } else if (strncmp(laguna_info.model, "GW2387", 6) == 0) {
887+ // configure GPIO's
888+ laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2387));
889+ // configure LED's
890+ laguna_gpio_leds_data.num_leds = 2;
891+ } else if (strncmp(laguna_info.model, "GW2384", 6) == 0) {
892+ // configure GPIO's
893+ laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2384));
894+ // configure LED's
895+ laguna_gpio_leds_data.num_leds = 1;
896+ } else if (strncmp(laguna_info.model, "GW2383", 6) == 0) {
897+ // configure GPIO's
898+ laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2383));
899+ // configure LED's
900+ laguna_gpio_leds[0].gpio = 107;
901+ laguna_gpio_leds_data.num_leds = 1;
902+ } else if (strncmp(laguna_info.model, "GW2382", 6) == 0) {
903+ // configure GPIO's
904+ laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2382));
905+ // configure LED's
906+ laguna_gpio_leds[0].gpio = 107;
907+ laguna_gpio_leds_data.num_leds = 1;
908+ } else if (strncmp(laguna_info.model, "GW2380", 6) == 0) {
909+ // configure GPIO's
910+ laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2380));
911+ // configure LED's
912+ laguna_gpio_leds[0].gpio = 107;
913+ laguna_gpio_leds[1].gpio = 106;
914+ laguna_gpio_leds_data.num_leds = 2;
915+ } else if (strncmp(laguna_info.model, "GW2391", 6) == 0) {
916+ // configure GPIO's
917+ laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2391));
918+ // configure LED's
919+ laguna_gpio_leds_data.num_leds = 2;
920+ }
921+ platform_device_register(&laguna_gpio_leds_device);
922+ platform_device_register(&laguna_gpio_dev);
923+ } else {
924+ // Do some defaults here, not sure what yet
925+ }
926+ return 0;
927+}
928+
929+late_initcall(laguna_model_setup);
930+
931+MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform")
932+ .atag_offset = 0x100,
933+ .map_io = laguna_map_io,
934+ .init_irq = cns3xxx_init_irq,
935+ .timer = &cns3xxx_timer,
936+ .handle_irq = gic_handle_irq,
937+ .init_machine = laguna_init,
938+ .restart = cns3xxx_restart,
939+MACHINE_END
940--- a/arch/arm/mach-cns3xxx/Kconfig
941+++ b/arch/arm/mach-cns3xxx/Kconfig
942@@ -11,4 +11,14 @@ config MACH_CNS3420VB
943       This is a platform with an on-board ARM11 MPCore and has support
944       for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc.
945 
946+config MACH_GW2388
947+ bool "Support for Gateworks Laguna Platform"
948+ select HAVE_ARM_SCU if SMP
949+ select MIGHT_HAVE_PCI
950+ help
951+ Include support for the Gateworks Laguna Platform
952+
953+ This is a platform with an on-board ARM11 MPCore and has support
954+ for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, I2C, GIG, etc.
955+
956 endmenu
957--- a/arch/arm/mach-cns3xxx/Makefile
958+++ b/arch/arm/mach-cns3xxx/Makefile
959@@ -1,6 +1,7 @@
960 obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o
961 obj-$(CONFIG_PCI) += pcie.o
962 obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
963+obj-$(CONFIG_MACH_GW2388) += laguna.o
964 obj-$(CONFIG_SMP) += platsmp.o headsmp.o
965 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
966 obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
967--- a/arch/arm/mach-cns3xxx/devices.c
968+++ b/arch/arm/mach-cns3xxx/devices.c
969@@ -19,6 +19,7 @@
970 #include <mach/cns3xxx.h>
971 #include <mach/irqs.h>
972 #include <mach/pm.h>
973+#include <asm/mach-types.h>
974 #include "core.h"
975 #include "devices.h"
976 
977@@ -102,7 +103,11 @@ void __init cns3xxx_sdhci_init(void)
978     u32 gpioa_pins = __raw_readl(gpioa);
979 
980     /* MMC/SD pins share with GPIOA */
981- gpioa_pins |= 0x1fff0004;
982+ if (machine_is_gw2388()) {
983+ gpioa_pins |= 0x1fff0000;
984+ } else {
985+ gpioa_pins |= 0x1fff0004;
986+ }
987     __raw_writel(gpioa_pins, gpioa);
988 
989     cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
990

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