Root/target/linux/coldfire/patches/003-MCF547x-and-MCF548x-support-in-Linux-2.6.38.patch

1From b19b66d24fe96f4f79753762048328fe985351a6 Mon Sep 17 00:00:00 2001
2From: Alison Wang <b18965@freescale.com>
3Date: Thu, 4 Aug 2011 09:59:38 +0800
4Subject: [PATCH 03/52] MCF547x and MCF548x support in Linux 2.6.38
5
6MCF547x and MCF548x support in Linux 2.6.38.
7
8Signed-off-by: Alison Wang <b18965@freescale.com>
9---
10 arch/m68k/coldfire/m547x/Makefile | 7 +
11 arch/m68k/coldfire/m547x/config.c | 412 ++++++++
12 arch/m68k/coldfire/m547x/devices.c | 176 +++
13 arch/m68k/coldfire/m547x/mcf548x-devices.c | 126 +++
14 arch/m68k/configs/m5474lite_defconfig | 1269 ++++++++++++++++++++++
15 arch/m68k/configs/m5475evb_defconfig | 1324 +++++++++++++++++++++++
16 arch/m68k/configs/m5485evb_defconfig | 1582 ++++++++++++++++++++++++++++
17 arch/m68k/include/asm/cf_548x_cacheflush.h | 262 +++++
18 arch/m68k/include/asm/m5485dma.h | 98 ++
19 arch/m68k/include/asm/m5485dspi.h | 146 +++
20 arch/m68k/include/asm/m5485gpio.h | 695 ++++++++++++
21 arch/m68k/include/asm/m5485gpt.h | 90 ++
22 arch/m68k/include/asm/m5485pci.h | 380 +++++++
23 arch/m68k/include/asm/m5485psc.h | 475 +++++++++
24 arch/m68k/include/asm/m5485sec.h | 177 ++++
25 arch/m68k/include/asm/m5485sim.h | 346 ++++++
26 arch/m68k/include/asm/m5485sram.h | 12 +
27 17 files changed, 7577 insertions(+), 0 deletions(-)
28 create mode 100644 arch/m68k/coldfire/m547x/Makefile
29 create mode 100644 arch/m68k/coldfire/m547x/config.c
30 create mode 100644 arch/m68k/coldfire/m547x/devices.c
31 create mode 100644 arch/m68k/coldfire/m547x/mcf548x-devices.c
32 create mode 100644 arch/m68k/configs/m5474lite_defconfig
33 create mode 100644 arch/m68k/configs/m5475evb_defconfig
34 create mode 100644 arch/m68k/configs/m5485evb_defconfig
35 create mode 100644 arch/m68k/include/asm/cf_548x_cacheflush.h
36 create mode 100644 arch/m68k/include/asm/m5485dma.h
37 create mode 100644 arch/m68k/include/asm/m5485dspi.h
38 create mode 100644 arch/m68k/include/asm/m5485gpio.h
39 create mode 100644 arch/m68k/include/asm/m5485gpt.h
40 create mode 100644 arch/m68k/include/asm/m5485pci.h
41 create mode 100644 arch/m68k/include/asm/m5485psc.h
42 create mode 100644 arch/m68k/include/asm/m5485sec.h
43 create mode 100644 arch/m68k/include/asm/m5485sim.h
44 create mode 100644 arch/m68k/include/asm/m5485sram.h
45
46--- /dev/null
47+++ b/arch/m68k/coldfire/m547x/Makefile
48@@ -0,0 +1,7 @@
49+#
50+# Makefile for Linux arch/m68k/coldfire/m547x source directory
51+#
52+
53+obj-$(CONFIG_M547X_8X) += config.o mcf548x-devices.o devices.o
54+obj-$(CONFIG_PCI) += pci.o pci_dummy.o
55+obj-$(CONFIG_MCD_DMA) += dma.o
56--- /dev/null
57+++ b/arch/m68k/coldfire/m547x/config.c
58@@ -0,0 +1,412 @@
59+/*
60+ * linux/arch/m68k/coldfire/config.c
61+ *
62+ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
63+ * Kurt Mahan kmahan@freescale.com
64+ * Matt Waddel Matt.Waddel@freescale.com
65+ * Shrek Wu b16972@freescale.com
66+ *
67+ * This program is free software; you can redistribute it and/or modify
68+ * it under the terms of the GNU General Public License as published by
69+ * the Free Software Foundation; either version 2 of the License, or
70+ * (at your option) any later version.
71+ */
72+
73+#include <linux/module.h>
74+#include <linux/init.h>
75+#include <linux/string.h>
76+#include <linux/kernel.h>
77+#include <linux/console.h>
78+#include <linux/bootmem.h>
79+#include <linux/mm.h>
80+#include <linux/clockchips.h>
81+#include <asm/bootinfo.h>
82+#include <asm/machdep.h>
83+#include <asm/coldfire.h>
84+#include <asm/cfcache.h>
85+#include <asm/cacheflush.h>
86+#include <linux/io.h>
87+#include <asm/cfmmu.h>
88+#include <asm/setup.h>
89+#include <asm/irq.h>
90+#include <asm/traps.h>
91+#include <asm/movs.h>
92+#include <asm/movs.h>
93+#include <asm/page.h>
94+#include <asm/pgalloc.h>
95+
96+#include <asm/mcfsim.h>
97+
98+#define UBOOT_PCI
99+#include <asm/bootinfo.h>
100+#include <asm/m5485gpt.h>
101+
102+extern int get_irq_list(struct seq_file *p, void *v);
103+extern char _text, _end;
104+extern char _etext, _edata, __init_begin, __init_end;
105+extern struct console mcfrs_console;
106+extern char m68k_command_line[CL_SIZE];
107+extern unsigned long availmem;
108+extern struct mem_info m68k_ramdisk;
109+
110+static int irq_enable[NR_IRQS];
111+unsigned long num_pages;
112+
113+/* cf dma physical addresses */
114+unsigned long cf_dma_base;
115+EXPORT_SYMBOL(cf_dma_base);
116+unsigned long cf_dma_end;
117+EXPORT_SYMBOL(cf_dma_end);
118+unsigned long cf_dma_size;
119+EXPORT_SYMBOL(cf_dma_size);
120+
121+/* ethernet mac addresses from uboot */
122+unsigned char uboot_enet0[6];
123+unsigned char uboot_enet1[6];
124+
125+void coldfire_sort_memrec(void)
126+{
127+ int i, j;
128+
129+ /* Sort the m68k_memory records by address */
130+ for (i = 0; i < m68k_num_memory; ++i) {
131+ for (j = i + 1; j < m68k_num_memory; ++j) {
132+ if (m68k_memory[i].addr > m68k_memory[j].addr) {
133+ struct mem_info tmp;
134+ tmp = m68k_memory[i];
135+ m68k_memory[i] = m68k_memory[j];
136+ m68k_memory[j] = tmp;
137+ }
138+ }
139+ }
140+ /* Trim off discontiguous bits */
141+ for (i = 1; i < m68k_num_memory; ++i) {
142+ if ((m68k_memory[i-1].addr + m68k_memory[i-1].size) !=
143+ m68k_memory[i].addr) {
144+ printk(KERN_DEBUG "m68k_parse_bootinfo: "
145+ "addr gap between 0x%lx & 0x%lx\n",
146+ m68k_memory[i-1].addr+m68k_memory[i-1].size,
147+ m68k_memory[i].addr);
148+ m68k_num_memory = i;
149+ break;
150+ }
151+ }
152+}
153+
154+/*
155+ * UBoot Handler
156+ */
157+int __init uboot_commandline(char *bootargs)
158+{
159+ int len = 0, cmd_line_len;
160+ static struct uboot_record uboot_info;
161+ u32 offset = PAGE_OFFSET_RAW - PHYS_OFFSET;
162+
163+ extern unsigned long uboot_info_stk;
164+
165+ /* validate address */
166+ if ((uboot_info_stk < PAGE_OFFSET_RAW) ||
167+ (uboot_info_stk >= (PAGE_OFFSET_RAW + CONFIG_SDRAM_SIZE)))
168+ return 0;
169+
170+ /* Add offset to get post-remapped kernel memory location */
171+ uboot_info.bdi = (struct bd_info *)((*(u32 *)(uboot_info_stk))
172+ + offset);
173+ uboot_info.initrd_start = (*(u32 *)(uboot_info_stk+4)) + offset;
174+ uboot_info.initrd_end = (*(u32 *)(uboot_info_stk+8)) + offset;
175+ uboot_info.cmd_line_start = (*(u32 *)(uboot_info_stk+12)) + offset;
176+ uboot_info.cmd_line_stop = (*(u32 *)(uboot_info_stk+16)) + offset;
177+
178+#if defined(CONFIG_BLK_DEV_INITRD)
179+ m68k_ramdisk.addr = uboot_info.initrd_start;
180+ m68k_ramdisk.size = (uboot_info.initrd_end - uboot_info.initrd_start) ?
181+ (uboot_info.initrd_end - uboot_info.initrd_start + 1) : 0;
182+#endif
183+
184+ /* copy over mac addresses */
185+ memcpy(uboot_enet0, uboot_info.bdi->bi_enet0addr, 6);
186+ memcpy(uboot_enet1, uboot_info.bdi->bi_enet1addr, 6);
187+
188+ /* copy command line */
189+ cmd_line_len = uboot_info.cmd_line_stop - uboot_info.cmd_line_start;
190+ if ((cmd_line_len > 0) && (cmd_line_len < CL_SIZE-1))
191+ len = (int)strncpy(bootargs, (char *)uboot_info.cmd_line_start,\
192+ cmd_line_len);
193+
194+ return len;
195+}
196+
197+/*
198+ * This routine does things not done in the bootloader.
199+ */
200+#define DEFAULT_COMMAND_LINE \
201+ "debug root=/dev/nfs rw \
202+ nfsroot=172.27.155.1:/tftpboot/rigo/rootfs/ \
203+ ip=172.27.155.75:172.27.155.1"
204+
205+asmlinkage void __init cf_early_init(void)
206+{
207+ SET_VBR((void *)MCF_RAMBAR0);
208+
209+ /* Mask all interrupts */
210+ MCF_IMRL = 0xFFFFFFFF;
211+ MCF_IMRH = 0xFFFFFFFF;
212+
213+ m68k_machtype = MACH_CFMMU;
214+ m68k_fputype = FPU_CFV4E;
215+ m68k_mmutype = MMU_CFV4E;
216+ m68k_cputype = CPU_CFV4E;
217+
218+ m68k_num_memory = 0;
219+ m68k_memory[m68k_num_memory].addr = CONFIG_SDRAM_BASE;
220+ m68k_memory[m68k_num_memory++].size = CONFIG_SDRAM_SIZE;
221+
222+ if (!uboot_commandline(m68k_command_line)) {
223+#if defined(CONFIG_BOOTPARAM)
224+ strncpy(m68k_command_line, CONFIG_BOOTPARAM_STRING, CL_SIZE-1);
225+#else
226+ strcpy(m68k_command_line, DEFAULT_COMMAND_LINE);
227+#endif
228+ }
229+
230+ /* Invalidate caches via CACR */
231+ flush_bcache();
232+ cacr_set(CACHE_DISABLE_MODE);
233+
234+ /* Turn on caches via CACR, enable EUSP */
235+ cacr_set(CACHE_INITIAL_MODE);
236+}
237+
238+/* Assembler routines */
239+asmlinkage void buserr(void);
240+asmlinkage void trap(void);
241+asmlinkage void system_call(void);
242+asmlinkage void inthandler(void);
243+
244+void __init coldfire_trap_init(void)
245+{
246+ int i = 0;
247+ e_vector *vectors;
248+
249+ vectors = (e_vector *)MCF_RAMBAR0;
250+ /*
251+ * There is a common trap handler and common interrupt
252+ * handler that handle almost every vector. We treat
253+ * the system call and bus error special, they get their
254+ * own first level handlers.
255+ */
256+ for (i = 3; (i <= 23); i++)
257+ vectors[i] = trap;
258+ for (i = 33; (i <= 63); i++)
259+ vectors[i] = trap;
260+ for (i = 24; (i <= 31); i++)
261+ vectors[i] = inthandler;
262+ for (i = 64; (i < 255); i++)
263+ vectors[i] = inthandler;
264+
265+ vectors[255] = 0;
266+ vectors[2] = buserr;
267+ vectors[32] = system_call;
268+}
269+
270+void coldfire_tick(void)
271+{
272+ /* Reset the ColdFire timer */
273+ MCF_SSR(0) = MCF_SSR_ST;
274+}
275+
276+void __init coldfire_sched_init(irq_handler_t handler)
277+{
278+ int irq = ISC_SLTn(0);
279+
280+ MCF_SCR(0) = 0;
281+ MCF_ICR(irq) = ILP_SLT0;
282+ request_irq(64 + irq, handler, IRQF_DISABLED, "ColdFire Timer 0", NULL);
283+ MCF_SLTCNT(0) = MCF_BUSCLK / HZ;
284+ MCF_SCR(0) |= MCF_SCR_TEN | MCF_SCR_IEN | MCF_SCR_RUN;
285+}
286+
287+unsigned long coldfire_gettimeoffset(void)
288+{
289+ volatile unsigned long trr, tcn, offset;
290+ trr = MCF_SLTCNT(0);
291+ tcn = MCF_SCNT(0);
292+
293+ offset = (trr - tcn) * ((1000000 >> 3) / HZ) / (trr >> 3);
294+ if (MCF_SSR(0) & MCF_SSR_ST)
295+ offset += 1000000 / HZ;
296+
297+ return offset;
298+}
299+
300+static unsigned long long sched_dtim_clk_val;
301+
302+unsigned long long sched_clock(void)
303+{
304+ unsigned long flags;
305+ unsigned long long cycles;
306+ volatile unsigned long trr, tcn, offset;
307+
308+ local_irq_save(flags);
309+ trr = MCF_SLTCNT(0);
310+ tcn = MCF_SCNT(0);
311+ offset = (trr - tcn);
312+ cycles = sched_dtim_clk_val;
313+ local_irq_restore(flags);
314+
315+ return cycles + offset;
316+}
317+
318+unsigned long long sys_dtim2_read(void)
319+{
320+ unsigned long flags;
321+ unsigned long long cycles;
322+ volatile unsigned long trr, tcn, offset;
323+
324+ local_irq_save(flags);
325+ trr = MCF_SLTCNT(0);
326+ tcn = MCF_SCNT(0);
327+ offset = (trr - tcn);
328+ cycles = sched_dtim_clk_val;
329+ local_irq_restore(flags);
330+
331+ return cycles + offset;
332+}
333+
334+static irqreturn_t coldfire_dtim_clk_irq(int irq, void *dev)
335+{
336+ struct clock_event_device *evt =
337+ (struct clock_event_device *)dev;
338+
339+ MCF_SSR(0) = MCF_SSR_ST;
340+ sched_dtim_clk_val += (MCF_BUSCLK) / HZ;
341+ evt->event_handler(evt);
342+ return IRQ_HANDLED;
343+}
344+
345+void sys_dtim2_init(struct clock_event_device *evt)
346+{
347+ int irq = ISC_SLTn(0);
348+
349+ sched_dtim_clk_val = 0;
350+ MCF_SCR(0) = 0;
351+ MCF_ICR(irq) = ILP_SLT0;
352+ request_irq(64 + irq, coldfire_dtim_clk_irq, IRQF_DISABLED,
353+ "ColdFire Timer 0", (void *)evt);
354+ MCF_SLTCNT(0) = MCF_BUSCLK / HZ;
355+ MCF_SCR(0) |= MCF_SCR_TEN | MCF_SCR_IEN | MCF_SCR_RUN;
356+}
357+
358+void coldfire_reboot(void)
359+{
360+ /* disable interrupts and enable the watchdog */
361+ printk(KERN_INFO "Rebooting\n");
362+
363+ /*Disable the XLB priority settings, then set the core to same priority
364+ * level as other XLB masters, also disable the PCI here, otherwise the
365+ * watchdog may fail to reset.
366+ */
367+ MCF_XARB_PRIEN = 0;
368+ MCF_SPCR &= ~0x02;
369+ asm("tpf");
370+ asm("movew #0x2700, %sr\n");
371+ MCF_GPT_GMS0 = MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4);
372+ MCF_GPT_GCIR0 = (0x0A << 16) | 0x03;
373+}
374+
375+static void coldfire_get_model(char *model)
376+{
377+ sprintf(model, "Version 4 ColdFire");
378+}
379+
380+static void __init
381+coldfire_bootmem_alloc(unsigned long memory_start, unsigned long memory_end)
382+{
383+ unsigned long base_pfn;
384+
385+ /* compute total pages in system */
386+ num_pages = PAGE_ALIGN(memory_end - PAGE_OFFSET) >> PAGE_SHIFT;
387+
388+ /* align start/end to page boundries */
389+ memory_start = PAGE_ALIGN(memory_start);
390+ memory_end = memory_end & PAGE_MASK;
391+
392+ /* page numbers */
393+ base_pfn = __pa(PAGE_OFFSET) >> PAGE_SHIFT;
394+ min_low_pfn = __pa(memory_start) >> PAGE_SHIFT;
395+ max_low_pfn = __pa(memory_end) >> PAGE_SHIFT;
396+
397+ high_memory = (void *)memory_end;
398+ availmem = memory_start;
399+
400+ /* setup bootmem data */
401+ m68k_setup_node(0);
402+ availmem += init_bootmem_node(NODE_DATA(0), min_low_pfn,
403+ base_pfn, max_low_pfn);
404+ availmem = PAGE_ALIGN(availmem);
405+
406+ printk(KERN_INFO "** availmem=0x%lx pa(am)=0x%lx\n",
407+ availmem, __pa(availmem));
408+ printk(KERN_INFO "** mstart=0x%lx mend=0x%lx\n",
409+ memory_start, memory_end);
410+ printk(KERN_INFO "bpfn=0x%lx minpfn=0x%lx maxpfn=0x%lx\n",
411+ base_pfn, min_low_pfn, max_low_pfn);
412+
413+ /* turn over physram */
414+ free_bootmem(__pa(availmem), memory_end - (availmem));
415+
416+ /* configure physical dma area */
417+ cf_dma_base = __pa(PAGE_ALIGN(memory_start));
418+ cf_dma_size = CONFIG_DMA_SIZE;
419+ cf_dma_end = CONFIG_SDRAM_BASE + cf_dma_size - 1;
420+
421+ printk(KERN_INFO "dma: phys base=0x%lx phys end=0x%lx virt base=0x%x\n",
422+ cf_dma_base, cf_dma_end, CONFIG_DMA_BASE);
423+
424+ printk(KERN_INFO "mdma=0x%x pa(mdma)=0x%lx\n",
425+ MAX_DMA_ADDRESS, __pa(MAX_DMA_ADDRESS));
426+}
427+
428+void __init config_coldfire(void)
429+{
430+ unsigned long endmem, startmem;
431+ int i;
432+
433+ /*
434+ * Calculate endmem from m68k_memory, assume all are contiguous
435+ */
436+ startmem = ((((int) &_end) + (PAGE_SIZE - 1)) & PAGE_MASK);
437+ endmem = PAGE_OFFSET;
438+ for (i = 0; i < m68k_num_memory; ++i)
439+ endmem += m68k_memory[i].size;
440+
441+ printk(KERN_INFO "starting up linux startmem 0x%lx, endmem 0x%lx, \
442+ size %luMB\n", startmem, endmem, (endmem - startmem) >> 20);
443+
444+ memset(irq_enable, 0, sizeof(irq_enable));
445+
446+ /*
447+ * Setup coldfire mach-specific handlers
448+ */
449+ mach_max_dma_address = 0xffffffff;
450+ mach_sched_init = coldfire_sched_init;
451+ mach_tick = coldfire_tick;
452+ mach_gettimeoffset = coldfire_gettimeoffset;
453+ mach_reset = coldfire_reboot;
454+ mach_get_model = coldfire_get_model;
455+
456+ coldfire_bootmem_alloc(startmem, endmem-1);
457+
458+#if defined(CONFIG_DUMMY_CONSOLE) || defined(CONFIG_FRAMEBUFFER_CONSOLE)
459+ conswitchp = &dummy_con;
460+#endif
461+
462+#if defined(CONFIG_SERIAL_COLDFIRE)
463+ /*
464+ * This causes trouble when it is re-registered later.
465+ * Currently this is fixed by conditionally commenting
466+ * out the register_console in mcf_serial.c
467+ */
468+ register_console(&mcfrs_console);
469+#endif
470+}
471--- /dev/null
472+++ b/arch/m68k/coldfire/m547x/devices.c
473@@ -0,0 +1,176 @@
474+/*
475+ * arch/m68k/coldfire/m547x/devices.c
476+ *
477+ * Coldfire M547x/M548x Platform Device Configuration
478+ *
479+ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
480+ *
481+ * Kurt Mahan <kmahan@freescale.com>
482+ */
483+#include <linux/module.h>
484+#include <linux/kernel.h>
485+#include <linux/init.h>
486+#include <linux/platform_device.h>
487+#include <linux/fsl_devices.h>
488+#include <linux/spi/spi.h>
489+#include <linux/i2c.h>
490+
491+#include <asm/coldfire.h>
492+#include <asm/mcfsim.h>
493+#include <asm/mcfqspi.h>
494+
495+
496+#ifdef CONFIG_SPI
497+/*
498+ *
499+ * DSPI
500+ *
501+ */
502+
503+/* number of supported SPI selects */
504+#define SPI_NUM_CHIPSELECTS 8
505+
506+void coldfire_spi_cs_control(u8 cs, u8 command)
507+{
508+ /* nothing special required */
509+}
510+
511+#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
512+static struct coldfire_spi_chip spidev_chip_info = {
513+ .bits_per_word = 8,
514+};
515+#endif
516+
517+static struct spi_board_info spi_board_info[] = {
518+#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
519+ {
520+ .modalias = "spidev",
521+ .max_speed_hz = 16000000, /* max clk (SCK) speed in HZ */
522+ .bus_num = 1,
523+ .chip_select = 0, /* CS0 */
524+ .controller_data = &spidev_chip_info,
525+ }
526+#endif
527+};
528+
529+static int spi_irq_list[] = {
530+ /* IRQ, ICR Offset, ICR Val,Mask */
531+ 64 + ISC_DSPI_OVRFW, ISC_DSPI_OVRFW, 0x18, 0,
532+ 64 + ISC_DSPI_RFOF, ISC_DSPI_RFOF, 0x18, 0,
533+ 64 + ISC_DSPI_RFDF, ISC_DSPI_RFDF, 0x18, 0,
534+ 64 + ISC_DSPI_TFUF, ISC_DSPI_TFUF, 0x18, 0,
535+ 64 + ISC_DSPI_TCF, ISC_DSPI_TCF, 0x18, 0,
536+ 64 + ISC_DSPI_TFFF, ISC_DSPI_TFFF, 0x18, 0,
537+ 64 + ISC_DSPI_EOQF, ISC_DSPI_EOQF, 0x18, 0,
538+ 0, 0, 0, 0,
539+};
540+
541+static struct coldfire_spi_master coldfire_master_info = {
542+ .bus_num = 1,
543+ .num_chipselect = SPI_NUM_CHIPSELECTS,
544+ .irq_list = spi_irq_list,
545+ .irq_source = 0, /* not used */
546+ .irq_vector = 0, /* not used */
547+ .irq_mask = 0, /* not used */
548+ .irq_lp = 0, /* not used */
549+ .par_val = 0, /* not used */
550+ .cs_control = coldfire_spi_cs_control,
551+};
552+
553+static struct resource coldfire_spi_resources[] = {
554+ [0] = {
555+ .name = "spi-par",
556+ .start = MCF_MBAR + 0x00000a50, /* PAR_DSPI */
557+ .end = MCF_MBAR + 0x00000a50, /* PAR_DSPI */
558+ .flags = IORESOURCE_MEM
559+ },
560+
561+ [1] = {
562+ .name = "spi-module",
563+ .start = MCF_MBAR + 0x00008a00, /* DSPI MCR Base */
564+ .end = MCF_MBAR + 0x00008ab8, /* DSPI mem map end */
565+ .flags = IORESOURCE_MEM
566+ },
567+
568+ [2] = {
569+ .name = "spi-int-level",
570+ .start = MCF_MBAR + 0x740, /* ICR start */
571+ .end = MCF_MBAR + 0x740 + ISC_DSPI_EOQF, /* ICR end */
572+ .flags = IORESOURCE_MEM
573+ },
574+
575+ [3] = {
576+ .name = "spi-int-mask",
577+ .start = MCF_MBAR + 0x70c, /* IMRL */
578+ .end = MCF_MBAR + 0x70c, /* IMRL */
579+ .flags = IORESOURCE_MEM
580+ }
581+};
582+
583+static struct platform_device coldfire_spi = {
584+ .name = "spi_coldfire",
585+ .id = -1,
586+ .resource = coldfire_spi_resources,
587+ .num_resources = ARRAY_SIZE(coldfire_spi_resources),
588+ .dev = {
589+ .platform_data = &coldfire_master_info,
590+ }
591+};
592+
593+/**
594+ * m547x_8x_spi_init - Initialize SPI
595+ */
596+static int __init m547x_8x_spi_init(void)
597+{
598+ int retval;
599+
600+ /* initialize the DSPI PAR */
601+ MCF_GPIO_PAR_DSPI = (MCF_GPIO_PAR_DSPI_PAR_CS5 |
602+ MCF_GPIO_PAR_DSPI_PAR_CS3_DSPICS |
603+ MCF_GPIO_PAR_DSPI_PAR_CS2_DSPICS |
604+ MCF_GPIO_PAR_DSPI_PAR_CS0_DSPICS |
605+ MCF_GPIO_PAR_DSPI_PAR_SCK_SCK |
606+ MCF_GPIO_PAR_DSPI_PAR_SIN_SIN |
607+ MCF_GPIO_PAR_DSPI_PAR_SOUT_SOUT);
608+
609+ /* register device */
610+ retval = platform_device_register(&coldfire_spi);
611+ if (retval < 0)
612+ goto out;
613+
614+ /* register board info */
615+ if (ARRAY_SIZE(spi_board_info))
616+ retval = spi_register_board_info(spi_board_info,
617+ ARRAY_SIZE(spi_board_info));
618+
619+out:
620+ return retval;
621+}
622+#endif
623+
624+#ifdef CONFIG_I2C_BOARDINFO
625+static struct i2c_board_info mcf_i2c_devices[] = {
626+ {
627+ I2C_BOARD_INFO("rv5c387a", 0x32),
628+ },
629+};
630+#endif
631+
632+/**
633+ * m547x_8x_init_devices - Initialize M547X_8X devices
634+ *
635+ * Returns 0 on success.
636+ */
637+static int __init m547x_8x_init_devices(void)
638+{
639+#ifdef CONFIG_SPI
640+ m547x_8x_spi_init();
641+#endif
642+#ifdef CONFIG_I2C_BOARDINFO
643+ i2c_register_board_info(0, mcf_i2c_devices,
644+ ARRAY_SIZE(mcf_i2c_devices));
645+#endif
646+
647+ return 0;
648+}
649+arch_initcall(m547x_8x_init_devices);
650--- /dev/null
651+++ b/arch/m68k/coldfire/m547x/mcf548x-devices.c
652@@ -0,0 +1,126 @@
653+/*
654+ * arch/m68k/coldfire/m547x/mcf548x-devices.c
655+ *
656+ * Coldfire M548x Platform Device Configuration
657+ *
658+ * Based on the Freescale MXC devices.c
659+ *
660+ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
661+ *
662+ * Kurt Mahan <kmahan@freescale.com>
663+ */
664+#include <linux/module.h>
665+#include <linux/kernel.h>
666+#include <linux/init.h>
667+#include <linux/mtd/physmap.h>
668+#include <linux/platform_device.h>
669+#include <linux/fsl_devices.h>
670+
671+#include <asm/coldfire.h>
672+#include <asm/mcfsim.h>
673+#include <asm/mcfuart.h>
674+
675+static struct resource coldfire_i2c_resources[] = {
676+ { /* I/O */
677+ .start = MCF_MBAR + 0x008F00,
678+ .end = MCF_MBAR + 0x008F20,
679+ .flags = IORESOURCE_MEM,
680+ },
681+ { /* IRQ */
682+ .start = 40,
683+ .end = 40,
684+ .flags = IORESOURCE_IRQ,
685+ },
686+};
687+
688+static struct platform_device coldfire_i2c_device = {
689+ .name = "mcf-i2c",
690+ .id = 0, /*bus number*/
691+ .num_resources = ARRAY_SIZE(coldfire_i2c_resources),
692+ .resource = coldfire_i2c_resources,
693+};
694+
695+static struct resource coldfire_sec_resources[] = {
696+ [0] = { /* I/O */
697+ .start = MCF_MBAR + 0x00020000,
698+ .end = MCF_MBAR + 0x00033000,
699+ .flags = IORESOURCE_MEM,
700+ },
701+ [2] = { /* IRQ */
702+ .start = ISC_SEC,
703+ .end = ISC_SEC,
704+ .flags = IORESOURCE_IRQ,
705+ },
706+};
707+
708+static struct platform_device coldfire_sec_device = {
709+ .name = "fsl-sec1",
710+ .id = -1,
711+ .num_resources = ARRAY_SIZE(coldfire_sec_resources),
712+ .resource = coldfire_sec_resources,
713+};
714+
715+static int __init mcf5485_init_devices(void)
716+{
717+ printk(KERN_INFO "MCF5485x INIT_DEVICES\n");
718+
719+ platform_device_register(&coldfire_i2c_device);
720+ platform_device_register(&coldfire_sec_device);
721+ return 0;
722+}
723+arch_initcall(mcf5485_init_devices);
724+
725+static struct mcf_platform_uart m548x_uart_platform[] = {
726+ {
727+ .mapbase = MCF_MBAR + MCFUART_BASE1,
728+ .irq = MCFINT_VECBASE + MCFINT_UART0,
729+ },
730+ {
731+ .mapbase = MCF_MBAR + MCFUART_BASE2,
732+ .irq = MCFINT_VECBASE + MCFINT_UART1,
733+ },
734+ {
735+ .mapbase = MCF_MBAR + MCFUART_BASE3,
736+ .irq = MCFINT_VECBASE + MCFINT_UART2,
737+ },
738+ {
739+ .mapbase = MCF_MBAR + MCFUART_BASE4,
740+ .irq = MCFINT_VECBASE + MCFINT_UART3,
741+ },
742+ { },
743+};
744+
745+static struct platform_device m548x_uart = {
746+ .name = "mcfuart",
747+ .id = 0,
748+ .dev.platform_data = m548x_uart_platform,
749+};
750+
751+static struct platform_device *m548x_devices[] __initdata = {
752+ &m548x_uart,
753+};
754+
755+void m548x_uarts_init(void)
756+{
757+ const int nrlines = ARRAY_SIZE(m548x_uart_platform);
758+ int line;
759+
760+ /* Set GPIO port register to enable PSC(port) signals */
761+ for (line = 0; (line < nrlines); line++) {
762+ MCF_PAR_PSCn(line) = (0
763+ | MCF_PAR_PSC_TXD
764+ | MCF_PAR_PSC_RXD);
765+
766+ MCF_ICR(m548x_uart_platform[line].irq - 64) = ILP_PSCn(line);
767+ }
768+}
769+/***************************************************************************/
770+
771+static int __init init_BSP(void)
772+{
773+ m548x_uarts_init();
774+ platform_add_devices(m548x_devices, ARRAY_SIZE(m548x_devices));
775+ return 0;
776+}
777+
778+arch_initcall(init_BSP);
779--- /dev/null
780+++ b/arch/m68k/configs/m5474lite_defconfig
781@@ -0,0 +1,1269 @@
782+#
783+# Automatically generated make config: don't edit
784+# Linux kernel version: 2.6.29
785+# Tue Aug 24 16:17:48 2010
786+#
787+CONFIG_M68K=y
788+CONFIG_MMU=y
789+CONFIG_GENERIC_TIME=y
790+CONFIG_GENERIC_CLOCKEVENTS=y
791+CONFIG_RWSEM_GENERIC_SPINLOCK=y
792+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
793+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
794+CONFIG_GENERIC_HWEIGHT=y
795+CONFIG_GENERIC_CALIBRATE_DELAY=y
796+# CONFIG_TIME_LOW_RES is not set
797+CONFIG_GENERIC_IOMAP=y
798+# CONFIG_NO_IOPORT is not set
799+# CONFIG_NO_DMA is not set
800+CONFIG_HZ=100
801+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
802+
803+#
804+# General setup
805+#
806+CONFIG_EXPERIMENTAL=y
807+CONFIG_BROKEN_ON_SMP=y
808+CONFIG_INIT_ENV_ARG_LIMIT=32
809+CONFIG_LOCALVERSION=""
810+# CONFIG_LOCALVERSION_AUTO is not set
811+CONFIG_SWAP=y
812+CONFIG_SYSVIPC=y
813+CONFIG_SYSVIPC_SYSCTL=y
814+# CONFIG_POSIX_MQUEUE is not set
815+# CONFIG_BSD_PROCESS_ACCT is not set
816+# CONFIG_TASKSTATS is not set
817+# CONFIG_AUDIT is not set
818+
819+#
820+# RCU Subsystem
821+#
822+CONFIG_CLASSIC_RCU=y
823+# CONFIG_TREE_RCU is not set
824+# CONFIG_PREEMPT_RCU is not set
825+# CONFIG_TREE_RCU_TRACE is not set
826+# CONFIG_PREEMPT_RCU_TRACE is not set
827+CONFIG_IKCONFIG=y
828+CONFIG_IKCONFIG_PROC=y
829+CONFIG_LOG_BUF_SHIFT=17
830+CONFIG_GROUP_SCHED=y
831+CONFIG_FAIR_GROUP_SCHED=y
832+# CONFIG_RT_GROUP_SCHED is not set
833+CONFIG_USER_SCHED=y
834+# CONFIG_CGROUP_SCHED is not set
835+# CONFIG_CGROUPS is not set
836+CONFIG_SYSFS_DEPRECATED=y
837+CONFIG_SYSFS_DEPRECATED_V2=y
838+# CONFIG_RELAY is not set
839+CONFIG_NAMESPACES=y
840+# CONFIG_UTS_NS is not set
841+# CONFIG_IPC_NS is not set
842+# CONFIG_USER_NS is not set
843+# CONFIG_PID_NS is not set
844+# CONFIG_NET_NS is not set
845+# CONFIG_BLK_DEV_INITRD is not set
846+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
847+CONFIG_SYSCTL=y
848+CONFIG_ANON_INODES=y
849+# CONFIG_EMBEDDED is not set
850+CONFIG_UID16=y
851+CONFIG_SYSCTL_SYSCALL=y
852+CONFIG_KALLSYMS=y
853+# CONFIG_KALLSYMS_EXTRA_PASS is not set
854+CONFIG_HOTPLUG=y
855+CONFIG_PRINTK=y
856+CONFIG_BUG=y
857+CONFIG_ELF_CORE=y
858+CONFIG_BASE_FULL=y
859+CONFIG_FUTEX=y
860+CONFIG_EPOLL=y
861+CONFIG_SIGNALFD=y
862+CONFIG_TIMERFD=y
863+CONFIG_EVENTFD=y
864+CONFIG_SHMEM=y
865+CONFIG_AIO=y
866+CONFIG_VM_EVENT_COUNTERS=y
867+CONFIG_PCI_QUIRKS=y
868+CONFIG_COMPAT_BRK=y
869+CONFIG_SLAB=y
870+# CONFIG_SLUB is not set
871+# CONFIG_SLOB is not set
872+# CONFIG_PROFILING is not set
873+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
874+CONFIG_SLABINFO=y
875+CONFIG_RT_MUTEXES=y
876+CONFIG_BASE_SMALL=0
877+CONFIG_MODULES=y
878+# CONFIG_MODULE_FORCE_LOAD is not set
879+CONFIG_MODULE_UNLOAD=y
880+CONFIG_MODULE_FORCE_UNLOAD=y
881+# CONFIG_MODVERSIONS is not set
882+# CONFIG_MODULE_SRCVERSION_ALL is not set
883+CONFIG_BLOCK=y
884+CONFIG_LBD=y
885+# CONFIG_BLK_DEV_IO_TRACE is not set
886+# CONFIG_BLK_DEV_BSG is not set
887+# CONFIG_BLK_DEV_INTEGRITY is not set
888+
889+#
890+# IO Schedulers
891+#
892+CONFIG_IOSCHED_NOOP=y
893+CONFIG_IOSCHED_AS=y
894+CONFIG_IOSCHED_DEADLINE=y
895+CONFIG_IOSCHED_CFQ=y
896+# CONFIG_DEFAULT_AS is not set
897+# CONFIG_DEFAULT_DEADLINE is not set
898+CONFIG_DEFAULT_CFQ=y
899+# CONFIG_DEFAULT_NOOP is not set
900+CONFIG_DEFAULT_IOSCHED="cfq"
901+# CONFIG_FREEZER is not set
902+
903+#
904+# Platform dependent setup
905+#
906+CONFIG_COLDFIRE=y
907+CONFIG_CFV4E=y
908+# CONFIG_FPU is not set
909+CONFIG_MCD_DMA=y
910+# CONFIG_AMIGA is not set
911+# CONFIG_ATARI is not set
912+CONFIG_PCI=y
913+# CONFIG_MAC is not set
914+# CONFIG_APOLLO is not set
915+# CONFIG_VME is not set
916+# CONFIG_HP300 is not set
917+# CONFIG_SUN3X is not set
918+# CONFIG_Q40 is not set
919+# CONFIG_SUN3 is not set
920+
921+#
922+# Processor type
923+#
924+# CONFIG_M68020 is not set
925+# CONFIG_M68030 is not set
926+# CONFIG_M68040 is not set
927+# CONFIG_M68060 is not set
928+# CONFIG_M5445X is not set
929+# CONFIG_HAVE_FSL_USB_DR is not set
930+CONFIG_M547X_8X=y
931+CONFIG_M547X=y
932+# CONFIG_M548X is not set
933+CONFIG_M5474LITE=y
934+# CONFIG_M5475AFE is not set
935+# CONFIG_M5475BFE is not set
936+# CONFIG_M5475CFE is not set
937+# CONFIG_M5475DFE is not set
938+# CONFIG_M5475EFE is not set
939+# CONFIG_M5475FFE is not set
940+# CONFIG_M5484LITE is not set
941+# CONFIG_M5485AFE is not set
942+# CONFIG_M5485BFE is not set
943+# CONFIG_M5485CFE is not set
944+# CONFIG_M5485DFE is not set
945+# CONFIG_M5485EFE is not set
946+# CONFIG_M5485FFE is not set
947+# CONFIG_M5441X is not set
948+CONFIG_MCFCLK=266000000
949+# CONFIG_MCF_USER_HALT is not set
950+CONFIG_MMU_CFV4E=y
951+CONFIG_SDRAM_BASE=0x00000000
952+CONFIG_SDRAM_SIZE=0x04000000
953+CONFIG_NOR_FLASH_BASE=0xFF800000
954+CONFIG_DMA_BASE=0xef000000
955+CONFIG_DMA_SIZE=0x800000
956+CONFIG_VDSO=y
957+# CONFIG_M68KFPU_EMU is not set
958+CONFIG_ADVANCED=y
959+# CONFIG_RMW_INSNS is not set
960+CONFIG_SINGLE_MEMORY_CHUNK=y
961+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
962+CONFIG_SELECT_MEMORY_MODEL=y
963+CONFIG_FLATMEM_MANUAL=y
964+# CONFIG_DISCONTIGMEM_MANUAL is not set
965+# CONFIG_SPARSEMEM_MANUAL is not set
966+CONFIG_FLATMEM=y
967+CONFIG_FLAT_NODE_MEM_MAP=y
968+CONFIG_NEED_MULTIPLE_NODES=y
969+CONFIG_PAGEFLAGS_EXTENDED=y
970+CONFIG_SPLIT_PTLOCK_CPUS=4
971+# CONFIG_PHYS_ADDR_T_64BIT is not set
972+CONFIG_ZONE_DMA_FLAG=1
973+CONFIG_BOUNCE=y
974+CONFIG_VIRT_TO_BUS=y
975+CONFIG_UNEVICTABLE_LRU=y
976+
977+#
978+# General setup
979+#
980+CONFIG_BINFMT_ELF=y
981+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
982+CONFIG_HAVE_AOUT=y
983+# CONFIG_BINFMT_AOUT is not set
984+# CONFIG_BINFMT_MISC is not set
985+CONFIG_PROC_HARDWARE=y
986+CONFIG_ZONE_DMA=y
987+# CONFIG_ARCH_SUPPORTS_MSI is not set
988+CONFIG_PCI_LEGACY=y
989+# CONFIG_PCI_STUB is not set
990+
991+#
992+# Power management options
993+#
994+# CONFIG_PM is not set
995+CONFIG_NET=y
996+
997+#
998+# Networking options
999+#
1000+CONFIG_COMPAT_NET_DEV_OPS=y
1001+CONFIG_PACKET=y
1002+# CONFIG_PACKET_MMAP is not set
1003+CONFIG_UNIX=y
1004+CONFIG_XFRM=y
1005+# CONFIG_XFRM_USER is not set
1006+# CONFIG_XFRM_SUB_POLICY is not set
1007+# CONFIG_XFRM_MIGRATE is not set
1008+# CONFIG_XFRM_STATISTICS is not set
1009+CONFIG_NET_KEY=y
1010+# CONFIG_NET_KEY_MIGRATE is not set
1011+CONFIG_INET=y
1012+# CONFIG_IP_MULTICAST is not set
1013+CONFIG_IP_ADVANCED_ROUTER=y
1014+CONFIG_ASK_IP_FIB_HASH=y
1015+# CONFIG_IP_FIB_TRIE is not set
1016+CONFIG_IP_FIB_HASH=y
1017+# CONFIG_IP_MULTIPLE_TABLES is not set
1018+# CONFIG_IP_ROUTE_MULTIPATH is not set
1019+# CONFIG_IP_ROUTE_VERBOSE is not set
1020+CONFIG_IP_PNP=y
1021+# CONFIG_IP_PNP_DHCP is not set
1022+# CONFIG_IP_PNP_BOOTP is not set
1023+# CONFIG_IP_PNP_RARP is not set
1024+# CONFIG_NET_IPIP is not set
1025+# CONFIG_NET_IPGRE is not set
1026+# CONFIG_ARPD is not set
1027+# CONFIG_SYN_COOKIES is not set
1028+CONFIG_INET_AH=y
1029+CONFIG_INET_ESP=y
1030+# CONFIG_INET_IPCOMP is not set
1031+# CONFIG_INET_XFRM_TUNNEL is not set
1032+# CONFIG_INET_TUNNEL is not set
1033+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
1034+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
1035+# CONFIG_INET_XFRM_MODE_BEET is not set
1036+# CONFIG_INET_LRO is not set
1037+CONFIG_INET_DIAG=y
1038+CONFIG_INET_TCP_DIAG=y
1039+# CONFIG_TCP_CONG_ADVANCED is not set
1040+CONFIG_TCP_CONG_CUBIC=y
1041+CONFIG_DEFAULT_TCP_CONG="cubic"
1042+# CONFIG_TCP_MD5SIG is not set
1043+# CONFIG_IPV6 is not set
1044+# CONFIG_NETWORK_SECMARK is not set
1045+# CONFIG_NETFILTER is not set
1046+# CONFIG_IP_DCCP is not set
1047+# CONFIG_IP_SCTP is not set
1048+# CONFIG_TIPC is not set
1049+# CONFIG_ATM is not set
1050+# CONFIG_BRIDGE is not set
1051+# CONFIG_NET_DSA is not set
1052+# CONFIG_VLAN_8021Q is not set
1053+# CONFIG_DECNET is not set
1054+# CONFIG_LLC2 is not set
1055+# CONFIG_IPX is not set
1056+# CONFIG_ATALK is not set
1057+# CONFIG_X25 is not set
1058+# CONFIG_LAPB is not set
1059+# CONFIG_ECONET is not set
1060+# CONFIG_WAN_ROUTER is not set
1061+# CONFIG_NET_SCHED is not set
1062+# CONFIG_DCB is not set
1063+
1064+#
1065+# Network testing
1066+#
1067+# CONFIG_NET_PKTGEN is not set
1068+# CONFIG_HAMRADIO is not set
1069+CONFIG_CAN=y
1070+CONFIG_CAN_RAW=y
1071+# CONFIG_CAN_BCM is not set
1072+
1073+#
1074+# CAN Device Drivers
1075+#
1076+# CONFIG_CAN_VCAN is not set
1077+# CONFIG_CAN_DEV is not set
1078+CONFIG_CAN_FLEXCAN=y
1079+# CONFIG_CAN_DEBUG_DEVICES is not set
1080+# CONFIG_IRDA is not set
1081+# CONFIG_BT is not set
1082+# CONFIG_AF_RXRPC is not set
1083+# CONFIG_PHONET is not set
1084+CONFIG_WIRELESS=y
1085+# CONFIG_CFG80211 is not set
1086+CONFIG_WIRELESS_OLD_REGULATORY=y
1087+# CONFIG_WIRELESS_EXT is not set
1088+# CONFIG_LIB80211 is not set
1089+# CONFIG_MAC80211 is not set
1090+# CONFIG_WIMAX is not set
1091+# CONFIG_RFKILL is not set
1092+# CONFIG_NET_9P is not set
1093+# CONFIG_KLIPS is not set
1094+
1095+#
1096+# Device Drivers
1097+#
1098+
1099+#
1100+# Generic Driver Options
1101+#
1102+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
1103+# CONFIG_STANDALONE is not set
1104+CONFIG_PREVENT_FIRMWARE_BUILD=y
1105+CONFIG_FW_LOADER=y
1106+CONFIG_FIRMWARE_IN_KERNEL=y
1107+CONFIG_EXTRA_FIRMWARE=""
1108+# CONFIG_SYS_HYPERVISOR is not set
1109+# CONFIG_CONNECTOR is not set
1110+CONFIG_MTD=y
1111+# CONFIG_MTD_DEBUG is not set
1112+CONFIG_MTD_CONCAT=y
1113+CONFIG_MTD_PARTITIONS=y
1114+# CONFIG_MTD_TESTS is not set
1115+# CONFIG_MTD_REDBOOT_PARTS is not set
1116+CONFIG_MTD_CMDLINE_PARTS=y
1117+# CONFIG_MTD_AR7_PARTS is not set
1118+
1119+#
1120+# User Modules And Translation Layers
1121+#
1122+CONFIG_MTD_CHAR=y
1123+CONFIG_MTD_BLKDEVS=y
1124+CONFIG_MTD_BLOCK=y
1125+# CONFIG_FTL is not set
1126+# CONFIG_NFTL is not set
1127+# CONFIG_INFTL is not set
1128+# CONFIG_RFD_FTL is not set
1129+# CONFIG_SSFDC is not set
1130+# CONFIG_MTD_OOPS is not set
1131+
1132+#
1133+# RAM/ROM/Flash chip drivers
1134+#
1135+CONFIG_MTD_CFI=y
1136+# CONFIG_MTD_JEDECPROBE is not set
1137+CONFIG_MTD_GEN_PROBE=y
1138+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
1139+CONFIG_MTD_MAP_BANK_WIDTH_1=y
1140+CONFIG_MTD_MAP_BANK_WIDTH_2=y
1141+CONFIG_MTD_MAP_BANK_WIDTH_4=y
1142+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
1143+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
1144+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
1145+CONFIG_MTD_CFI_I1=y
1146+CONFIG_MTD_CFI_I2=y
1147+# CONFIG_MTD_CFI_I4 is not set
1148+# CONFIG_MTD_CFI_I8 is not set
1149+CONFIG_MTD_CFI_INTELEXT=y
1150+CONFIG_MTD_CFI_AMDSTD=y
1151+CONFIG_MTD_CFI_STAA=y
1152+CONFIG_MTD_CFI_UTIL=y
1153+CONFIG_MTD_RAM=y
1154+CONFIG_MTD_ROM=y
1155+# CONFIG_MTD_ABSENT is not set
1156+
1157+#
1158+# Mapping drivers for chip access
1159+#
1160+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
1161+CONFIG_MTD_PHYSMAP=y
1162+CONFIG_MTD_PHYSMAP_COMPAT=y
1163+CONFIG_MTD_PHYSMAP_START=0xff800000
1164+CONFIG_MTD_PHYSMAP_LEN=0x400000
1165+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
1166+# CONFIG_MTD_INTEL_VR_NOR is not set
1167+# CONFIG_MTD_PLATRAM is not set
1168+
1169+#
1170+# Self-contained MTD device drivers
1171+#
1172+# CONFIG_MTD_PMC551 is not set
1173+# CONFIG_MTD_SLRAM is not set
1174+# CONFIG_MTD_PHRAM is not set
1175+# CONFIG_MTD_MTDRAM is not set
1176+# CONFIG_MTD_BLOCK2MTD is not set
1177+
1178+#
1179+# Disk-On-Chip Device Drivers
1180+#
1181+# CONFIG_MTD_DOC2000 is not set
1182+# CONFIG_MTD_DOC2001 is not set
1183+# CONFIG_MTD_DOC2001PLUS is not set
1184+# CONFIG_MTD_NAND is not set
1185+# CONFIG_MTD_ONENAND is not set
1186+
1187+#
1188+# LPDDR flash memory drivers
1189+#
1190+# CONFIG_MTD_LPDDR is not set
1191+
1192+#
1193+# UBI - Unsorted block images
1194+#
1195+# CONFIG_MTD_UBI is not set
1196+# CONFIG_PARPORT is not set
1197+CONFIG_BLK_DEV=y
1198+# CONFIG_BLK_CPQ_DA is not set
1199+# CONFIG_BLK_CPQ_CISS_DA is not set
1200+# CONFIG_BLK_DEV_DAC960 is not set
1201+# CONFIG_BLK_DEV_UMEM is not set
1202+# CONFIG_BLK_DEV_COW_COMMON is not set
1203+CONFIG_BLK_DEV_LOOP=y
1204+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
1205+# CONFIG_BLK_DEV_NBD is not set
1206+# CONFIG_BLK_DEV_SX8 is not set
1207+CONFIG_BLK_DEV_RAM=y
1208+CONFIG_BLK_DEV_RAM_COUNT=16
1209+CONFIG_BLK_DEV_RAM_SIZE=64000
1210+# CONFIG_BLK_DEV_XIP is not set
1211+# CONFIG_CDROM_PKTCDVD is not set
1212+# CONFIG_ATA_OVER_ETH is not set
1213+# CONFIG_BLK_DEV_HD is not set
1214+CONFIG_MISC_DEVICES=y
1215+# CONFIG_PHANTOM is not set
1216+# CONFIG_SGI_IOC4 is not set
1217+# CONFIG_TIFM_CORE is not set
1218+# CONFIG_ICS932S401 is not set
1219+# CONFIG_ENCLOSURE_SERVICES is not set
1220+# CONFIG_HP_ILO is not set
1221+# CONFIG_C2PORT is not set
1222+
1223+#
1224+# EEPROM support
1225+#
1226+# CONFIG_EEPROM_AT24 is not set
1227+# CONFIG_EEPROM_LEGACY is not set
1228+# CONFIG_EEPROM_93CX6 is not set
1229+CONFIG_HAVE_IDE=y
1230+CONFIG_IDE=y
1231+
1232+#
1233+# Please see Documentation/ide/ide.txt for help/info on IDE drives
1234+#
1235+# CONFIG_BLK_DEV_IDE_SATA is not set
1236+CONFIG_IDE_GD=y
1237+CONFIG_IDE_GD_ATA=y
1238+# CONFIG_IDE_GD_ATAPI is not set
1239+# CONFIG_BLK_DEV_IDECD is not set
1240+# CONFIG_BLK_DEV_IDETAPE is not set
1241+# CONFIG_IDE_TASK_IOCTL is not set
1242+CONFIG_IDE_PROC_FS=y
1243+
1244+#
1245+# IDE chipset support/bugfixes
1246+#
1247+# CONFIG_BLK_DEV_PLATFORM is not set
1248+
1249+#
1250+# PCI IDE chipsets support
1251+#
1252+# CONFIG_BLK_DEV_GENERIC is not set
1253+# CONFIG_BLK_DEV_OPTI621 is not set
1254+# CONFIG_BLK_DEV_AEC62XX is not set
1255+# CONFIG_BLK_DEV_ALI15X3 is not set
1256+# CONFIG_BLK_DEV_AMD74XX is not set
1257+# CONFIG_BLK_DEV_CMD64X is not set
1258+# CONFIG_BLK_DEV_TRIFLEX is not set
1259+# CONFIG_BLK_DEV_CS5520 is not set
1260+# CONFIG_BLK_DEV_CS5530 is not set
1261+# CONFIG_BLK_DEV_HPT366 is not set
1262+# CONFIG_BLK_DEV_JMICRON is not set
1263+# CONFIG_BLK_DEV_SC1200 is not set
1264+# CONFIG_BLK_DEV_PIIX is not set
1265+# CONFIG_BLK_DEV_IT8172 is not set
1266+# CONFIG_BLK_DEV_IT8213 is not set
1267+# CONFIG_BLK_DEV_IT821X is not set
1268+# CONFIG_BLK_DEV_NS87415 is not set
1269+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
1270+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
1271+# CONFIG_BLK_DEV_SVWKS is not set
1272+# CONFIG_BLK_DEV_SIIMAGE is not set
1273+# CONFIG_BLK_DEV_SLC90E66 is not set
1274+# CONFIG_BLK_DEV_TRM290 is not set
1275+# CONFIG_BLK_DEV_VIA82CXXX is not set
1276+# CONFIG_BLK_DEV_TC86C001 is not set
1277+# CONFIG_BLK_DEV_IDEDMA is not set
1278+
1279+#
1280+# SCSI device support
1281+#
1282+# CONFIG_RAID_ATTRS is not set
1283+CONFIG_SCSI=y
1284+CONFIG_SCSI_DMA=y
1285+# CONFIG_SCSI_TGT is not set
1286+# CONFIG_SCSI_NETLINK is not set
1287+CONFIG_SCSI_PROC_FS=y
1288+
1289+#
1290+# SCSI support type (disk, tape, CD-ROM)
1291+#
1292+CONFIG_BLK_DEV_SD=y
1293+# CONFIG_CHR_DEV_ST is not set
1294+# CONFIG_CHR_DEV_OSST is not set
1295+# CONFIG_BLK_DEV_SR is not set
1296+# CONFIG_CHR_DEV_SG is not set
1297+# CONFIG_CHR_DEV_SCH is not set
1298+
1299+#
1300+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
1301+#
1302+CONFIG_SCSI_MULTI_LUN=y
1303+# CONFIG_SCSI_CONSTANTS is not set
1304+# CONFIG_SCSI_LOGGING is not set
1305+# CONFIG_SCSI_SCAN_ASYNC is not set
1306+CONFIG_SCSI_WAIT_SCAN=m
1307+
1308+#
1309+# SCSI Transports
1310+#
1311+# CONFIG_SCSI_SPI_ATTRS is not set
1312+# CONFIG_SCSI_FC_ATTRS is not set
1313+# CONFIG_SCSI_ISCSI_ATTRS is not set
1314+# CONFIG_SCSI_SAS_LIBSAS is not set
1315+# CONFIG_SCSI_SRP_ATTRS is not set
1316+# CONFIG_SCSI_LOWLEVEL is not set
1317+# CONFIG_SCSI_DH is not set
1318+CONFIG_ATA=y
1319+# CONFIG_ATA_NONSTANDARD is not set
1320+CONFIG_SATA_PMP=y
1321+# CONFIG_SATA_AHCI is not set
1322+CONFIG_SATA_SIL24=y
1323+CONFIG_ATA_SFF=y
1324+# CONFIG_SATA_SVW is not set
1325+# CONFIG_ATA_PIIX is not set
1326+# CONFIG_SATA_MV is not set
1327+# CONFIG_SATA_NV is not set
1328+# CONFIG_PDC_ADMA is not set
1329+# CONFIG_SATA_QSTOR is not set
1330+# CONFIG_SATA_PROMISE is not set
1331+# CONFIG_SATA_SX4 is not set
1332+CONFIG_SATA_SIL=y
1333+# CONFIG_SATA_SIS is not set
1334+# CONFIG_SATA_ULI is not set
1335+# CONFIG_SATA_VIA is not set
1336+# CONFIG_SATA_VITESSE is not set
1337+# CONFIG_SATA_INIC162X is not set
1338+# CONFIG_PATA_ALI is not set
1339+# CONFIG_PATA_AMD is not set
1340+# CONFIG_PATA_ARTOP is not set
1341+# CONFIG_PATA_ATIIXP is not set
1342+# CONFIG_PATA_CMD640_PCI is not set
1343+# CONFIG_PATA_CMD64X is not set
1344+# CONFIG_PATA_CS5520 is not set
1345+# CONFIG_PATA_CS5530 is not set
1346+# CONFIG_PATA_CYPRESS is not set
1347+# CONFIG_PATA_EFAR is not set
1348+# CONFIG_ATA_GENERIC is not set
1349+# CONFIG_PATA_HPT366 is not set
1350+# CONFIG_PATA_HPT37X is not set
1351+# CONFIG_PATA_HPT3X2N is not set
1352+# CONFIG_PATA_HPT3X3 is not set
1353+# CONFIG_PATA_IT821X is not set
1354+# CONFIG_PATA_IT8213 is not set
1355+# CONFIG_PATA_JMICRON is not set
1356+# CONFIG_PATA_TRIFLEX is not set
1357+# CONFIG_PATA_MARVELL is not set
1358+# CONFIG_PATA_MPIIX is not set
1359+# CONFIG_PATA_OLDPIIX is not set
1360+# CONFIG_PATA_NETCELL is not set
1361+# CONFIG_PATA_NINJA32 is not set
1362+# CONFIG_PATA_NS87410 is not set
1363+# CONFIG_PATA_NS87415 is not set
1364+# CONFIG_PATA_OPTI is not set
1365+# CONFIG_PATA_OPTIDMA is not set
1366+# CONFIG_PATA_PDC_OLD is not set
1367+# CONFIG_PATA_RADISYS is not set
1368+# CONFIG_PATA_RZ1000 is not set
1369+# CONFIG_PATA_SC1200 is not set
1370+# CONFIG_PATA_SERVERWORKS is not set
1371+# CONFIG_PATA_PDC2027X is not set
1372+# CONFIG_PATA_SIL680 is not set
1373+# CONFIG_PATA_SIS is not set
1374+# CONFIG_PATA_VIA is not set
1375+# CONFIG_PATA_WINBOND is not set
1376+# CONFIG_PATA_SCH is not set
1377+# CONFIG_MD is not set
1378+# CONFIG_FUSION is not set
1379+
1380+#
1381+# IEEE 1394 (FireWire) support
1382+#
1383+
1384+#
1385+# Enable only one of the two stacks, unless you know what you are doing
1386+#
1387+# CONFIG_FIREWIRE is not set
1388+# CONFIG_IEEE1394 is not set
1389+# CONFIG_I2O is not set
1390+CONFIG_NETDEVICES=y
1391+# CONFIG_DUMMY is not set
1392+# CONFIG_BONDING is not set
1393+# CONFIG_MACVLAN is not set
1394+# CONFIG_EQUALIZER is not set
1395+# CONFIG_TUN is not set
1396+# CONFIG_VETH is not set
1397+# CONFIG_ARCNET is not set
1398+CONFIG_PHYLIB=y
1399+
1400+#
1401+# MII PHY device drivers
1402+#
1403+# CONFIG_MARVELL_PHY is not set
1404+# CONFIG_DAVICOM_PHY is not set
1405+# CONFIG_QSEMI_PHY is not set
1406+# CONFIG_LXT_PHY is not set
1407+# CONFIG_CICADA_PHY is not set
1408+# CONFIG_VITESSE_PHY is not set
1409+# CONFIG_SMSC_PHY is not set
1410+# CONFIG_BROADCOM_PHY is not set
1411+CONFIG_BROADCOM5222_PHY=y
1412+# CONFIG_ICPLUS_PHY is not set
1413+# CONFIG_REALTEK_PHY is not set
1414+# CONFIG_NATIONAL_PHY is not set
1415+# CONFIG_NATIONAL8364x_PHY is not set
1416+# CONFIG_NATIONAL8384x_PHY is not set
1417+# CONFIG_MicrelKSZ8041_PHY is not set
1418+# CONFIG_STE10XP is not set
1419+# CONFIG_LSI_ET1011C_PHY is not set
1420+# CONFIG_FIXED_PHY is not set
1421+# CONFIG_MDIO_BITBANG is not set
1422+CONFIG_NET_ETHERNET=y
1423+CONFIG_MII=y
1424+# CONFIG_HAPPYMEAL is not set
1425+# CONFIG_SUNGEM is not set
1426+# CONFIG_CASSINI is not set
1427+# CONFIG_NET_VENDOR_3COM is not set
1428+# CONFIG_DNET is not set
1429+# CONFIG_NET_TULIP is not set
1430+# CONFIG_HP100 is not set
1431+# CONFIG_IBM_NEW_EMAC_ZMII is not set
1432+# CONFIG_IBM_NEW_EMAC_RGMII is not set
1433+# CONFIG_IBM_NEW_EMAC_TAH is not set
1434+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
1435+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
1436+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
1437+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
1438+CONFIG_NET_PCI=y
1439+# CONFIG_PCNET32 is not set
1440+# CONFIG_AMD8111_ETH is not set
1441+# CONFIG_ADAPTEC_STARFIRE is not set
1442+# CONFIG_B44 is not set
1443+# CONFIG_FORCEDETH is not set
1444+CONFIG_E100=y
1445+# CONFIG_FEALNX is not set
1446+# CONFIG_NATSEMI is not set
1447+CONFIG_NE2K_PCI=y
1448+# CONFIG_8139CP is not set
1449+CONFIG_8139TOO=y
1450+CONFIG_8139TOO_PIO=y
1451+# CONFIG_8139TOO_TUNE_TWISTER is not set
1452+# CONFIG_8139TOO_8129 is not set
1453+# CONFIG_8139_OLD_RX_RESET is not set
1454+# CONFIG_R6040 is not set
1455+# CONFIG_SIS900 is not set
1456+# CONFIG_EPIC100 is not set
1457+# CONFIG_SMSC9420 is not set
1458+# CONFIG_SUNDANCE is not set
1459+# CONFIG_TLAN is not set
1460+# CONFIG_VIA_RHINE is not set
1461+# CONFIG_SC92031 is not set
1462+CONFIG_FEC_548x=y
1463+CONFIG_FEC_548x_ENABLE_FEC2=y
1464+CONFIG_FEC_548x_SHARED_PHY=y
1465+# CONFIG_ATL2 is not set
1466+CONFIG_NETDEV_1000=y
1467+# CONFIG_ACENIC is not set
1468+# CONFIG_DL2K is not set
1469+CONFIG_E1000=y
1470+# CONFIG_E1000E is not set
1471+# CONFIG_IP1000 is not set
1472+# CONFIG_IGB is not set
1473+# CONFIG_NS83820 is not set
1474+# CONFIG_HAMACHI is not set
1475+# CONFIG_YELLOWFIN is not set
1476+# CONFIG_R8169 is not set
1477+# CONFIG_SIS190 is not set
1478+# CONFIG_SKGE is not set
1479+# CONFIG_SKY2 is not set
1480+# CONFIG_VIA_VELOCITY is not set
1481+# CONFIG_TIGON3 is not set
1482+# CONFIG_BNX2 is not set
1483+# CONFIG_QLA3XXX is not set
1484+# CONFIG_ATL1 is not set
1485+# CONFIG_ATL1E is not set
1486+# CONFIG_ATL1C is not set
1487+# CONFIG_JME is not set
1488+# CONFIG_NETDEV_10000 is not set
1489+# CONFIG_TR is not set
1490+
1491+#
1492+# Wireless LAN
1493+#
1494+# CONFIG_WLAN_PRE80211 is not set
1495+# CONFIG_WLAN_80211 is not set
1496+# CONFIG_IWLWIFI_LEDS is not set
1497+
1498+#
1499+# Enable WiMAX (Networking options) to see the WiMAX drivers
1500+#
1501+# CONFIG_WAN is not set
1502+# CONFIG_FDDI is not set
1503+# CONFIG_HIPPI is not set
1504+# CONFIG_PPP is not set
1505+# CONFIG_SLIP is not set
1506+# CONFIG_NET_FC is not set
1507+# CONFIG_NETCONSOLE is not set
1508+# CONFIG_NETPOLL is not set
1509+# CONFIG_NET_POLL_CONTROLLER is not set
1510+# CONFIG_ISDN is not set
1511+# CONFIG_PHONE is not set
1512+
1513+#
1514+# Input device support
1515+#
1516+CONFIG_INPUT=y
1517+# CONFIG_INPUT_FF_MEMLESS is not set
1518+# CONFIG_INPUT_POLLDEV is not set
1519+
1520+#
1521+# Userland interfaces
1522+#
1523+CONFIG_INPUT_MOUSEDEV=y
1524+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
1525+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
1526+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
1527+# CONFIG_INPUT_JOYDEV is not set
1528+CONFIG_INPUT_EVDEV=y
1529+# CONFIG_INPUT_EVBUG is not set
1530+
1531+#
1532+# Input Device Drivers
1533+#
1534+CONFIG_INPUT_KEYBOARD=y
1535+# CONFIG_KEYBOARD_ATKBD is not set
1536+# CONFIG_KEYBOARD_SUNKBD is not set
1537+# CONFIG_KEYBOARD_LKKBD is not set
1538+# CONFIG_KEYBOARD_XTKBD is not set
1539+# CONFIG_KEYBOARD_NEWTON is not set
1540+# CONFIG_KEYBOARD_STOWAWAY is not set
1541+# CONFIG_INPUT_MOUSE is not set
1542+# CONFIG_INPUT_JOYSTICK is not set
1543+# CONFIG_INPUT_TABLET is not set
1544+# CONFIG_INPUT_TOUCHSCREEN is not set
1545+# CONFIG_INPUT_MISC is not set
1546+
1547+#
1548+# Hardware I/O ports
1549+#
1550+CONFIG_SERIO=y
1551+CONFIG_SERIO_SERPORT=y
1552+# CONFIG_SERIO_PCIPS2 is not set
1553+# CONFIG_SERIO_RAW is not set
1554+# CONFIG_GAMEPORT is not set
1555+
1556+#
1557+# Character devices
1558+#
1559+CONFIG_VT=y
1560+CONFIG_CONSOLE_TRANSLATIONS=y
1561+CONFIG_VT_CONSOLE=y
1562+CONFIG_HW_CONSOLE=y
1563+# CONFIG_VT_HW_CONSOLE_BINDING is not set
1564+CONFIG_DEVKMEM=y
1565+# CONFIG_SERIAL_NONSTANDARD is not set
1566+# CONFIG_NOZOMI is not set
1567+
1568+#
1569+# Serial drivers
1570+#
1571+# CONFIG_SERIAL_8250 is not set
1572+
1573+#
1574+# Non-8250 serial port support
1575+#
1576+CONFIG_SERIAL_CORE=y
1577+CONFIG_SERIAL_CORE_CONSOLE=y
1578+# CONFIG_SERIAL_COLDFIRE_IRDA is not set
1579+# CONFIG_SERIAL_COLDFIRE_EDMA is not set
1580+CONFIG_SERIAL_MCF=y
1581+CONFIG_SERIAL_MCF_BAUDRATE=115200
1582+CONFIG_SERIAL_MCF_CONSOLE=y
1583+# CONFIG_SERIAL_JSM is not set
1584+CONFIG_UNIX98_PTYS=y
1585+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
1586+# CONFIG_LEGACY_PTYS is not set
1587+# CONFIG_IPMI_HANDLER is not set
1588+# CONFIG_HW_RANDOM is not set
1589+# CONFIG_GEN_RTC is not set
1590+# CONFIG_R3964 is not set
1591+# CONFIG_APPLICOM is not set
1592+# CONFIG_RAW_DRIVER is not set
1593+# CONFIG_TCG_TPM is not set
1594+CONFIG_I2C=y
1595+CONFIG_I2C_BOARDINFO=y
1596+# CONFIG_I2C_CHARDEV is not set
1597+CONFIG_I2C_HELPER_AUTO=y
1598+
1599+#
1600+# I2C Hardware Bus support
1601+#
1602+
1603+#
1604+# PC SMBus host controller drivers
1605+#
1606+# CONFIG_I2C_ALI1535 is not set
1607+# CONFIG_I2C_ALI1563 is not set
1608+# CONFIG_I2C_ALI15X3 is not set
1609+# CONFIG_I2C_AMD756 is not set
1610+# CONFIG_I2C_AMD8111 is not set
1611+# CONFIG_I2C_I801 is not set
1612+# CONFIG_I2C_ISCH is not set
1613+# CONFIG_I2C_PIIX4 is not set
1614+# CONFIG_I2C_NFORCE2 is not set
1615+# CONFIG_I2C_SIS5595 is not set
1616+# CONFIG_I2C_SIS630 is not set
1617+# CONFIG_I2C_SIS96X is not set
1618+# CONFIG_I2C_VIA is not set
1619+# CONFIG_I2C_VIAPRO is not set
1620+
1621+#
1622+# I2C system bus drivers (mostly embedded / system-on-chip)
1623+#
1624+CONFIG_I2C_MCF=y
1625+# CONFIG_I2C_OCORES is not set
1626+# CONFIG_I2C_SIMTEC is not set
1627+
1628+#
1629+# External I2C/SMBus adapter drivers
1630+#
1631+# CONFIG_I2C_PARPORT_LIGHT is not set
1632+# CONFIG_I2C_TAOS_EVM is not set
1633+
1634+#
1635+# Graphics adapter I2C/DDC channel drivers
1636+#
1637+# CONFIG_I2C_VOODOO3 is not set
1638+
1639+#
1640+# Other I2C/SMBus bus drivers
1641+#
1642+# CONFIG_I2C_PCA_PLATFORM is not set
1643+# CONFIG_I2C_STUB is not set
1644+
1645+#
1646+# Miscellaneous I2C Chip support
1647+#
1648+# CONFIG_DS1682 is not set
1649+# CONFIG_SENSORS_PCF8574 is not set
1650+# CONFIG_PCF8575 is not set
1651+# CONFIG_SENSORS_PCA9539 is not set
1652+# CONFIG_SENSORS_PCF8591 is not set
1653+# CONFIG_SENSORS_MAX6875 is not set
1654+# CONFIG_SENSORS_TSL2550 is not set
1655+# CONFIG_I2C_DEBUG_CORE is not set
1656+# CONFIG_I2C_DEBUG_ALGO is not set
1657+# CONFIG_I2C_DEBUG_BUS is not set
1658+# CONFIG_I2C_DEBUG_CHIP is not set
1659+# CONFIG_SPI is not set
1660+# CONFIG_W1 is not set
1661+# CONFIG_POWER_SUPPLY is not set
1662+# CONFIG_HWMON is not set
1663+# CONFIG_THERMAL is not set
1664+# CONFIG_THERMAL_HWMON is not set
1665+# CONFIG_WATCHDOG is not set
1666+CONFIG_SSB_POSSIBLE=y
1667+
1668+#
1669+# Sonics Silicon Backplane
1670+#
1671+# CONFIG_SSB is not set
1672+
1673+#
1674+# Multifunction device drivers
1675+#
1676+# CONFIG_MFD_CORE is not set
1677+# CONFIG_MFD_SM501 is not set
1678+# CONFIG_HTC_PASIC3 is not set
1679+# CONFIG_MFD_TMIO is not set
1680+# CONFIG_PMIC_DA903X is not set
1681+# CONFIG_MFD_WM8400 is not set
1682+# CONFIG_MFD_WM8350_I2C is not set
1683+# CONFIG_MFD_PCF50633 is not set
1684+# CONFIG_REGULATOR is not set
1685+
1686+#
1687+# Multimedia devices
1688+#
1689+
1690+#
1691+# Multimedia core support
1692+#
1693+# CONFIG_VIDEO_DEV is not set
1694+# CONFIG_DVB_CORE is not set
1695+# CONFIG_VIDEO_MEDIA is not set
1696+
1697+#
1698+# Multimedia drivers
1699+#
1700+CONFIG_DAB=y
1701+
1702+#
1703+# Graphics support
1704+#
1705+# CONFIG_DRM is not set
1706+# CONFIG_VGASTATE is not set
1707+CONFIG_VIDEO_OUTPUT_CONTROL=m
1708+# CONFIG_FB is not set
1709+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1710+
1711+#
1712+# Display device support
1713+#
1714+# CONFIG_DISPLAY_SUPPORT is not set
1715+
1716+#
1717+# Console display driver support
1718+#
1719+CONFIG_DUMMY_CONSOLE=y
1720+# CONFIG_SOUND is not set
1721+# CONFIG_HID_SUPPORT is not set
1722+# CONFIG_USB_SUPPORT is not set
1723+# CONFIG_UWB is not set
1724+# CONFIG_MMC is not set
1725+# CONFIG_MEMSTICK is not set
1726+# CONFIG_NEW_LEDS is not set
1727+# CONFIG_ACCESSIBILITY is not set
1728+# CONFIG_INFINIBAND is not set
1729+# CONFIG_RTC_CLASS is not set
1730+# CONFIG_DMADEVICES is not set
1731+# CONFIG_UIO is not set
1732+# CONFIG_STAGING is not set
1733+
1734+#
1735+# Character devices
1736+#
1737+CONFIG_TICK_ONESHOT=y
1738+CONFIG_NO_HZ=y
1739+CONFIG_HIGH_RES_TIMERS=y
1740+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
1741+
1742+#
1743+# File systems
1744+#
1745+CONFIG_EXT2_FS=y
1746+# CONFIG_EXT2_FS_XATTR is not set
1747+# CONFIG_EXT2_FS_XIP is not set
1748+CONFIG_EXT3_FS=y
1749+CONFIG_EXT3_FS_XATTR=y
1750+# CONFIG_EXT3_FS_POSIX_ACL is not set
1751+# CONFIG_EXT3_FS_SECURITY is not set
1752+# CONFIG_EXT4_FS is not set
1753+CONFIG_JBD=y
1754+CONFIG_FS_MBCACHE=y
1755+# CONFIG_REISERFS_FS is not set
1756+# CONFIG_JFS_FS is not set
1757+# CONFIG_FS_POSIX_ACL is not set
1758+CONFIG_FILE_LOCKING=y
1759+# CONFIG_XFS_FS is not set
1760+# CONFIG_GFS2_FS is not set
1761+# CONFIG_OCFS2_FS is not set
1762+# CONFIG_BTRFS_FS is not set
1763+CONFIG_DNOTIFY=y
1764+# CONFIG_INOTIFY is not set
1765+# CONFIG_QUOTA is not set
1766+# CONFIG_AUTOFS_FS is not set
1767+# CONFIG_AUTOFS4_FS is not set
1768+# CONFIG_FUSE_FS is not set
1769+
1770+#
1771+# CD-ROM/DVD Filesystems
1772+#
1773+# CONFIG_ISO9660_FS is not set
1774+# CONFIG_UDF_FS is not set
1775+
1776+#
1777+# DOS/FAT/NT Filesystems
1778+#
1779+CONFIG_FAT_FS=y
1780+CONFIG_MSDOS_FS=y
1781+CONFIG_VFAT_FS=y
1782+CONFIG_FAT_DEFAULT_CODEPAGE=437
1783+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1784+CONFIG_NTFS_FS=y
1785+# CONFIG_NTFS_DEBUG is not set
1786+CONFIG_NTFS_RW=y
1787+
1788+#
1789+# Pseudo filesystems
1790+#
1791+CONFIG_PROC_FS=y
1792+# CONFIG_PROC_KCORE is not set
1793+CONFIG_PROC_SYSCTL=y
1794+CONFIG_PROC_PAGE_MONITOR=y
1795+CONFIG_SYSFS=y
1796+CONFIG_TMPFS=y
1797+# CONFIG_TMPFS_POSIX_ACL is not set
1798+# CONFIG_HUGETLB_PAGE is not set
1799+# CONFIG_CONFIGFS_FS is not set
1800+CONFIG_MISC_FILESYSTEMS=y
1801+# CONFIG_ADFS_FS is not set
1802+# CONFIG_AFFS_FS is not set
1803+# CONFIG_HFS_FS is not set
1804+# CONFIG_HFSPLUS_FS is not set
1805+# CONFIG_BEFS_FS is not set
1806+# CONFIG_BFS_FS is not set
1807+# CONFIG_EFS_FS is not set
1808+# CONFIG_JFFS2_FS is not set
1809+# CONFIG_CRAMFS is not set
1810+# CONFIG_SQUASHFS is not set
1811+# CONFIG_VXFS_FS is not set
1812+CONFIG_MINIX_FS=y
1813+# CONFIG_OMFS_FS is not set
1814+# CONFIG_HPFS_FS is not set
1815+# CONFIG_QNX4FS_FS is not set
1816+CONFIG_ROMFS_FS=y
1817+# CONFIG_SYSV_FS is not set
1818+# CONFIG_UFS_FS is not set
1819+CONFIG_NETWORK_FILESYSTEMS=y
1820+CONFIG_NFS_FS=y
1821+# CONFIG_NFS_V3 is not set
1822+# CONFIG_NFS_V4 is not set
1823+CONFIG_ROOT_NFS=y
1824+# CONFIG_NFSD is not set
1825+CONFIG_LOCKD=y
1826+CONFIG_NFS_COMMON=y
1827+CONFIG_SUNRPC=y
1828+# CONFIG_SUNRPC_REGISTER_V4 is not set
1829+# CONFIG_RPCSEC_GSS_KRB5 is not set
1830+# CONFIG_RPCSEC_GSS_SPKM3 is not set
1831+# CONFIG_SMB_FS is not set
1832+# CONFIG_CIFS is not set
1833+# CONFIG_NCP_FS is not set
1834+# CONFIG_CODA_FS is not set
1835+# CONFIG_AFS_FS is not set
1836+
1837+#
1838+# Partition Types
1839+#
1840+CONFIG_PARTITION_ADVANCED=y
1841+# CONFIG_ACORN_PARTITION is not set
1842+# CONFIG_OSF_PARTITION is not set
1843+# CONFIG_AMIGA_PARTITION is not set
1844+# CONFIG_ATARI_PARTITION is not set
1845+# CONFIG_MAC_PARTITION is not set
1846+CONFIG_MSDOS_PARTITION=y
1847+# CONFIG_BSD_DISKLABEL is not set
1848+# CONFIG_MINIX_SUBPARTITION is not set
1849+# CONFIG_SOLARIS_X86_PARTITION is not set
1850+# CONFIG_UNIXWARE_DISKLABEL is not set
1851+# CONFIG_LDM_PARTITION is not set
1852+# CONFIG_SGI_PARTITION is not set
1853+# CONFIG_ULTRIX_PARTITION is not set
1854+# CONFIG_SUN_PARTITION is not set
1855+# CONFIG_KARMA_PARTITION is not set
1856+# CONFIG_EFI_PARTITION is not set
1857+# CONFIG_SYSV68_PARTITION is not set
1858+CONFIG_NLS=y
1859+CONFIG_NLS_DEFAULT="iso8859-1"
1860+CONFIG_NLS_CODEPAGE_437=y
1861+# CONFIG_NLS_CODEPAGE_737 is not set
1862+# CONFIG_NLS_CODEPAGE_775 is not set
1863+# CONFIG_NLS_CODEPAGE_850 is not set
1864+# CONFIG_NLS_CODEPAGE_852 is not set
1865+# CONFIG_NLS_CODEPAGE_855 is not set
1866+# CONFIG_NLS_CODEPAGE_857 is not set
1867+# CONFIG_NLS_CODEPAGE_860 is not set
1868+# CONFIG_NLS_CODEPAGE_861 is not set
1869+# CONFIG_NLS_CODEPAGE_862 is not set
1870+# CONFIG_NLS_CODEPAGE_863 is not set
1871+# CONFIG_NLS_CODEPAGE_864 is not set
1872+# CONFIG_NLS_CODEPAGE_865 is not set
1873+# CONFIG_NLS_CODEPAGE_866 is not set
1874+# CONFIG_NLS_CODEPAGE_869 is not set
1875+# CONFIG_NLS_CODEPAGE_936 is not set
1876+# CONFIG_NLS_CODEPAGE_950 is not set
1877+# CONFIG_NLS_CODEPAGE_932 is not set
1878+# CONFIG_NLS_CODEPAGE_949 is not set
1879+# CONFIG_NLS_CODEPAGE_874 is not set
1880+# CONFIG_NLS_ISO8859_8 is not set
1881+# CONFIG_NLS_CODEPAGE_1250 is not set
1882+# CONFIG_NLS_CODEPAGE_1251 is not set
1883+# CONFIG_NLS_ASCII is not set
1884+CONFIG_NLS_ISO8859_1=y
1885+# CONFIG_NLS_ISO8859_2 is not set
1886+# CONFIG_NLS_ISO8859_3 is not set
1887+# CONFIG_NLS_ISO8859_4 is not set
1888+# CONFIG_NLS_ISO8859_5 is not set
1889+# CONFIG_NLS_ISO8859_6 is not set
1890+# CONFIG_NLS_ISO8859_7 is not set
1891+# CONFIG_NLS_ISO8859_9 is not set
1892+# CONFIG_NLS_ISO8859_13 is not set
1893+# CONFIG_NLS_ISO8859_14 is not set
1894+# CONFIG_NLS_ISO8859_15 is not set
1895+# CONFIG_NLS_KOI8_R is not set
1896+# CONFIG_NLS_KOI8_U is not set
1897+CONFIG_NLS_UTF8=y
1898+# CONFIG_DLM is not set
1899+
1900+#
1901+# Kernel hacking
1902+#
1903+# CONFIG_PRINTK_TIME is not set
1904+CONFIG_ENABLE_WARN_DEPRECATED=y
1905+# CONFIG_ENABLE_MUST_CHECK is not set
1906+CONFIG_FRAME_WARN=1024
1907+# CONFIG_MAGIC_SYSRQ is not set
1908+# CONFIG_UNUSED_SYMBOLS is not set
1909+# CONFIG_DEBUG_FS is not set
1910+# CONFIG_HEADERS_CHECK is not set
1911+# CONFIG_DEBUG_KERNEL is not set
1912+CONFIG_DEBUG_BUGVERBOSE=y
1913+CONFIG_DEBUG_MEMORY_INIT=y
1914+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1915+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
1916+
1917+#
1918+# Tracers
1919+#
1920+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
1921+# CONFIG_SAMPLES is not set
1922+# CONFIG_BOOTPARAM is not set
1923+
1924+#
1925+# Security options
1926+#
1927+# CONFIG_KEYS is not set
1928+# CONFIG_SECURITY is not set
1929+# CONFIG_SECURITYFS is not set
1930+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1931+CONFIG_CRYPTO=y
1932+
1933+#
1934+# Crypto core or helper
1935+#
1936+# CONFIG_CRYPTO_FIPS is not set
1937+CONFIG_CRYPTO_ALGAPI=y
1938+CONFIG_CRYPTO_ALGAPI2=y
1939+CONFIG_CRYPTO_AEAD=y
1940+CONFIG_CRYPTO_AEAD2=y
1941+CONFIG_CRYPTO_BLKCIPHER=y
1942+CONFIG_CRYPTO_BLKCIPHER2=y
1943+CONFIG_CRYPTO_HASH=y
1944+CONFIG_CRYPTO_HASH2=y
1945+CONFIG_CRYPTO_RNG2=y
1946+CONFIG_CRYPTO_MANAGER=y
1947+CONFIG_CRYPTO_MANAGER2=y
1948+# CONFIG_CRYPTO_GF128MUL is not set
1949+# CONFIG_CRYPTO_NULL is not set
1950+# CONFIG_CRYPTO_CRYPTD is not set
1951+CONFIG_CRYPTO_AUTHENC=y
1952+CONFIG_CRYPTO_TEST=m
1953+
1954+#
1955+# Authenticated Encryption with Associated Data
1956+#
1957+# CONFIG_CRYPTO_CCM is not set
1958+# CONFIG_CRYPTO_GCM is not set
1959+# CONFIG_CRYPTO_SEQIV is not set
1960+
1961+#
1962+# Block modes
1963+#
1964+CONFIG_CRYPTO_CBC=y
1965+# CONFIG_CRYPTO_CTR is not set
1966+# CONFIG_CRYPTO_CTS is not set
1967+# CONFIG_CRYPTO_ECB is not set
1968+# CONFIG_CRYPTO_LRW is not set
1969+# CONFIG_CRYPTO_PCBC is not set
1970+# CONFIG_CRYPTO_XTS is not set
1971+
1972+#
1973+# Hash modes
1974+#
1975+CONFIG_CRYPTO_HMAC=y
1976+# CONFIG_CRYPTO_XCBC is not set
1977+
1978+#
1979+# Digest
1980+#
1981+CONFIG_CRYPTO_CRC32C=y
1982+# CONFIG_CRYPTO_MD4 is not set
1983+CONFIG_CRYPTO_MD5=y
1984+# CONFIG_CRYPTO_MICHAEL_MIC is not set
1985+# CONFIG_CRYPTO_RMD128 is not set
1986+# CONFIG_CRYPTO_RMD160 is not set
1987+# CONFIG_CRYPTO_RMD256 is not set
1988+# CONFIG_CRYPTO_RMD320 is not set
1989+CONFIG_CRYPTO_SHA1=y
1990+# CONFIG_CRYPTO_SHA256 is not set
1991+# CONFIG_CRYPTO_SHA512 is not set
1992+# CONFIG_CRYPTO_TGR192 is not set
1993+# CONFIG_CRYPTO_WP512 is not set
1994+
1995+#
1996+# Ciphers
1997+#
1998+# CONFIG_CRYPTO_AES is not set
1999+# CONFIG_CRYPTO_ANUBIS is not set
2000+# CONFIG_CRYPTO_ARC4 is not set
2001+# CONFIG_CRYPTO_BLOWFISH is not set
2002+# CONFIG_CRYPTO_CAMELLIA is not set
2003+# CONFIG_CRYPTO_CAST5 is not set
2004+# CONFIG_CRYPTO_CAST6 is not set
2005+CONFIG_CRYPTO_DES=y
2006+# CONFIG_CRYPTO_FCRYPT is not set
2007+# CONFIG_CRYPTO_KHAZAD is not set
2008+# CONFIG_CRYPTO_SALSA20 is not set
2009+# CONFIG_CRYPTO_SEED is not set
2010+# CONFIG_CRYPTO_SERPENT is not set
2011+# CONFIG_CRYPTO_TEA is not set
2012+# CONFIG_CRYPTO_TWOFISH is not set
2013+
2014+#
2015+# Compression
2016+#
2017+# CONFIG_CRYPTO_DEFLATE is not set
2018+# CONFIG_CRYPTO_LZO is not set
2019+
2020+#
2021+# Random Number Generation
2022+#
2023+# CONFIG_CRYPTO_ANSI_CPRNG is not set
2024+
2025+#
2026+# OCF Configuration
2027+#
2028+# CONFIG_OCF_OCF is not set
2029+
2030+#
2031+# Talitos Driver
2032+#
2033+# CONFIG_CRYPTO_HW is not set
2034+
2035+#
2036+# Library routines
2037+#
2038+CONFIG_BITREVERSE=y
2039+CONFIG_GENERIC_FIND_LAST_BIT=y
2040+CONFIG_CRC_CCITT=y
2041+CONFIG_CRC16=y
2042+# CONFIG_CRC_T10DIF is not set
2043+# CONFIG_CRC_ITU_T is not set
2044+CONFIG_CRC32=y
2045+# CONFIG_CRC7 is not set
2046+CONFIG_LIBCRC32C=y
2047+CONFIG_PLIST=y
2048+CONFIG_HAS_IOMEM=y
2049+CONFIG_HAS_IOPORT=y
2050+CONFIG_HAS_DMA=y
2051--- /dev/null
2052+++ b/arch/m68k/configs/m5475evb_defconfig
2053@@ -0,0 +1,1324 @@
2054+#
2055+# Automatically generated make config: don't edit
2056+# Linux kernel version: 2.6.29
2057+# Tue Aug 24 15:41:10 2010
2058+#
2059+CONFIG_M68K=y
2060+CONFIG_MMU=y
2061+CONFIG_GENERIC_TIME=y
2062+CONFIG_GENERIC_CLOCKEVENTS=y
2063+CONFIG_RWSEM_GENERIC_SPINLOCK=y
2064+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
2065+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
2066+CONFIG_GENERIC_HWEIGHT=y
2067+CONFIG_GENERIC_CALIBRATE_DELAY=y
2068+# CONFIG_TIME_LOW_RES is not set
2069+CONFIG_GENERIC_IOMAP=y
2070+# CONFIG_NO_IOPORT is not set
2071+# CONFIG_NO_DMA is not set
2072+CONFIG_HZ=100
2073+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
2074+
2075+#
2076+# General setup
2077+#
2078+CONFIG_EXPERIMENTAL=y
2079+CONFIG_BROKEN_ON_SMP=y
2080+CONFIG_INIT_ENV_ARG_LIMIT=32
2081+CONFIG_LOCALVERSION=""
2082+# CONFIG_LOCALVERSION_AUTO is not set
2083+CONFIG_SWAP=y
2084+CONFIG_SYSVIPC=y
2085+CONFIG_SYSVIPC_SYSCTL=y
2086+# CONFIG_POSIX_MQUEUE is not set
2087+# CONFIG_BSD_PROCESS_ACCT is not set
2088+# CONFIG_TASKSTATS is not set
2089+# CONFIG_AUDIT is not set
2090+
2091+#
2092+# RCU Subsystem
2093+#
2094+CONFIG_CLASSIC_RCU=y
2095+# CONFIG_TREE_RCU is not set
2096+# CONFIG_PREEMPT_RCU is not set
2097+# CONFIG_TREE_RCU_TRACE is not set
2098+# CONFIG_PREEMPT_RCU_TRACE is not set
2099+CONFIG_IKCONFIG=y
2100+CONFIG_IKCONFIG_PROC=y
2101+CONFIG_LOG_BUF_SHIFT=17
2102+CONFIG_GROUP_SCHED=y
2103+CONFIG_FAIR_GROUP_SCHED=y
2104+# CONFIG_RT_GROUP_SCHED is not set
2105+CONFIG_USER_SCHED=y
2106+# CONFIG_CGROUP_SCHED is not set
2107+# CONFIG_CGROUPS is not set
2108+CONFIG_SYSFS_DEPRECATED=y
2109+CONFIG_SYSFS_DEPRECATED_V2=y
2110+# CONFIG_RELAY is not set
2111+CONFIG_NAMESPACES=y
2112+# CONFIG_UTS_NS is not set
2113+# CONFIG_IPC_NS is not set
2114+# CONFIG_USER_NS is not set
2115+# CONFIG_PID_NS is not set
2116+# CONFIG_NET_NS is not set
2117+CONFIG_BLK_DEV_INITRD=y
2118+CONFIG_INITRAMFS_SOURCE=""
2119+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
2120+CONFIG_SYSCTL=y
2121+CONFIG_ANON_INODES=y
2122+# CONFIG_EMBEDDED is not set
2123+CONFIG_UID16=y
2124+CONFIG_SYSCTL_SYSCALL=y
2125+CONFIG_KALLSYMS=y
2126+CONFIG_KALLSYMS_EXTRA_PASS=y
2127+CONFIG_HOTPLUG=y
2128+CONFIG_PRINTK=y
2129+CONFIG_BUG=y
2130+CONFIG_ELF_CORE=y
2131+CONFIG_BASE_FULL=y
2132+CONFIG_FUTEX=y
2133+CONFIG_EPOLL=y
2134+CONFIG_SIGNALFD=y
2135+CONFIG_TIMERFD=y
2136+CONFIG_EVENTFD=y
2137+CONFIG_SHMEM=y
2138+CONFIG_AIO=y
2139+CONFIG_VM_EVENT_COUNTERS=y
2140+CONFIG_PCI_QUIRKS=y
2141+CONFIG_COMPAT_BRK=y
2142+CONFIG_SLAB=y
2143+# CONFIG_SLUB is not set
2144+# CONFIG_SLOB is not set
2145+# CONFIG_PROFILING is not set
2146+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
2147+CONFIG_SLABINFO=y
2148+CONFIG_RT_MUTEXES=y
2149+CONFIG_BASE_SMALL=0
2150+CONFIG_MODULES=y
2151+# CONFIG_MODULE_FORCE_LOAD is not set
2152+CONFIG_MODULE_UNLOAD=y
2153+CONFIG_MODULE_FORCE_UNLOAD=y
2154+# CONFIG_MODVERSIONS is not set
2155+# CONFIG_MODULE_SRCVERSION_ALL is not set
2156+CONFIG_BLOCK=y
2157+CONFIG_LBD=y
2158+# CONFIG_BLK_DEV_IO_TRACE is not set
2159+# CONFIG_BLK_DEV_BSG is not set
2160+# CONFIG_BLK_DEV_INTEGRITY is not set
2161+
2162+#
2163+# IO Schedulers
2164+#
2165+CONFIG_IOSCHED_NOOP=y
2166+CONFIG_IOSCHED_AS=y
2167+CONFIG_IOSCHED_DEADLINE=y
2168+CONFIG_IOSCHED_CFQ=y
2169+# CONFIG_DEFAULT_AS is not set
2170+# CONFIG_DEFAULT_DEADLINE is not set
2171+CONFIG_DEFAULT_CFQ=y
2172+# CONFIG_DEFAULT_NOOP is not set
2173+CONFIG_DEFAULT_IOSCHED="cfq"
2174+# CONFIG_FREEZER is not set
2175+
2176+#
2177+# Platform dependent setup
2178+#
2179+CONFIG_COLDFIRE=y
2180+CONFIG_CFV4E=y
2181+# CONFIG_FPU is not set
2182+CONFIG_MCD_DMA=y
2183+# CONFIG_AMIGA is not set
2184+# CONFIG_ATARI is not set
2185+CONFIG_PCI=y
2186+# CONFIG_MAC is not set
2187+# CONFIG_APOLLO is not set
2188+# CONFIG_VME is not set
2189+# CONFIG_HP300 is not set
2190+# CONFIG_SUN3X is not set
2191+# CONFIG_Q40 is not set
2192+# CONFIG_SUN3 is not set
2193+
2194+#
2195+# Processor type
2196+#
2197+# CONFIG_M68020 is not set
2198+# CONFIG_M68030 is not set
2199+# CONFIG_M68040 is not set
2200+# CONFIG_M68060 is not set
2201+# CONFIG_M5445X is not set
2202+# CONFIG_HAVE_FSL_USB_DR is not set
2203+CONFIG_M547X_8X=y
2204+CONFIG_M547X=y
2205+# CONFIG_M548X is not set
2206+# CONFIG_M5474LITE is not set
2207+# CONFIG_M5475AFE is not set
2208+# CONFIG_M5475BFE is not set
2209+CONFIG_M5475CFE=y
2210+# CONFIG_M5475DFE is not set
2211+# CONFIG_M5475EFE is not set
2212+# CONFIG_M5475FFE is not set
2213+# CONFIG_M5484LITE is not set
2214+# CONFIG_M5485AFE is not set
2215+# CONFIG_M5485BFE is not set
2216+# CONFIG_M5485CFE is not set
2217+# CONFIG_M5485DFE is not set
2218+# CONFIG_M5485EFE is not set
2219+# CONFIG_M5485FFE is not set
2220+# CONFIG_M5441X is not set
2221+CONFIG_MCFCLK=266000000
2222+# CONFIG_MCF_USER_HALT is not set
2223+CONFIG_MMU_CFV4E=y
2224+CONFIG_SDRAM_BASE=0x00000000
2225+CONFIG_SDRAM_SIZE=0x04000000
2226+CONFIG_NOR_FLASH_BASE=0xE0000000
2227+CONFIG_DMA_BASE=0xef000000
2228+CONFIG_DMA_SIZE=0x800000
2229+CONFIG_VDSO=y
2230+# CONFIG_M68KFPU_EMU is not set
2231+CONFIG_ADVANCED=y
2232+# CONFIG_RMW_INSNS is not set
2233+CONFIG_SINGLE_MEMORY_CHUNK=y
2234+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
2235+CONFIG_SELECT_MEMORY_MODEL=y
2236+CONFIG_FLATMEM_MANUAL=y
2237+# CONFIG_DISCONTIGMEM_MANUAL is not set
2238+# CONFIG_SPARSEMEM_MANUAL is not set
2239+CONFIG_FLATMEM=y
2240+CONFIG_FLAT_NODE_MEM_MAP=y
2241+CONFIG_NEED_MULTIPLE_NODES=y
2242+CONFIG_PAGEFLAGS_EXTENDED=y
2243+CONFIG_SPLIT_PTLOCK_CPUS=4
2244+# CONFIG_PHYS_ADDR_T_64BIT is not set
2245+CONFIG_ZONE_DMA_FLAG=1
2246+CONFIG_BOUNCE=y
2247+CONFIG_VIRT_TO_BUS=y
2248+CONFIG_UNEVICTABLE_LRU=y
2249+
2250+#
2251+# General setup
2252+#
2253+CONFIG_BINFMT_ELF=y
2254+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
2255+CONFIG_HAVE_AOUT=y
2256+# CONFIG_BINFMT_AOUT is not set
2257+# CONFIG_BINFMT_MISC is not set
2258+CONFIG_PROC_HARDWARE=y
2259+CONFIG_ZONE_DMA=y
2260+# CONFIG_ARCH_SUPPORTS_MSI is not set
2261+CONFIG_PCI_LEGACY=y
2262+# CONFIG_PCI_STUB is not set
2263+
2264+#
2265+# Power management options
2266+#
2267+CONFIG_PM=y
2268+CONFIG_NET=y
2269+
2270+#
2271+# Networking options
2272+#
2273+CONFIG_COMPAT_NET_DEV_OPS=y
2274+CONFIG_PACKET=y
2275+# CONFIG_PACKET_MMAP is not set
2276+CONFIG_UNIX=y
2277+CONFIG_XFRM=y
2278+# CONFIG_XFRM_USER is not set
2279+# CONFIG_XFRM_SUB_POLICY is not set
2280+# CONFIG_XFRM_MIGRATE is not set
2281+# CONFIG_XFRM_STATISTICS is not set
2282+CONFIG_NET_KEY=y
2283+# CONFIG_NET_KEY_MIGRATE is not set
2284+CONFIG_INET=y
2285+# CONFIG_IP_MULTICAST is not set
2286+CONFIG_IP_ADVANCED_ROUTER=y
2287+CONFIG_ASK_IP_FIB_HASH=y
2288+# CONFIG_IP_FIB_TRIE is not set
2289+CONFIG_IP_FIB_HASH=y
2290+# CONFIG_IP_MULTIPLE_TABLES is not set
2291+# CONFIG_IP_ROUTE_MULTIPATH is not set
2292+# CONFIG_IP_ROUTE_VERBOSE is not set
2293+CONFIG_IP_PNP=y
2294+# CONFIG_IP_PNP_DHCP is not set
2295+# CONFIG_IP_PNP_BOOTP is not set
2296+# CONFIG_IP_PNP_RARP is not set
2297+# CONFIG_NET_IPIP is not set
2298+# CONFIG_NET_IPGRE is not set
2299+# CONFIG_ARPD is not set
2300+# CONFIG_SYN_COOKIES is not set
2301+CONFIG_INET_AH=y
2302+CONFIG_INET_ESP=y
2303+# CONFIG_INET_IPCOMP is not set
2304+# CONFIG_INET_XFRM_TUNNEL is not set
2305+# CONFIG_INET_TUNNEL is not set
2306+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
2307+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
2308+# CONFIG_INET_XFRM_MODE_BEET is not set
2309+# CONFIG_INET_LRO is not set
2310+CONFIG_INET_DIAG=y
2311+CONFIG_INET_TCP_DIAG=y
2312+# CONFIG_TCP_CONG_ADVANCED is not set
2313+CONFIG_TCP_CONG_CUBIC=y
2314+CONFIG_DEFAULT_TCP_CONG="cubic"
2315+# CONFIG_TCP_MD5SIG is not set
2316+# CONFIG_IPV6 is not set
2317+# CONFIG_NETWORK_SECMARK is not set
2318+# CONFIG_NETFILTER is not set
2319+# CONFIG_IP_DCCP is not set
2320+# CONFIG_IP_SCTP is not set
2321+# CONFIG_TIPC is not set
2322+# CONFIG_ATM is not set
2323+# CONFIG_BRIDGE is not set
2324+# CONFIG_NET_DSA is not set
2325+# CONFIG_VLAN_8021Q is not set
2326+# CONFIG_DECNET is not set
2327+# CONFIG_LLC2 is not set
2328+# CONFIG_IPX is not set
2329+# CONFIG_ATALK is not set
2330+# CONFIG_X25 is not set
2331+# CONFIG_LAPB is not set
2332+# CONFIG_ECONET is not set
2333+# CONFIG_WAN_ROUTER is not set
2334+# CONFIG_NET_SCHED is not set
2335+# CONFIG_DCB is not set
2336+
2337+#
2338+# Network testing
2339+#
2340+# CONFIG_NET_PKTGEN is not set
2341+# CONFIG_HAMRADIO is not set
2342+CONFIG_CAN=y
2343+CONFIG_CAN_RAW=y
2344+# CONFIG_CAN_BCM is not set
2345+
2346+#
2347+# CAN Device Drivers
2348+#
2349+# CONFIG_CAN_VCAN is not set
2350+# CONFIG_CAN_DEV is not set
2351+# CONFIG_CAN_FLEXCAN is not set
2352+# CONFIG_CAN_DEBUG_DEVICES is not set
2353+# CONFIG_IRDA is not set
2354+# CONFIG_BT is not set
2355+# CONFIG_AF_RXRPC is not set
2356+# CONFIG_PHONET is not set
2357+CONFIG_WIRELESS=y
2358+# CONFIG_CFG80211 is not set
2359+CONFIG_WIRELESS_OLD_REGULATORY=y
2360+# CONFIG_WIRELESS_EXT is not set
2361+# CONFIG_LIB80211 is not set
2362+# CONFIG_MAC80211 is not set
2363+# CONFIG_WIMAX is not set
2364+# CONFIG_RFKILL is not set
2365+# CONFIG_NET_9P is not set
2366+# CONFIG_KLIPS is not set
2367+
2368+#
2369+# Device Drivers
2370+#
2371+
2372+#
2373+# Generic Driver Options
2374+#
2375+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
2376+# CONFIG_STANDALONE is not set
2377+CONFIG_PREVENT_FIRMWARE_BUILD=y
2378+CONFIG_FW_LOADER=y
2379+CONFIG_FIRMWARE_IN_KERNEL=y
2380+CONFIG_EXTRA_FIRMWARE=""
2381+# CONFIG_SYS_HYPERVISOR is not set
2382+# CONFIG_CONNECTOR is not set
2383+CONFIG_MTD=y
2384+# CONFIG_MTD_DEBUG is not set
2385+# CONFIG_MTD_CONCAT is not set
2386+CONFIG_MTD_PARTITIONS=y
2387+# CONFIG_MTD_TESTS is not set
2388+# CONFIG_MTD_REDBOOT_PARTS is not set
2389+CONFIG_MTD_CMDLINE_PARTS=y
2390+# CONFIG_MTD_AR7_PARTS is not set
2391+
2392+#
2393+# User Modules And Translation Layers
2394+#
2395+# CONFIG_MTD_CHAR is not set
2396+CONFIG_MTD_BLKDEVS=y
2397+CONFIG_MTD_BLOCK=y
2398+# CONFIG_FTL is not set
2399+# CONFIG_NFTL is not set
2400+# CONFIG_INFTL is not set
2401+# CONFIG_RFD_FTL is not set
2402+# CONFIG_SSFDC is not set
2403+# CONFIG_MTD_OOPS is not set
2404+
2405+#
2406+# RAM/ROM/Flash chip drivers
2407+#
2408+CONFIG_MTD_CFI=y
2409+CONFIG_MTD_JEDECPROBE=y
2410+CONFIG_MTD_GEN_PROBE=y
2411+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
2412+CONFIG_MTD_MAP_BANK_WIDTH_1=y
2413+CONFIG_MTD_MAP_BANK_WIDTH_2=y
2414+CONFIG_MTD_MAP_BANK_WIDTH_4=y
2415+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
2416+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
2417+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
2418+CONFIG_MTD_CFI_I1=y
2419+CONFIG_MTD_CFI_I2=y
2420+# CONFIG_MTD_CFI_I4 is not set
2421+# CONFIG_MTD_CFI_I8 is not set
2422+CONFIG_MTD_CFI_INTELEXT=y
2423+CONFIG_MTD_CFI_AMDSTD=y
2424+# CONFIG_MTD_CFI_STAA is not set
2425+CONFIG_MTD_CFI_UTIL=y
2426+CONFIG_MTD_RAM=y
2427+CONFIG_MTD_ROM=y
2428+# CONFIG_MTD_ABSENT is not set
2429+
2430+#
2431+# Mapping drivers for chip access
2432+#
2433+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
2434+CONFIG_MTD_PHYSMAP=y
2435+CONFIG_MTD_PHYSMAP_COMPAT=y
2436+CONFIG_MTD_PHYSMAP_START=0xe0000000
2437+CONFIG_MTD_PHYSMAP_LEN=0x1000000
2438+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
2439+# CONFIG_MTD_INTEL_VR_NOR is not set
2440+# CONFIG_MTD_PLATRAM is not set
2441+
2442+#
2443+# Self-contained MTD device drivers
2444+#
2445+# CONFIG_MTD_PMC551 is not set
2446+# CONFIG_MTD_SLRAM is not set
2447+# CONFIG_MTD_PHRAM is not set
2448+# CONFIG_MTD_MTDRAM is not set
2449+# CONFIG_MTD_BLOCK2MTD is not set
2450+
2451+#
2452+# Disk-On-Chip Device Drivers
2453+#
2454+# CONFIG_MTD_DOC2000 is not set
2455+# CONFIG_MTD_DOC2001 is not set
2456+# CONFIG_MTD_DOC2001PLUS is not set
2457+# CONFIG_MTD_NAND is not set
2458+# CONFIG_MTD_ONENAND is not set
2459+
2460+#
2461+# LPDDR flash memory drivers
2462+#
2463+# CONFIG_MTD_LPDDR is not set
2464+
2465+#
2466+# UBI - Unsorted block images
2467+#
2468+# CONFIG_MTD_UBI is not set
2469+# CONFIG_PARPORT is not set
2470+CONFIG_BLK_DEV=y
2471+# CONFIG_BLK_CPQ_DA is not set
2472+# CONFIG_BLK_CPQ_CISS_DA is not set
2473+# CONFIG_BLK_DEV_DAC960 is not set
2474+# CONFIG_BLK_DEV_UMEM is not set
2475+# CONFIG_BLK_DEV_COW_COMMON is not set
2476+CONFIG_BLK_DEV_LOOP=y
2477+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
2478+# CONFIG_BLK_DEV_NBD is not set
2479+# CONFIG_BLK_DEV_SX8 is not set
2480+# CONFIG_BLK_DEV_UB is not set
2481+CONFIG_BLK_DEV_RAM=y
2482+CONFIG_BLK_DEV_RAM_COUNT=16
2483+CONFIG_BLK_DEV_RAM_SIZE=64000
2484+# CONFIG_BLK_DEV_XIP is not set
2485+# CONFIG_CDROM_PKTCDVD is not set
2486+# CONFIG_ATA_OVER_ETH is not set
2487+# CONFIG_BLK_DEV_HD is not set
2488+CONFIG_MISC_DEVICES=y
2489+# CONFIG_PHANTOM is not set
2490+# CONFIG_SGI_IOC4 is not set
2491+# CONFIG_TIFM_CORE is not set
2492+# CONFIG_ICS932S401 is not set
2493+# CONFIG_ENCLOSURE_SERVICES is not set
2494+# CONFIG_HP_ILO is not set
2495+# CONFIG_C2PORT is not set
2496+
2497+#
2498+# EEPROM support
2499+#
2500+# CONFIG_EEPROM_AT24 is not set
2501+# CONFIG_EEPROM_LEGACY is not set
2502+# CONFIG_EEPROM_93CX6 is not set
2503+CONFIG_HAVE_IDE=y
2504+# CONFIG_IDE is not set
2505+
2506+#
2507+# SCSI device support
2508+#
2509+# CONFIG_RAID_ATTRS is not set
2510+CONFIG_SCSI=y
2511+CONFIG_SCSI_DMA=y
2512+# CONFIG_SCSI_TGT is not set
2513+# CONFIG_SCSI_NETLINK is not set
2514+CONFIG_SCSI_PROC_FS=y
2515+
2516+#
2517+# SCSI support type (disk, tape, CD-ROM)
2518+#
2519+CONFIG_BLK_DEV_SD=y
2520+# CONFIG_CHR_DEV_ST is not set
2521+# CONFIG_CHR_DEV_OSST is not set
2522+# CONFIG_BLK_DEV_SR is not set
2523+# CONFIG_CHR_DEV_SG is not set
2524+# CONFIG_CHR_DEV_SCH is not set
2525+
2526+#
2527+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
2528+#
2529+CONFIG_SCSI_MULTI_LUN=y
2530+# CONFIG_SCSI_CONSTANTS is not set
2531+# CONFIG_SCSI_LOGGING is not set
2532+# CONFIG_SCSI_SCAN_ASYNC is not set
2533+CONFIG_SCSI_WAIT_SCAN=m
2534+
2535+#
2536+# SCSI Transports
2537+#
2538+# CONFIG_SCSI_SPI_ATTRS is not set
2539+# CONFIG_SCSI_FC_ATTRS is not set
2540+# CONFIG_SCSI_ISCSI_ATTRS is not set
2541+# CONFIG_SCSI_SAS_LIBSAS is not set
2542+# CONFIG_SCSI_SRP_ATTRS is not set
2543+# CONFIG_SCSI_LOWLEVEL is not set
2544+# CONFIG_SCSI_DH is not set
2545+# CONFIG_ATA is not set
2546+# CONFIG_MD is not set
2547+# CONFIG_FUSION is not set
2548+
2549+#
2550+# IEEE 1394 (FireWire) support
2551+#
2552+
2553+#
2554+# Enable only one of the two stacks, unless you know what you are doing
2555+#
2556+# CONFIG_FIREWIRE is not set
2557+# CONFIG_IEEE1394 is not set
2558+# CONFIG_I2O is not set
2559+CONFIG_NETDEVICES=y
2560+# CONFIG_DUMMY is not set
2561+# CONFIG_BONDING is not set
2562+# CONFIG_MACVLAN is not set
2563+# CONFIG_EQUALIZER is not set
2564+# CONFIG_TUN is not set
2565+# CONFIG_VETH is not set
2566+# CONFIG_ARCNET is not set
2567+CONFIG_PHYLIB=y
2568+
2569+#
2570+# MII PHY device drivers
2571+#
2572+# CONFIG_MARVELL_PHY is not set
2573+# CONFIG_DAVICOM_PHY is not set
2574+# CONFIG_QSEMI_PHY is not set
2575+# CONFIG_LXT_PHY is not set
2576+# CONFIG_CICADA_PHY is not set
2577+# CONFIG_VITESSE_PHY is not set
2578+# CONFIG_SMSC_PHY is not set
2579+# CONFIG_BROADCOM_PHY is not set
2580+CONFIG_BROADCOM5222_PHY=y
2581+# CONFIG_ICPLUS_PHY is not set
2582+# CONFIG_REALTEK_PHY is not set
2583+# CONFIG_NATIONAL_PHY is not set
2584+# CONFIG_NATIONAL8364x_PHY is not set
2585+# CONFIG_NATIONAL8384x_PHY is not set
2586+# CONFIG_MicrelKSZ8041_PHY is not set
2587+# CONFIG_STE10XP is not set
2588+# CONFIG_LSI_ET1011C_PHY is not set
2589+# CONFIG_FIXED_PHY is not set
2590+# CONFIG_MDIO_BITBANG is not set
2591+CONFIG_NET_ETHERNET=y
2592+CONFIG_MII=y
2593+# CONFIG_HAPPYMEAL is not set
2594+# CONFIG_SUNGEM is not set
2595+# CONFIG_CASSINI is not set
2596+# CONFIG_NET_VENDOR_3COM is not set
2597+# CONFIG_DNET is not set
2598+# CONFIG_NET_TULIP is not set
2599+# CONFIG_HP100 is not set
2600+# CONFIG_IBM_NEW_EMAC_ZMII is not set
2601+# CONFIG_IBM_NEW_EMAC_RGMII is not set
2602+# CONFIG_IBM_NEW_EMAC_TAH is not set
2603+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
2604+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
2605+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
2606+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
2607+# CONFIG_NET_PCI is not set
2608+# CONFIG_B44 is not set
2609+CONFIG_FEC_548x=y
2610+CONFIG_FEC_548x_ENABLE_FEC2=y
2611+CONFIG_FEC_548x_SHARED_PHY=y
2612+# CONFIG_ATL2 is not set
2613+# CONFIG_NETDEV_1000 is not set
2614+# CONFIG_NETDEV_10000 is not set
2615+# CONFIG_TR is not set
2616+
2617+#
2618+# Wireless LAN
2619+#
2620+# CONFIG_WLAN_PRE80211 is not set
2621+# CONFIG_WLAN_80211 is not set
2622+# CONFIG_IWLWIFI_LEDS is not set
2623+
2624+#
2625+# Enable WiMAX (Networking options) to see the WiMAX drivers
2626+#
2627+
2628+#
2629+# USB Network Adapters
2630+#
2631+# CONFIG_USB_CATC is not set
2632+# CONFIG_USB_KAWETH is not set
2633+# CONFIG_USB_PEGASUS is not set
2634+# CONFIG_USB_RTL8150 is not set
2635+# CONFIG_USB_USBNET is not set
2636+# CONFIG_WAN is not set
2637+# CONFIG_FDDI is not set
2638+# CONFIG_HIPPI is not set
2639+# CONFIG_PPP is not set
2640+# CONFIG_SLIP is not set
2641+# CONFIG_NET_FC is not set
2642+# CONFIG_NETCONSOLE is not set
2643+# CONFIG_NETPOLL is not set
2644+# CONFIG_NET_POLL_CONTROLLER is not set
2645+# CONFIG_ISDN is not set
2646+# CONFIG_PHONE is not set
2647+
2648+#
2649+# Input device support
2650+#
2651+CONFIG_INPUT=y
2652+# CONFIG_INPUT_FF_MEMLESS is not set
2653+# CONFIG_INPUT_POLLDEV is not set
2654+
2655+#
2656+# Userland interfaces
2657+#
2658+CONFIG_INPUT_MOUSEDEV=y
2659+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
2660+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
2661+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
2662+# CONFIG_INPUT_JOYDEV is not set
2663+CONFIG_INPUT_EVDEV=y
2664+# CONFIG_INPUT_EVBUG is not set
2665+
2666+#
2667+# Input Device Drivers
2668+#
2669+CONFIG_INPUT_KEYBOARD=y
2670+# CONFIG_KEYBOARD_ATKBD is not set
2671+# CONFIG_KEYBOARD_SUNKBD is not set
2672+# CONFIG_KEYBOARD_LKKBD is not set
2673+# CONFIG_KEYBOARD_XTKBD is not set
2674+# CONFIG_KEYBOARD_NEWTON is not set
2675+# CONFIG_KEYBOARD_STOWAWAY is not set
2676+# CONFIG_INPUT_MOUSE is not set
2677+# CONFIG_INPUT_JOYSTICK is not set
2678+# CONFIG_INPUT_TABLET is not set
2679+# CONFIG_INPUT_TOUCHSCREEN is not set
2680+# CONFIG_INPUT_MISC is not set
2681+
2682+#
2683+# Hardware I/O ports
2684+#
2685+CONFIG_SERIO=y
2686+CONFIG_SERIO_SERPORT=y
2687+# CONFIG_SERIO_PCIPS2 is not set
2688+# CONFIG_SERIO_RAW is not set
2689+# CONFIG_GAMEPORT is not set
2690+
2691+#
2692+# Character devices
2693+#
2694+CONFIG_VT=y
2695+CONFIG_CONSOLE_TRANSLATIONS=y
2696+CONFIG_VT_CONSOLE=y
2697+CONFIG_HW_CONSOLE=y
2698+# CONFIG_VT_HW_CONSOLE_BINDING is not set
2699+CONFIG_DEVKMEM=y
2700+# CONFIG_SERIAL_NONSTANDARD is not set
2701+# CONFIG_NOZOMI is not set
2702+
2703+#
2704+# Serial drivers
2705+#
2706+# CONFIG_SERIAL_8250 is not set
2707+
2708+#
2709+# Non-8250 serial port support
2710+#
2711+CONFIG_SERIAL_CORE=y
2712+CONFIG_SERIAL_CORE_CONSOLE=y
2713+# CONFIG_SERIAL_COLDFIRE_IRDA is not set
2714+# CONFIG_SERIAL_COLDFIRE_EDMA is not set
2715+CONFIG_SERIAL_MCF=y
2716+CONFIG_SERIAL_MCF_BAUDRATE=115200
2717+CONFIG_SERIAL_MCF_CONSOLE=y
2718+# CONFIG_SERIAL_JSM is not set
2719+CONFIG_UNIX98_PTYS=y
2720+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
2721+# CONFIG_LEGACY_PTYS is not set
2722+# CONFIG_IPMI_HANDLER is not set
2723+# CONFIG_HW_RANDOM is not set
2724+# CONFIG_R3964 is not set
2725+# CONFIG_APPLICOM is not set
2726+# CONFIG_RAW_DRIVER is not set
2727+# CONFIG_TCG_TPM is not set
2728+CONFIG_I2C=y
2729+CONFIG_I2C_BOARDINFO=y
2730+CONFIG_I2C_CHARDEV=y
2731+CONFIG_I2C_HELPER_AUTO=y
2732+
2733+#
2734+# I2C Hardware Bus support
2735+#
2736+
2737+#
2738+# PC SMBus host controller drivers
2739+#
2740+# CONFIG_I2C_ALI1535 is not set
2741+# CONFIG_I2C_ALI1563 is not set
2742+# CONFIG_I2C_ALI15X3 is not set
2743+# CONFIG_I2C_AMD756 is not set
2744+# CONFIG_I2C_AMD8111 is not set
2745+# CONFIG_I2C_I801 is not set
2746+# CONFIG_I2C_ISCH is not set
2747+# CONFIG_I2C_PIIX4 is not set
2748+# CONFIG_I2C_NFORCE2 is not set
2749+# CONFIG_I2C_SIS5595 is not set
2750+# CONFIG_I2C_SIS630 is not set
2751+# CONFIG_I2C_SIS96X is not set
2752+# CONFIG_I2C_VIA is not set
2753+# CONFIG_I2C_VIAPRO is not set
2754+
2755+#
2756+# I2C system bus drivers (mostly embedded / system-on-chip)
2757+#
2758+CONFIG_I2C_MCF=y
2759+# CONFIG_I2C_OCORES is not set
2760+# CONFIG_I2C_SIMTEC is not set
2761+
2762+#
2763+# External I2C/SMBus adapter drivers
2764+#
2765+# CONFIG_I2C_PARPORT_LIGHT is not set
2766+# CONFIG_I2C_TAOS_EVM is not set
2767+# CONFIG_I2C_TINY_USB is not set
2768+
2769+#
2770+# Graphics adapter I2C/DDC channel drivers
2771+#
2772+# CONFIG_I2C_VOODOO3 is not set
2773+
2774+#
2775+# Other I2C/SMBus bus drivers
2776+#
2777+# CONFIG_I2C_PCA_PLATFORM is not set
2778+# CONFIG_I2C_STUB is not set
2779+
2780+#
2781+# Miscellaneous I2C Chip support
2782+#
2783+# CONFIG_DS1682 is not set
2784+# CONFIG_SENSORS_PCF8574 is not set
2785+# CONFIG_PCF8575 is not set
2786+# CONFIG_SENSORS_PCA9539 is not set
2787+# CONFIG_SENSORS_PCF8591 is not set
2788+# CONFIG_SENSORS_MAX6875 is not set
2789+# CONFIG_SENSORS_TSL2550 is not set
2790+# CONFIG_I2C_DEBUG_CORE is not set
2791+# CONFIG_I2C_DEBUG_ALGO is not set
2792+# CONFIG_I2C_DEBUG_BUS is not set
2793+# CONFIG_I2C_DEBUG_CHIP is not set
2794+# CONFIG_SPI is not set
2795+# CONFIG_W1 is not set
2796+# CONFIG_POWER_SUPPLY is not set
2797+# CONFIG_HWMON is not set
2798+# CONFIG_THERMAL is not set
2799+# CONFIG_THERMAL_HWMON is not set
2800+CONFIG_WATCHDOG=y
2801+# CONFIG_WATCHDOG_NOWAYOUT is not set
2802+
2803+#
2804+# Watchdog Device Drivers
2805+#
2806+# CONFIG_SOFT_WATCHDOG is not set
2807+# CONFIG_ALIM7101_WDT is not set
2808+CONFIG_COLDFIRE_WATCHDOG=y
2809+
2810+#
2811+# PCI-based Watchdog Cards
2812+#
2813+# CONFIG_PCIPCWATCHDOG is not set
2814+# CONFIG_WDTPCI is not set
2815+
2816+#
2817+# USB-based Watchdog Cards
2818+#
2819+# CONFIG_USBPCWATCHDOG is not set
2820+CONFIG_SSB_POSSIBLE=y
2821+
2822+#
2823+# Sonics Silicon Backplane
2824+#
2825+# CONFIG_SSB is not set
2826+
2827+#
2828+# Multifunction device drivers
2829+#
2830+# CONFIG_MFD_CORE is not set
2831+# CONFIG_MFD_SM501 is not set
2832+# CONFIG_HTC_PASIC3 is not set
2833+# CONFIG_MFD_TMIO is not set
2834+# CONFIG_PMIC_DA903X is not set
2835+# CONFIG_MFD_WM8400 is not set
2836+# CONFIG_MFD_WM8350_I2C is not set
2837+# CONFIG_MFD_PCF50633 is not set
2838+# CONFIG_REGULATOR is not set
2839+
2840+#
2841+# Multimedia devices
2842+#
2843+
2844+#
2845+# Multimedia core support
2846+#
2847+# CONFIG_VIDEO_DEV is not set
2848+# CONFIG_DVB_CORE is not set
2849+# CONFIG_VIDEO_MEDIA is not set
2850+
2851+#
2852+# Multimedia drivers
2853+#
2854+CONFIG_DAB=y
2855+# CONFIG_USB_DABUSB is not set
2856+
2857+#
2858+# Graphics support
2859+#
2860+# CONFIG_DRM is not set
2861+# CONFIG_VGASTATE is not set
2862+CONFIG_VIDEO_OUTPUT_CONTROL=m
2863+# CONFIG_FB is not set
2864+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
2865+
2866+#
2867+# Display device support
2868+#
2869+# CONFIG_DISPLAY_SUPPORT is not set
2870+
2871+#
2872+# Console display driver support
2873+#
2874+CONFIG_DUMMY_CONSOLE=y
2875+# CONFIG_SOUND is not set
2876+# CONFIG_HID_SUPPORT is not set
2877+CONFIG_USB_SUPPORT=y
2878+CONFIG_USB_ARCH_HAS_HCD=y
2879+CONFIG_USB_ARCH_HAS_OHCI=y
2880+CONFIG_USB_ARCH_HAS_EHCI=y
2881+CONFIG_USB=y
2882+# CONFIG_USB_DEBUG is not set
2883+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
2884+
2885+#
2886+# Miscellaneous USB options
2887+#
2888+# CONFIG_USB_DEVICEFS is not set
2889+CONFIG_USB_DEVICE_CLASS=y
2890+# CONFIG_USB_DYNAMIC_MINORS is not set
2891+# CONFIG_USB_SUSPEND is not set
2892+# CONFIG_USB_OTG is not set
2893+CONFIG_USB_MON=y
2894+# CONFIG_USB_WUSB is not set
2895+# CONFIG_USB_WUSB_CBAF is not set
2896+
2897+#
2898+# USB Host Controller Drivers
2899+#
2900+# CONFIG_USB_C67X00_HCD is not set
2901+CONFIG_USB_EHCI_HCD=y
2902+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
2903+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
2904+# CONFIG_USB_OXU210HP_HCD is not set
2905+# CONFIG_USB_ISP116X_HCD is not set
2906+# CONFIG_USB_ISP1760_HCD is not set
2907+# CONFIG_USB_OHCI_HCD is not set
2908+# CONFIG_USB_UHCI_HCD is not set
2909+# CONFIG_USB_SL811_HCD is not set
2910+# CONFIG_USB_R8A66597_HCD is not set
2911+# CONFIG_USB_WHCI_HCD is not set
2912+# CONFIG_USB_HWA_HCD is not set
2913+
2914+#
2915+# USB Device Class drivers
2916+#
2917+# CONFIG_USB_ACM is not set
2918+# CONFIG_USB_PRINTER is not set
2919+# CONFIG_USB_WDM is not set
2920+# CONFIG_USB_TMC is not set
2921+
2922+#
2923+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
2924+#
2925+
2926+#
2927+# see USB_STORAGE Help for more information
2928+#
2929+CONFIG_USB_STORAGE=y
2930+# CONFIG_USB_STORAGE_DEBUG is not set
2931+# CONFIG_USB_STORAGE_DATAFAB is not set
2932+# CONFIG_USB_STORAGE_FREECOM is not set
2933+# CONFIG_USB_STORAGE_ISD200 is not set
2934+# CONFIG_USB_STORAGE_USBAT is not set
2935+# CONFIG_USB_STORAGE_SDDR09 is not set
2936+# CONFIG_USB_STORAGE_SDDR55 is not set
2937+# CONFIG_USB_STORAGE_JUMPSHOT is not set
2938+# CONFIG_USB_STORAGE_ALAUDA is not set
2939+# CONFIG_USB_STORAGE_ONETOUCH is not set
2940+# CONFIG_USB_STORAGE_KARMA is not set
2941+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
2942+# CONFIG_USB_LIBUSUAL is not set
2943+
2944+#
2945+# USB Imaging devices
2946+#
2947+# CONFIG_USB_MDC800 is not set
2948+# CONFIG_USB_MICROTEK is not set
2949+
2950+#
2951+# USB port drivers
2952+#
2953+# CONFIG_USB_SERIAL is not set
2954+
2955+#
2956+# USB Miscellaneous drivers
2957+#
2958+# CONFIG_USB_EMI62 is not set
2959+# CONFIG_USB_EMI26 is not set
2960+# CONFIG_USB_ADUTUX is not set
2961+# CONFIG_USB_SEVSEG is not set
2962+# CONFIG_USB_RIO500 is not set
2963+# CONFIG_USB_LEGOTOWER is not set
2964+# CONFIG_USB_LCD is not set
2965+# CONFIG_USB_BERRY_CHARGE is not set
2966+# CONFIG_USB_LED is not set
2967+# CONFIG_USB_CYPRESS_CY7C63 is not set
2968+# CONFIG_USB_CYTHERM is not set
2969+# CONFIG_USB_PHIDGET is not set
2970+# CONFIG_USB_IDMOUSE is not set
2971+# CONFIG_USB_FTDI_ELAN is not set
2972+# CONFIG_USB_APPLEDISPLAY is not set
2973+# CONFIG_USB_SISUSBVGA is not set
2974+# CONFIG_USB_LD is not set
2975+# CONFIG_USB_TRANCEVIBRATOR is not set
2976+# CONFIG_USB_IOWARRIOR is not set
2977+# CONFIG_USB_ISIGHTFW is not set
2978+# CONFIG_USB_VST is not set
2979+# CONFIG_USB_GADGET is not set
2980+
2981+#
2982+# OTG and related infrastructure
2983+#
2984+# CONFIG_UWB is not set
2985+# CONFIG_MMC is not set
2986+# CONFIG_MEMSTICK is not set
2987+# CONFIG_NEW_LEDS is not set
2988+# CONFIG_ACCESSIBILITY is not set
2989+# CONFIG_INFINIBAND is not set
2990+CONFIG_RTC_LIB=y
2991+CONFIG_RTC_CLASS=y
2992+CONFIG_RTC_HCTOSYS=y
2993+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
2994+# CONFIG_RTC_DEBUG is not set
2995+
2996+#
2997+# RTC interfaces
2998+#
2999+CONFIG_RTC_INTF_SYSFS=y
3000+CONFIG_RTC_INTF_PROC=y
3001+CONFIG_RTC_INTF_DEV=y
3002+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
3003+# CONFIG_RTC_DRV_TEST is not set
3004+
3005+#
3006+# I2C RTC drivers
3007+#
3008+# CONFIG_RTC_DRV_DS1307 is not set
3009+# CONFIG_RTC_DRV_DS1374 is not set
3010+# CONFIG_RTC_DRV_DS1672 is not set
3011+# CONFIG_RTC_DRV_MAX6900 is not set
3012+CONFIG_RTC_DRV_RS5C372=y
3013+# CONFIG_RTC_DRV_ISL1208 is not set
3014+# CONFIG_RTC_DRV_X1205 is not set
3015+# CONFIG_RTC_DRV_PCF8563 is not set
3016+# CONFIG_RTC_DRV_PCF8583 is not set
3017+# CONFIG_RTC_DRV_M41T80 is not set
3018+# CONFIG_RTC_DRV_S35390A is not set
3019+# CONFIG_RTC_DRV_FM3130 is not set
3020+# CONFIG_RTC_DRV_RX8581 is not set
3021+
3022+#
3023+# SPI RTC drivers
3024+#
3025+
3026+#
3027+# Platform RTC drivers
3028+#
3029+# CONFIG_RTC_DRV_DS1286 is not set
3030+# CONFIG_RTC_DRV_DS1511 is not set
3031+# CONFIG_RTC_DRV_DS1553 is not set
3032+# CONFIG_RTC_DRV_DS1742 is not set
3033+# CONFIG_RTC_DRV_STK17TA8 is not set
3034+# CONFIG_RTC_DRV_M48T86 is not set
3035+# CONFIG_RTC_DRV_M48T35 is not set
3036+# CONFIG_RTC_DRV_M48T59 is not set
3037+# CONFIG_RTC_DRV_BQ4802 is not set
3038+# CONFIG_RTC_DRV_V3020 is not set
3039+
3040+#
3041+# on-CPU RTC drivers
3042+#
3043+# CONFIG_RTC_MCF is not set
3044+# CONFIG_RTC_M5441X is not set
3045+# CONFIG_DMADEVICES is not set
3046+# CONFIG_UIO is not set
3047+# CONFIG_STAGING is not set
3048+
3049+#
3050+# Character devices
3051+#
3052+CONFIG_TICK_ONESHOT=y
3053+CONFIG_NO_HZ=y
3054+CONFIG_HIGH_RES_TIMERS=y
3055+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
3056+
3057+#
3058+# File systems
3059+#
3060+CONFIG_EXT2_FS=y
3061+# CONFIG_EXT2_FS_XATTR is not set
3062+# CONFIG_EXT2_FS_XIP is not set
3063+CONFIG_EXT3_FS=y
3064+CONFIG_EXT3_FS_XATTR=y
3065+# CONFIG_EXT3_FS_POSIX_ACL is not set
3066+# CONFIG_EXT3_FS_SECURITY is not set
3067+# CONFIG_EXT4_FS is not set
3068+CONFIG_JBD=y
3069+CONFIG_FS_MBCACHE=y
3070+# CONFIG_REISERFS_FS is not set
3071+# CONFIG_JFS_FS is not set
3072+# CONFIG_FS_POSIX_ACL is not set
3073+CONFIG_FILE_LOCKING=y
3074+# CONFIG_XFS_FS is not set
3075+# CONFIG_GFS2_FS is not set
3076+# CONFIG_OCFS2_FS is not set
3077+# CONFIG_BTRFS_FS is not set
3078+CONFIG_DNOTIFY=y
3079+# CONFIG_INOTIFY is not set
3080+# CONFIG_QUOTA is not set
3081+# CONFIG_AUTOFS_FS is not set
3082+# CONFIG_AUTOFS4_FS is not set
3083+# CONFIG_FUSE_FS is not set
3084+
3085+#
3086+# CD-ROM/DVD Filesystems
3087+#
3088+# CONFIG_ISO9660_FS is not set
3089+# CONFIG_UDF_FS is not set
3090+
3091+#
3092+# DOS/FAT/NT Filesystems
3093+#
3094+CONFIG_FAT_FS=y
3095+CONFIG_MSDOS_FS=y
3096+CONFIG_VFAT_FS=y
3097+CONFIG_FAT_DEFAULT_CODEPAGE=437
3098+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
3099+CONFIG_NTFS_FS=y
3100+# CONFIG_NTFS_DEBUG is not set
3101+CONFIG_NTFS_RW=y
3102+
3103+#
3104+# Pseudo filesystems
3105+#
3106+CONFIG_PROC_FS=y
3107+# CONFIG_PROC_KCORE is not set
3108+CONFIG_PROC_SYSCTL=y
3109+CONFIG_PROC_PAGE_MONITOR=y
3110+CONFIG_SYSFS=y
3111+CONFIG_TMPFS=y
3112+# CONFIG_TMPFS_POSIX_ACL is not set
3113+# CONFIG_HUGETLB_PAGE is not set
3114+# CONFIG_CONFIGFS_FS is not set
3115+CONFIG_MISC_FILESYSTEMS=y
3116+# CONFIG_ADFS_FS is not set
3117+# CONFIG_AFFS_FS is not set
3118+# CONFIG_HFS_FS is not set
3119+# CONFIG_HFSPLUS_FS is not set
3120+# CONFIG_BEFS_FS is not set
3121+# CONFIG_BFS_FS is not set
3122+# CONFIG_EFS_FS is not set
3123+CONFIG_JFFS2_FS=y
3124+CONFIG_JFFS2_FS_DEBUG=0
3125+CONFIG_JFFS2_FS_WRITEBUFFER=y
3126+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
3127+# CONFIG_JFFS2_SUMMARY is not set
3128+# CONFIG_JFFS2_FS_XATTR is not set
3129+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
3130+CONFIG_JFFS2_ZLIB=y
3131+# CONFIG_JFFS2_LZO is not set
3132+CONFIG_JFFS2_RTIME=y
3133+# CONFIG_JFFS2_RUBIN is not set
3134+# CONFIG_CRAMFS is not set
3135+# CONFIG_SQUASHFS is not set
3136+# CONFIG_VXFS_FS is not set
3137+CONFIG_MINIX_FS=y
3138+# CONFIG_OMFS_FS is not set
3139+# CONFIG_HPFS_FS is not set
3140+# CONFIG_QNX4FS_FS is not set
3141+CONFIG_ROMFS_FS=y
3142+# CONFIG_SYSV_FS is not set
3143+# CONFIG_UFS_FS is not set
3144+CONFIG_NETWORK_FILESYSTEMS=y
3145+CONFIG_NFS_FS=y
3146+# CONFIG_NFS_V3 is not set
3147+# CONFIG_NFS_V4 is not set
3148+CONFIG_ROOT_NFS=y
3149+# CONFIG_NFSD is not set
3150+CONFIG_LOCKD=y
3151+CONFIG_NFS_COMMON=y
3152+CONFIG_SUNRPC=y
3153+# CONFIG_SUNRPC_REGISTER_V4 is not set
3154+# CONFIG_RPCSEC_GSS_KRB5 is not set
3155+# CONFIG_RPCSEC_GSS_SPKM3 is not set
3156+# CONFIG_SMB_FS is not set
3157+# CONFIG_CIFS is not set
3158+# CONFIG_NCP_FS is not set
3159+# CONFIG_CODA_FS is not set
3160+# CONFIG_AFS_FS is not set
3161+
3162+#
3163+# Partition Types
3164+#
3165+CONFIG_PARTITION_ADVANCED=y
3166+# CONFIG_ACORN_PARTITION is not set
3167+# CONFIG_OSF_PARTITION is not set
3168+# CONFIG_AMIGA_PARTITION is not set
3169+# CONFIG_ATARI_PARTITION is not set
3170+# CONFIG_MAC_PARTITION is not set
3171+CONFIG_MSDOS_PARTITION=y
3172+# CONFIG_BSD_DISKLABEL is not set
3173+# CONFIG_MINIX_SUBPARTITION is not set
3174+# CONFIG_SOLARIS_X86_PARTITION is not set
3175+# CONFIG_UNIXWARE_DISKLABEL is not set
3176+# CONFIG_LDM_PARTITION is not set
3177+# CONFIG_SGI_PARTITION is not set
3178+# CONFIG_ULTRIX_PARTITION is not set
3179+# CONFIG_SUN_PARTITION is not set
3180+# CONFIG_KARMA_PARTITION is not set
3181+# CONFIG_EFI_PARTITION is not set
3182+# CONFIG_SYSV68_PARTITION is not set
3183+CONFIG_NLS=y
3184+CONFIG_NLS_DEFAULT="iso8859-1"
3185+CONFIG_NLS_CODEPAGE_437=y
3186+# CONFIG_NLS_CODEPAGE_737 is not set
3187+# CONFIG_NLS_CODEPAGE_775 is not set
3188+# CONFIG_NLS_CODEPAGE_850 is not set
3189+# CONFIG_NLS_CODEPAGE_852 is not set
3190+# CONFIG_NLS_CODEPAGE_855 is not set
3191+# CONFIG_NLS_CODEPAGE_857 is not set
3192+# CONFIG_NLS_CODEPAGE_860 is not set
3193+# CONFIG_NLS_CODEPAGE_861 is not set
3194+# CONFIG_NLS_CODEPAGE_862 is not set
3195+# CONFIG_NLS_CODEPAGE_863 is not set
3196+# CONFIG_NLS_CODEPAGE_864 is not set
3197+# CONFIG_NLS_CODEPAGE_865 is not set
3198+# CONFIG_NLS_CODEPAGE_866 is not set
3199+# CONFIG_NLS_CODEPAGE_869 is not set
3200+# CONFIG_NLS_CODEPAGE_936 is not set
3201+# CONFIG_NLS_CODEPAGE_950 is not set
3202+# CONFIG_NLS_CODEPAGE_932 is not set
3203+# CONFIG_NLS_CODEPAGE_949 is not set
3204+# CONFIG_NLS_CODEPAGE_874 is not set
3205+# CONFIG_NLS_ISO8859_8 is not set
3206+# CONFIG_NLS_CODEPAGE_1250 is not set
3207+# CONFIG_NLS_CODEPAGE_1251 is not set
3208+# CONFIG_NLS_ASCII is not set
3209+CONFIG_NLS_ISO8859_1=y
3210+# CONFIG_NLS_ISO8859_2 is not set
3211+# CONFIG_NLS_ISO8859_3 is not set
3212+# CONFIG_NLS_ISO8859_4 is not set
3213+# CONFIG_NLS_ISO8859_5 is not set
3214+# CONFIG_NLS_ISO8859_6 is not set
3215+# CONFIG_NLS_ISO8859_7 is not set
3216+# CONFIG_NLS_ISO8859_9 is not set
3217+# CONFIG_NLS_ISO8859_13 is not set
3218+# CONFIG_NLS_ISO8859_14 is not set
3219+# CONFIG_NLS_ISO8859_15 is not set
3220+# CONFIG_NLS_KOI8_R is not set
3221+# CONFIG_NLS_KOI8_U is not set
3222+CONFIG_NLS_UTF8=y
3223+# CONFIG_DLM is not set
3224+
3225+#
3226+# Kernel hacking
3227+#
3228+# CONFIG_PRINTK_TIME is not set
3229+CONFIG_ENABLE_WARN_DEPRECATED=y
3230+# CONFIG_ENABLE_MUST_CHECK is not set
3231+CONFIG_FRAME_WARN=1024
3232+# CONFIG_MAGIC_SYSRQ is not set
3233+# CONFIG_UNUSED_SYMBOLS is not set
3234+# CONFIG_DEBUG_FS is not set
3235+# CONFIG_HEADERS_CHECK is not set
3236+# CONFIG_DEBUG_KERNEL is not set
3237+CONFIG_DEBUG_BUGVERBOSE=y
3238+CONFIG_DEBUG_MEMORY_INIT=y
3239+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
3240+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
3241+
3242+#
3243+# Tracers
3244+#
3245+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
3246+# CONFIG_SAMPLES is not set
3247+# CONFIG_BOOTPARAM is not set
3248+
3249+#
3250+# Security options
3251+#
3252+# CONFIG_KEYS is not set
3253+# CONFIG_SECURITY is not set
3254+# CONFIG_SECURITYFS is not set
3255+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
3256+CONFIG_CRYPTO=y
3257+
3258+#
3259+# Crypto core or helper
3260+#
3261+# CONFIG_CRYPTO_FIPS is not set
3262+CONFIG_CRYPTO_ALGAPI=y
3263+CONFIG_CRYPTO_ALGAPI2=y
3264+CONFIG_CRYPTO_AEAD=y
3265+CONFIG_CRYPTO_AEAD2=y
3266+CONFIG_CRYPTO_BLKCIPHER=y
3267+CONFIG_CRYPTO_BLKCIPHER2=y
3268+CONFIG_CRYPTO_HASH=y
3269+CONFIG_CRYPTO_HASH2=y
3270+CONFIG_CRYPTO_RNG2=y
3271+CONFIG_CRYPTO_MANAGER=y
3272+CONFIG_CRYPTO_MANAGER2=y
3273+# CONFIG_CRYPTO_GF128MUL is not set
3274+# CONFIG_CRYPTO_NULL is not set
3275+# CONFIG_CRYPTO_CRYPTD is not set
3276+CONFIG_CRYPTO_AUTHENC=y
3277+CONFIG_CRYPTO_TEST=m
3278+
3279+#
3280+# Authenticated Encryption with Associated Data
3281+#
3282+# CONFIG_CRYPTO_CCM is not set
3283+# CONFIG_CRYPTO_GCM is not set
3284+# CONFIG_CRYPTO_SEQIV is not set
3285+
3286+#
3287+# Block modes
3288+#
3289+CONFIG_CRYPTO_CBC=y
3290+# CONFIG_CRYPTO_CTR is not set
3291+# CONFIG_CRYPTO_CTS is not set
3292+# CONFIG_CRYPTO_ECB is not set
3293+# CONFIG_CRYPTO_LRW is not set
3294+# CONFIG_CRYPTO_PCBC is not set
3295+# CONFIG_CRYPTO_XTS is not set
3296+
3297+#
3298+# Hash modes
3299+#
3300+CONFIG_CRYPTO_HMAC=y
3301+# CONFIG_CRYPTO_XCBC is not set
3302+
3303+#
3304+# Digest
3305+#
3306+CONFIG_CRYPTO_CRC32C=y
3307+# CONFIG_CRYPTO_MD4 is not set
3308+CONFIG_CRYPTO_MD5=y
3309+# CONFIG_CRYPTO_MICHAEL_MIC is not set
3310+# CONFIG_CRYPTO_RMD128 is not set
3311+# CONFIG_CRYPTO_RMD160 is not set
3312+# CONFIG_CRYPTO_RMD256 is not set
3313+# CONFIG_CRYPTO_RMD320 is not set
3314+CONFIG_CRYPTO_SHA1=y
3315+# CONFIG_CRYPTO_SHA256 is not set
3316+# CONFIG_CRYPTO_SHA512 is not set
3317+# CONFIG_CRYPTO_TGR192 is not set
3318+# CONFIG_CRYPTO_WP512 is not set
3319+
3320+#
3321+# Ciphers
3322+#
3323+# CONFIG_CRYPTO_AES is not set
3324+# CONFIG_CRYPTO_ANUBIS is not set
3325+# CONFIG_CRYPTO_ARC4 is not set
3326+# CONFIG_CRYPTO_BLOWFISH is not set
3327+# CONFIG_CRYPTO_CAMELLIA is not set
3328+# CONFIG_CRYPTO_CAST5 is not set
3329+# CONFIG_CRYPTO_CAST6 is not set
3330+CONFIG_CRYPTO_DES=y
3331+# CONFIG_CRYPTO_FCRYPT is not set
3332+# CONFIG_CRYPTO_KHAZAD is not set
3333+# CONFIG_CRYPTO_SALSA20 is not set
3334+# CONFIG_CRYPTO_SEED is not set
3335+# CONFIG_CRYPTO_SERPENT is not set
3336+# CONFIG_CRYPTO_TEA is not set
3337+# CONFIG_CRYPTO_TWOFISH is not set
3338+
3339+#
3340+# Compression
3341+#
3342+# CONFIG_CRYPTO_DEFLATE is not set
3343+# CONFIG_CRYPTO_LZO is not set
3344+
3345+#
3346+# Random Number Generation
3347+#
3348+# CONFIG_CRYPTO_ANSI_CPRNG is not set
3349+
3350+#
3351+# OCF Configuration
3352+#
3353+# CONFIG_OCF_OCF is not set
3354+
3355+#
3356+# Talitos Driver
3357+#
3358+# CONFIG_CRYPTO_HW is not set
3359+
3360+#
3361+# Library routines
3362+#
3363+CONFIG_BITREVERSE=y
3364+CONFIG_GENERIC_FIND_LAST_BIT=y
3365+CONFIG_CRC_CCITT=y
3366+CONFIG_CRC16=y
3367+# CONFIG_CRC_T10DIF is not set
3368+# CONFIG_CRC_ITU_T is not set
3369+CONFIG_CRC32=y
3370+# CONFIG_CRC7 is not set
3371+CONFIG_LIBCRC32C=y
3372+CONFIG_ZLIB_INFLATE=y
3373+CONFIG_ZLIB_DEFLATE=y
3374+CONFIG_PLIST=y
3375+CONFIG_HAS_IOMEM=y
3376+CONFIG_HAS_IOPORT=y
3377+CONFIG_HAS_DMA=y
3378--- /dev/null
3379+++ b/arch/m68k/configs/m5485evb_defconfig
3380@@ -0,0 +1,1582 @@
3381+#
3382+# Automatically generated make config: don't edit
3383+# Linux kernel version: 2.6.29
3384+# Tue Aug 24 16:19:05 2010
3385+#
3386+CONFIG_M68K=y
3387+CONFIG_MMU=y
3388+CONFIG_GENERIC_TIME=y
3389+CONFIG_GENERIC_CLOCKEVENTS=y
3390+CONFIG_RWSEM_GENERIC_SPINLOCK=y
3391+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
3392+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
3393+CONFIG_GENERIC_HWEIGHT=y
3394+CONFIG_GENERIC_CALIBRATE_DELAY=y
3395+# CONFIG_TIME_LOW_RES is not set
3396+CONFIG_GENERIC_IOMAP=y
3397+# CONFIG_NO_IOPORT is not set
3398+# CONFIG_NO_DMA is not set
3399+CONFIG_HZ=100
3400+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
3401+
3402+#
3403+# General setup
3404+#
3405+CONFIG_EXPERIMENTAL=y
3406+CONFIG_BROKEN_ON_SMP=y
3407+CONFIG_INIT_ENV_ARG_LIMIT=32
3408+CONFIG_LOCALVERSION=""
3409+# CONFIG_LOCALVERSION_AUTO is not set
3410+CONFIG_SWAP=y
3411+CONFIG_SYSVIPC=y
3412+CONFIG_SYSVIPC_SYSCTL=y
3413+# CONFIG_POSIX_MQUEUE is not set
3414+# CONFIG_BSD_PROCESS_ACCT is not set
3415+# CONFIG_TASKSTATS is not set
3416+# CONFIG_AUDIT is not set
3417+
3418+#
3419+# RCU Subsystem
3420+#
3421+CONFIG_CLASSIC_RCU=y
3422+# CONFIG_TREE_RCU is not set
3423+# CONFIG_PREEMPT_RCU is not set
3424+# CONFIG_TREE_RCU_TRACE is not set
3425+# CONFIG_PREEMPT_RCU_TRACE is not set
3426+CONFIG_IKCONFIG=y
3427+CONFIG_IKCONFIG_PROC=y
3428+CONFIG_LOG_BUF_SHIFT=17
3429+CONFIG_GROUP_SCHED=y
3430+CONFIG_FAIR_GROUP_SCHED=y
3431+# CONFIG_RT_GROUP_SCHED is not set
3432+CONFIG_USER_SCHED=y
3433+# CONFIG_CGROUP_SCHED is not set
3434+# CONFIG_CGROUPS is not set
3435+CONFIG_SYSFS_DEPRECATED=y
3436+CONFIG_SYSFS_DEPRECATED_V2=y
3437+# CONFIG_RELAY is not set
3438+CONFIG_NAMESPACES=y
3439+# CONFIG_UTS_NS is not set
3440+# CONFIG_IPC_NS is not set
3441+# CONFIG_USER_NS is not set
3442+# CONFIG_PID_NS is not set
3443+# CONFIG_NET_NS is not set
3444+# CONFIG_BLK_DEV_INITRD is not set
3445+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
3446+CONFIG_SYSCTL=y
3447+CONFIG_ANON_INODES=y
3448+# CONFIG_EMBEDDED is not set
3449+CONFIG_UID16=y
3450+CONFIG_SYSCTL_SYSCALL=y
3451+CONFIG_KALLSYMS=y
3452+# CONFIG_KALLSYMS_EXTRA_PASS is not set
3453+CONFIG_HOTPLUG=y
3454+CONFIG_PRINTK=y
3455+CONFIG_BUG=y
3456+CONFIG_ELF_CORE=y
3457+CONFIG_BASE_FULL=y
3458+CONFIG_FUTEX=y
3459+CONFIG_EPOLL=y
3460+CONFIG_SIGNALFD=y
3461+CONFIG_TIMERFD=y
3462+CONFIG_EVENTFD=y
3463+CONFIG_SHMEM=y
3464+CONFIG_AIO=y
3465+CONFIG_VM_EVENT_COUNTERS=y
3466+CONFIG_PCI_QUIRKS=y
3467+CONFIG_COMPAT_BRK=y
3468+CONFIG_SLAB=y
3469+# CONFIG_SLUB is not set
3470+# CONFIG_SLOB is not set
3471+# CONFIG_PROFILING is not set
3472+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
3473+CONFIG_SLABINFO=y
3474+CONFIG_RT_MUTEXES=y
3475+CONFIG_BASE_SMALL=0
3476+CONFIG_MODULES=y
3477+# CONFIG_MODULE_FORCE_LOAD is not set
3478+CONFIG_MODULE_UNLOAD=y
3479+CONFIG_MODULE_FORCE_UNLOAD=y
3480+# CONFIG_MODVERSIONS is not set
3481+# CONFIG_MODULE_SRCVERSION_ALL is not set
3482+CONFIG_BLOCK=y
3483+CONFIG_LBD=y
3484+# CONFIG_BLK_DEV_IO_TRACE is not set
3485+# CONFIG_BLK_DEV_BSG is not set
3486+# CONFIG_BLK_DEV_INTEGRITY is not set
3487+
3488+#
3489+# IO Schedulers
3490+#
3491+CONFIG_IOSCHED_NOOP=y
3492+CONFIG_IOSCHED_AS=y
3493+CONFIG_IOSCHED_DEADLINE=y
3494+CONFIG_IOSCHED_CFQ=y
3495+# CONFIG_DEFAULT_AS is not set
3496+# CONFIG_DEFAULT_DEADLINE is not set
3497+CONFIG_DEFAULT_CFQ=y
3498+# CONFIG_DEFAULT_NOOP is not set
3499+CONFIG_DEFAULT_IOSCHED="cfq"
3500+# CONFIG_FREEZER is not set
3501+
3502+#
3503+# Platform dependent setup
3504+#
3505+CONFIG_COLDFIRE=y
3506+CONFIG_CFV4E=y
3507+# CONFIG_FPU is not set
3508+CONFIG_MCD_DMA=y
3509+# CONFIG_AMIGA is not set
3510+# CONFIG_ATARI is not set
3511+CONFIG_PCI=y
3512+# CONFIG_MAC is not set
3513+# CONFIG_APOLLO is not set
3514+# CONFIG_VME is not set
3515+# CONFIG_HP300 is not set
3516+# CONFIG_SUN3X is not set
3517+# CONFIG_Q40 is not set
3518+# CONFIG_SUN3 is not set
3519+
3520+#
3521+# Processor type
3522+#
3523+# CONFIG_M68020 is not set
3524+# CONFIG_M68030 is not set
3525+# CONFIG_M68040 is not set
3526+# CONFIG_M68060 is not set
3527+# CONFIG_M5445X is not set
3528+# CONFIG_HAVE_FSL_USB_DR is not set
3529+CONFIG_M547X_8X=y
3530+# CONFIG_M547X is not set
3531+CONFIG_M548X=y
3532+# CONFIG_M5474LITE is not set
3533+# CONFIG_M5475AFE is not set
3534+# CONFIG_M5475BFE is not set
3535+# CONFIG_M5475CFE is not set
3536+# CONFIG_M5475DFE is not set
3537+# CONFIG_M5475EFE is not set
3538+# CONFIG_M5475FFE is not set
3539+# CONFIG_M5484LITE is not set
3540+# CONFIG_M5485AFE is not set
3541+# CONFIG_M5485BFE is not set
3542+CONFIG_M5485CFE=y
3543+# CONFIG_M5485DFE is not set
3544+# CONFIG_M5485EFE is not set
3545+# CONFIG_M5485FFE is not set
3546+# CONFIG_M5441X is not set
3547+CONFIG_MCFCLK=200000000
3548+# CONFIG_MCF_USER_HALT is not set
3549+CONFIG_MMU_CFV4E=y
3550+CONFIG_SDRAM_BASE=0x00000000
3551+CONFIG_SDRAM_SIZE=0x04000000
3552+CONFIG_NOR_FLASH_BASE=0xE0000000
3553+CONFIG_DMA_BASE=0xef000000
3554+CONFIG_DMA_SIZE=0x800000
3555+CONFIG_VDSO=y
3556+# CONFIG_M68KFPU_EMU is not set
3557+CONFIG_ADVANCED=y
3558+# CONFIG_RMW_INSNS is not set
3559+CONFIG_SINGLE_MEMORY_CHUNK=y
3560+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
3561+CONFIG_SELECT_MEMORY_MODEL=y
3562+CONFIG_FLATMEM_MANUAL=y
3563+# CONFIG_DISCONTIGMEM_MANUAL is not set
3564+# CONFIG_SPARSEMEM_MANUAL is not set
3565+CONFIG_FLATMEM=y
3566+CONFIG_FLAT_NODE_MEM_MAP=y
3567+CONFIG_NEED_MULTIPLE_NODES=y
3568+CONFIG_PAGEFLAGS_EXTENDED=y
3569+CONFIG_SPLIT_PTLOCK_CPUS=4
3570+# CONFIG_PHYS_ADDR_T_64BIT is not set
3571+CONFIG_ZONE_DMA_FLAG=1
3572+CONFIG_BOUNCE=y
3573+CONFIG_VIRT_TO_BUS=y
3574+CONFIG_UNEVICTABLE_LRU=y
3575+
3576+#
3577+# General setup
3578+#
3579+CONFIG_BINFMT_ELF=y
3580+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
3581+CONFIG_HAVE_AOUT=y
3582+# CONFIG_BINFMT_AOUT is not set
3583+# CONFIG_BINFMT_MISC is not set
3584+CONFIG_PROC_HARDWARE=y
3585+CONFIG_ZONE_DMA=y
3586+# CONFIG_ARCH_SUPPORTS_MSI is not set
3587+CONFIG_PCI_LEGACY=y
3588+# CONFIG_PCI_STUB is not set
3589+
3590+#
3591+# Power management options
3592+#
3593+CONFIG_PM=y
3594+CONFIG_NET=y
3595+
3596+#
3597+# Networking options
3598+#
3599+CONFIG_COMPAT_NET_DEV_OPS=y
3600+CONFIG_PACKET=y
3601+# CONFIG_PACKET_MMAP is not set
3602+CONFIG_UNIX=y
3603+CONFIG_XFRM=y
3604+# CONFIG_XFRM_USER is not set
3605+# CONFIG_XFRM_SUB_POLICY is not set
3606+# CONFIG_XFRM_MIGRATE is not set
3607+# CONFIG_XFRM_STATISTICS is not set
3608+CONFIG_NET_KEY=y
3609+# CONFIG_NET_KEY_MIGRATE is not set
3610+CONFIG_INET=y
3611+# CONFIG_IP_MULTICAST is not set
3612+CONFIG_IP_ADVANCED_ROUTER=y
3613+CONFIG_ASK_IP_FIB_HASH=y
3614+# CONFIG_IP_FIB_TRIE is not set
3615+CONFIG_IP_FIB_HASH=y
3616+# CONFIG_IP_MULTIPLE_TABLES is not set
3617+# CONFIG_IP_ROUTE_MULTIPATH is not set
3618+# CONFIG_IP_ROUTE_VERBOSE is not set
3619+CONFIG_IP_PNP=y
3620+# CONFIG_IP_PNP_DHCP is not set
3621+# CONFIG_IP_PNP_BOOTP is not set
3622+# CONFIG_IP_PNP_RARP is not set
3623+# CONFIG_NET_IPIP is not set
3624+# CONFIG_NET_IPGRE is not set
3625+# CONFIG_ARPD is not set
3626+# CONFIG_SYN_COOKIES is not set
3627+CONFIG_INET_AH=y
3628+CONFIG_INET_ESP=y
3629+# CONFIG_INET_IPCOMP is not set
3630+# CONFIG_INET_XFRM_TUNNEL is not set
3631+# CONFIG_INET_TUNNEL is not set
3632+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
3633+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
3634+# CONFIG_INET_XFRM_MODE_BEET is not set
3635+# CONFIG_INET_LRO is not set
3636+CONFIG_INET_DIAG=y
3637+CONFIG_INET_TCP_DIAG=y
3638+# CONFIG_TCP_CONG_ADVANCED is not set
3639+CONFIG_TCP_CONG_CUBIC=y
3640+CONFIG_DEFAULT_TCP_CONG="cubic"
3641+# CONFIG_TCP_MD5SIG is not set
3642+# CONFIG_IPV6 is not set
3643+# CONFIG_NETWORK_SECMARK is not set
3644+# CONFIG_NETFILTER is not set
3645+# CONFIG_IP_DCCP is not set
3646+# CONFIG_IP_SCTP is not set
3647+# CONFIG_TIPC is not set
3648+# CONFIG_ATM is not set
3649+# CONFIG_BRIDGE is not set
3650+# CONFIG_NET_DSA is not set
3651+# CONFIG_VLAN_8021Q is not set
3652+# CONFIG_DECNET is not set
3653+# CONFIG_LLC2 is not set
3654+# CONFIG_IPX is not set
3655+# CONFIG_ATALK is not set
3656+# CONFIG_X25 is not set
3657+# CONFIG_LAPB is not set
3658+# CONFIG_ECONET is not set
3659+# CONFIG_WAN_ROUTER is not set
3660+# CONFIG_NET_SCHED is not set
3661+# CONFIG_DCB is not set
3662+
3663+#
3664+# Network testing
3665+#
3666+# CONFIG_NET_PKTGEN is not set
3667+# CONFIG_HAMRADIO is not set
3668+CONFIG_CAN=y
3669+CONFIG_CAN_RAW=y
3670+# CONFIG_CAN_BCM is not set
3671+
3672+#
3673+# CAN Device Drivers
3674+#
3675+# CONFIG_CAN_VCAN is not set
3676+CONFIG_CAN_DEV=y
3677+CONFIG_CAN_CALC_BITTIMING=y
3678+CONFIG_CAN_FLEXCAN=y
3679+CONFIG_CAN_MCF=y
3680+# CONFIG_CAN_DEBUG_DEVICES is not set
3681+# CONFIG_IRDA is not set
3682+# CONFIG_BT is not set
3683+# CONFIG_AF_RXRPC is not set
3684+# CONFIG_PHONET is not set
3685+CONFIG_WIRELESS=y
3686+# CONFIG_CFG80211 is not set
3687+CONFIG_WIRELESS_OLD_REGULATORY=y
3688+# CONFIG_WIRELESS_EXT is not set
3689+# CONFIG_LIB80211 is not set
3690+# CONFIG_MAC80211 is not set
3691+# CONFIG_WIMAX is not set
3692+# CONFIG_RFKILL is not set
3693+# CONFIG_NET_9P is not set
3694+# CONFIG_KLIPS is not set
3695+
3696+#
3697+# Device Drivers
3698+#
3699+
3700+#
3701+# Generic Driver Options
3702+#
3703+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
3704+# CONFIG_STANDALONE is not set
3705+CONFIG_PREVENT_FIRMWARE_BUILD=y
3706+CONFIG_FW_LOADER=y
3707+CONFIG_FIRMWARE_IN_KERNEL=y
3708+CONFIG_EXTRA_FIRMWARE=""
3709+# CONFIG_SYS_HYPERVISOR is not set
3710+# CONFIG_CONNECTOR is not set
3711+CONFIG_MTD=y
3712+# CONFIG_MTD_DEBUG is not set
3713+CONFIG_MTD_CONCAT=y
3714+CONFIG_MTD_PARTITIONS=y
3715+# CONFIG_MTD_TESTS is not set
3716+# CONFIG_MTD_REDBOOT_PARTS is not set
3717+CONFIG_MTD_CMDLINE_PARTS=y
3718+# CONFIG_MTD_AR7_PARTS is not set
3719+
3720+#
3721+# User Modules And Translation Layers
3722+#
3723+CONFIG_MTD_CHAR=y
3724+CONFIG_MTD_BLKDEVS=y
3725+CONFIG_MTD_BLOCK=y
3726+# CONFIG_FTL is not set
3727+# CONFIG_NFTL is not set
3728+# CONFIG_INFTL is not set
3729+# CONFIG_RFD_FTL is not set
3730+# CONFIG_SSFDC is not set
3731+# CONFIG_MTD_OOPS is not set
3732+
3733+#
3734+# RAM/ROM/Flash chip drivers
3735+#
3736+CONFIG_MTD_CFI=y
3737+# CONFIG_MTD_JEDECPROBE is not set
3738+CONFIG_MTD_GEN_PROBE=y
3739+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
3740+CONFIG_MTD_MAP_BANK_WIDTH_1=y
3741+CONFIG_MTD_MAP_BANK_WIDTH_2=y
3742+CONFIG_MTD_MAP_BANK_WIDTH_4=y
3743+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
3744+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
3745+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
3746+CONFIG_MTD_CFI_I1=y
3747+CONFIG_MTD_CFI_I2=y
3748+# CONFIG_MTD_CFI_I4 is not set
3749+# CONFIG_MTD_CFI_I8 is not set
3750+CONFIG_MTD_CFI_INTELEXT=y
3751+CONFIG_MTD_CFI_AMDSTD=y
3752+# CONFIG_MTD_CFI_STAA is not set
3753+CONFIG_MTD_CFI_UTIL=y
3754+CONFIG_MTD_RAM=y
3755+CONFIG_MTD_ROM=y
3756+# CONFIG_MTD_ABSENT is not set
3757+
3758+#
3759+# Mapping drivers for chip access
3760+#
3761+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
3762+CONFIG_MTD_PHYSMAP=y
3763+CONFIG_MTD_PHYSMAP_COMPAT=y
3764+CONFIG_MTD_PHYSMAP_START=0xE0000000
3765+CONFIG_MTD_PHYSMAP_LEN=0x1000000
3766+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
3767+# CONFIG_MTD_INTEL_VR_NOR is not set
3768+# CONFIG_MTD_PLATRAM is not set
3769+
3770+#
3771+# Self-contained MTD device drivers
3772+#
3773+# CONFIG_MTD_PMC551 is not set
3774+# CONFIG_MTD_SLRAM is not set
3775+# CONFIG_MTD_PHRAM is not set
3776+# CONFIG_MTD_MTDRAM is not set
3777+# CONFIG_MTD_BLOCK2MTD is not set
3778+
3779+#
3780+# Disk-On-Chip Device Drivers
3781+#
3782+# CONFIG_MTD_DOC2000 is not set
3783+# CONFIG_MTD_DOC2001 is not set
3784+# CONFIG_MTD_DOC2001PLUS is not set
3785+# CONFIG_MTD_NAND is not set
3786+# CONFIG_MTD_ONENAND is not set
3787+
3788+#
3789+# LPDDR flash memory drivers
3790+#
3791+# CONFIG_MTD_LPDDR is not set
3792+
3793+#
3794+# UBI - Unsorted block images
3795+#
3796+# CONFIG_MTD_UBI is not set
3797+# CONFIG_PARPORT is not set
3798+CONFIG_BLK_DEV=y
3799+# CONFIG_BLK_CPQ_DA is not set
3800+# CONFIG_BLK_CPQ_CISS_DA is not set
3801+# CONFIG_BLK_DEV_DAC960 is not set
3802+# CONFIG_BLK_DEV_UMEM is not set
3803+# CONFIG_BLK_DEV_COW_COMMON is not set
3804+CONFIG_BLK_DEV_LOOP=y
3805+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
3806+# CONFIG_BLK_DEV_NBD is not set
3807+# CONFIG_BLK_DEV_SX8 is not set
3808+# CONFIG_BLK_DEV_UB is not set
3809+CONFIG_BLK_DEV_RAM=y
3810+CONFIG_BLK_DEV_RAM_COUNT=16
3811+CONFIG_BLK_DEV_RAM_SIZE=64000
3812+# CONFIG_BLK_DEV_XIP is not set
3813+# CONFIG_CDROM_PKTCDVD is not set
3814+# CONFIG_ATA_OVER_ETH is not set
3815+# CONFIG_BLK_DEV_HD is not set
3816+CONFIG_MISC_DEVICES=y
3817+# CONFIG_PHANTOM is not set
3818+# CONFIG_SGI_IOC4 is not set
3819+# CONFIG_TIFM_CORE is not set
3820+# CONFIG_ICS932S401 is not set
3821+# CONFIG_ENCLOSURE_SERVICES is not set
3822+# CONFIG_HP_ILO is not set
3823+# CONFIG_C2PORT is not set
3824+
3825+#
3826+# EEPROM support
3827+#
3828+# CONFIG_EEPROM_AT24 is not set
3829+# CONFIG_EEPROM_LEGACY is not set
3830+# CONFIG_EEPROM_93CX6 is not set
3831+CONFIG_HAVE_IDE=y
3832+CONFIG_IDE=y
3833+
3834+#
3835+# Please see Documentation/ide/ide.txt for help/info on IDE drives
3836+#
3837+# CONFIG_BLK_DEV_IDE_SATA is not set
3838+CONFIG_IDE_GD=y
3839+CONFIG_IDE_GD_ATA=y
3840+# CONFIG_IDE_GD_ATAPI is not set
3841+# CONFIG_BLK_DEV_IDECD is not set
3842+# CONFIG_BLK_DEV_IDETAPE is not set
3843+# CONFIG_IDE_TASK_IOCTL is not set
3844+CONFIG_IDE_PROC_FS=y
3845+
3846+#
3847+# IDE chipset support/bugfixes
3848+#
3849+# CONFIG_BLK_DEV_PLATFORM is not set
3850+
3851+#
3852+# PCI IDE chipsets support
3853+#
3854+# CONFIG_BLK_DEV_GENERIC is not set
3855+# CONFIG_BLK_DEV_OPTI621 is not set
3856+# CONFIG_BLK_DEV_AEC62XX is not set
3857+# CONFIG_BLK_DEV_ALI15X3 is not set
3858+# CONFIG_BLK_DEV_AMD74XX is not set
3859+# CONFIG_BLK_DEV_CMD64X is not set
3860+# CONFIG_BLK_DEV_TRIFLEX is not set
3861+# CONFIG_BLK_DEV_CS5520 is not set
3862+# CONFIG_BLK_DEV_CS5530 is not set
3863+# CONFIG_BLK_DEV_HPT366 is not set
3864+# CONFIG_BLK_DEV_JMICRON is not set
3865+# CONFIG_BLK_DEV_SC1200 is not set
3866+# CONFIG_BLK_DEV_PIIX is not set
3867+# CONFIG_BLK_DEV_IT8172 is not set
3868+# CONFIG_BLK_DEV_IT8213 is not set
3869+# CONFIG_BLK_DEV_IT821X is not set
3870+# CONFIG_BLK_DEV_NS87415 is not set
3871+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
3872+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
3873+# CONFIG_BLK_DEV_SVWKS is not set
3874+# CONFIG_BLK_DEV_SIIMAGE is not set
3875+# CONFIG_BLK_DEV_SLC90E66 is not set
3876+# CONFIG_BLK_DEV_TRM290 is not set
3877+# CONFIG_BLK_DEV_VIA82CXXX is not set
3878+# CONFIG_BLK_DEV_TC86C001 is not set
3879+# CONFIG_BLK_DEV_IDEDMA is not set
3880+
3881+#
3882+# SCSI device support
3883+#
3884+# CONFIG_RAID_ATTRS is not set
3885+CONFIG_SCSI=y
3886+CONFIG_SCSI_DMA=y
3887+# CONFIG_SCSI_TGT is not set
3888+# CONFIG_SCSI_NETLINK is not set
3889+CONFIG_SCSI_PROC_FS=y
3890+
3891+#
3892+# SCSI support type (disk, tape, CD-ROM)
3893+#
3894+CONFIG_BLK_DEV_SD=y
3895+# CONFIG_CHR_DEV_ST is not set
3896+# CONFIG_CHR_DEV_OSST is not set
3897+# CONFIG_BLK_DEV_SR is not set
3898+# CONFIG_CHR_DEV_SG is not set
3899+# CONFIG_CHR_DEV_SCH is not set
3900+
3901+#
3902+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
3903+#
3904+CONFIG_SCSI_MULTI_LUN=y
3905+# CONFIG_SCSI_CONSTANTS is not set
3906+# CONFIG_SCSI_LOGGING is not set
3907+# CONFIG_SCSI_SCAN_ASYNC is not set
3908+CONFIG_SCSI_WAIT_SCAN=m
3909+
3910+#
3911+# SCSI Transports
3912+#
3913+# CONFIG_SCSI_SPI_ATTRS is not set
3914+# CONFIG_SCSI_FC_ATTRS is not set
3915+# CONFIG_SCSI_ISCSI_ATTRS is not set
3916+# CONFIG_SCSI_SAS_LIBSAS is not set
3917+# CONFIG_SCSI_SRP_ATTRS is not set
3918+# CONFIG_SCSI_LOWLEVEL is not set
3919+# CONFIG_SCSI_DH is not set
3920+CONFIG_ATA=y
3921+# CONFIG_ATA_NONSTANDARD is not set
3922+CONFIG_SATA_PMP=y
3923+# CONFIG_SATA_AHCI is not set
3924+CONFIG_SATA_SIL24=y
3925+CONFIG_ATA_SFF=y
3926+# CONFIG_SATA_SVW is not set
3927+# CONFIG_ATA_PIIX is not set
3928+# CONFIG_SATA_MV is not set
3929+# CONFIG_SATA_NV is not set
3930+# CONFIG_PDC_ADMA is not set
3931+# CONFIG_SATA_QSTOR is not set
3932+# CONFIG_SATA_PROMISE is not set
3933+# CONFIG_SATA_SX4 is not set
3934+CONFIG_SATA_SIL=y
3935+# CONFIG_SATA_SIS is not set
3936+# CONFIG_SATA_ULI is not set
3937+# CONFIG_SATA_VIA is not set
3938+# CONFIG_SATA_VITESSE is not set
3939+# CONFIG_SATA_INIC162X is not set
3940+# CONFIG_PATA_ALI is not set
3941+# CONFIG_PATA_AMD is not set
3942+# CONFIG_PATA_ARTOP is not set
3943+# CONFIG_PATA_ATIIXP is not set
3944+# CONFIG_PATA_CMD640_PCI is not set
3945+# CONFIG_PATA_CMD64X is not set
3946+# CONFIG_PATA_CS5520 is not set
3947+# CONFIG_PATA_CS5530 is not set
3948+# CONFIG_PATA_CYPRESS is not set
3949+# CONFIG_PATA_EFAR is not set
3950+# CONFIG_ATA_GENERIC is not set
3951+# CONFIG_PATA_HPT366 is not set
3952+# CONFIG_PATA_HPT37X is not set
3953+# CONFIG_PATA_HPT3X2N is not set
3954+# CONFIG_PATA_HPT3X3 is not set
3955+# CONFIG_PATA_IT821X is not set
3956+# CONFIG_PATA_IT8213 is not set
3957+# CONFIG_PATA_JMICRON is not set
3958+# CONFIG_PATA_TRIFLEX is not set
3959+# CONFIG_PATA_MARVELL is not set
3960+# CONFIG_PATA_MPIIX is not set
3961+# CONFIG_PATA_OLDPIIX is not set
3962+# CONFIG_PATA_NETCELL is not set
3963+# CONFIG_PATA_NINJA32 is not set
3964+# CONFIG_PATA_NS87410 is not set
3965+# CONFIG_PATA_NS87415 is not set
3966+# CONFIG_PATA_OPTI is not set
3967+# CONFIG_PATA_OPTIDMA is not set
3968+# CONFIG_PATA_PDC_OLD is not set
3969+# CONFIG_PATA_RADISYS is not set
3970+# CONFIG_PATA_RZ1000 is not set
3971+# CONFIG_PATA_SC1200 is not set
3972+# CONFIG_PATA_SERVERWORKS is not set
3973+# CONFIG_PATA_PDC2027X is not set
3974+# CONFIG_PATA_SIL680 is not set
3975+# CONFIG_PATA_SIS is not set
3976+# CONFIG_PATA_VIA is not set
3977+# CONFIG_PATA_WINBOND is not set
3978+# CONFIG_PATA_SCH is not set
3979+# CONFIG_MD is not set
3980+# CONFIG_FUSION is not set
3981+
3982+#
3983+# IEEE 1394 (FireWire) support
3984+#
3985+
3986+#
3987+# Enable only one of the two stacks, unless you know what you are doing
3988+#
3989+# CONFIG_FIREWIRE is not set
3990+# CONFIG_IEEE1394 is not set
3991+# CONFIG_I2O is not set
3992+CONFIG_NETDEVICES=y
3993+# CONFIG_DUMMY is not set
3994+# CONFIG_BONDING is not set
3995+# CONFIG_MACVLAN is not set
3996+# CONFIG_EQUALIZER is not set
3997+# CONFIG_TUN is not set
3998+# CONFIG_VETH is not set
3999+# CONFIG_ARCNET is not set
4000+CONFIG_PHYLIB=y
4001+
4002+#
4003+# MII PHY device drivers
4004+#
4005+# CONFIG_MARVELL_PHY is not set
4006+# CONFIG_DAVICOM_PHY is not set
4007+# CONFIG_QSEMI_PHY is not set
4008+# CONFIG_LXT_PHY is not set
4009+# CONFIG_CICADA_PHY is not set
4010+# CONFIG_VITESSE_PHY is not set
4011+# CONFIG_SMSC_PHY is not set
4012+# CONFIG_BROADCOM_PHY is not set
4013+CONFIG_BROADCOM5222_PHY=y
4014+# CONFIG_ICPLUS_PHY is not set
4015+# CONFIG_REALTEK_PHY is not set
4016+# CONFIG_NATIONAL_PHY is not set
4017+# CONFIG_NATIONAL8364x_PHY is not set
4018+# CONFIG_NATIONAL8384x_PHY is not set
4019+# CONFIG_MicrelKSZ8041_PHY is not set
4020+# CONFIG_STE10XP is not set
4021+# CONFIG_LSI_ET1011C_PHY is not set
4022+# CONFIG_FIXED_PHY is not set
4023+# CONFIG_MDIO_BITBANG is not set
4024+CONFIG_NET_ETHERNET=y
4025+CONFIG_MII=y
4026+# CONFIG_HAPPYMEAL is not set
4027+# CONFIG_SUNGEM is not set
4028+# CONFIG_CASSINI is not set
4029+# CONFIG_NET_VENDOR_3COM is not set
4030+# CONFIG_DNET is not set
4031+# CONFIG_NET_TULIP is not set
4032+# CONFIG_HP100 is not set
4033+# CONFIG_IBM_NEW_EMAC_ZMII is not set
4034+# CONFIG_IBM_NEW_EMAC_RGMII is not set
4035+# CONFIG_IBM_NEW_EMAC_TAH is not set
4036+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
4037+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
4038+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
4039+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
4040+CONFIG_NET_PCI=y
4041+# CONFIG_PCNET32 is not set
4042+# CONFIG_AMD8111_ETH is not set
4043+# CONFIG_ADAPTEC_STARFIRE is not set
4044+# CONFIG_B44 is not set
4045+# CONFIG_FORCEDETH is not set
4046+CONFIG_E100=y
4047+# CONFIG_FEALNX is not set
4048+# CONFIG_NATSEMI is not set
4049+CONFIG_NE2K_PCI=y
4050+CONFIG_8139CP=y
4051+CONFIG_8139TOO=y
4052+CONFIG_8139TOO_PIO=y
4053+# CONFIG_8139TOO_TUNE_TWISTER is not set
4054+# CONFIG_8139TOO_8129 is not set
4055+# CONFIG_8139_OLD_RX_RESET is not set
4056+# CONFIG_R6040 is not set
4057+# CONFIG_SIS900 is not set
4058+# CONFIG_EPIC100 is not set
4059+# CONFIG_SMSC9420 is not set
4060+# CONFIG_SUNDANCE is not set
4061+# CONFIG_TLAN is not set
4062+# CONFIG_VIA_RHINE is not set
4063+# CONFIG_SC92031 is not set
4064+CONFIG_FEC_548x=y
4065+CONFIG_FEC_548x_ENABLE_FEC2=y
4066+CONFIG_FEC_548x_SHARED_PHY=y
4067+# CONFIG_ATL2 is not set
4068+CONFIG_NETDEV_1000=y
4069+# CONFIG_ACENIC is not set
4070+# CONFIG_DL2K is not set
4071+CONFIG_E1000=y
4072+# CONFIG_E1000E is not set
4073+# CONFIG_IP1000 is not set
4074+# CONFIG_IGB is not set
4075+# CONFIG_NS83820 is not set
4076+# CONFIG_HAMACHI is not set
4077+# CONFIG_YELLOWFIN is not set
4078+CONFIG_R8169=y
4079+# CONFIG_SIS190 is not set
4080+# CONFIG_SKGE is not set
4081+# CONFIG_SKY2 is not set
4082+# CONFIG_VIA_VELOCITY is not set
4083+# CONFIG_TIGON3 is not set
4084+# CONFIG_BNX2 is not set
4085+# CONFIG_QLA3XXX is not set
4086+# CONFIG_ATL1 is not set
4087+# CONFIG_ATL1E is not set
4088+# CONFIG_ATL1C is not set
4089+# CONFIG_JME is not set
4090+# CONFIG_NETDEV_10000 is not set
4091+# CONFIG_TR is not set
4092+
4093+#
4094+# Wireless LAN
4095+#
4096+# CONFIG_WLAN_PRE80211 is not set
4097+# CONFIG_WLAN_80211 is not set
4098+# CONFIG_IWLWIFI_LEDS is not set
4099+
4100+#
4101+# Enable WiMAX (Networking options) to see the WiMAX drivers
4102+#
4103+
4104+#
4105+# USB Network Adapters
4106+#
4107+# CONFIG_USB_CATC is not set
4108+# CONFIG_USB_KAWETH is not set
4109+# CONFIG_USB_PEGASUS is not set
4110+# CONFIG_USB_RTL8150 is not set
4111+# CONFIG_USB_USBNET is not set
4112+# CONFIG_WAN is not set
4113+# CONFIG_FDDI is not set
4114+# CONFIG_HIPPI is not set
4115+# CONFIG_PPP is not set
4116+# CONFIG_SLIP is not set
4117+# CONFIG_NET_FC is not set
4118+# CONFIG_NETCONSOLE is not set
4119+# CONFIG_NETPOLL is not set
4120+# CONFIG_NET_POLL_CONTROLLER is not set
4121+# CONFIG_ISDN is not set
4122+# CONFIG_PHONE is not set
4123+
4124+#
4125+# Input device support
4126+#
4127+CONFIG_INPUT=y
4128+# CONFIG_INPUT_FF_MEMLESS is not set
4129+# CONFIG_INPUT_POLLDEV is not set
4130+
4131+#
4132+# Userland interfaces
4133+#
4134+CONFIG_INPUT_MOUSEDEV=y
4135+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
4136+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
4137+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
4138+# CONFIG_INPUT_JOYDEV is not set
4139+CONFIG_INPUT_EVDEV=y
4140+# CONFIG_INPUT_EVBUG is not set
4141+
4142+#
4143+# Input Device Drivers
4144+#
4145+CONFIG_INPUT_KEYBOARD=y
4146+# CONFIG_KEYBOARD_ATKBD is not set
4147+# CONFIG_KEYBOARD_SUNKBD is not set
4148+# CONFIG_KEYBOARD_LKKBD is not set
4149+# CONFIG_KEYBOARD_XTKBD is not set
4150+# CONFIG_KEYBOARD_NEWTON is not set
4151+# CONFIG_KEYBOARD_STOWAWAY is not set
4152+# CONFIG_INPUT_MOUSE is not set
4153+# CONFIG_INPUT_JOYSTICK is not set
4154+# CONFIG_INPUT_TABLET is not set
4155+# CONFIG_INPUT_TOUCHSCREEN is not set
4156+# CONFIG_INPUT_MISC is not set
4157+
4158+#
4159+# Hardware I/O ports
4160+#
4161+CONFIG_SERIO=y
4162+CONFIG_SERIO_SERPORT=y
4163+# CONFIG_SERIO_PCIPS2 is not set
4164+# CONFIG_SERIO_RAW is not set
4165+# CONFIG_GAMEPORT is not set
4166+
4167+#
4168+# Character devices
4169+#
4170+CONFIG_VT=y
4171+CONFIG_CONSOLE_TRANSLATIONS=y
4172+CONFIG_VT_CONSOLE=y
4173+CONFIG_HW_CONSOLE=y
4174+# CONFIG_VT_HW_CONSOLE_BINDING is not set
4175+CONFIG_DEVKMEM=y
4176+# CONFIG_SERIAL_NONSTANDARD is not set
4177+# CONFIG_NOZOMI is not set
4178+
4179+#
4180+# Serial drivers
4181+#
4182+# CONFIG_SERIAL_8250 is not set
4183+
4184+#
4185+# Non-8250 serial port support
4186+#
4187+CONFIG_SERIAL_CORE=y
4188+CONFIG_SERIAL_CORE_CONSOLE=y
4189+# CONFIG_SERIAL_COLDFIRE_IRDA is not set
4190+# CONFIG_SERIAL_COLDFIRE_EDMA is not set
4191+CONFIG_SERIAL_MCF=y
4192+CONFIG_SERIAL_MCF_BAUDRATE=115200
4193+CONFIG_SERIAL_MCF_CONSOLE=y
4194+# CONFIG_SERIAL_JSM is not set
4195+CONFIG_UNIX98_PTYS=y
4196+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
4197+# CONFIG_LEGACY_PTYS is not set
4198+# CONFIG_IPMI_HANDLER is not set
4199+# CONFIG_HW_RANDOM is not set
4200+# CONFIG_R3964 is not set
4201+# CONFIG_APPLICOM is not set
4202+# CONFIG_RAW_DRIVER is not set
4203+# CONFIG_TCG_TPM is not set
4204+CONFIG_I2C=y
4205+CONFIG_I2C_BOARDINFO=y
4206+CONFIG_I2C_CHARDEV=y
4207+CONFIG_I2C_HELPER_AUTO=y
4208+
4209+#
4210+# I2C Hardware Bus support
4211+#
4212+
4213+#
4214+# PC SMBus host controller drivers
4215+#
4216+# CONFIG_I2C_ALI1535 is not set
4217+# CONFIG_I2C_ALI1563 is not set
4218+# CONFIG_I2C_ALI15X3 is not set
4219+# CONFIG_I2C_AMD756 is not set
4220+# CONFIG_I2C_AMD8111 is not set
4221+# CONFIG_I2C_I801 is not set
4222+# CONFIG_I2C_ISCH is not set
4223+# CONFIG_I2C_PIIX4 is not set
4224+# CONFIG_I2C_NFORCE2 is not set
4225+# CONFIG_I2C_SIS5595 is not set
4226+# CONFIG_I2C_SIS630 is not set
4227+# CONFIG_I2C_SIS96X is not set
4228+# CONFIG_I2C_VIA is not set
4229+# CONFIG_I2C_VIAPRO is not set
4230+
4231+#
4232+# I2C system bus drivers (mostly embedded / system-on-chip)
4233+#
4234+CONFIG_I2C_MCF=y
4235+# CONFIG_I2C_OCORES is not set
4236+# CONFIG_I2C_SIMTEC is not set
4237+
4238+#
4239+# External I2C/SMBus adapter drivers
4240+#
4241+# CONFIG_I2C_PARPORT_LIGHT is not set
4242+# CONFIG_I2C_TAOS_EVM is not set
4243+# CONFIG_I2C_TINY_USB is not set
4244+
4245+#
4246+# Graphics adapter I2C/DDC channel drivers
4247+#
4248+# CONFIG_I2C_VOODOO3 is not set
4249+
4250+#
4251+# Other I2C/SMBus bus drivers
4252+#
4253+# CONFIG_I2C_PCA_PLATFORM is not set
4254+# CONFIG_I2C_STUB is not set
4255+
4256+#
4257+# Miscellaneous I2C Chip support
4258+#
4259+# CONFIG_DS1682 is not set
4260+# CONFIG_SENSORS_PCF8574 is not set
4261+# CONFIG_PCF8575 is not set
4262+# CONFIG_SENSORS_PCA9539 is not set
4263+# CONFIG_SENSORS_PCF8591 is not set
4264+# CONFIG_SENSORS_MAX6875 is not set
4265+# CONFIG_SENSORS_TSL2550 is not set
4266+# CONFIG_I2C_DEBUG_CORE is not set
4267+# CONFIG_I2C_DEBUG_ALGO is not set
4268+# CONFIG_I2C_DEBUG_BUS is not set
4269+# CONFIG_I2C_DEBUG_CHIP is not set
4270+# CONFIG_SPI is not set
4271+# CONFIG_W1 is not set
4272+# CONFIG_POWER_SUPPLY is not set
4273+# CONFIG_HWMON is not set
4274+# CONFIG_THERMAL is not set
4275+# CONFIG_THERMAL_HWMON is not set
4276+CONFIG_WATCHDOG=y
4277+# CONFIG_WATCHDOG_NOWAYOUT is not set
4278+
4279+#
4280+# Watchdog Device Drivers
4281+#
4282+# CONFIG_SOFT_WATCHDOG is not set
4283+# CONFIG_ALIM7101_WDT is not set
4284+CONFIG_COLDFIRE_WATCHDOG=y
4285+
4286+#
4287+# PCI-based Watchdog Cards
4288+#
4289+# CONFIG_PCIPCWATCHDOG is not set
4290+# CONFIG_WDTPCI is not set
4291+
4292+#
4293+# USB-based Watchdog Cards
4294+#
4295+# CONFIG_USBPCWATCHDOG is not set
4296+CONFIG_SSB_POSSIBLE=y
4297+
4298+#
4299+# Sonics Silicon Backplane
4300+#
4301+# CONFIG_SSB is not set
4302+
4303+#
4304+# Multifunction device drivers
4305+#
4306+# CONFIG_MFD_CORE is not set
4307+# CONFIG_MFD_SM501 is not set
4308+# CONFIG_HTC_PASIC3 is not set
4309+# CONFIG_MFD_TMIO is not set
4310+# CONFIG_PMIC_DA903X is not set
4311+# CONFIG_MFD_WM8400 is not set
4312+# CONFIG_MFD_WM8350_I2C is not set
4313+# CONFIG_MFD_PCF50633 is not set
4314+# CONFIG_REGULATOR is not set
4315+
4316+#
4317+# Multimedia devices
4318+#
4319+
4320+#
4321+# Multimedia core support
4322+#
4323+# CONFIG_VIDEO_DEV is not set
4324+# CONFIG_DVB_CORE is not set
4325+# CONFIG_VIDEO_MEDIA is not set
4326+
4327+#
4328+# Multimedia drivers
4329+#
4330+CONFIG_DAB=y
4331+# CONFIG_USB_DABUSB is not set
4332+
4333+#
4334+# Graphics support
4335+#
4336+# CONFIG_DRM is not set
4337+# CONFIG_VGASTATE is not set
4338+CONFIG_VIDEO_OUTPUT_CONTROL=m
4339+CONFIG_FB=y
4340+# CONFIG_FIRMWARE_EDID is not set
4341+# CONFIG_FB_DDC is not set
4342+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
4343+CONFIG_FB_CFB_FILLRECT=y
4344+CONFIG_FB_CFB_COPYAREA=y
4345+CONFIG_FB_CFB_IMAGEBLIT=y
4346+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
4347+# CONFIG_FB_SYS_FILLRECT is not set
4348+# CONFIG_FB_SYS_COPYAREA is not set
4349+# CONFIG_FB_SYS_IMAGEBLIT is not set
4350+# CONFIG_FB_FOREIGN_ENDIAN is not set
4351+# CONFIG_FB_SYS_FOPS is not set
4352+CONFIG_FB_DEFERRED_IO=y
4353+# CONFIG_FB_SVGALIB is not set
4354+# CONFIG_FB_MACMODES is not set
4355+# CONFIG_FB_BACKLIGHT is not set
4356+# CONFIG_FB_MODE_HELPERS is not set
4357+# CONFIG_FB_TILEBLITTING is not set
4358+
4359+#
4360+# Frame buffer hardware drivers
4361+#
4362+CONFIG_FB_SMI=y
4363+# CONFIG_FB_CIRRUS is not set
4364+# CONFIG_FB_PM2 is not set
4365+# CONFIG_FB_CYBER2000 is not set
4366+# CONFIG_FB_ASILIANT is not set
4367+# CONFIG_FB_IMSTT is not set
4368+# CONFIG_FB_S1D13XXX is not set
4369+# CONFIG_FB_NVIDIA is not set
4370+# CONFIG_FB_RIVA is not set
4371+# CONFIG_FB_MATROX is not set
4372+# CONFIG_FB_RADEON is not set
4373+# CONFIG_FB_ATY128 is not set
4374+# CONFIG_FB_ATY is not set
4375+# CONFIG_FB_S3 is not set
4376+# CONFIG_FB_SAVAGE is not set
4377+# CONFIG_FB_SIS is not set
4378+# CONFIG_FB_VIA is not set
4379+# CONFIG_FB_NEOMAGIC is not set
4380+# CONFIG_FB_KYRO is not set
4381+# CONFIG_FB_3DFX is not set
4382+# CONFIG_FB_VOODOO1 is not set
4383+# CONFIG_FB_VT8623 is not set
4384+# CONFIG_FB_TRIDENT is not set
4385+# CONFIG_FB_ARK is not set
4386+# CONFIG_FB_PM3 is not set
4387+# CONFIG_FB_CARMINE is not set
4388+# CONFIG_FB_VIRTUAL is not set
4389+# CONFIG_FB_METRONOME is not set
4390+# CONFIG_FB_MB862XX is not set
4391+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
4392+
4393+#
4394+# Display device support
4395+#
4396+# CONFIG_DISPLAY_SUPPORT is not set
4397+
4398+#
4399+# Console display driver support
4400+#
4401+CONFIG_DUMMY_CONSOLE=y
4402+CONFIG_FRAMEBUFFER_CONSOLE=y
4403+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
4404+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
4405+CONFIG_FONTS=y
4406+CONFIG_FONT_8x8=y
4407+CONFIG_FONT_8x16=y
4408+CONFIG_FONT_6x11=y
4409+# CONFIG_FONT_7x14 is not set
4410+CONFIG_FONT_PEARL_8x8=y
4411+CONFIG_FONT_ACORN_8x8=y
4412+CONFIG_FONT_MINI_4x6=y
4413+CONFIG_FONT_SUN8x16=y
4414+CONFIG_FONT_SUN12x22=y
4415+CONFIG_FONT_10x18=y
4416+CONFIG_LOGO=y
4417+CONFIG_LOGO_LINUX_MONO=y
4418+CONFIG_LOGO_LINUX_VGA16=y
4419+CONFIG_LOGO_LINUX_CLUT224=y
4420+# CONFIG_SOUND is not set
4421+CONFIG_HID_SUPPORT=y
4422+CONFIG_HID=y
4423+CONFIG_HID_DEBUG=y
4424+# CONFIG_HIDRAW is not set
4425+
4426+#
4427+# USB Input Devices
4428+#
4429+CONFIG_USB_HID=y
4430+# CONFIG_HID_PID is not set
4431+# CONFIG_USB_HIDDEV is not set
4432+
4433+#
4434+# Special HID drivers
4435+#
4436+CONFIG_HID_COMPAT=y
4437+CONFIG_HID_A4TECH=y
4438+CONFIG_HID_APPLE=y
4439+CONFIG_HID_BELKIN=y
4440+CONFIG_HID_CHERRY=y
4441+CONFIG_HID_CHICONY=y
4442+CONFIG_HID_CYPRESS=y
4443+CONFIG_HID_EZKEY=y
4444+CONFIG_HID_GYRATION=y
4445+CONFIG_HID_LOGITECH=y
4446+# CONFIG_LOGITECH_FF is not set
4447+# CONFIG_LOGIRUMBLEPAD2_FF is not set
4448+CONFIG_HID_MICROSOFT=y
4449+CONFIG_HID_MONTEREY=y
4450+CONFIG_HID_NTRIG=y
4451+CONFIG_HID_PANTHERLORD=y
4452+# CONFIG_PANTHERLORD_FF is not set
4453+CONFIG_HID_PETALYNX=y
4454+CONFIG_HID_SAMSUNG=y
4455+CONFIG_HID_SONY=y
4456+CONFIG_HID_SUNPLUS=y
4457+# CONFIG_GREENASIA_FF is not set
4458+CONFIG_HID_TOPSEED=y
4459+# CONFIG_THRUSTMASTER_FF is not set
4460+# CONFIG_ZEROPLUS_FF is not set
4461+CONFIG_USB_SUPPORT=y
4462+CONFIG_USB_ARCH_HAS_HCD=y
4463+CONFIG_USB_ARCH_HAS_OHCI=y
4464+CONFIG_USB_ARCH_HAS_EHCI=y
4465+CONFIG_USB=y
4466+# CONFIG_USB_DEBUG is not set
4467+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
4468+
4469+#
4470+# Miscellaneous USB options
4471+#
4472+CONFIG_USB_DEVICEFS=y
4473+# CONFIG_USB_DEVICE_CLASS is not set
4474+# CONFIG_USB_DYNAMIC_MINORS is not set
4475+# CONFIG_USB_SUSPEND is not set
4476+# CONFIG_USB_OTG is not set
4477+CONFIG_USB_MON=y
4478+# CONFIG_USB_WUSB is not set
4479+# CONFIG_USB_WUSB_CBAF is not set
4480+
4481+#
4482+# USB Host Controller Drivers
4483+#
4484+# CONFIG_USB_C67X00_HCD is not set
4485+CONFIG_USB_EHCI_HCD=y
4486+CONFIG_USB_EHCI_ROOT_HUB_TT=y
4487+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
4488+# CONFIG_USB_OXU210HP_HCD is not set
4489+# CONFIG_USB_ISP116X_HCD is not set
4490+# CONFIG_USB_ISP1760_HCD is not set
4491+# CONFIG_USB_OHCI_HCD is not set
4492+# CONFIG_USB_UHCI_HCD is not set
4493+# CONFIG_USB_SL811_HCD is not set
4494+# CONFIG_USB_R8A66597_HCD is not set
4495+# CONFIG_USB_WHCI_HCD is not set
4496+# CONFIG_USB_HWA_HCD is not set
4497+
4498+#
4499+# USB Device Class drivers
4500+#
4501+# CONFIG_USB_ACM is not set
4502+# CONFIG_USB_PRINTER is not set
4503+# CONFIG_USB_WDM is not set
4504+# CONFIG_USB_TMC is not set
4505+
4506+#
4507+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
4508+#
4509+
4510+#
4511+# see USB_STORAGE Help for more information
4512+#
4513+CONFIG_USB_STORAGE=y
4514+# CONFIG_USB_STORAGE_DEBUG is not set
4515+# CONFIG_USB_STORAGE_DATAFAB is not set
4516+# CONFIG_USB_STORAGE_FREECOM is not set
4517+# CONFIG_USB_STORAGE_ISD200 is not set
4518+# CONFIG_USB_STORAGE_USBAT is not set
4519+# CONFIG_USB_STORAGE_SDDR09 is not set
4520+# CONFIG_USB_STORAGE_SDDR55 is not set
4521+# CONFIG_USB_STORAGE_JUMPSHOT is not set
4522+# CONFIG_USB_STORAGE_ALAUDA is not set
4523+# CONFIG_USB_STORAGE_ONETOUCH is not set
4524+# CONFIG_USB_STORAGE_KARMA is not set
4525+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
4526+# CONFIG_USB_LIBUSUAL is not set
4527+
4528+#
4529+# USB Imaging devices
4530+#
4531+# CONFIG_USB_MDC800 is not set
4532+# CONFIG_USB_MICROTEK is not set
4533+
4534+#
4535+# USB port drivers
4536+#
4537+# CONFIG_USB_SERIAL is not set
4538+
4539+#
4540+# USB Miscellaneous drivers
4541+#
4542+# CONFIG_USB_EMI62 is not set
4543+# CONFIG_USB_EMI26 is not set
4544+# CONFIG_USB_ADUTUX is not set
4545+# CONFIG_USB_SEVSEG is not set
4546+# CONFIG_USB_RIO500 is not set
4547+# CONFIG_USB_LEGOTOWER is not set
4548+# CONFIG_USB_LCD is not set
4549+# CONFIG_USB_BERRY_CHARGE is not set
4550+# CONFIG_USB_LED is not set
4551+# CONFIG_USB_CYPRESS_CY7C63 is not set
4552+# CONFIG_USB_CYTHERM is not set
4553+# CONFIG_USB_PHIDGET is not set
4554+# CONFIG_USB_IDMOUSE is not set
4555+# CONFIG_USB_FTDI_ELAN is not set
4556+# CONFIG_USB_APPLEDISPLAY is not set
4557+# CONFIG_USB_SISUSBVGA is not set
4558+# CONFIG_USB_LD is not set
4559+# CONFIG_USB_TRANCEVIBRATOR is not set
4560+# CONFIG_USB_IOWARRIOR is not set
4561+# CONFIG_USB_TEST is not set
4562+# CONFIG_USB_ISIGHTFW is not set
4563+# CONFIG_USB_VST is not set
4564+# CONFIG_USB_GADGET is not set
4565+
4566+#
4567+# OTG and related infrastructure
4568+#
4569+# CONFIG_UWB is not set
4570+# CONFIG_MMC is not set
4571+# CONFIG_MEMSTICK is not set
4572+# CONFIG_NEW_LEDS is not set
4573+# CONFIG_ACCESSIBILITY is not set
4574+# CONFIG_INFINIBAND is not set
4575+CONFIG_RTC_LIB=y
4576+CONFIG_RTC_CLASS=y
4577+CONFIG_RTC_HCTOSYS=y
4578+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
4579+# CONFIG_RTC_DEBUG is not set
4580+
4581+#
4582+# RTC interfaces
4583+#
4584+CONFIG_RTC_INTF_SYSFS=y
4585+CONFIG_RTC_INTF_PROC=y
4586+CONFIG_RTC_INTF_DEV=y
4587+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
4588+# CONFIG_RTC_DRV_TEST is not set
4589+
4590+#
4591+# I2C RTC drivers
4592+#
4593+# CONFIG_RTC_DRV_DS1307 is not set
4594+# CONFIG_RTC_DRV_DS1374 is not set
4595+# CONFIG_RTC_DRV_DS1672 is not set
4596+# CONFIG_RTC_DRV_MAX6900 is not set
4597+CONFIG_RTC_DRV_RS5C372=y
4598+# CONFIG_RTC_DRV_ISL1208 is not set
4599+# CONFIG_RTC_DRV_X1205 is not set
4600+# CONFIG_RTC_DRV_PCF8563 is not set
4601+# CONFIG_RTC_DRV_PCF8583 is not set
4602+# CONFIG_RTC_DRV_M41T80 is not set
4603+# CONFIG_RTC_DRV_S35390A is not set
4604+# CONFIG_RTC_DRV_FM3130 is not set
4605+# CONFIG_RTC_DRV_RX8581 is not set
4606+
4607+#
4608+# SPI RTC drivers
4609+#
4610+
4611+#
4612+# Platform RTC drivers
4613+#
4614+# CONFIG_RTC_DRV_DS1286 is not set
4615+# CONFIG_RTC_DRV_DS1511 is not set
4616+# CONFIG_RTC_DRV_DS1553 is not set
4617+# CONFIG_RTC_DRV_DS1742 is not set
4618+# CONFIG_RTC_DRV_STK17TA8 is not set
4619+# CONFIG_RTC_DRV_M48T86 is not set
4620+# CONFIG_RTC_DRV_M48T35 is not set
4621+# CONFIG_RTC_DRV_M48T59 is not set
4622+# CONFIG_RTC_DRV_BQ4802 is not set
4623+# CONFIG_RTC_DRV_V3020 is not set
4624+
4625+#
4626+# on-CPU RTC drivers
4627+#
4628+# CONFIG_RTC_MCF is not set
4629+# CONFIG_RTC_M5441X is not set
4630+# CONFIG_DMADEVICES is not set
4631+# CONFIG_UIO is not set
4632+# CONFIG_STAGING is not set
4633+
4634+#
4635+# Character devices
4636+#
4637+CONFIG_TICK_ONESHOT=y
4638+CONFIG_NO_HZ=y
4639+CONFIG_HIGH_RES_TIMERS=y
4640+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
4641+
4642+#
4643+# File systems
4644+#
4645+CONFIG_EXT2_FS=y
4646+# CONFIG_EXT2_FS_XATTR is not set
4647+# CONFIG_EXT2_FS_XIP is not set
4648+CONFIG_EXT3_FS=y
4649+CONFIG_EXT3_FS_XATTR=y
4650+# CONFIG_EXT3_FS_POSIX_ACL is not set
4651+# CONFIG_EXT3_FS_SECURITY is not set
4652+# CONFIG_EXT4_FS is not set
4653+CONFIG_JBD=y
4654+CONFIG_FS_MBCACHE=y
4655+# CONFIG_REISERFS_FS is not set
4656+# CONFIG_JFS_FS is not set
4657+# CONFIG_FS_POSIX_ACL is not set
4658+CONFIG_FILE_LOCKING=y
4659+# CONFIG_XFS_FS is not set
4660+# CONFIG_GFS2_FS is not set
4661+# CONFIG_OCFS2_FS is not set
4662+# CONFIG_BTRFS_FS is not set
4663+CONFIG_DNOTIFY=y
4664+# CONFIG_INOTIFY is not set
4665+# CONFIG_QUOTA is not set
4666+# CONFIG_AUTOFS_FS is not set
4667+# CONFIG_AUTOFS4_FS is not set
4668+# CONFIG_FUSE_FS is not set
4669+
4670+#
4671+# CD-ROM/DVD Filesystems
4672+#
4673+# CONFIG_ISO9660_FS is not set
4674+# CONFIG_UDF_FS is not set
4675+
4676+#
4677+# DOS/FAT/NT Filesystems
4678+#
4679+CONFIG_FAT_FS=y
4680+CONFIG_MSDOS_FS=y
4681+CONFIG_VFAT_FS=y
4682+CONFIG_FAT_DEFAULT_CODEPAGE=437
4683+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
4684+CONFIG_NTFS_FS=y
4685+# CONFIG_NTFS_DEBUG is not set
4686+CONFIG_NTFS_RW=y
4687+
4688+#
4689+# Pseudo filesystems
4690+#
4691+CONFIG_PROC_FS=y
4692+# CONFIG_PROC_KCORE is not set
4693+CONFIG_PROC_SYSCTL=y
4694+CONFIG_PROC_PAGE_MONITOR=y
4695+CONFIG_SYSFS=y
4696+CONFIG_TMPFS=y
4697+# CONFIG_TMPFS_POSIX_ACL is not set
4698+# CONFIG_HUGETLB_PAGE is not set
4699+# CONFIG_CONFIGFS_FS is not set
4700+CONFIG_MISC_FILESYSTEMS=y
4701+# CONFIG_ADFS_FS is not set
4702+# CONFIG_AFFS_FS is not set
4703+# CONFIG_HFS_FS is not set
4704+# CONFIG_HFSPLUS_FS is not set
4705+# CONFIG_BEFS_FS is not set
4706+# CONFIG_BFS_FS is not set
4707+# CONFIG_EFS_FS is not set
4708+CONFIG_JFFS2_FS=y
4709+CONFIG_JFFS2_FS_DEBUG=0
4710+CONFIG_JFFS2_FS_WRITEBUFFER=y
4711+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
4712+# CONFIG_JFFS2_SUMMARY is not set
4713+# CONFIG_JFFS2_FS_XATTR is not set
4714+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
4715+CONFIG_JFFS2_ZLIB=y
4716+# CONFIG_JFFS2_LZO is not set
4717+CONFIG_JFFS2_RTIME=y
4718+# CONFIG_JFFS2_RUBIN is not set
4719+# CONFIG_CRAMFS is not set
4720+# CONFIG_SQUASHFS is not set
4721+# CONFIG_VXFS_FS is not set
4722+CONFIG_MINIX_FS=y
4723+# CONFIG_OMFS_FS is not set
4724+# CONFIG_HPFS_FS is not set
4725+# CONFIG_QNX4FS_FS is not set
4726+CONFIG_ROMFS_FS=y
4727+# CONFIG_SYSV_FS is not set
4728+# CONFIG_UFS_FS is not set
4729+CONFIG_NETWORK_FILESYSTEMS=y
4730+CONFIG_NFS_FS=y
4731+# CONFIG_NFS_V3 is not set
4732+# CONFIG_NFS_V4 is not set
4733+CONFIG_ROOT_NFS=y
4734+# CONFIG_NFSD is not set
4735+CONFIG_LOCKD=y
4736+CONFIG_NFS_COMMON=y
4737+CONFIG_SUNRPC=y
4738+# CONFIG_SUNRPC_REGISTER_V4 is not set
4739+# CONFIG_RPCSEC_GSS_KRB5 is not set
4740+# CONFIG_RPCSEC_GSS_SPKM3 is not set
4741+# CONFIG_SMB_FS is not set
4742+# CONFIG_CIFS is not set
4743+# CONFIG_NCP_FS is not set
4744+# CONFIG_CODA_FS is not set
4745+# CONFIG_AFS_FS is not set
4746+
4747+#
4748+# Partition Types
4749+#
4750+CONFIG_PARTITION_ADVANCED=y
4751+# CONFIG_ACORN_PARTITION is not set
4752+# CONFIG_OSF_PARTITION is not set
4753+# CONFIG_AMIGA_PARTITION is not set
4754+# CONFIG_ATARI_PARTITION is not set
4755+# CONFIG_MAC_PARTITION is not set
4756+CONFIG_MSDOS_PARTITION=y
4757+# CONFIG_BSD_DISKLABEL is not set
4758+# CONFIG_MINIX_SUBPARTITION is not set
4759+# CONFIG_SOLARIS_X86_PARTITION is not set
4760+# CONFIG_UNIXWARE_DISKLABEL is not set
4761+# CONFIG_LDM_PARTITION is not set
4762+# CONFIG_SGI_PARTITION is not set
4763+# CONFIG_ULTRIX_PARTITION is not set
4764+# CONFIG_SUN_PARTITION is not set
4765+# CONFIG_KARMA_PARTITION is not set
4766+# CONFIG_EFI_PARTITION is not set
4767+# CONFIG_SYSV68_PARTITION is not set
4768+CONFIG_NLS=y
4769+CONFIG_NLS_DEFAULT="iso8859-1"
4770+CONFIG_NLS_CODEPAGE_437=y
4771+# CONFIG_NLS_CODEPAGE_737 is not set
4772+# CONFIG_NLS_CODEPAGE_775 is not set
4773+# CONFIG_NLS_CODEPAGE_850 is not set
4774+# CONFIG_NLS_CODEPAGE_852 is not set
4775+# CONFIG_NLS_CODEPAGE_855 is not set
4776+# CONFIG_NLS_CODEPAGE_857 is not set
4777+# CONFIG_NLS_CODEPAGE_860 is not set
4778+# CONFIG_NLS_CODEPAGE_861 is not set
4779+# CONFIG_NLS_CODEPAGE_862 is not set
4780+# CONFIG_NLS_CODEPAGE_863 is not set
4781+# CONFIG_NLS_CODEPAGE_864 is not set
4782+# CONFIG_NLS_CODEPAGE_865 is not set
4783+# CONFIG_NLS_CODEPAGE_866 is not set
4784+# CONFIG_NLS_CODEPAGE_869 is not set
4785+# CONFIG_NLS_CODEPAGE_936 is not set
4786+# CONFIG_NLS_CODEPAGE_950 is not set
4787+# CONFIG_NLS_CODEPAGE_932 is not set
4788+# CONFIG_NLS_CODEPAGE_949 is not set
4789+# CONFIG_NLS_CODEPAGE_874 is not set
4790+# CONFIG_NLS_ISO8859_8 is not set
4791+# CONFIG_NLS_CODEPAGE_1250 is not set
4792+# CONFIG_NLS_CODEPAGE_1251 is not set
4793+# CONFIG_NLS_ASCII is not set
4794+CONFIG_NLS_ISO8859_1=y
4795+# CONFIG_NLS_ISO8859_2 is not set
4796+# CONFIG_NLS_ISO8859_3 is not set
4797+# CONFIG_NLS_ISO8859_4 is not set
4798+# CONFIG_NLS_ISO8859_5 is not set
4799+# CONFIG_NLS_ISO8859_6 is not set
4800+# CONFIG_NLS_ISO8859_7 is not set
4801+# CONFIG_NLS_ISO8859_9 is not set
4802+# CONFIG_NLS_ISO8859_13 is not set
4803+# CONFIG_NLS_ISO8859_14 is not set
4804+# CONFIG_NLS_ISO8859_15 is not set
4805+# CONFIG_NLS_KOI8_R is not set
4806+# CONFIG_NLS_KOI8_U is not set
4807+CONFIG_NLS_UTF8=y
4808+# CONFIG_DLM is not set
4809+
4810+#
4811+# Kernel hacking
4812+#
4813+# CONFIG_PRINTK_TIME is not set
4814+CONFIG_ENABLE_WARN_DEPRECATED=y
4815+# CONFIG_ENABLE_MUST_CHECK is not set
4816+CONFIG_FRAME_WARN=1024
4817+# CONFIG_MAGIC_SYSRQ is not set
4818+# CONFIG_UNUSED_SYMBOLS is not set
4819+# CONFIG_DEBUG_FS is not set
4820+# CONFIG_HEADERS_CHECK is not set
4821+# CONFIG_DEBUG_KERNEL is not set
4822+CONFIG_DEBUG_BUGVERBOSE=y
4823+CONFIG_DEBUG_MEMORY_INIT=y
4824+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
4825+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
4826+
4827+#
4828+# Tracers
4829+#
4830+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
4831+# CONFIG_SAMPLES is not set
4832+# CONFIG_BOOTPARAM is not set
4833+
4834+#
4835+# Security options
4836+#
4837+# CONFIG_KEYS is not set
4838+# CONFIG_SECURITY is not set
4839+# CONFIG_SECURITYFS is not set
4840+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
4841+CONFIG_CRYPTO=y
4842+
4843+#
4844+# Crypto core or helper
4845+#
4846+# CONFIG_CRYPTO_FIPS is not set
4847+CONFIG_CRYPTO_ALGAPI=y
4848+CONFIG_CRYPTO_ALGAPI2=y
4849+CONFIG_CRYPTO_AEAD=y
4850+CONFIG_CRYPTO_AEAD2=y
4851+CONFIG_CRYPTO_BLKCIPHER=y
4852+CONFIG_CRYPTO_BLKCIPHER2=y
4853+CONFIG_CRYPTO_HASH=y
4854+CONFIG_CRYPTO_HASH2=y
4855+CONFIG_CRYPTO_RNG2=y
4856+CONFIG_CRYPTO_MANAGER=y
4857+CONFIG_CRYPTO_MANAGER2=y
4858+# CONFIG_CRYPTO_GF128MUL is not set
4859+# CONFIG_CRYPTO_NULL is not set
4860+# CONFIG_CRYPTO_CRYPTD is not set
4861+CONFIG_CRYPTO_AUTHENC=y
4862+CONFIG_CRYPTO_TEST=m
4863+
4864+#
4865+# Authenticated Encryption with Associated Data
4866+#
4867+# CONFIG_CRYPTO_CCM is not set
4868+# CONFIG_CRYPTO_GCM is not set
4869+# CONFIG_CRYPTO_SEQIV is not set
4870+
4871+#
4872+# Block modes
4873+#
4874+CONFIG_CRYPTO_CBC=y
4875+# CONFIG_CRYPTO_CTR is not set
4876+# CONFIG_CRYPTO_CTS is not set
4877+# CONFIG_CRYPTO_ECB is not set
4878+# CONFIG_CRYPTO_LRW is not set
4879+# CONFIG_CRYPTO_PCBC is not set
4880+# CONFIG_CRYPTO_XTS is not set
4881+
4882+#
4883+# Hash modes
4884+#
4885+CONFIG_CRYPTO_HMAC=y
4886+# CONFIG_CRYPTO_XCBC is not set
4887+
4888+#
4889+# Digest
4890+#
4891+CONFIG_CRYPTO_CRC32C=y
4892+# CONFIG_CRYPTO_MD4 is not set
4893+CONFIG_CRYPTO_MD5=y
4894+# CONFIG_CRYPTO_MICHAEL_MIC is not set
4895+# CONFIG_CRYPTO_RMD128 is not set
4896+# CONFIG_CRYPTO_RMD160 is not set
4897+# CONFIG_CRYPTO_RMD256 is not set
4898+# CONFIG_CRYPTO_RMD320 is not set
4899+CONFIG_CRYPTO_SHA1=y
4900+# CONFIG_CRYPTO_SHA256 is not set
4901+# CONFIG_CRYPTO_SHA512 is not set
4902+# CONFIG_CRYPTO_TGR192 is not set
4903+# CONFIG_CRYPTO_WP512 is not set
4904+
4905+#
4906+# Ciphers
4907+#
4908+# CONFIG_CRYPTO_AES is not set
4909+# CONFIG_CRYPTO_ANUBIS is not set
4910+# CONFIG_CRYPTO_ARC4 is not set
4911+# CONFIG_CRYPTO_BLOWFISH is not set
4912+# CONFIG_CRYPTO_CAMELLIA is not set
4913+# CONFIG_CRYPTO_CAST5 is not set
4914+# CONFIG_CRYPTO_CAST6 is not set
4915+CONFIG_CRYPTO_DES=y
4916+# CONFIG_CRYPTO_FCRYPT is not set
4917+# CONFIG_CRYPTO_KHAZAD is not set
4918+# CONFIG_CRYPTO_SALSA20 is not set
4919+# CONFIG_CRYPTO_SEED is not set
4920+# CONFIG_CRYPTO_SERPENT is not set
4921+# CONFIG_CRYPTO_TEA is not set
4922+# CONFIG_CRYPTO_TWOFISH is not set
4923+
4924+#
4925+# Compression
4926+#
4927+# CONFIG_CRYPTO_DEFLATE is not set
4928+# CONFIG_CRYPTO_LZO is not set
4929+
4930+#
4931+# Random Number Generation
4932+#
4933+# CONFIG_CRYPTO_ANSI_CPRNG is not set
4934+
4935+#
4936+# OCF Configuration
4937+#
4938+# CONFIG_OCF_OCF is not set
4939+
4940+#
4941+# Talitos Driver
4942+#
4943+# CONFIG_CRYPTO_HW is not set
4944+
4945+#
4946+# Library routines
4947+#
4948+CONFIG_BITREVERSE=y
4949+CONFIG_GENERIC_FIND_LAST_BIT=y
4950+CONFIG_CRC_CCITT=y
4951+CONFIG_CRC16=y
4952+# CONFIG_CRC_T10DIF is not set
4953+# CONFIG_CRC_ITU_T is not set
4954+CONFIG_CRC32=y
4955+# CONFIG_CRC7 is not set
4956+CONFIG_LIBCRC32C=y
4957+CONFIG_ZLIB_INFLATE=y
4958+CONFIG_ZLIB_DEFLATE=y
4959+CONFIG_PLIST=y
4960+CONFIG_HAS_IOMEM=y
4961+CONFIG_HAS_IOPORT=y
4962+CONFIG_HAS_DMA=y
4963--- /dev/null
4964+++ b/arch/m68k/include/asm/cf_548x_cacheflush.h
4965@@ -0,0 +1,262 @@
4966+/*
4967+ * arch/m68k/include/asm/cf_548x_cacheflush.h - Coldfire 547x/548x Cache
4968+ *
4969+ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
4970+ * Kurt Mahan kmahan@freescale.com
4971+ * Shrek Wu b16972@freescale.com
4972+ *
4973+ * Based on include/asm-m68k/cacheflush.h
4974+ *
4975+ * This program is free software; you can redistribute it and/or modify it
4976+ * under the terms of the GNU General Public License as published by the
4977+ * Free Software Foundation; either version 2 of the License, or (at your
4978+ * option) any later version.
4979+ */
4980+#ifndef M68K_CF_548x_CACHEFLUSH_H
4981+#define M68K_CF_548x_CACHEFLUSH_H
4982+
4983+#include <asm/cfcache.h>
4984+/*
4985+ * Cache handling functions
4986+ */
4987+
4988+#define flush_icache() \
4989+({ \
4990+ unsigned long set; \
4991+ unsigned long start_set; \
4992+ unsigned long end_set; \
4993+ \
4994+ start_set = 0; \
4995+ end_set = (unsigned long)LAST_DCACHE_ADDR; \
4996+ \
4997+ for (set = start_set; set <= end_set; set += (0x10 - 3)) {\
4998+ asm volatile("cpushl %%ic,(%0)\n" \
4999+ "\taddq%.l #1,%0\n" \
5000+ "\tcpushl %%ic,(%0)\n" \
5001+ "\taddq%.l #1,%0\n" \
5002+ "\tcpushl %%ic,(%0)\n" \
5003+ "\taddq%.l #1,%0\n" \
5004+ "\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set)); \
5005+ } \
5006+})
5007+
5008+#define flush_dcache() \
5009+({ \
5010+ unsigned long set; \
5011+ unsigned long start_set; \
5012+ unsigned long end_set; \
5013+ \
5014+ start_set = 0; \
5015+ end_set = (unsigned long)LAST_DCACHE_ADDR; \
5016+ \
5017+ for (set = start_set; set <= end_set; set += (0x10 - 3)) { \
5018+ asm volatile("cpushl %%dc,(%0)\n" \
5019+ "\taddq%.l #1,%0\n" \
5020+ "\tcpushl %%dc,(%0)\n" \
5021+ "\taddq%.l #1,%0\n" \
5022+ "\tcpushl %%dc,(%0)\n" \
5023+ "\taddq%.l #1,%0\n" \
5024+ "\tcpushl %%dc,(%0)" : "=a" (set) : "a" (set)); \
5025+ } \
5026+})
5027+
5028+#define flush_bcache() \
5029+({ \
5030+ unsigned long set; \
5031+ unsigned long start_set; \
5032+ unsigned long end_set; \
5033+ \
5034+ start_set = 0; \
5035+ end_set = (unsigned long)LAST_DCACHE_ADDR; \
5036+ \
5037+ for (set = start_set; set <= end_set; set += (0x10 - 3)) { \
5038+ asm volatile("cpushl %%bc,(%0)\n" \
5039+ "\taddq%.l #1,%0\n" \
5040+ "\tcpushl %%bc,(%0)\n" \
5041+ "\taddq%.l #1,%0\n" \
5042+ "\tcpushl %%bc,(%0)\n" \
5043+ "\taddq%.l #1,%0\n" \
5044+ "\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set)); \
5045+ } \
5046+})
5047+
5048+/*
5049+ * invalidate the cache for the specified memory range.
5050+ * It starts at the physical address specified for
5051+ * the given number of bytes.
5052+ */
5053+extern void cache_clear(unsigned long paddr, int len);
5054+/*
5055+ * push any dirty cache in the specified memory range.
5056+ * It starts at the physical address specified for
5057+ * the given number of bytes.
5058+ */
5059+extern void cache_push(unsigned long paddr, int len);
5060+
5061+/*
5062+ * push and invalidate pages in the specified user virtual
5063+ * memory range.
5064+ */
5065+extern void cache_push_v(unsigned long vaddr, int len);
5066+
5067+/* This is needed whenever the virtual mapping of the current
5068+ process changes. */
5069+
5070+/**
5071+ * flush_cache_mm - Flush an mm_struct
5072+ * @mm: mm_struct to flush
5073+ */
5074+static inline void flush_cache_mm(struct mm_struct *mm)
5075+{
5076+ if (mm == current->mm)
5077+ flush_bcache();
5078+}
5079+
5080+#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
5081+
5082+#define flush_cache_all() flush_bcache()
5083+
5084+/**
5085+ * flush_cache_range - Flush a cache range
5086+ * @vma: vma struct
5087+ * @start: Starting address
5088+ * @end: Ending address
5089+ *
5090+ * flush_cache_range must be a macro to avoid a dependency on
5091+ * linux/mm.h which includes this file.
5092+ */
5093+static inline void flush_cache_range(struct vm_area_struct *vma,
5094+ unsigned long start, unsigned long end)
5095+{
5096+ if (vma->vm_mm == current->mm)
5097+ flush_bcache();
5098+/*cf_cache_flush_range(start, end);*/
5099+}
5100+
5101+/**
5102+ * flush_cache_page - Flush a page of the cache
5103+ * @vma: vma struct
5104+ * @vmaddr:
5105+ * @pfn: page numer
5106+ *
5107+ * flush_cache_page must be a macro to avoid a dependency on
5108+ * linux/mm.h which includes this file.
5109+ */
5110+static inline void flush_cache_page(struct vm_area_struct *vma,
5111+ unsigned long vmaddr, unsigned long pfn)
5112+{
5113+ if (vma->vm_mm == current->mm)
5114+ flush_bcache();
5115+/*cf_cache_flush_range(vmaddr, vmaddr+PAGE_SIZE);*/
5116+}
5117+
5118+/* Push the page at kernel virtual address and clear the icache */
5119+/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
5120+#define flush_page_to_ram(page) __flush_page_to_ram((void *) page_address(page))
5121+extern inline void __flush_page_to_ram(void *address)
5122+{
5123+ unsigned long set;
5124+ unsigned long start_set;
5125+ unsigned long end_set;
5126+ unsigned long addr = (unsigned long) address;
5127+
5128+ addr &= ~(PAGE_SIZE - 1);
5129+ /* round down to page start address */
5130+
5131+ start_set = addr & _ICACHE_SET_MASK;
5132+ end_set = (addr + PAGE_SIZE-1) & _ICACHE_SET_MASK;
5133+
5134+ if (start_set > end_set) {
5135+ /* from the begining to the lowest address */
5136+ for (set = 0; set <= end_set; set += (0x10 - 3)) {
5137+ asm volatile("cpushl %%bc,(%0)\n"
5138+ "\taddq%.l #1,%0\n"
5139+ "\tcpushl %%bc,(%0)\n"
5140+ "\taddq%.l #1,%0\n"
5141+ "\tcpushl %%bc,(%0)\n"
5142+ "\taddq%.l #1,%0\n"
5143+ "\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set));
5144+ }
5145+ /* next loop will finish the cache ie pass the hole */
5146+ end_set = LAST_ICACHE_ADDR;
5147+ }
5148+
5149+ for (set = start_set; set <= end_set; set += (0x10 - 3)) {
5150+ asm volatile("cpushl %%bc,(%0)\n"
5151+ "\taddq%.l #1,%0\n"
5152+ "\tcpushl %%bc,(%0)\n"
5153+ "\taddq%.l #1,%0\n"
5154+ "\tcpushl %%bc,(%0)\n"
5155+ "\taddq%.l #1,%0\n"
5156+ "\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set));
5157+ }
5158+}
5159+
5160+/* Use __flush_page_to_ram() for flush_dcache_page all values are same - MW */
5161+#define flush_dcache_page(page) \
5162+ __flush_page_to_ram((void *) page_address(page))
5163+#define flush_icache_page(vma, pg) \
5164+ __flush_page_to_ram((void *) page_address(pg))
5165+#define flush_icache_user_range(adr, len) \
5166+ do { } while (0)
5167+/* NL */
5168+#define flush_icache_user_page(vma, page, addr, len) \
5169+ do { } while (0)
5170+
5171+/* Push n pages at kernel virtual address and clear the icache */
5172+/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
5173+extern inline void flush_icache_range(unsigned long address,
5174+ unsigned long endaddr)
5175+{
5176+ unsigned long set;
5177+ unsigned long start_set;
5178+ unsigned long end_set;
5179+
5180+ start_set = address & _ICACHE_SET_MASK;
5181+ end_set = endaddr & _ICACHE_SET_MASK;
5182+
5183+ if (start_set > end_set) {
5184+ /* from the begining to the lowest address */
5185+ for (set = 0; set <= end_set; set += (0x10 - 3)) {
5186+ asm volatile("cpushl %%ic,(%0)\n"
5187+ "\taddq%.l #1,%0\n"
5188+ "\tcpushl %%ic,(%0)\n"
5189+ "\taddq%.l #1,%0\n"
5190+ "\tcpushl %%ic,(%0)\n"
5191+ "\taddq%.l #1,%0\n"
5192+ "\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set));
5193+ }
5194+ /* next loop will finish the cache ie pass the hole */
5195+ end_set = LAST_ICACHE_ADDR;
5196+ }
5197+ for (set = start_set; set <= end_set; set += (0x10 - 3)) {
5198+ asm volatile("cpushl %%ic,(%0)\n"
5199+ "\taddq%.l #1,%0\n"
5200+ "\tcpushl %%ic,(%0)\n"
5201+ "\taddq%.l #1,%0\n"
5202+ "\tcpushl %%ic,(%0)\n"
5203+ "\taddq%.l #1,%0\n"
5204+ "\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set));
5205+ }
5206+}
5207+
5208+static inline void copy_to_user_page(struct vm_area_struct *vma,
5209+ struct page *page, unsigned long vaddr,
5210+ void *dst, void *src, int len)
5211+{
5212+ memcpy(dst, src, len);
5213+ flush_icache_user_page(vma, page, vaddr, len);
5214+}
5215+static inline void copy_from_user_page(struct vm_area_struct *vma,
5216+ struct page *page, unsigned long vaddr,
5217+ void *dst, void *src, int len)
5218+{
5219+ memcpy(dst, src, len);
5220+}
5221+
5222+#define flush_cache_vmap(start, end) flush_cache_all()
5223+#define flush_cache_vunmap(start, end) flush_cache_all()
5224+#define flush_dcache_mmap_lock(mapping) do { } while (0)
5225+#define flush_dcache_mmap_unlock(mapping) do { } while (0)
5226+
5227+#endif /* M68K_CF_548x_CACHEFLUSH_H */
5228--- /dev/null
5229+++ b/arch/m68k/include/asm/m5485dma.h
5230@@ -0,0 +1,98 @@
5231+/*
5232+ * m5485dma.h -- ColdFire 547x/548x DMA controller support.
5233+ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
5234+ */
5235+#ifndef __MCF548X_DMA_H__
5236+#define __MCF548X_DMA_H__
5237+
5238+
5239+/* Register read/write macros */
5240+#define MCF_DMA_DIPR MCF_REG32(0x008014)
5241+#define MCF_DMA_DIMR MCF_REG32(0x008018)
5242+#define MCF_DMA_IMCR MCF_REG32(0x00805C)
5243+
5244+/* Bit definitions and macros for MCF_DMA_DIPR */
5245+#define MCF_DMA_DIPR_TASK0 (0x00000001)
5246+#define MCF_DMA_DIPR_TASK1 (0x00000002)
5247+#define MCF_DMA_DIPR_TASK2 (0x00000004)
5248+#define MCF_DMA_DIPR_TASK3 (0x00000008)
5249+#define MCF_DMA_DIPR_TASK4 (0x00000010)
5250+#define MCF_DMA_DIPR_TASK5 (0x00000020)
5251+#define MCF_DMA_DIPR_TASK6 (0x00000040)
5252+#define MCF_DMA_DIPR_TASK7 (0x00000080)
5253+#define MCF_DMA_DIPR_TASK8 (0x00000100)
5254+#define MCF_DMA_DIPR_TASK9 (0x00000200)
5255+#define MCF_DMA_DIPR_TASK10 (0x00000400)
5256+#define MCF_DMA_DIPR_TASK11 (0x00000800)
5257+#define MCF_DMA_DIPR_TASK12 (0x00001000)
5258+#define MCF_DMA_DIPR_TASK13 (0x00002000)
5259+#define MCF_DMA_DIPR_TASK14 (0x00004000)
5260+#define MCF_DMA_DIPR_TASK15 (0x00008000)
5261+
5262+/* Bit definitions and macros for MCF_DMA_DIMR */
5263+#define MCF_DMA_DIMR_TASK0 (0x00000001)
5264+#define MCF_DMA_DIMR_TASK1 (0x00000002)
5265+#define MCF_DMA_DIMR_TASK2 (0x00000004)
5266+#define MCF_DMA_DIMR_TASK3 (0x00000008)
5267+#define MCF_DMA_DIMR_TASK4 (0x00000010)
5268+#define MCF_DMA_DIMR_TASK5 (0x00000020)
5269+#define MCF_DMA_DIMR_TASK6 (0x00000040)
5270+#define MCF_DMA_DIMR_TASK7 (0x00000080)
5271+#define MCF_DMA_DIMR_TASK8 (0x00000100)
5272+#define MCF_DMA_DIMR_TASK9 (0x00000200)
5273+#define MCF_DMA_DIMR_TASK10 (0x00000400)
5274+#define MCF_DMA_DIMR_TASK11 (0x00000800)
5275+#define MCF_DMA_DIMR_TASK12 (0x00001000)
5276+#define MCF_DMA_DIMR_TASK13 (0x00002000)
5277+#define MCF_DMA_DIMR_TASK14 (0x00004000)
5278+#define MCF_DMA_DIMR_TASK15 (0x00008000)
5279+
5280+/* Bit definitions and macros for MCF_DMA_IMCR */
5281+#define MCF_DMA_IMCR_SRC16(x) (((x)&0x00000003)<<0)
5282+#define MCF_DMA_IMCR_SRC17(x) (((x)&0x00000003)<<2)
5283+#define MCF_DMA_IMCR_SRC18(x) (((x)&0x00000003)<<4)
5284+#define MCF_DMA_IMCR_SRC19(x) (((x)&0x00000003)<<6)
5285+#define MCF_DMA_IMCR_SRC20(x) (((x)&0x00000003)<<8)
5286+#define MCF_DMA_IMCR_SRC21(x) (((x)&0x00000003)<<10)
5287+#define MCF_DMA_IMCR_SRC22(x) (((x)&0x00000003)<<12)
5288+#define MCF_DMA_IMCR_SRC23(x) (((x)&0x00000003)<<14)
5289+#define MCF_DMA_IMCR_SRC24(x) (((x)&0x00000003)<<16)
5290+#define MCF_DMA_IMCR_SRC25(x) (((x)&0x00000003)<<18)
5291+#define MCF_DMA_IMCR_SRC26(x) (((x)&0x00000003)<<20)
5292+#define MCF_DMA_IMCR_SRC27(x) (((x)&0x00000003)<<22)
5293+#define MCF_DMA_IMCR_SRC28(x) (((x)&0x00000003)<<24)
5294+#define MCF_DMA_IMCR_SRC29(x) (((x)&0x00000003)<<26)
5295+#define MCF_DMA_IMCR_SRC30(x) (((x)&0x00000003)<<28)
5296+#define MCF_DMA_IMCR_SRC31(x) (((x)&0x00000003)<<30)
5297+#define MCF_DMA_IMCR_SRC16_FEC0RX (0x00000000)
5298+#define MCF_DMA_IMCR_SRC17_FEC0TX (0x00000000)
5299+#define MCF_DMA_IMCR_SRC18_FEC0RX (0x00000020)
5300+#define MCF_DMA_IMCR_SRC19_FEC0TX (0x00000080)
5301+#define MCF_DMA_IMCR_SRC20_FEC1RX (0x00000100)
5302+#define MCF_DMA_IMCR_SRC21_DREQ1 (0x00000000)
5303+#define MCF_DMA_IMCR_SRC21_FEC1TX (0x00000400)
5304+#define MCF_DMA_IMCR_SRC22_FEC0RX (0x00001000)
5305+#define MCF_DMA_IMCR_SRC23_FEC0TX (0x00004000)
5306+#define MCF_DMA_IMCR_SRC24_CTM0 (0x00010000)
5307+#define MCF_DMA_IMCR_SRC24_FEC1RX (0x00020000)
5308+#define MCF_DMA_IMCR_SRC25_CTM1 (0x00040000)
5309+#define MCF_DMA_IMCR_SRC25_FEC1TX (0x00080000)
5310+#define MCF_DMA_IMCR_SRC26_USBEP4 (0x00000000)
5311+#define MCF_DMA_IMCR_SRC26_CTM2 (0x00200000)
5312+#define MCF_DMA_IMCR_SRC27_USBEP5 (0x00000000)
5313+#define MCF_DMA_IMCR_SRC27_CTM3 (0x00800000)
5314+#define MCF_DMA_IMCR_SRC28_USBEP6 (0x00000000)
5315+#define MCF_DMA_IMCR_SRC28_CTM4 (0x01000000)
5316+#define MCF_DMA_IMCR_SRC28_DREQ1 (0x02000000)
5317+#define MCF_DMA_IMCR_SRC28_PSC2RX (0x03000000)
5318+#define MCF_DMA_IMCR_SRC29_DREQ1 (0x04000000)
5319+#define MCF_DMA_IMCR_SRC29_CTM5 (0x08000000)
5320+#define MCF_DMA_IMCR_SRC29_PSC2TX (0x0C000000)
5321+#define MCF_DMA_IMCR_SRC30_FEC1RX (0x00000000)
5322+#define MCF_DMA_IMCR_SRC30_CTM6 (0x10000000)
5323+#define MCF_DMA_IMCR_SRC30_PSC3RX (0x30000000)
5324+#define MCF_DMA_IMCR_SRC31_FEC1TX (0x00000000)
5325+#define MCF_DMA_IMCR_SRC31_CTM7 (0x80000000)
5326+#define MCF_DMA_IMCR_SRC31_PSC3TX (0xC0000000)
5327+
5328+#endif /* __MCF548X_DMA_H__ */
5329--- /dev/null
5330+++ b/arch/m68k/include/asm/m5485dspi.h
5331@@ -0,0 +1,146 @@
5332+/*
5333+ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
5334+ *
5335+ * File: mcf548x_dspi.h
5336+ * Purpose: Register and bit definitions for the MCF548X
5337+ *
5338+ * Notes:
5339+ *
5340+ */
5341+
5342+#ifndef _M5485DSPI_H_
5343+#define _M5485DSPI_H_
5344+
5345+/*
5346+ *
5347+ * DMA Serial Peripheral Interface (DSPI)
5348+ *
5349+ */
5350+
5351+/* Register read/write macros */
5352+#define MCF_DSPI_DMCR MCF_REG32(0x008A00)
5353+#define MCF_DSPI_DTCR MCF_REG32(0x008A08)
5354+#define MCF_DSPI_DCTAR0 MCF_REG32(0x008A0C)
5355+#define MCF_DSPI_DCTAR1 MCF_REG32(0x008A10)
5356+#define MCF_DSPI_DCTAR2 MCF_REG32(0x008A14)
5357+#define MCF_DSPI_DCTAR3 MCF_REG32(0x008A18)
5358+#define MCF_DSPI_DCTAR4 MCF_REG32(0x008A1C)
5359+#define MCF_DSPI_DCTAR5 MCF_REG32(0x008A20)
5360+#define MCF_DSPI_DCTAR6 MCF_REG32(0x008A24)
5361+#define MCF_DSPI_DCTAR7 MCF_REG32(0x008A28)
5362+#define MCF_DSPI_DCTARn(x) MCF_REG32(0x008A0C+(x*4))
5363+#define MCF_DSPI_DSR MCF_REG32(0x008A2C)
5364+#define MCF_DSPI_DRSER MCF_REG32(0x008A30)
5365+#define MCF_DSPI_DTFR MCF_REG32(0x008A34)
5366+#define MCF_DSPI_DRFR MCF_REG32(0x008A38)
5367+#define MCF_DSPI_DTFDR0 MCF_REG32(0x008A3C)
5368+#define MCF_DSPI_DTFDR1 MCF_REG32(0x008A40)
5369+#define MCF_DSPI_DTFDR2 MCF_REG32(0x008A44)
5370+#define MCF_DSPI_DTFDR3 MCF_REG32(0x008A48)
5371+#define MCF_DSPI_DTFDRn(x) MCF_REG32(0x008A3C+(x*4))
5372+#define MCF_DSPI_DRFDR0 MCF_REG32(0x008A7C)
5373+#define MCF_DSPI_DRFDR1 MCF_REG32(0x008A80)
5374+#define MCF_DSPI_DRFDR2 MCF_REG32(0x008A84)
5375+#define MCF_DSPI_DRFDR3 MCF_REG32(0x008A88)
5376+#define MCF_DSPI_DRFDRn(x) MCF_REG32(0x008A7C+(x*4))
5377+
5378+/* Bit definitions and macros for MCF_DSPI_DMCR */
5379+#define MCF_DSPI_DMCR_HALT (0x00000001)
5380+#define MCF_DSPI_DMCR_SMPL_PT(x) (((x)&0x00000003)<<8)
5381+#define MCF_DSPI_DMCR_CRXF (0x00000400)
5382+#define MCF_DSPI_DMCR_CTXF (0x00000800)
5383+#define MCF_DSPI_DMCR_DRXF (0x00001000)
5384+#define MCF_DSPI_DMCR_DTXF (0x00002000)
5385+#define MCF_DSPI_DMCR_CSIS0 (0x00010000)
5386+#define MCF_DSPI_DMCR_CSIS2 (0x00040000)
5387+#define MCF_DSPI_DMCR_CSIS3 (0x00080000)
5388+#define MCF_DSPI_DMCR_CSIS5 (0x00200000)
5389+#define MCF_DSPI_DMCR_ROOE (0x01000000)
5390+#define MCF_DSPI_DMCR_PCSSE (0x02000000)
5391+#define MCF_DSPI_DMCR_MTFE (0x04000000)
5392+#define MCF_DSPI_DMCR_FRZ (0x08000000)
5393+#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28)
5394+#define MCF_DSPI_DMCR_CSCK (0x40000000)
5395+#define MCF_DSPI_DMCR_MSTR (0x80000000)
5396+
5397+/* Bit definitions and macros for MCF_DSPI_DTCR */
5398+#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16)
5399+
5400+/* Bit definitions and macros for MCF_DSPI_DCTARn */
5401+#define MCF_DSPI_DCTAR_BR(x) (((x)&0x0000000F)<<0)
5402+#define MCF_DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4)
5403+#define MCF_DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8)
5404+#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12)
5405+#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16)
5406+#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18)
5407+#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20)
5408+#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22)
5409+#define MCF_DSPI_DCTAR_LSBFE (0x01000000)
5410+#define MCF_DSPI_DCTAR_CPHA (0x02000000)
5411+#define MCF_DSPI_DCTAR_CPOL (0x04000000)
5412+/* #define MCF_DSPI_DCTAR_TRSZ(x) (((x)&0x0000000F)<<27) */
5413+#define MCF_DSPI_DCTAR_FMSZ(x) (((x)&0x0000000F)<<27)
5414+#define MCF_DSPI_DCTAR_PCSSCK_1CLK (0x00000000)
5415+#define MCF_DSPI_DCTAR_PCSSCK_3CLK (0x00400000)
5416+#define MCF_DSPI_DCTAR_PCSSCK_5CLK (0x00800000)
5417+#define MCF_DSPI_DCTAR_PCSSCK_7CLK (0x00A00000)
5418+#define MCF_DSPI_DCTAR_PASC_1CLK (0x00000000)
5419+#define MCF_DSPI_DCTAR_PASC_3CLK (0x00100000)
5420+#define MCF_DSPI_DCTAR_PASC_5CLK (0x00200000)
5421+#define MCF_DSPI_DCTAR_PASC_7CLK (0x00300000)
5422+#define MCF_DSPI_DCTAR_PDT_1CLK (0x00000000)
5423+#define MCF_DSPI_DCTAR_PDT_3CLK (0x00040000)
5424+#define MCF_DSPI_DCTAR_PDT_5CLK (0x00080000)
5425+#define MCF_DSPI_DCTAR_PDT_7CLK (0x000A0000)
5426+#define MCF_DSPI_DCTAR_PBR_1CLK (0x00000000)
5427+#define MCF_DSPI_DCTAR_PBR_3CLK (0x00010000)
5428+#define MCF_DSPI_DCTAR_PBR_5CLK (0x00020000)
5429+#define MCF_DSPI_DCTAR_PBR_7CLK (0x00030000)
5430+
5431+/* Bit definitions and macros for MCF_DSPI_DSR */
5432+#define MCF_DSPI_DSR_RXPTR(x) (((x)&0x0000000F)<<0)
5433+#define MCF_DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4)
5434+#define MCF_DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8)
5435+#define MCF_DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12)
5436+#define MCF_DSPI_DSR_RFDF (0x00020000)
5437+#define MCF_DSPI_DSR_RFOF (0x00080000)
5438+#define MCF_DSPI_DSR_TFFF (0x02000000)
5439+#define MCF_DSPI_DSR_TFUF (0x08000000)
5440+#define MCF_DSPI_DSR_EOQF (0x10000000)
5441+#define MCF_DSPI_DSR_TXRXS (0x40000000)
5442+#define MCF_DSPI_DSR_TCF (0x80000000)
5443+
5444+/* Bit definitions and macros for MCF_DSPI_DRSER */
5445+#define MCF_DSPI_DRSER_RFDFS (0x00010000)
5446+#define MCF_DSPI_DRSER_RFDFE (0x00020000)
5447+#define MCF_DSPI_DRSER_RFOFE (0x00080000)
5448+#define MCF_DSPI_DRSER_TFFFS (0x01000000)
5449+#define MCF_DSPI_DRSER_TFFFE (0x02000000)
5450+#define MCF_DSPI_DRSER_TFUFE (0x08000000)
5451+#define MCF_DSPI_DRSER_EOQFE (0x10000000)
5452+#define MCF_DSPI_DRSER_TCFE (0x80000000)
5453+
5454+/* Bit definitions and macros for MCF_DSPI_DTFR */
5455+#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF)<<0)
5456+#define MCF_DSPI_DTFR_CS0 (0x00010000)
5457+#define MCF_DSPI_DTFR_CS2 (0x00040000)
5458+#define MCF_DSPI_DTFR_CS3 (0x00080000)
5459+#define MCF_DSPI_DTFR_CS5 (0x00200000)
5460+#define MCF_DSPI_DTFR_CTCNT (0x04000000)
5461+#define MCF_DSPI_DTFR_EOQ (0x08000000)
5462+#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28)
5463+#define MCF_DSPI_DTFR_CONT (0x80000000)
5464+
5465+/* Bit definitions and macros for MCF_DSPI_DRFR */
5466+#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF)<<0)
5467+
5468+/* Bit definitions and macros for MCF_DSPI_DTFDRn */
5469+#define MCF_DSPI_DTFDRn_TXDATA(x) (((x)&0x0000FFFF)<<0)
5470+#define MCF_DSPI_DTFDRn_TXCMD(x) (((x)&0x0000FFFF)<<16)
5471+
5472+/* Bit definitions and macros for MCF_DSPI_DRFDRn */
5473+#define MCF_DSPI_DRFDRn_RXDATA(x) (((x)&0x0000FFFF)<<0)
5474+
5475+/********************************************************************/
5476+
5477+#endif /* _M5485DSPI_H_ */
5478--- /dev/null
5479+++ b/arch/m68k/include/asm/m5485gpio.h
5480@@ -0,0 +1,695 @@
5481+/*
5482+ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
5483+ * File: mcf548x_gpio.h
5484+ * Purpose: Register and bit definitions for the MCF548X
5485+ *
5486+ * Notes:
5487+ *
5488+ */
5489+
5490+#ifndef _M5485GPIO_H_
5491+#define _M5485GPIO_H_
5492+
5493+/*********************************************************************
5494+*
5495+* General Purpose I/O (GPIO)
5496+*
5497+*********************************************************************/
5498+
5499+/* Register read/write macros */
5500+#define MCF_GPIO_PODR_FBCTL MCF_REG08(0x000A00)
5501+#define MCF_GPIO_PODR_FBCS MCF_REG08(0x000A01)
5502+#define MCF_GPIO_PODR_DMA MCF_REG08(0x000A02)
5503+#define MCF_GPIO_PODR_FEC0H MCF_REG08(0x000A04)
5504+#define MCF_GPIO_PODR_FEC0L MCF_REG08(0x000A05)
5505+#define MCF_GPIO_PODR_FEC1H MCF_REG08(0x000A06)
5506+#define MCF_GPIO_PODR_FEC1L MCF_REG08(0x000A07)
5507+#define MCF_GPIO_PODR_FECI2C MCF_REG08(0x000A08)
5508+#define MCF_GPIO_PODR_PCIBG MCF_REG08(0x000A09)
5509+#define MCF_GPIO_PODR_PCIBR MCF_REG08(0x000A0A)
5510+#define MCF_GPIO_PODR_PSC3PSC2 MCF_REG08(0x000A0C)
5511+#define MCF_GPIO_PODR_PSC1PSC0 MCF_REG08(0x000A0D)
5512+#define MCF_GPIO_PODR_DSPI MCF_REG08(0x000A0E)
5513+#define MCF_GPIO_PDDR_FBCTL MCF_REG08(0x000A10)
5514+#define MCF_GPIO_PDDR_FBCS MCF_REG08(0x000A11)
5515+#define MCF_GPIO_PDDR_DMA MCF_REG08(0x000A12)
5516+#define MCF_GPIO_PDDR_FEC0H MCF_REG08(0x000A14)
5517+#define MCF_GPIO_PDDR_FEC0L MCF_REG08(0x000A15)
5518+#define MCF_GPIO_PDDR_FEC1H MCF_REG08(0x000A16)
5519+#define MCF_GPIO_PDDR_FEC1L MCF_REG08(0x000A17)
5520+#define MCF_GPIO_PDDR_FECI2C MCF_REG08(0x000A18)
5521+#define MCF_GPIO_PDDR_PCIBG MCF_REG08(0x000A19)
5522+#define MCF_GPIO_PDDR_PCIBR MCF_REG08(0x000A1A)
5523+#define MCF_GPIO_PDDR_PSC3PSC2 MCF_REG08(0x000A1C)
5524+#define MCF_GPIO_PDDR_PSC1PSC0 MCF_REG08(0x000A1D)
5525+#define MCF_GPIO_PDDR_DSPI MCF_REG08(0x000A1E)
5526+#define MCF_GPIO_PPDSDR_FBCTL MCF_REG08(0x000A20)
5527+#define MCF_GPIO_PPDSDR_FBCS MCF_REG08(0x000A21)
5528+#define MCF_GPIO_PPDSDR_DMA MCF_REG08(0x000A22)
5529+#define MCF_GPIO_PPDSDR_FEC0H MCF_REG08(0x000A24)
5530+#define MCF_GPIO_PPDSDR_FEC0L MCF_REG08(0x000A25)
5531+#define MCF_GPIO_PPDSDR_FEC1H MCF_REG08(0x000A26)
5532+#define MCF_GPIO_PPDSDR_FEC1L MCF_REG08(0x000A27)
5533+#define MCF_GPIO_PPDSDR_FECI2C MCF_REG08(0x000A28)
5534+#define MCF_GPIO_PPDSDR_PCIBG MCF_REG08(0x000A29)
5535+#define MCF_GPIO_PPDSDR_PCIBR MCF_REG08(0x000A2A)
5536+#define MCF_GPIO_PPDSDR_PSC3PSC2 MCF_REG08(0x000A2C)
5537+#define MCF_GPIO_PPDSDR_PSC1PSC0 MCF_REG08(0x000A2D)
5538+#define MCF_GPIO_PPDSDR_DSPI MCF_REG08(0x000A2E)
5539+#define MCF_GPIO_PCLRR_FBCTL MCF_REG08(0x000A30)
5540+#define MCF_GPIO_PCLRR_FBCS MCF_REG08(0x000A31)
5541+#define MCF_GPIO_PCLRR_DMA MCF_REG08(0x000A32)
5542+#define MCF_GPIO_PCLRR_FEC0H MCF_REG08(0x000A34)
5543+#define MCF_GPIO_PCLRR_FEC0L MCF_REG08(0x000A35)
5544+#define MCF_GPIO_PCLRR_FEC1H MCF_REG08(0x000A36)
5545+#define MCF_GPIO_PCLRR_FEC1L MCF_REG08(0x000A37)
5546+#define MCF_GPIO_PCLRR_FECI2C MCF_REG08(0x000A38)
5547+#define MCF_GPIO_PCLRR_PCIBG MCF_REG08(0x000A39)
5548+#define MCF_GPIO_PCLRR_PCIBR MCF_REG08(0x000A3A)
5549+#define MCF_GPIO_PCLRR_PSC3PSC2 MCF_REG08(0x000A3C)
5550+#define MCF_GPIO_PCLRR_PSC1PSC0 MCF_REG08(0x000A3D)
5551+#define MCF_GPIO_PCLRR_DSPI MCF_REG08(0x000A3E)
5552+#define MCF_GPIO_PAR_FBCTL MCF_REG16(0x000A40)
5553+#define MCF_GPIO_PAR_FBCS MCF_REG08(0x000A42)
5554+#define MCF_GPIO_PAR_DMA MCF_REG08(0x000A43)
5555+#define MCF_GPIO_PAR_FECI2CIRQ MCF_REG16(0x000A44)
5556+#define MCF_GPIO_PAR_PCIBG MCF_REG16(0x000A48)
5557+#define MCF_GPIO_PAR_PCIBR MCF_REG16(0x000A4A)
5558+#define MCF_GPIO_PAR_PSC3 MCF_REG08(0x000A4C)
5559+#define MCF_GPIO_PAR_PSC2 MCF_REG08(0x000A4D)
5560+#define MCF_GPIO_PAR_PSC1 MCF_REG08(0x000A4E)
5561+#define MCF_GPIO_PAR_PSC0 MCF_REG08(0x000A4F)
5562+#define MCF_GPIO_PAR_DSPI MCF_REG16(0x000A50)
5563+#define MCF_GPIO_PAR_TIMER MCF_REG08(0x000A52)
5564+
5565+/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */
5566+#define MCF_GPIO_PODR_FBCTL_PODRFBCTL0 (0x01)
5567+#define MCF_GPIO_PODR_FBCTL_PODRFBCTL1 (0x02)
5568+#define MCF_GPIO_PODR_FBCTL_PODRFBCTL2 (0x04)
5569+#define MCF_GPIO_PODR_FBCTL_PODRFBCTL3 (0x08)
5570+#define MCF_GPIO_PODR_FBCTL_PODRFBCTL4 (0x10)
5571+#define MCF_GPIO_PODR_FBCTL_PODRFBCTL5 (0x20)
5572+#define MCF_GPIO_PODR_FBCTL_PODRFBCTL6 (0x40)
5573+#define MCF_GPIO_PODR_FBCTL_PODRFBCTL7 (0x80)
5574+
5575+/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */
5576+#define MCF_GPIO_PODR_FBCS_PODRFBCS1 (0x02)
5577+#define MCF_GPIO_PODR_FBCS_PODRFBCS2 (0x04)
5578+#define MCF_GPIO_PODR_FBCS_PODRFBCS3 (0x08)
5579+#define MCF_GPIO_PODR_FBCS_PODRFBCS4 (0x10)
5580+#define MCF_GPIO_PODR_FBCS_PODRFBCS5 (0x20)
5581+
5582+/* Bit definitions and macros for MCF_GPIO_PODR_DMA */
5583+#define MCF_GPIO_PODR_DMA_PODRDMA0 (0x01)
5584+#define MCF_GPIO_PODR_DMA_PODRDMA1 (0x02)
5585+#define MCF_GPIO_PODR_DMA_PODRDMA2 (0x04)
5586+#define MCF_GPIO_PODR_DMA_PODRDMA3 (0x08)
5587+
5588+/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */
5589+#define MCF_GPIO_PODR_FEC0H_PODRFEC0H0 (0x01)
5590+#define MCF_GPIO_PODR_FEC0H_PODRFEC0H1 (0x02)
5591+#define MCF_GPIO_PODR_FEC0H_PODRFEC0H2 (0x04)
5592+#define MCF_GPIO_PODR_FEC0H_PODRFEC0H3 (0x08)
5593+#define MCF_GPIO_PODR_FEC0H_PODRFEC0H4 (0x10)
5594+#define MCF_GPIO_PODR_FEC0H_PODRFEC0H5 (0x20)
5595+#define MCF_GPIO_PODR_FEC0H_PODRFEC0H6 (0x40)
5596+#define MCF_GPIO_PODR_FEC0H_PODRFEC0H7 (0x80)
5597+
5598+/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */
5599+#define MCF_GPIO_PODR_FEC0L_PODRFEC0L0 (0x01)
5600+#define MCF_GPIO_PODR_FEC0L_PODRFEC0L1 (0x02)
5601+#define MCF_GPIO_PODR_FEC0L_PODRFEC0L2 (0x04)
5602+#define MCF_GPIO_PODR_FEC0L_PODRFEC0L3 (0x08)
5603+#define MCF_GPIO_PODR_FEC0L_PODRFEC0L4 (0x10)
5604+#define MCF_GPIO_PODR_FEC0L_PODRFEC0L5 (0x20)
5605+#define MCF_GPIO_PODR_FEC0L_PODRFEC0L6 (0x40)
5606+#define MCF_GPIO_PODR_FEC0L_PODRFEC0L7 (0x80)
5607+
5608+/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */
5609+#define MCF_GPIO_PODR_FEC1H_PODRFEC1H0 (0x01)
5610+#define MCF_GPIO_PODR_FEC1H_PODRFEC1H1 (0x02)
5611+#define MCF_GPIO_PODR_FEC1H_PODRFEC1H2 (0x04)
5612+#define MCF_GPIO_PODR_FEC1H_PODRFEC1H3 (0x08)
5613+#define MCF_GPIO_PODR_FEC1H_PODRFEC1H4 (0x10)
5614+#define MCF_GPIO_PODR_FEC1H_PODRFEC1H5 (0x20)
5615+#define MCF_GPIO_PODR_FEC1H_PODRFEC1H6 (0x40)
5616+#define MCF_GPIO_PODR_FEC1H_PODRFEC1H7 (0x80)
5617+
5618+/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */
5619+#define MCF_GPIO_PODR_FEC1L_PODRFEC1L0 (0x01)
5620+#define MCF_GPIO_PODR_FEC1L_PODRFEC1L1 (0x02)
5621+#define MCF_GPIO_PODR_FEC1L_PODRFEC1L2 (0x04)
5622+#define MCF_GPIO_PODR_FEC1L_PODRFEC1L3 (0x08)
5623+#define MCF_GPIO_PODR_FEC1L_PODRFEC1L4 (0x10)
5624+#define MCF_GPIO_PODR_FEC1L_PODRFEC1L5 (0x20)
5625+#define MCF_GPIO_PODR_FEC1L_PODRFEC1L6 (0x40)
5626+#define MCF_GPIO_PODR_FEC1L_PODRFEC1L7 (0x80)
5627+
5628+/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
5629+#define MCF_GPIO_PODR_FECI2C_PODRFECI2C0 (0x01)
5630+#define MCF_GPIO_PODR_FECI2C_PODRFECI2C1 (0x02)
5631+#define MCF_GPIO_PODR_FECI2C_PODRFECI2C2 (0x04)
5632+#define MCF_GPIO_PODR_FECI2C_PODRFECI2C3 (0x08)
5633+
5634+/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */
5635+#define MCF_GPIO_PODR_PCIBG_PODRPCIBG0 (0x01)
5636+#define MCF_GPIO_PODR_PCIBG_PODRPCIBG1 (0x02)
5637+#define MCF_GPIO_PODR_PCIBG_PODRPCIBG2 (0x04)
5638+#define MCF_GPIO_PODR_PCIBG_PODRPCIBG3 (0x08)
5639+#define MCF_GPIO_PODR_PCIBG_PODRPCIBG4 (0x10)
5640+
5641+/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */
5642+#define MCF_GPIO_PODR_PCIBR_PODRPCIBR0 (0x01)
5643+#define MCF_GPIO_PODR_PCIBR_PODRPCIBR1 (0x02)
5644+#define MCF_GPIO_PODR_PCIBR_PODRPCIBR2 (0x04)
5645+#define MCF_GPIO_PODR_PCIBR_PODRPCIBR3 (0x08)
5646+#define MCF_GPIO_PODR_PCIBR_PODRPCIBR4 (0x10)
5647+
5648+/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC2 */
5649+#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC20 (0x01)
5650+#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC21 (0x02)
5651+#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC22 (0x04)
5652+#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC23 (0x08)
5653+#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC24 (0x10)
5654+#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC25 (0x20)
5655+#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC26 (0x40)
5656+#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC27 (0x80)
5657+
5658+/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC0 */
5659+#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC00 (0x01)
5660+#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC01 (0x02)
5661+#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC02 (0x04)
5662+#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC03 (0x08)
5663+#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC04 (0x10)
5664+#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC05 (0x20)
5665+#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC06 (0x40)
5666+#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC07 (0x80)
5667+
5668+/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */
5669+#define MCF_GPIO_PODR_DSPI_PODRDSPI0 (0x01)
5670+#define MCF_GPIO_PODR_DSPI_PODRDSPI1 (0x02)
5671+#define MCF_GPIO_PODR_DSPI_PODRDSPI2 (0x04)
5672+#define MCF_GPIO_PODR_DSPI_PODRDSPI3 (0x08)
5673+#define MCF_GPIO_PODR_DSPI_PODRDSPI4 (0x10)
5674+#define MCF_GPIO_PODR_DSPI_PODRDSPI5 (0x20)
5675+#define MCF_GPIO_PODR_DSPI_PODRDSPI6 (0x40)
5676+
5677+/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */
5678+#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL0 (0x01)
5679+#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL1 (0x02)
5680+#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL2 (0x04)
5681+#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL3 (0x08)
5682+#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL4 (0x10)
5683+#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL5 (0x20)
5684+#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL6 (0x40)
5685+#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL7 (0x80)
5686+
5687+/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */
5688+#define MCF_GPIO_PDDR_FBCS_PDDRFBCS1 (0x02)
5689+#define MCF_GPIO_PDDR_FBCS_PDDRFBCS2 (0x04)
5690+#define MCF_GPIO_PDDR_FBCS_PDDRFBCS3 (0x08)
5691+#define MCF_GPIO_PDDR_FBCS_PDDRFBCS4 (0x10)
5692+#define MCF_GPIO_PDDR_FBCS_PDDRFBCS5 (0x20)
5693+
5694+/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */
5695+#define MCF_GPIO_PDDR_DMA_PDDRDMA0 (0x01)
5696+#define MCF_GPIO_PDDR_DMA_PDDRDMA1 (0x02)
5697+#define MCF_GPIO_PDDR_DMA_PDDRDMA2 (0x04)
5698+#define MCF_GPIO_PDDR_DMA_PDDRDMA3 (0x08)
5699+
5700+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */
5701+#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H0 (0x01)
5702+#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H1 (0x02)
5703+#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H2 (0x04)
5704+#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H3 (0x08)
5705+#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H4 (0x10)
5706+#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H5 (0x20)
5707+#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H6 (0x40)
5708+#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H7 (0x80)
5709+
5710+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */
5711+#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L0 (0x01)
5712+#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L1 (0x02)
5713+#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L2 (0x04)
5714+#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L3 (0x08)
5715+#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L4 (0x10)
5716+#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L5 (0x20)
5717+#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L6 (0x40)
5718+#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L7 (0x80)
5719+
5720+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */
5721+#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H0 (0x01)
5722+#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H1 (0x02)
5723+#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H2 (0x04)
5724+#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H3 (0x08)
5725+#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H4 (0x10)
5726+#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H5 (0x20)
5727+#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H6 (0x40)
5728+#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H7 (0x80)
5729+
5730+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */
5731+#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L0 (0x01)
5732+#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L1 (0x02)
5733+#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L2 (0x04)
5734+#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L3 (0x08)
5735+#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L4 (0x10)
5736+#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L5 (0x20)
5737+#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L6 (0x40)
5738+#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L7 (0x80)
5739+
5740+/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
5741+#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C0 (0x01)
5742+#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C1 (0x02)
5743+#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C2 (0x04)
5744+#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C3 (0x08)
5745+
5746+/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */
5747+#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG0 (0x01)
5748+#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG1 (0x02)
5749+#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG2 (0x04)
5750+#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG3 (0x08)
5751+#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG4 (0x10)
5752+
5753+/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */
5754+#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR0 (0x01)
5755+#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR1 (0x02)
5756+#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR2 (0x04)
5757+#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR3 (0x08)
5758+#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR4 (0x10)
5759+
5760+/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC2 */
5761+#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC20 (0x01)
5762+#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC21 (0x02)
5763+#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC22 (0x04)
5764+#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC23 (0x08)
5765+#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC24 (0x10)
5766+#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC25 (0x20)
5767+#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC26 (0x40)
5768+#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC27 (0x80)
5769+
5770+/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC0 */
5771+#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC00 (0x01)
5772+#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC01 (0x02)
5773+#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC02 (0x04)
5774+#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC03 (0x08)
5775+#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC04 (0x10)
5776+#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC05 (0x20)
5777+#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC06 (0x40)
5778+#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC07 (0x80)
5779+
5780+/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */
5781+#define MCF_GPIO_PDDR_DSPI_PDDRDSPI0 (0x01)
5782+#define MCF_GPIO_PDDR_DSPI_PDDRDSPI1 (0x02)
5783+#define MCF_GPIO_PDDR_DSPI_PDDRDSPI2 (0x04)
5784+#define MCF_GPIO_PDDR_DSPI_PDDRDSPI3 (0x08)
5785+#define MCF_GPIO_PDDR_DSPI_PDDRDSPI4 (0x10)
5786+#define MCF_GPIO_PDDR_DSPI_PDDRDSPI5 (0x20)
5787+#define MCF_GPIO_PDDR_DSPI_PDDRDSPI6 (0x40)
5788+
5789+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */
5790+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL0 (0x01)
5791+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL1 (0x02)
5792+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL2 (0x04)
5793+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL3 (0x08)
5794+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL4 (0x10)
5795+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL5 (0x20)
5796+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL6 (0x40)
5797+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL7 (0x80)
5798+
5799+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */
5800+#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS1 (0x02)
5801+#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS2 (0x04)
5802+#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS3 (0x08)
5803+#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS4 (0x10)
5804+#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS5 (0x20)
5805+
5806+/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */
5807+#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA0 (0x01)
5808+#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA1 (0x02)
5809+#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA2 (0x04)
5810+#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA3 (0x08)
5811+
5812+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */
5813+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H0 (0x01)
5814+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H1 (0x02)
5815+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H2 (0x04)
5816+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H3 (0x08)
5817+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H4 (0x10)
5818+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H5 (0x20)
5819+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H6 (0x40)
5820+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H7 (0x80)
5821+
5822+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */
5823+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L0 (0x01)
5824+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L1 (0x02)
5825+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L2 (0x04)
5826+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L3 (0x08)
5827+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L4 (0x10)
5828+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L5 (0x20)
5829+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L6 (0x40)
5830+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L7 (0x80)
5831+
5832+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */
5833+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H0 (0x01)
5834+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H1 (0x02)
5835+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H2 (0x04)
5836+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H3 (0x08)
5837+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H4 (0x10)
5838+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H5 (0x20)
5839+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H6 (0x40)
5840+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H7 (0x80)
5841+
5842+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */
5843+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L0 (0x01)
5844+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L1 (0x02)
5845+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L2 (0x04)
5846+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L3 (0x08)
5847+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L4 (0x10)
5848+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L5 (0x20)
5849+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L6 (0x40)
5850+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L7 (0x80)
5851+
5852+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
5853+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C0 (0x01)
5854+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C1 (0x02)
5855+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C2 (0x04)
5856+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C3 (0x08)
5857+
5858+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */
5859+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG0 (0x01)
5860+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG1 (0x02)
5861+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG2 (0x04)
5862+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG3 (0x08)
5863+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG4 (0x10)
5864+
5865+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */
5866+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR0 (0x01)
5867+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR1 (0x02)
5868+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR2 (0x04)
5869+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR3 (0x08)
5870+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR4 (0x10)
5871+
5872+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC2 */
5873+#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC20 (0x01)
5874+#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC21 (0x02)
5875+#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC22 (0x04)
5876+#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC23 (0x08)
5877+#define MCF_GPIO_PPDSDR_PSC3PSC2_PDDRPSC3PSC24 (0x10)
5878+#define MCF_GPIO_PPDSDR_PSC3PSC2_PDDRPSC3PSC25 (0x20)
5879+#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC26 (0x40)
5880+#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC27 (0x80)
5881+
5882+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC0 */
5883+#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC00 (0x01)
5884+#define MCF_GPIO_PPDSDR_PSC1PSC0_PDDRPSC1PSC01 (0x02)
5885+#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC02 (0x04)
5886+#define MCF_GPIO_PPDSDR_PSC1PSC0_PDDRPSC1PSC03 (0x08)
5887+#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC04 (0x10)
5888+#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC05 (0x20)
5889+#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC06 (0x40)
5890+#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC07 (0x80)
5891+
5892+/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */
5893+#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI0 (0x01)
5894+#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI1 (0x02)
5895+#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI2 (0x04)
5896+#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI3 (0x08)
5897+#define MCF_GPIO_PPDSDR_DSPI_PDDRDSPI4 (0x10)
5898+#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI5 (0x20)
5899+#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI6 (0x40)
5900+
5901+/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */
5902+#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL0 (0x01)
5903+#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL1 (0x02)
5904+#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL2 (0x04)
5905+#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL3 (0x08)
5906+#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL4 (0x10)
5907+#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL5 (0x20)
5908+#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL6 (0x40)
5909+#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL7 (0x80)
5910+
5911+/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */
5912+#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS1 (0x02)
5913+#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS2 (0x04)
5914+#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS3 (0x08)
5915+#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS4 (0x10)
5916+#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS5 (0x20)
5917+
5918+/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */
5919+#define MCF_GPIO_PCLRR_DMA_PCLRRDMA0 (0x01)
5920+#define MCF_GPIO_PCLRR_DMA_PCLRRDMA1 (0x02)
5921+#define MCF_GPIO_PCLRR_DMA_PCLRRDMA2 (0x04)
5922+#define MCF_GPIO_PCLRR_DMA_PCLRRDMA3 (0x08)
5923+
5924+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */
5925+#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H0 (0x01)
5926+#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H1 (0x02)
5927+#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H2 (0x04)
5928+#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H3 (0x08)
5929+#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H4 (0x10)
5930+#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H5 (0x20)
5931+#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H6 (0x40)
5932+#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H7 (0x80)
5933+
5934+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */
5935+#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L0 (0x01)
5936+#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L1 (0x02)
5937+#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L2 (0x04)
5938+#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L3 (0x08)
5939+#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L4 (0x10)
5940+#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L5 (0x20)
5941+#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L6 (0x40)
5942+#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L7 (0x80)
5943+
5944+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */
5945+#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H0 (0x01)
5946+#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H1 (0x02)
5947+#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H2 (0x04)
5948+#define MCF_GPIO_PCLRR_FEC1H_PODRFEC1H3 (0x08)
5949+#define MCF_GPIO_PCLRR_FEC1H_PODRFEC1H4 (0x10)
5950+#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H5 (0x20)
5951+#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H6 (0x40)
5952+#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H7 (0x80)
5953+
5954+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */
5955+#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L0 (0x01)
5956+#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L1 (0x02)
5957+#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L2 (0x04)
5958+#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L3 (0x08)
5959+#define MCF_GPIO_PCLRR_FEC1L_PODRFEC1L4 (0x10)
5960+#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L5 (0x20)
5961+#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L6 (0x40)
5962+#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L7 (0x80)
5963+
5964+/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
5965+#define MCF_GPIO_PCLRR_FECI2C_PCLRRFECI2C0 (0x01)
5966+#define MCF_GPIO_PCLRR_FECI2C_PCLRRFECI2C1 (0x02)
5967+#define MCF_GPIO_PCLRR_FECI2C_PODRFECI2C2 (0x04)
5968+#define MCF_GPIO_PCLRR_FECI2C_PCLRRFECI2C3 (0x08)
5969+
5970+/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */
5971+#define MCF_GPIO_PCLRR_PCIBG_PODRPCIBG0 (0x01)
5972+#define MCF_GPIO_PCLRR_PCIBG_PODRPCIBG1 (0x02)
5973+#define MCF_GPIO_PCLRR_PCIBG_PODRPCIBG2 (0x04)
5974+#define MCF_GPIO_PCLRR_PCIBG_PCLRRPCIBG3 (0x08)
5975+#define MCF_GPIO_PCLRR_PCIBG_PCLRRPCIBG4 (0x10)
5976+
5977+/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */
5978+#define MCF_GPIO_PCLRR_PCIBR_PCLRRPCIBR0 (0x01)
5979+#define MCF_GPIO_PCLRR_PCIBR_PCLRRPCIBR1 (0x02)
5980+#define MCF_GPIO_PCLRR_PCIBR_PCLRRPCIBR2 (0x04)
5981+#define MCF_GPIO_PCLRR_PCIBR_PODRPCIBR3 (0x08)
5982+#define MCF_GPIO_PCLRR_PCIBR_PODRPCIBR4 (0x10)
5983+
5984+/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC2 */
5985+#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC20 (0x01)
5986+#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC21 (0x02)
5987+#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC22 (0x04)
5988+#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC23 (0x08)
5989+#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC24 (0x10)
5990+#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC25 (0x20)
5991+#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC26 (0x40)
5992+#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC27 (0x80)
5993+
5994+/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC0 */
5995+#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC00 (0x01)
5996+#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC01 (0x02)
5997+#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC02 (0x04)
5998+#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC03 (0x08)
5999+#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC04 (0x10)
6000+#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC05 (0x20)
6001+#define MCF_GPIO_PCLRR_PSC1PSC0_PODRPSC1PSC06 (0x40)
6002+#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC07 (0x80)
6003+
6004+/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */
6005+#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI0 (0x01)
6006+#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI1 (0x02)
6007+#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI2 (0x04)
6008+#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI3 (0x08)
6009+#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI4 (0x10)
6010+#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI5 (0x20)
6011+#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI6 (0x40)
6012+
6013+/* Bit definitions and macros for MCF_GPIO_PAR_FBCTL */
6014+#define MCF_GPIO_PAR_FBCTL_PAR_TS(x) (((x)&0x0003)<<0)
6015+#define MCF_GPIO_PAR_FBCTL_PAR_TA (0x0004)
6016+#define MCF_GPIO_PAR_FBCTL_PAR_RWB (0x0010)
6017+#define MCF_GPIO_PAR_FBCTL_PAR_OE (0x0040)
6018+#define MCF_GPIO_PAR_FBCTL_PAR_BWE0 (0x0100)
6019+#define MCF_GPIO_PAR_FBCTL_PAR_BWE1 (0x0400)
6020+#define MCF_GPIO_PAR_FBCTL_PAR_BWE2 (0x1000)
6021+#define MCF_GPIO_PAR_FBCTL_PAR_BWE3 (0x4000)
6022+#define MCF_GPIO_PAR_FBCTL_PAR_TS_GPIO (0)
6023+#define MCF_GPIO_PAR_FBCTL_PAR_TS_TBST (2)
6024+#define MCF_GPIO_PAR_FBCTL_PAR_TS_TS (3)
6025+
6026+/* Bit definitions and macros for MCF_GPIO_PAR_FBCS */
6027+#define MCF_GPIO_PAR_FBCS_PAR_CS1 (0x02)
6028+#define MCF_GPIO_PAR_FBCS_PAR_CS2 (0x04)
6029+#define MCF_GPIO_PAR_FBCS_PAR_CS3 (0x08)
6030+#define MCF_GPIO_PAR_FBCS_PAR_CS4 (0x10)
6031+#define MCF_GPIO_PAR_FBCS_PAR_CS5 (0x20)
6032+
6033+/* Bit definitions and macros for MCF_GPIO_PAR_DMA */
6034+#define MCF_GPIO_PAR_DMA_PAR_DREQ0(x) (((x)&0x03)<<0)
6035+#define MCF_GPIO_PAR_DMA_PAR_DREQ1(x) (((x)&0x03)<<2)
6036+#define MCF_GPIO_PAR_DMA_PAR_DACK0(x) (((x)&0x03)<<4)
6037+#define MCF_GPIO_PAR_DMA_PAR_DACK1(x) (((x)&0x03)<<6)
6038+#define MCF_GPIO_PAR_DMA_PAR_DACKx_GPIO (0)
6039+#define MCF_GPIO_PAR_DMA_PAR_DACKx_TOUT (2)
6040+#define MCF_GPIO_PAR_DMA_PAR_DACKx_DACK (3)
6041+#define MCF_GPIO_PAR_DMA_PAR_DREQx_GPIO (0)
6042+#define MCF_GPIO_PAR_DMA_PAR_DREQx_TIN (2)
6043+#define MCF_GPIO_PAR_DMA_PAR_DREQx_DREQ (3)
6044+
6045+/* Bit definitions and macros for MCF_GPIO_PAR_FECI2CIRQ */
6046+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_IRQ5 (0x0001)
6047+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_IRQ6 (0x0002)
6048+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_SCL (0x0004)
6049+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_SDA (0x0008)
6050+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC(x) (((x)&0x0003)<<6)
6051+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO(x) (((x)&0x0003)<<8)
6052+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MII (0x0400)
6053+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E17 (0x0800)
6054+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDC (0x1000)
6055+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO (0x2000)
6056+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MII (0x4000)
6057+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E07 (0x8000)
6058+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_CANRX (0x0000)
6059+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x0200)
6060+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO (0x0300)
6061+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_CANTX (0x0000)
6062+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_SCL (0x0080)
6063+#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC (0x00C0)
6064+
6065+/* Bit definitions and macros for MCF_GPIO_PAR_PCIBG */
6066+#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG0(x) (((x)&0x0003)<<0)
6067+#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG1(x) (((x)&0x0003)<<2)
6068+#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG2(x) (((x)&0x0003)<<4)
6069+#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG3(x) (((x)&0x0003)<<6)
6070+#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG4(x) (((x)&0x0003)<<8)
6071+
6072+/* Bit definitions and macros for MCF_GPIO_PAR_PCIBR */
6073+#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG0(x) (((x)&0x0003)<<0)
6074+#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG1(x) (((x)&0x0003)<<2)
6075+#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG2(x) (((x)&0x0003)<<4)
6076+#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG3(x) (((x)&0x0003)<<6)
6077+#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR4(x) (((x)&0x0003)<<8)
6078+
6079+/* Bit definitions and macros for MCF_GPIO_PAR_PSC3 */
6080+#define MCF_GPIO_PAR_PSC3_PAR_TXD3 (0x04)
6081+#define MCF_GPIO_PAR_PSC3_PAR_RXD3 (0x08)
6082+#define MCF_GPIO_PAR_PSC3_PAR_RTS3(x) (((x)&0x03)<<4)
6083+#define MCF_GPIO_PAR_PSC3_PAR_CTS3(x) (((x)&0x03)<<6)
6084+#define MCF_GPIO_PAR_PSC3_PAR_CTS3_GPIO (0x00)
6085+#define MCF_GPIO_PAR_PSC3_PAR_CTS3_BCLK (0x80)
6086+#define MCF_GPIO_PAR_PSC3_PAR_CTS3_CTS (0xC0)
6087+#define MCF_GPIO_PAR_PSC3_PAR_RTS3_GPIO (0x00)
6088+#define MCF_GPIO_PAR_PSC3_PAR_RTS3_FSYNC (0x20)
6089+#define MCF_GPIO_PAR_PSC3_PAR_RTS3_RTS (0x30)
6090+#define MCF_GPIO_PAR_PSC3_PAR_CTS2_CANRX (0x40)
6091+
6092+/* Bit definitions and macros for MCF_GPIO_PAR_PSC2 */
6093+#define MCF_GPIO_PAR_PSC2_PAR_TXD2 (0x04)
6094+#define MCF_GPIO_PAR_PSC2_PAR_RXD2 (0x08)
6095+#define MCF_GPIO_PAR_PSC2_PAR_RTS2(x) (((x)&0x03)<<4)
6096+#define MCF_GPIO_PAR_PSC2_PAR_CTS2(x) (((x)&0x03)<<6)
6097+#define MCF_GPIO_PAR_PSC2_PAR_CTS2_GPIO (0x00)
6098+#define MCF_GPIO_PAR_PSC2_PAR_CTS2_BCLK (0x80)
6099+#define MCF_GPIO_PAR_PSC2_PAR_CTS2_CTS (0xC0)
6100+#define MCF_GPIO_PAR_PSC2_PAR_RTS2_GPIO (0x00)
6101+#define MCF_GPIO_PAR_PSC2_PAR_RTS2_CANTX (0x10)
6102+#define MCF_GPIO_PAR_PSC2_PAR_RTS2_FSYNC (0x20)
6103+#define MCF_GPIO_PAR_PSC2_PAR_RTS2_RTS (0x30)
6104+#define MCF_GPIO_PAR_PSC2_PAR_RTS2_CANRX (0x40)
6105+
6106+/* Bit definitions and macros for MCF_GPIO_PAR_PSC1 */
6107+#define MCF_GPIO_PAR_PSC1_PAR_TXD1 (0x04)
6108+#define MCF_GPIO_PAR_PSC1_PAR_RXD1 (0x08)
6109+#define MCF_GPIO_PAR_PSC1_PAR_RTS1(x) (((x)&0x03)<<4)
6110+#define MCF_GPIO_PAR_PSC1_PAR_CTS1(x) (((x)&0x03)<<6)
6111+#define MCF_GPIO_PAR_PSC1_PAR_CTS1_GPIO (0x00)
6112+#define MCF_GPIO_PAR_PSC1_PAR_CTS1_BCLK (0x80)
6113+#define MCF_GPIO_PAR_PSC1_PAR_CTS1_CTS (0xC0)
6114+#define MCF_GPIO_PAR_PSC1_PAR_RTS1_GPIO (0x00)
6115+#define MCF_GPIO_PAR_PSC1_PAR_RTS1_FSYNC (0x20)
6116+#define MCF_GPIO_PAR_PSC1_PAR_RTS1_RTS (0x30)
6117+
6118+/* Bit definitions and macros for MCF_GPIO_PAR_PSC0 */
6119+#define MCF_GPIO_PAR_PSC0_PAR_TXD0 (0x04)
6120+#define MCF_GPIO_PAR_PSC0_PAR_RXD0 (0x08)
6121+#define MCF_GPIO_PAR_PSC0_PAR_RTS0(x) (((x)&0x03)<<4)
6122+#define MCF_GPIO_PAR_PSC0_PAR_CTS0(x) (((x)&0x03)<<6)
6123+#define MCF_GPIO_PAR_PSC0_PAR_CTS0_GPIO (0x00)
6124+#define MCF_GPIO_PAR_PSC0_PAR_CTS0_BCLK (0x80)
6125+#define MCF_GPIO_PAR_PSC0_PAR_CTS0_CTS (0xC0)
6126+#define MCF_GPIO_PAR_PSC0_PAR_RTS0_GPIO (0x00)
6127+#define MCF_GPIO_PAR_PSC0_PAR_RTS0_FSYNC (0x20)
6128+#define MCF_GPIO_PAR_PSC0_PAR_RTS0_RTS (0x30)
6129+
6130+/* Bit definitions and macros for MCF_GPIO_PAR_DSPI */
6131+#define MCF_GPIO_PAR_DSPI_PAR_SOUT(x) (((x)&0x0003)<<0)
6132+#define MCF_GPIO_PAR_DSPI_PAR_SIN(x) (((x)&0x0003)<<2)
6133+#define MCF_GPIO_PAR_DSPI_PAR_SCK(x) (((x)&0x0003)<<4)
6134+#define MCF_GPIO_PAR_DSPI_PAR_CS0(x) (((x)&0x0003)<<6)
6135+#define MCF_GPIO_PAR_DSPI_PAR_CS2(x) (((x)&0x0003)<<8)
6136+#define MCF_GPIO_PAR_DSPI_PAR_CS3(x) (((x)&0x0003)<<10)
6137+#define MCF_GPIO_PAR_DSPI_PAR_CS5 (0x1000)
6138+#define MCF_GPIO_PAR_DSPI_PAR_CS3_GPIO (0x0000)
6139+#define MCF_GPIO_PAR_DSPI_PAR_CS3_CANTX (0x0400)
6140+#define MCF_GPIO_PAR_DSPI_PAR_CS3_TOUT (0x0800)
6141+#define MCF_GPIO_PAR_DSPI_PAR_CS3_DSPICS (0x0C00)
6142+#define MCF_GPIO_PAR_DSPI_PAR_CS2_GPIO (0x0000)
6143+#define MCF_GPIO_PAR_DSPI_PAR_CS2_CANTX (0x0100)
6144+#define MCF_GPIO_PAR_DSPI_PAR_CS2_TOUT (0x0200)
6145+#define MCF_GPIO_PAR_DSPI_PAR_CS2_DSPICS (0x0300)
6146+#define MCF_GPIO_PAR_DSPI_PAR_CS0_GPIO (0x0000)
6147+#define MCF_GPIO_PAR_DSPI_PAR_CS0_FSYNC (0x0040)
6148+#define MCF_GPIO_PAR_DSPI_PAR_CS0_RTS (0x0080)
6149+#define MCF_GPIO_PAR_DSPI_PAR_CS0_DSPICS (0x00C0)
6150+#define MCF_GPIO_PAR_DSPI_PAR_SCK_GPIO (0x0000)
6151+#define MCF_GPIO_PAR_DSPI_PAR_SCK_BCLK (0x0010)
6152+#define MCF_GPIO_PAR_DSPI_PAR_SCK_CTS (0x0020)
6153+#define MCF_GPIO_PAR_DSPI_PAR_SCK_SCK (0x0030)
6154+#define MCF_GPIO_PAR_DSPI_PAR_SIN_GPIO (0x0000)
6155+#define MCF_GPIO_PAR_DSPI_PAR_SIN_RXD (0x0008)
6156+#define MCF_GPIO_PAR_DSPI_PAR_SIN_SIN (0x000C)
6157+#define MCF_GPIO_PAR_DSPI_PAR_SOUT_GPIO (0x0000)
6158+#define MCF_GPIO_PAR_DSPI_PAR_SOUT_TXD (0x0002)
6159+#define MCF_GPIO_PAR_DSPI_PAR_SOUT_SOUT (0x0003)
6160+
6161+/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */
6162+#define MCF_GPIO_PAR_TIMER_PAR_TOUT2 (0x01)
6163+#define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<1)
6164+#define MCF_GPIO_PAR_TIMER_PAR_TOUT3 (0x08)
6165+#define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<4)
6166+#define MCF_GPIO_PAR_TIMER_PAR_TIN3_CANRX (0x00)
6167+#define MCF_GPIO_PAR_TIMER_PAR_TIN3_IRQ (0x20)
6168+#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN (0x30)
6169+#define MCF_GPIO_PAR_TIMER_PAR_TIN2_CANRX (0x00)
6170+#define MCF_GPIO_PAR_TIMER_PAR_TIN2_IRQ (0x04)
6171+#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN (0x06)
6172+
6173+/********************************************************************/
6174+
6175+#endif /* _M5485GPIO_H_ */
6176--- /dev/null
6177+++ b/arch/m68k/include/asm/m5485gpt.h
6178@@ -0,0 +1,90 @@
6179+/*
6180+ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
6181+ * File: mcf548x_gpt.h
6182+ * Purpose: Register and bit definitions for the MCF548X
6183+ *
6184+ * Notes:
6185+ *
6186+ */
6187+
6188+#ifndef __MCF548X_GPT_H__
6189+#define __MCF548X_GPT_H__
6190+
6191+/*********************************************************************
6192+*
6193+* General Purpose Timers (GPT)
6194+*
6195+*********************************************************************/
6196+
6197+/* Register read/write macros */
6198+#define MCF_GPT_GMS0 MCF_REG32(0x000800)
6199+#define MCF_GPT_GCIR0 MCF_REG32(0x000804)
6200+#define MCF_GPT_GPWM0 MCF_REG32(0x000808)
6201+#define MCF_GPT_GSR0 MCF_REG32(0x00080C)
6202+#define MCF_GPT_GMS1 MCF_REG32(0x000810)
6203+#define MCF_GPT_GCIR1 MCF_REG32(0x000814)
6204+#define MCF_GPT_GPWM1 MCF_REG32(0x000818)
6205+#define MCF_GPT_GSR1 MCF_REG32(0x00081C)
6206+#define MCF_GPT_GMS2 MCF_REG32(0x000820)
6207+#define MCF_GPT_GCIR2 MCF_REG32(0x000824)
6208+#define MCF_GPT_GPWM2 MCF_REG32(0x000828)
6209+#define MCF_GPT_GSR2 MCF_REG32(0x00082C)
6210+#define MCF_GPT_GMS3 MCF_REG32(0x000830)
6211+#define MCF_GPT_GCIR3 MCF_REG32(0x000834)
6212+#define MCF_GPT_GPWM3 MCF_REG32(0x000838)
6213+#define MCF_GPT_GSR3 MCF_REG32(0x00083C)
6214+#define MCF_GPT_GMS(x) MCF_REG32(0x000800+((x)*0x010))
6215+#define MCF_GPT_GCIR(x) MCF_REG32(0x000804+((x)*0x010))
6216+#define MCF_GPT_GPWM(x) MCF_REG32(0x000808+((x)*0x010))
6217+#define MCF_GPT_GSR(x) MCF_REG32(0x00080C+((x)*0x010))
6218+
6219+/* Bit definitions and macros for MCF_GPT_GMS */
6220+#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0)
6221+#define MCF_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4)
6222+#define MCF_GPT_GMS_IEN (0x00000100)
6223+#define MCF_GPT_GMS_OD (0x00000200)
6224+#define MCF_GPT_GMS_SC (0x00000400)
6225+#define MCF_GPT_GMS_CE (0x00001000)
6226+#define MCF_GPT_GMS_WDEN (0x00008000)
6227+#define MCF_GPT_GMS_ICT(x) (((x)&0x00000003)<<16)
6228+#define MCF_GPT_GMS_OCT(x) (((x)&0x00000003)<<20)
6229+#define MCF_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24)
6230+#define MCF_GPT_GMS_OCT_FRCLOW (0x00000000)
6231+#define MCF_GPT_GMS_OCT_PULSEHI (0x00100000)
6232+#define MCF_GPT_GMS_OCT_PULSELO (0x00200000)
6233+#define MCF_GPT_GMS_OCT_TOGGLE (0x00300000)
6234+#define MCF_GPT_GMS_ICT_ANY (0x00000000)
6235+#define MCF_GPT_GMS_ICT_RISE (0x00010000)
6236+#define MCF_GPT_GMS_ICT_FALL (0x00020000)
6237+#define MCF_GPT_GMS_ICT_PULSE (0x00030000)
6238+#define MCF_GPT_GMS_GPIO_INPUT (0x00000000)
6239+#define MCF_GPT_GMS_GPIO_OUTLO (0x00000020)
6240+#define MCF_GPT_GMS_GPIO_OUTHI (0x00000030)
6241+#define MCF_GPT_GMS_TMS_DISABLE (0x00000000)
6242+#define MCF_GPT_GMS_TMS_INCAPT (0x00000001)
6243+#define MCF_GPT_GMS_TMS_OUTCAPT (0x00000002)
6244+#define MCF_GPT_GMS_TMS_PWM (0x00000003)
6245+#define MCF_GPT_GMS_TMS_GPIO (0x00000004)
6246+
6247+/* Bit definitions and macros for MCF_GPT_GCIR */
6248+#define MCF_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0)
6249+#define MCF_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16)
6250+
6251+/* Bit definitions and macros for MCF_GPT_GPWM */
6252+#define MCF_GPT_GPWM_LOAD (0x00000001)
6253+#define MCF_GPT_GPWM_PWMOP (0x00000100)
6254+#define MCF_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16)
6255+
6256+/* Bit definitions and macros for MCF_GPT_GSR */
6257+#define MCF_GPT_GSR_CAPT (0x00000001)
6258+#define MCF_GPT_GSR_COMP (0x00000002)
6259+#define MCF_GPT_GSR_PWMP (0x00000004)
6260+#define MCF_GPT_GSR_TEXP (0x00000008)
6261+#define MCF_GPT_GSR_PIN (0x00000100)
6262+#define MCF_GPT_GSR_OVF(x) (((x)&0x00000007)<<12)
6263+#define MCF_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16)
6264+
6265+#define MCF_GPT_MAX_TIMEOUT 30
6266+/********************************************************************/
6267+
6268+#endif /* __MCF548X_GPT_H__ */
6269--- /dev/null
6270+++ b/arch/m68k/include/asm/m5485pci.h
6271@@ -0,0 +1,380 @@
6272+/*
6273+ * m5485pci.h -- ColdFire 547x/548x PCI controller support.
6274+ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
6275+ */
6276+#ifndef __MCF548X_PCI_H__
6277+#define __MCF548X_PCI_H__
6278+
6279+
6280+/* PCI Type 0 Configuration Registers */
6281+#define MCF_PCIIDR MCF_REG32(0x000B00)
6282+/* PCI Device ID/Vendor ID */
6283+#define MCF_PCISCR MCF_REG32(0x000B04)
6284+/* PCI Status/Command */
6285+#define MCF_PCICCRIR MCF_REG32(0x000B08)
6286+/* PCI Class Code / Revision ID */
6287+#define MCF_PCICR1 MCF_REG32(0x000B0C)
6288+/* PCI Configuration 1 Register */
6289+#define MCF_PCIBAR0 MCF_REG32(0x000B10)
6290+/* PCI Base Address Register 0 */
6291+#define MCF_PCIBAR1 MCF_REG32(0x000B14)
6292+/* PCI Base Address Register 1 */
6293+#define MCF_PCICCPR MCF_REG32(0x000B28)
6294+/* PCI Cardbus CIS Pointer */
6295+#define MCF_PCISID MCF_REG32(0x000B2C)
6296+/* Subsystem ID/Subsystem Vendor ID*/
6297+#define MCF_PCIERBAR MCF_REG32(0x000B30)
6298+/* PCI Expansion ROM */
6299+#define MCF_PCICPR MCF_REG32(0x000B30)
6300+/* PCI Capabilities Pointer */
6301+#define MCF_PCICR2 MCF_REG32(0x000B3C)
6302+/* PCI Configuration Register 2 */
6303+
6304+/* General Control/Status Registers */
6305+#define MCF_PCIGSCR MCF_REG32(0x000B60)
6306+/* Global Status/Control Register */
6307+#define MCF_PCITBATR0 MCF_REG32(0x000B64)
6308+/* Target Base Address Translation 0*/
6309+#define MCF_PCITBATR1 MCF_REG32(0x000B68)
6310+/* Target Base Address Translation 1*/
6311+#define MCF_PCITCR MCF_REG32(0x000B6C)
6312+/* Target Control Register */
6313+#define MCF_PCIIW0BTAR MCF_REG32(0x000B70)
6314+/* Initiator Window 0 Base Address */
6315+#define MCF_PCIIW1BTAR MCF_REG32(0x000B74)
6316+/* Initiator Window 1 Base Address */
6317+#define MCF_PCIIW2BTAR MCF_REG32(0x000B78)
6318+/* Initiator Window 2 Base Address */
6319+#define MCF_PCIIWCR MCF_REG32(0x000B80)
6320+/* Initiator Window Configuration */
6321+#define MCF_PCIICR MCF_REG32(0x000B84)
6322+/* Initiator Control Register */
6323+#define MCF_PCIISR MCF_REG32(0x000B88)
6324+/* Initiator Status Register */
6325+#define MCF_PCICAR MCF_REG32(0x000BF8)
6326+/* Configuration Address Register */
6327+
6328+/* CommBus FIFO Transmit Interface Registers */
6329+#define MCF_PCITPSR MCF_REG32(0x008400)
6330+/* Tx Packet Size Register */
6331+#define MCF_PCITSAR MCF_REG32(0x008404)
6332+/* Tx Start Address Register */
6333+#define MCF_PCITTCR MCF_REG32(0x008408)
6334+/* Tx Transaction Control Register */
6335+#define MCF_PCITER MCF_REG32(0x00840C)
6336+/* Tx Enables Register */
6337+#define MCF_PCITNAR MCF_REG32(0x008410)
6338+/* Tx Next Address Register */
6339+#define MCF_PCITLWR MCF_REG32(0x008414)
6340+/* Tx Last Word Register */
6341+#define MCF_PCITDCR MCF_REG32(0x008418)
6342+/* Tx Done Counts Register */
6343+#define MCF_PCITSR MCF_REG32(0x00841C)
6344+/* Tx Status Register */
6345+#define MCF_PCITFDR MCF_REG32(0x008440)
6346+/* Tx FIFO Data Register */
6347+#define MCF_PCITFSR MCF_REG32(0x008444)
6348+/* Tx FIFO Status Register */
6349+#define MCF_PCITFCR MCF_REG32(0x008448)
6350+/* Tx FIFO Control Register */
6351+#define MCF_PCITFAR MCF_REG32(0x00844C)
6352+/* Tx FIFO Alarm Register */
6353+#define MCF_PCITFRPR MCF_REG32(0x008450)
6354+/* Tx FIFO Read Pointer Register */
6355+#define MCF_PCITFWPR MCF_REG32(0x008454)
6356+/* Tx FIFO Write Pointer Register */
6357+
6358+/* CommBus FIFO Receive Interface Registers */
6359+#define MCF_PCIRPSR MCF_REG32(0x008480)
6360+/* Tx Packet Size Register */
6361+#define MCF_PCIRSAR MCF_REG32(0x008484)
6362+/* Tx Start Address Register */
6363+#define MCF_PCIRTCR MCF_REG32(0x008488)
6364+/* Tx Transaction Control Register */
6365+#define MCF_PCIRER MCF_REG32(0x00848C)
6366+/* Tx Enables Register */
6367+#define MCF_PCIRNAR MCF_REG32(0x008490)
6368+/* Tx Next Address Register */
6369+#define MCF_PCIRDCR MCF_REG32(0x008498)
6370+/* Tx Done Counts Register */
6371+#define MCF_PCIRSR MCF_REG32(0x00849C)
6372+/* Tx Status Register */
6373+#define MCF_PCIRFDR MCF_REG32(0x0084C0)
6374+/* Tx FIFO Data Register */
6375+#define MCF_PCIRFSR MCF_REG32(0x0084C4)
6376+/* Tx FIFO Status Register */
6377+#define MCF_PCIRFCR MCF_REG32(0x0084C8)
6378+/* Tx FIFO Control Register */
6379+#define MCF_PCIRFAR MCF_REG32(0x0084CC)
6380+/* Tx FIFO Alarm Register */
6381+#define MCF_PCIRFRPR MCF_REG32(0x0084D0)
6382+/* Tx FIFO Read Pointer Register */
6383+#define MCF_PCIRFWPR MCF_REG32(0x0084D4)
6384+/* Tx FIFO Write Pointer Register */
6385+
6386+/* PCI Arbiter Registers */
6387+#define MCF_PCIARB_PACR MCF_REG32(0x000C00)
6388+#define MCF_PCIARB_PASR MCF_REG32(0x000C04)
6389+
6390+
6391+/* Bit definitions and macros for MCF_PCIIDR */
6392+#define MCF_PCIIDR_VENDORID(x) (((x)&0x0000FFFF)<<0)
6393+#define MCF_PCIIDR_DEVICEID(x) (((x)&0x0000FFFF)<<16)
6394+
6395+/* Bit definitions and macros for MCF_PCISCR */
6396+#define MCF_PCISCR_M (0x00000002)
6397+#define MCF_PCISCR_B (0x00000004)
6398+#define MCF_PCISCR_SP (0x00000008)
6399+#define MCF_PCISCR_MW (0x00000010)
6400+#define MCF_PCISCR_PER (0x00000040)
6401+#define MCF_PCISCR_S (0x00000100)
6402+#define MCF_PCISCR_F (0x00000200)
6403+#define MCF_PCISCR_C (0x00100000)
6404+#define MCF_PCISCR_66M (0x00200000)
6405+#define MCF_PCISCR_R (0x00400000)
6406+#define MCF_PCISCR_FC (0x00800000)
6407+#define MCF_PCISCR_DP (0x01000000)
6408+#define MCF_PCISCR_DT(x) (((x)&0x00000003)<<25)
6409+#define MCF_PCISCR_TS (0x08000000)
6410+#define MCF_PCISCR_TR (0x10000000)
6411+#define MCF_PCISCR_MA (0x20000000)
6412+#define MCF_PCISCR_SE (0x40000000)
6413+#define MCF_PCISCR_PE (0x80000000)
6414+
6415+/* Bit definitions and macros for MCF_PCICCRIR */
6416+#define MCF_PCICCRIR_REVID(x) (((x)&0x000000FF)<<0)
6417+#define MCF_PCICCRIR_CLASSCODE(x) (((x)&0x00FFFFFF)<<8)
6418+
6419+/* Bit definitions and macros for MCF_PCICR1 */
6420+#define MCF_PCICR1_CACHELINESIZE(x) (((x)&0x0000000F)<<0)
6421+#define MCF_PCICR1_LATTIMER(x) (((x)&0x000000FF)<<8)
6422+#define MCF_PCICR1_HEADERTYPE(x) (((x)&0x000000FF)<<16)
6423+#define MCF_PCICR1_BIST(x) (((x)&0x000000FF)<<24)
6424+
6425+/* Bit definitions and macros for MCF_PCIBAR# */
6426+#define MCF_PCIBAR0_ADDR(x) (((x)&0x00003FFF)<<18)
6427+#define MCF_PCIBAR1_ADDR(x) (((x)&0x00000003)<<30)
6428+
6429+/* Bit definitions and macros for MCF_PCICR2 */
6430+#define MCF_PCICR2_INTLINE(x) (((x)&0x000000FF)<<0)
6431+#define MCF_PCICR2_INTPIN(x) (((x)&0x000000FF)<<8)
6432+#define MCF_PCICR2_MINGNT(x) (((x)&0x000000FF)<<16)
6433+#define MCF_PCICR2_MAXLAT(x) (((x)&0x000000FF)<<24)
6434+
6435+/* Bit definitions and macros for MCF_PCIGSCR */
6436+#define MCF_PCIGSCR_PR (0x00000001)
6437+#define MCF_PCIGSCR_SEE (0x00001000)
6438+#define MCF_PCIGSCR_PEE (0x00002000)
6439+#define MCF_PCIGSCR_SE (0x10000000)
6440+#define MCF_PCIGSCR_PE (0x20000000)
6441+
6442+/* Bit definitions and macros for MCF_PCITBATR0 */
6443+#define MCF_PCITBATR0_EN (0x00000001)
6444+#define MCF_PCITBATR0_BAT0(x) (((x)&0x00003FFF)<<18)
6445+
6446+/* Bit definitions and macros for MCF_PCITBATR1 */
6447+#define MCF_PCITBATR1_EN (0x00000001)
6448+#define MCF_PCITBATR1_BAT1(x) (((x)&0x00000003)<<30)
6449+
6450+/* Bit definitions and macros for MCF_PCITCR */
6451+#define MCF_PCITCR_P (0x00010000)
6452+#define MCF_PCITCR_LD (0x01000000)
6453+
6454+/* Bit definitions and macros for MCF_PCIIW0BTAR */
6455+#define MCF_PCIIW0BTAR_WTA0(x) (((x)&0x000000FF)<<8)
6456+#define MCF_PCIIW0BTAR_WAM0(x) (((x)&0x000000FF)<<16)
6457+#define MCF_PCIIW0BTAR_WBA0(x) (((x)&0x000000FF)<<24)
6458+
6459+/* Bit definitions and macros for MCF_PCIIW1BTAR */
6460+#define MCF_PCIIW1BTAR_WTA1(x) (((x)&0x000000FF)<<8)
6461+#define MCF_PCIIW1BTAR_WAM1(x) (((x)&0x000000FF)<<16)
6462+#define MCF_PCIIW1BTAR_WBA1(x) (((x)&0x000000FF)<<24)
6463+
6464+/* Bit definitions and macros for MCF_PCIIW2BTAR */
6465+#define MCF_PCIIW2BTAR_WTA2(x) (((x)&0x000000FF)<<8)
6466+#define MCF_PCIIW2BTAR_WAM2(x) (((x)&0x000000FF)<<16)
6467+#define MCF_PCIIW2BTAR_WBA2(x) (((x)&0x000000FF)<<24)
6468+
6469+/* Bit definitions and macros for MCF_PCIIWCR */
6470+#define MCF_PCIIWCR_WINCTRL2(x) (((x)&0x0000000F)<<8)
6471+#define MCF_PCIIWCR_WINCTRL1(x) (((x)&0x0000000F)<<16)
6472+#define MCF_PCIIWCR_WINCTRL0(x) (((x)&0x0000000F)<<24)
6473+#define MCF_PCIIWCR_WINCTRL0_MEMREAD (0x01000000)
6474+#define MCF_PCIIWCR_WINCTRL0_MEMRDLINE (0x03000000)
6475+#define MCF_PCIIWCR_WINCTRL0_MEMRDMUL (0x05000000)
6476+#define MCF_PCIIWCR_WINCTRL0_IO (0x09000000)
6477+#define MCF_PCIIWCR_WINCTRL0_E (0x01000000)
6478+#define MCF_PCIIWCR_WINCTRL1_MEMREAD (0x00010000)
6479+#define MCF_PCIIWCR_WINCTRL1_MEMRDLINE (0x00030000)
6480+#define MCF_PCIIWCR_WINCTRL1_MEMRDMUL (0x00050000)
6481+#define MCF_PCIIWCR_WINCTRL1_IO (0x00090000)
6482+#define MCF_PCIIWCR_WINCTRL1_E (0x00010000)
6483+#define MCF_PCIIWCR_WINCTRL2_MEMREAD (0x00000100)
6484+#define MCF_PCIIWCR_WINCTRL2_MEMRDLINE (0x00000300)
6485+#define MCF_PCIIWCR_WINCTRL2_MEMRDMUL (0x00000500)
6486+#define MCF_PCIIWCR_WINCTRL2_IO (0x00000900)
6487+#define MCF_PCIIWCR_WINCTRL2_E (0x00000100)
6488+
6489+
6490+/* Bit definitions and macros for MCF_PCIICR */
6491+#define MCF_PCIICR_MAXRETRY(x) (((x)&0x000000FF)<<0)
6492+#define MCF_PCIICR_TAE (0x01000000)
6493+#define MCF_PCIICR_IAE (0x02000000)
6494+#define MCF_PCIICR_REE (0x04000000)
6495+
6496+/* Bit definitions and macros for MCF_PCIISR */
6497+#define MCF_PCIISR_TA (0x01000000)
6498+#define MCF_PCIISR_IA (0x02000000)
6499+#define MCF_PCIISR_RE (0x04000000)
6500+
6501+/* Bit definitions and macros for MCF_PCICAR */
6502+#define MCF_PCICAR_DWORD(x) (((x)&0x0000003F)<<2)
6503+#define MCF_PCICAR_FUNCNUM(x) (((x)&0x00000007)<<8)
6504+#define MCF_PCICAR_DEVNUM(x) (((x)&0x0000001F)<<11)
6505+#define MCF_PCICAR_BUSNUM(x) (((x)&0x000000FF)<<16)
6506+#define MCF_PCICAR_E (0x80000000)
6507+
6508+/* Bit definitions and macros for MCF_PCITPSR */
6509+#define MCF_PCITPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16)
6510+
6511+/* Bit definitions and macros for MCF_PCITTCR */
6512+#define MCF_PCITTCR_DI (0x00000001)
6513+#define MCF_PCITTCR_W (0x00000010)
6514+#define MCF_PCITTCR_MAXBEATS(x) (((x)&0x00000007)<<8)
6515+#define MCF_PCITTCR_MAXRETRY(x) (((x)&0x000000FF)<<16)
6516+#define MCF_PCITTCR_PCICMD(x) (((x)&0x0000000F)<<24)
6517+
6518+/* Bit definitions and macros for MCF_PCITER */
6519+#define MCF_PCITER_NE (0x00010000)
6520+#define MCF_PCITER_IAE (0x00020000)
6521+#define MCF_PCITER_TAE (0x00040000)
6522+#define MCF_PCITER_RE (0x00080000)
6523+#define MCF_PCITER_SE (0x00100000)
6524+#define MCF_PCITER_FEE (0x00200000)
6525+#define MCF_PCITER_ME (0x01000000)
6526+#define MCF_PCITER_BE (0x08000000)
6527+#define MCF_PCITER_CM (0x10000000)
6528+#define MCF_PCITER_RF (0x40000000)
6529+#define MCF_PCITER_RC (0x80000000)
6530+
6531+/* Bit definitions and macros for MCF_PCITDCR */
6532+#define MCF_PCITDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0)
6533+#define MCF_PCITDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16)
6534+
6535+/* Bit definitions and macros for MCF_PCITSR */
6536+#define MCF_PCITSR_IA (0x00010000)
6537+#define MCF_PCITSR_TA (0x00020000)
6538+#define MCF_PCITSR_RE (0x00040000)
6539+#define MCF_PCITSR_SE (0x00080000)
6540+#define MCF_PCITSR_FE (0x00100000)
6541+#define MCF_PCITSR_BE1 (0x00200000)
6542+#define MCF_PCITSR_BE2 (0x00400000)
6543+#define MCF_PCITSR_BE3 (0x00800000)
6544+#define MCF_PCITSR_NT (0x01000000)
6545+
6546+/* Bit definitions and macros for MCF_PCITFSR */
6547+#define MCF_PCITFSR_EMT (0x00010000)
6548+#define MCF_PCITFSR_ALARM (0x00020000)
6549+#define MCF_PCITFSR_FU (0x00040000)
6550+#define MCF_PCITFSR_FR (0x00080000)
6551+#define MCF_PCITFSR_OF (0x00100000)
6552+#define MCF_PCITFSR_UF (0x00200000)
6553+#define MCF_PCITFSR_RXW (0x00400000)
6554+
6555+/* Bit definitions and macros for MCF_PCITFCR */
6556+#define MCF_PCITFCR_OF_MSK (0x00080000)
6557+#define MCF_PCITFCR_UF_MSK (0x00100000)
6558+#define MCF_PCITFCR_RXW_MSK (0x00200000)
6559+#define MCF_PCITFCR_FAE_MSK (0x00400000)
6560+#define MCF_PCITFCR_IP_MSK (0x00800000)
6561+#define MCF_PCITFCR_GR(x) (((x)&0x00000007)<<24)
6562+
6563+/* Bit definitions and macros for MCF_PCITFAR */
6564+#define MCF_PCITFAR_ALARM(x) (((x)&0x0000007F)<<0)
6565+
6566+/* Bit definitions and macros for MCF_PCITFRPR */
6567+#define MCF_PCITFRPR_READ(x) (((x)&0x00000FFF)<<0)
6568+
6569+/* Bit definitions and macros for MCF_PCITFWPR */
6570+#define MCF_PCITFWPR_WRITE(x) (((x)&0x00000FFF)<<0)
6571+
6572+/* Bit definitions and macros for MCF_PCIRPSR */
6573+#define MCF_PCIRPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16)
6574+
6575+/* Bit definitions and macros for MCF_PCIRTCR */
6576+#define MCF_PCIRTCR_DI (0x00000001)
6577+#define MCF_PCIRTCR_W (0x00000010)
6578+#define MCF_PCIRTCR_MAXBEATS(x) (((x)&0x00000007)<<8)
6579+#define MCF_PCIRTCR_FB (0x00001000)
6580+#define MCF_PCIRTCR_MAXRETRY(x) (((x)&0x000000FF)<<16)
6581+#define MCF_PCIRTCR_PCICMD(x) (((x)&0x0000000F)<<24)
6582+
6583+/* Bit definitions and macros for MCF_PCIRER */
6584+#define MCF_PCIRER_NE (0x00010000)
6585+#define MCF_PCIRER_IAE (0x00020000)
6586+#define MCF_PCIRER_TAE (0x00040000)
6587+#define MCF_PCIRER_RE (0x00080000)
6588+#define MCF_PCIRER_SE (0x00100000)
6589+#define MCF_PCIRER_FEE (0x00200000)
6590+#define MCF_PCIRER_ME (0x01000000)
6591+#define MCF_PCIRER_BE (0x08000000)
6592+#define MCF_PCIRER_CM (0x10000000)
6593+#define MCF_PCIRER_FE (0x20000000)
6594+#define MCF_PCIRER_RF (0x40000000)
6595+#define MCF_PCIRER_RC (0x80000000)
6596+
6597+/* Bit definitions and macros for MCF_PCIRDCR */
6598+#define MCF_PCIRDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0)
6599+#define MCF_PCIRDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16)
6600+
6601+/* Bit definitions and macros for MCF_PCIRSR */
6602+#define MCF_PCIRSR_IA (0x00010000)
6603+#define MCF_PCIRSR_TA (0x00020000)
6604+#define MCF_PCIRSR_RE (0x00040000)
6605+#define MCF_PCIRSR_SE (0x00080000)
6606+#define MCF_PCIRSR_FE (0x00100000)
6607+#define MCF_PCIRSR_BE1 (0x00200000)
6608+#define MCF_PCIRSR_BE2 (0x00400000)
6609+#define MCF_PCIRSR_BE3 (0x00800000)
6610+#define MCF_PCIRSR_NT (0x01000000)
6611+
6612+/* Bit definitions and macros for MCF_PCIRFSR */
6613+#define MCF_PCIRFSR_EMT (0x00010000)
6614+#define MCF_PCIRFSR_ALARM (0x00020000)
6615+#define MCF_PCIRFSR_FU (0x00040000)
6616+#define MCF_PCIRFSR_FR (0x00080000)
6617+#define MCF_PCIRFSR_OF (0x00100000)
6618+#define MCF_PCIRFSR_UF (0x00200000)
6619+#define MCF_PCIRFSR_RXW (0x00400000)
6620+
6621+/* Bit definitions and macros for MCF_PCIRFCR */
6622+#define MCF_PCIRFCR_OF_MSK (0x00080000)
6623+#define MCF_PCIRFCR_UF_MSK (0x00100000)
6624+#define MCF_PCIRFCR_RXW_MSK (0x00200000)
6625+#define MCF_PCIRFCR_FAE_MSK (0x00400000)
6626+#define MCF_PCIRFCR_IP_MSK (0x00800000)
6627+#define MCF_PCIRFCR_GR(x) (((x)&0x00000007)<<24)
6628+
6629+/* Bit definitions and macros for MCF_PCIRFAR */
6630+#define MCF_PCIRFAR_ALARM(x) (((x)&0x0000007F)<<0)
6631+
6632+/* Bit definitions and macros for MCF_PCIRFRPR */
6633+#define MCF_PCIRFRPR_READ(x) (((x)&0x00000FFF)<<0)
6634+
6635+/* Bit definitions and macros for MCF_PCIRFWPR */
6636+#define MCF_PCIRFWPR_WRITE(x) (((x)&0x00000FFF)<<0)
6637+
6638+
6639+/* Bit definitions and macros for MCF_PCIARB_PACR */
6640+#define MCF_PCIARB_PACR_INTMPRI (0x00000001)
6641+#define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x0000001F)<<1)
6642+#define MCF_PCIARB_PACR_INTMINTEN (0x00010000)
6643+#define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x0000001F)<<17)
6644+#define MCF_PCIARB_PACR_PKMD (0x40000000)
6645+#define MCF_PCIARB_PACR_DS (0x80000000)
6646+
6647+/* Bit definitions and macros for MCF_PCIARB_PASR */
6648+#define MCF_PCIARB_PASR_ITLMBK (0x00010000)
6649+#define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x0000001F)<<17)
6650+
6651+#endif /* __MCF548X_PCI_H__ */
6652--- /dev/null
6653+++ b/arch/m68k/include/asm/m5485psc.h
6654@@ -0,0 +1,475 @@
6655+/*
6656+ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
6657+ * File: mcf548x_psc.h
6658+ * Purpose: Register and bit definitions for the MCF548X
6659+ *
6660+ * Notes
6661+ *
6662+ */
6663+
6664+#ifndef __MCF548X_PSC_H__
6665+#define __MCF548X_PSC_H__
6666+
6667+/*********************************************************************
6668+*
6669+* Programmable Serial Controller (PSC)
6670+*
6671+*********************************************************************/
6672+
6673+/* Register read/write macros */
6674+#define MCF_PSC_MR0 MCF_REG08(0x008600)
6675+#define MCF_PSC_SR0 MCF_REG16(0x008604)
6676+#define MCF_PSC_CSR0 MCF_REG08(0x008604)
6677+#define MCF_PSC_CR0 MCF_REG08(0x008608)
6678+#define MCF_PSC_RB0 MCF_REG32(0x00860C)
6679+#define MCF_PSC_TB0 MCF_REG32(0x00860C)
6680+#define MCF_PSC_TB_8BIT0 MCF_REG32(0x00860C)
6681+#define MCF_PSC_TB_16BIT0 MCF_REG32(0x00860C)
6682+#define MCF_PSC_TB_AC970 MCF_REG32(0x00860C)
6683+#define MCF_PSC_IPCR0 MCF_REG08(0x008610)
6684+#define MCF_PSC_ACR0 MCF_REG08(0x008610)
6685+#define MCF_PSC_ISR0 MCF_REG16(0x008614)
6686+#define MCF_PSC_IMR0 MCF_REG16(0x008614)
6687+#define MCF_PSC_CTUR0 MCF_REG08(0x008618)
6688+#define MCF_PSC_CTLR0 MCF_REG08(0x00861C)
6689+#define MCF_PSC_IP0 MCF_REG08(0x008634)
6690+#define MCF_PSC_OPSET0 MCF_REG08(0x008638)
6691+#define MCF_PSC_OPRESET0 MCF_REG08(0x00863C)
6692+#define MCF_PSC_SICR0 MCF_REG08(0x008640)
6693+#define MCF_PSC_IRCR10 MCF_REG08(0x008644)
6694+#define MCF_PSC_IRCR20 MCF_REG08(0x008648)
6695+#define MCF_PSC_IRSDR0 MCF_REG08(0x00864C)
6696+#define MCF_PSC_IRMDR0 MCF_REG08(0x008650)
6697+#define MCF_PSC_IRFDR0 MCF_REG08(0x008654)
6698+#define MCF_PSC_RFCNT0 MCF_REG16(0x008658)
6699+#define MCF_PSC_TFCNT0 MCF_REG16(0x00865C)
6700+#define MCF_PSC_RFSR0 MCF_REG16(0x008664)
6701+#define MCF_PSC_TFSR0 MCF_REG16(0x008684)
6702+#define MCF_PSC_RFCR0 MCF_REG32(0x008668)
6703+#define MCF_PSC_TFCR0 MCF_REG32(0x008688)
6704+#define MCF_PSC_RFAR0 MCF_REG16(0x00866E)
6705+#define MCF_PSC_TFAR0 MCF_REG16(0x00868E)
6706+#define MCF_PSC_RFRP0 MCF_REG16(0x008672)
6707+#define MCF_PSC_TFRP0 MCF_REG16(0x008692)
6708+#define MCF_PSC_RFWP0 MCF_REG16(0x008676)
6709+#define MCF_PSC_TFWP0 MCF_REG16(0x008696)
6710+#define MCF_PSC_RLRFP0 MCF_REG16(0x00867A)
6711+#define MCF_PSC_TLRFP0 MCF_REG16(0x00869A)
6712+#define MCF_PSC_RLWFP0 MCF_REG16(0x00867E)
6713+#define MCF_PSC_TLWFP0 MCF_REG16(0x00869E)
6714+#define MCF_PSC_MR1 MCF_REG08(0x008700)
6715+#define MCF_PSC_SR1 MCF_REG16(0x008704)
6716+#define MCF_PSC_CSR1 MCF_REG08(0x008704)
6717+#define MCF_PSC_CR1 MCF_REG08(0x008708)
6718+#define MCF_PSC_RB1 MCF_REG32(0x00870C)
6719+#define MCF_PSC_TB1 MCF_REG32(0x00870C)
6720+#define MCF_PSC_TB_8BIT1 MCF_REG32(0x00870C)
6721+#define MCF_PSC_TB_16BIT1 MCF_REG32(0x00870C)
6722+#define MCF_PSC_TB_AC971 MCF_REG32(0x00870C)
6723+#define MCF_PSC_IPCR1 MCF_REG08(0x008710)
6724+#define MCF_PSC_ACR1 MCF_REG08(0x008710)
6725+#define MCF_PSC_ISR1 MCF_REG16(0x008714)
6726+#define MCF_PSC_IMR1 MCF_REG16(0x008714)
6727+#define MCF_PSC_CTUR1 MCF_REG08(0x008718)
6728+#define MCF_PSC_CTLR1 MCF_REG08(0x00871C)
6729+#define MCF_PSC_IP1 MCF_REG08(0x008734)
6730+#define MCF_PSC_OPSET1 MCF_REG08(0x008738)
6731+#define MCF_PSC_OPRESET1 MCF_REG08(0x00873C)
6732+#define MCF_PSC_SICR1 MCF_REG08(0x008740)
6733+#define MCF_PSC_IRCR11 MCF_REG08(0x008744)
6734+#define MCF_PSC_IRCR21 MCF_REG08(0x008748)
6735+#define MCF_PSC_IRSDR1 MCF_REG08(0x00874C)
6736+#define MCF_PSC_IRMDR1 MCF_REG08(0x008750)
6737+#define MCF_PSC_IRFDR1 MCF_REG08(0x008754)
6738+#define MCF_PSC_RFCNT1 MCF_REG16(0x008758)
6739+#define MCF_PSC_TFCNT1 MCF_REG16(0x00875C)
6740+#define MCF_PSC_RFSR1 MCF_REG16(0x008764)
6741+#define MCF_PSC_TFSR1 MCF_REG16(0x008784)
6742+#define MCF_PSC_RFCR1 MCF_REG32(0x008768)
6743+#define MCF_PSC_TFCR1 MCF_REG32(0x008788)
6744+#define MCF_PSC_RFAR1 MCF_REG16(0x00876E)
6745+#define MCF_PSC_TFAR1 MCF_REG16(0x00878E)
6746+#define MCF_PSC_RFRP1 MCF_REG16(0x008772)
6747+#define MCF_PSC_TFRP1 MCF_REG16(0x008792)
6748+#define MCF_PSC_RFWP1 MCF_REG16(0x008776)
6749+#define MCF_PSC_TFWP1 MCF_REG16(0x008796)
6750+#define MCF_PSC_RLRFP1 MCF_REG16(0x00877A)
6751+#define MCF_PSC_TLRFP1 MCF_REG16(0x00879A)
6752+#define MCF_PSC_RLWFP1 MCF_REG16(0x00877E)
6753+#define MCF_PSC_TLWFP1 MCF_REG16(0x00879E)
6754+#define MCF_PSC_MR2 MCF_REG08(0x008800)
6755+#define MCF_PSC_SR2 MCF_REG16(0x008804)
6756+#define MCF_PSC_CSR2 MCF_REG08(0x008804)
6757+#define MCF_PSC_CR2 MCF_REG08(0x008808)
6758+#define MCF_PSC_RB2 MCF_REG32(0x00880C)
6759+#define MCF_PSC_TB2 MCF_REG32(0x00880C)
6760+#define MCF_PSC_TB_8BIT2 MCF_REG32(0x00880C)
6761+#define MCF_PSC_TB_16BIT2 MCF_REG32(0x00880C)
6762+#define MCF_PSC_TB_AC972 MCF_REG32(0x00880C)
6763+#define MCF_PSC_IPCR2 MCF_REG08(0x008810)
6764+#define MCF_PSC_ACR2 MCF_REG08(0x008810)
6765+#define MCF_PSC_ISR2 MCF_REG16(0x008814)
6766+#define MCF_PSC_IMR2 MCF_REG16(0x008814)
6767+#define MCF_PSC_CTUR2 MCF_REG08(0x008818)
6768+#define MCF_PSC_CTLR2 MCF_REG08(0x00881C)
6769+#define MCF_PSC_IP2 MCF_REG08(0x008834)
6770+#define MCF_PSC_OPSET2 MCF_REG08(0x008838)
6771+#define MCF_PSC_OPRESET2 MCF_REG08(0x00883C)
6772+#define MCF_PSC_SICR2 MCF_REG08(0x008840)
6773+#define MCF_PSC_IRCR12 MCF_REG08(0x008844)
6774+#define MCF_PSC_IRCR22 MCF_REG08(0x008848)
6775+#define MCF_PSC_IRSDR2 MCF_REG08(0x00884C)
6776+#define MCF_PSC_IRMDR2 MCF_REG08(0x008850)
6777+#define MCF_PSC_IRFDR2 MCF_REG08(0x008854)
6778+#define MCF_PSC_RFCNT2 MCF_REG16(0x008858)
6779+#define MCF_PSC_TFCNT2 MCF_REG16(0x00885C)
6780+#define MCF_PSC_RFSR2 MCF_REG16(0x008864)
6781+#define MCF_PSC_TFSR2 MCF_REG16(0x008884)
6782+#define MCF_PSC_RFCR2 MCF_REG32(0x008868)
6783+#define MCF_PSC_TFCR2 MCF_REG32(0x008888)
6784+#define MCF_PSC_RFAR2 MCF_REG16(0x00886E)
6785+#define MCF_PSC_TFAR2 MCF_REG16(0x00888E)
6786+#define MCF_PSC_RFRP2 MCF_REG16(0x008872)
6787+#define MCF_PSC_TFRP2 MCF_REG16(0x008892)
6788+#define MCF_PSC_RFWP2 MCF_REG16(0x008876)
6789+#define MCF_PSC_TFWP2 MCF_REG16(0x008896)
6790+#define MCF_PSC_RLRFP2 MCF_REG16(0x00887A)
6791+#define MCF_PSC_TLRFP2 MCF_REG16(0x00889A)
6792+#define MCF_PSC_RLWFP2 MCF_REG16(0x00887E)
6793+#define MCF_PSC_TLWFP2 MCF_REG16(0x00889E)
6794+#define MCF_PSC_MR3 MCF_REG08(0x008900)
6795+#define MCF_PSC_SR3 MCF_REG16(0x008904)
6796+#define MCF_PSC_CSR3 MCF_REG08(0x008904)
6797+#define MCF_PSC_CR3 MCF_REG08(0x008908)
6798+#define MCF_PSC_RB3 MCF_REG32(0x00890C)
6799+#define MCF_PSC_TB3 MCF_REG32(0x00890C)
6800+#define MCF_PSC_TB_8BIT3 MCF_REG32(0x00890C)
6801+#define MCF_PSC_TB_16BIT3 MCF_REG32(0x00890C)
6802+#define MCF_PSC_TB_AC973 MCF_REG32(0x00890C)
6803+#define MCF_PSC_IPCR3 MCF_REG08(0x008910)
6804+#define MCF_PSC_ACR3 MCF_REG08(0x008910)
6805+#define MCF_PSC_ISR3 MCF_REG16(0x008914)
6806+#define MCF_PSC_IMR3 MCF_REG16(0x008914)
6807+#define MCF_PSC_CTUR3 MCF_REG08(0x008918)
6808+#define MCF_PSC_CTLR3 MCF_REG08(0x00891C)
6809+#define MCF_PSC_IP3 MCF_REG08(0x008934)
6810+#define MCF_PSC_OPSET3 MCF_REG08(0x008938)
6811+#define MCF_PSC_OPRESET3 MCF_REG08(0x00893C)
6812+#define MCF_PSC_SICR3 MCF_REG08(0x008940)
6813+#define MCF_PSC_IRCR13 MCF_REG08(0x008944)
6814+#define MCF_PSC_IRCR23 MCF_REG08(0x008948)
6815+#define MCF_PSC_IRSDR3 MCF_REG08(0x00894C)
6816+#define MCF_PSC_IRMDR3 MCF_REG08(0x008950)
6817+#define MCF_PSC_IRFDR3 MCF_REG08(0x008954)
6818+#define MCF_PSC_RFCNT3 MCF_REG16(0x008958)
6819+#define MCF_PSC_TFCNT3 MCF_REG16(0x00895C)
6820+#define MCF_PSC_RFSR3 MCF_REG16(0x008964)
6821+#define MCF_PSC_TFSR3 MCF_REG16(0x008984)
6822+#define MCF_PSC_RFCR3 MCF_REG32(0x008968)
6823+#define MCF_PSC_TFCR3 MCF_REG32(0x008988)
6824+#define MCF_PSC_RFAR3 MCF_REG16(0x00896E)
6825+#define MCF_PSC_TFAR3 MCF_REG16(0x00898E)
6826+#define MCF_PSC_RFRP3 MCF_REG16(0x008972)
6827+#define MCF_PSC_TFRP3 MCF_REG16(0x008992)
6828+#define MCF_PSC_RFWP3 MCF_REG16(0x008976)
6829+#define MCF_PSC_TFWP3 MCF_REG16(0x008996)
6830+#define MCF_PSC_RLRFP3 MCF_REG16(0x00897A)
6831+#define MCF_PSC_TLRFP3 MCF_REG16(0x00899A)
6832+#define MCF_PSC_RLWFP3 MCF_REG16(0x00897E)
6833+#define MCF_PSC_TLWFP3 MCF_REG16(0x00899E)
6834+#define MCF_PSC_MR(x) MCF_REG08(0x008600+((x)*0x100))
6835+#define MCF_PSC_SR(x) MCF_REG16(0x008604+((x)*0x100))
6836+#define MCF_PSC_CSR(x) MCF_REG08(0x008604+((x)*0x100))
6837+#define MCF_PSC_CR(x) MCF_REG08(0x008608+((x)*0x100))
6838+#define MCF_PSC_RB(x) MCF_REG32(0x00860C+((x)*0x100))
6839+#define MCF_PSC_TB(x) MCF_REG32(0x00860C+((x)*0x100))
6840+#define MCF_PSC_TB_8BIT(x) MCF_REG32(0x00860C+((x)*0x100))
6841+#define MCF_PSC_TB_16BIT(x) MCF_REG32(0x00860C+((x)*0x100))
6842+#define MCF_PSC_TB_AC97(x) MCF_REG32(0x00860C+((x)*0x100))
6843+#define MCF_PSC_IPCR(x) MCF_REG08(0x008610+((x)*0x100))
6844+#define MCF_PSC_ACR(x) MCF_REG08(0x008610+((x)*0x100))
6845+#define MCF_PSC_ISR(x) MCF_REG16(0x008614+((x)*0x100))
6846+#define MCF_PSC_IMR(x) MCF_REG16(0x008614+((x)*0x100))
6847+#define MCF_PSC_CTUR(x) MCF_REG08(0x008618+((x)*0x100))
6848+#define MCF_PSC_CTLR(x) MCF_REG08(0x00861C+((x)*0x100))
6849+#define MCF_PSC_IP(x) MCF_REG08(0x008634+((x)*0x100))
6850+#define MCF_PSC_OPSET(x) MCF_REG08(0x008638+((x)*0x100))
6851+#define MCF_PSC_OPRESET(x) MCF_REG08(0x00863C+((x)*0x100))
6852+#define MCF_PSC_SICR(x) MCF_REG08(0x008640+((x)*0x100))
6853+#define MCF_PSC_IRCR1(x) MCF_REG08(0x008644+((x)*0x100))
6854+#define MCF_PSC_IRCR2(x) MCF_REG08(0x008648+((x)*0x100))
6855+#define MCF_PSC_IRSDR(x) MCF_REG08(0x00864C+((x)*0x100))
6856+#define MCF_PSC_IRMDR(x) MCF_REG08(0x008650+((x)*0x100))
6857+#define MCF_PSC_IRFDR(x) MCF_REG08(0x008654+((x)*0x100))
6858+#define MCF_PSC_RFCNT(x) MCF_REG16(0x008658+((x)*0x100))
6859+#define MCF_PSC_TFCNT(x) MCF_REG16(0x00865C+((x)*0x100))
6860+#define MCF_PSC_RFSR(x) MCF_REG16(0x008664+((x)*0x100))
6861+#define MCF_PSC_TFSR(x) MCF_REG16(0x008684+((x)*0x100))
6862+#define MCF_PSC_RFCR(x) MCF_REG32(0x008668+((x)*0x100))
6863+#define MCF_PSC_TFCR(x) MCF_REG32(0x008688+((x)*0x100))
6864+#define MCF_PSC_RFAR(x) MCF_REG16((0x00866E)+((x)*0x100))
6865+#define MCF_PSC_TFAR(x) MCF_REG16((0x00868E)+((x)*0x100))
6866+#define MCF_PSC_RFRP(x) MCF_REG16(0x008672+((x)*0x100))
6867+#define MCF_PSC_TFRP(x) MCF_REG16(0x008692+((x)*0x100))
6868+#define MCF_PSC_RFWP(x) MCF_REG16(0x008676+((x)*0x100))
6869+#define MCF_PSC_TFWP(x) MCF_REG16(0x008696+((x)*0x100))
6870+#define MCF_PSC_RLRFP(x) MCF_REG16(0x00867A+((x)*0x100))
6871+#define MCF_PSC_TLRFP(x) MCF_REG16(0x00869A+((x)*0x100))
6872+#define MCF_PSC_RLWFP(x) MCF_REG16(0x00867E+((x)*0x100))
6873+#define MCF_PSC_TLWFP(x) MCF_REG16(0x00869E+((x)*0x100))
6874+
6875+/* Bit definitions and macros for MCF_PSC_MR */
6876+#define MCF_PSC_MR_BC(x) (((x)&0x03)<<0)
6877+#define MCF_PSC_MR_PT (0x04)
6878+#define MCF_PSC_MR_PM(x) (((x)&0x03)<<3)
6879+#define MCF_PSC_MR_ERR (0x20)
6880+#define MCF_PSC_MR_RXIRQ (0x40)
6881+#define MCF_PSC_MR_RXRTS (0x80)
6882+#define MCF_PSC_MR_SB(x) (((x)&0x0F)<<0)
6883+#define MCF_PSC_MR_TXCTS (0x10)
6884+#define MCF_PSC_MR_TXRTS (0x20)
6885+#define MCF_PSC_MR_CM(x) (((x)&0x03)<<6)
6886+#define MCF_PSC_MR_PM_MULTI_ADDR (0x1C)
6887+#define MCF_PSC_MR_PM_MULTI_DATA (0x18)
6888+#define MCF_PSC_MR_PM_NONE (0x10)
6889+#define MCF_PSC_MR_PM_FORCE_HI (0x0C)
6890+#define MCF_PSC_MR_PM_FORCE_LO (0x08)
6891+#define MCF_PSC_MR_PM_ODD (0x04)
6892+#define MCF_PSC_MR_PM_EVEN (0x00)
6893+#define MCF_PSC_MR_BC_5 (0x00)
6894+#define MCF_PSC_MR_BC_6 (0x01)
6895+#define MCF_PSC_MR_BC_7 (0x02)
6896+#define MCF_PSC_MR_BC_8 (0x03)
6897+#define MCF_PSC_MR_CM_NORMAL (0x00)
6898+#define MCF_PSC_MR_CM_ECHO (0x40)
6899+#define MCF_PSC_MR_CM_LOCAL_LOOP (0x80)
6900+#define MCF_PSC_MR_CM_REMOTE_LOOP (0xC0)
6901+#define MCF_PSC_MR_SB_STOP_BITS_1 (0x07)
6902+#define MCF_PSC_MR_SB_STOP_BITS_15 (0x08)
6903+#define MCF_PSC_MR_SB_STOP_BITS_2 (0x0F)
6904+
6905+/* Bit definitions and macros for MCF_PSC_SR */
6906+#define MCF_PSC_SR_ERR (0x0040)
6907+#define MCF_PSC_SR_CDE_DEOF (0x0080)
6908+#define MCF_PSC_SR_RXRDY (0x0100)
6909+#define MCF_PSC_SR_FU (0x0200)
6910+#define MCF_PSC_SR_TXRDY (0x0400)
6911+#define MCF_PSC_SR_TXEMP_URERR (0x0800)
6912+#define MCF_PSC_SR_OE (0x1000)
6913+#define MCF_PSC_SR_PE_CRCERR (0x2000)
6914+#define MCF_PSC_SR_FE_PHYERR (0x4000)
6915+#define MCF_PSC_SR_RB_NEOF (0x8000)
6916+
6917+/* Bit definitions and macros for MCF_PSC_CSR */
6918+#define MCF_PSC_CSR_TCSEL(x) (((x)&0x0F)<<0)
6919+#define MCF_PSC_CSR_RCSEL(x) (((x)&0x0F)<<4)
6920+#define MCF_PSC_CSR_RCSEL_SYS_CLK (0xD0)
6921+#define MCF_PSC_CSR_RCSEL_CTM16 (0xE0)
6922+#define MCF_PSC_CSR_RCSEL_CTM (0xF0)
6923+#define MCF_PSC_CSR_TCSEL_SYS_CLK (0x0D)
6924+#define MCF_PSC_CSR_TCSEL_CTM16 (0x0E)
6925+#define MCF_PSC_CSR_TCSEL_CTM (0x0F)
6926+
6927+/* Bit definitions and macros for MCF_PSC_CR */
6928+#define MCF_PSC_CR_RXC(x) (((x)&0x03)<<0)
6929+#define MCF_PSC_CR_TXC(x) (((x)&0x03)<<2)
6930+#define MCF_PSC_CR_MISC(x) (((x)&0x07)<<4)
6931+#define MCF_PSC_CR_NONE (0x00)
6932+#define MCF_PSC_CR_STOP_BREAK (0x70)
6933+#define MCF_PSC_CR_START_BREAK (0x60)
6934+#define MCF_PSC_CR_BKCHGINT (0x50)
6935+#define MCF_PSC_CR_RESET_ERROR (0x40)
6936+#define MCF_PSC_CR_RESET_TX (0x30)
6937+#define MCF_PSC_CR_RESET_RX (0x20)
6938+#define MCF_PSC_CR_RESET_MR (0x10)
6939+#define MCF_PSC_CR_TX_DISABLED (0x08)
6940+#define MCF_PSC_CR_TX_ENABLED (0x04)
6941+#define MCF_PSC_CR_RX_DISABLED (0x02)
6942+#define MCF_PSC_CR_RX_ENABLED (0x01)
6943+
6944+/* Bit definitions and macros for MCF_PSC_TB_8BIT */
6945+#define MCF_PSC_TB_8BIT_TB3(x) (((x)&0x000000FF)<<0)
6946+#define MCF_PSC_TB_8BIT_TB2(x) (((x)&0x000000FF)<<8)
6947+#define MCF_PSC_TB_8BIT_TB1(x) (((x)&0x000000FF)<<16)
6948+#define MCF_PSC_TB_8BIT_TB0(x) (((x)&0x000000FF)<<24)
6949+
6950+/* Bit definitions and macros for MCF_PSC_TB_16BIT */
6951+#define MCF_PSC_TB_16BIT_TB1(x) (((x)&0x0000FFFF)<<0)
6952+#define MCF_PSC_TB_16BIT_TB0(x) (((x)&0x0000FFFF)<<16)
6953+
6954+/* Bit definitions and macros for MCF_PSC_TB_AC97 */
6955+#define MCF_PSC_TB_AC97_SOF (0x00000800)
6956+#define MCF_PSC_TB_AC97_TB(x) (((x)&0x000FFFFF)<<12)
6957+
6958+/* Bit definitions and macros for MCF_PSC_IPCR */
6959+#define MCF_PSC_IPCR_RESERVED (0x0C)
6960+#define MCF_PSC_IPCR_CTS (0x0D)
6961+#define MCF_PSC_IPCR_D_CTS (0x1C)
6962+#define MCF_PSC_IPCR_SYNC (0x8C)
6963+
6964+/* Bit definitions and macros for MCF_PSC_ACR */
6965+#define MCF_PSC_ACR_IEC0 (0x01)
6966+#define MCF_PSC_ACR_CTMS(x) (((x)&0x07)<<4)
6967+#define MCF_PSC_ACR_BRG (0x80)
6968+
6969+/* Bit definitions and macros for MCF_PSC_ISR */
6970+#define MCF_PSC_ISR_ERR (0x0040)
6971+#define MCF_PSC_ISR_DEOF (0x0080)
6972+#define MCF_PSC_ISR_TXRDY (0x0100)
6973+#define MCF_PSC_ISR_RXRDY_FU (0x0200)
6974+#define MCF_PSC_ISR_DB (0x0400)
6975+#define MCF_PSC_ISR_IPC (0x8000)
6976+
6977+/* Bit definitions and macros for MCF_PSC_IMR */
6978+#define MCF_PSC_IMR_ERR (0x0040)
6979+#define MCF_PSC_IMR_DEOF (0x0080)
6980+#define MCF_PSC_IMR_TXRDY (0x0100)
6981+#define MCF_PSC_IMR_RXRDY_FU (0x0200)
6982+#define MCF_PSC_IMR_DB (0x0400)
6983+#define MCF_PSC_IMR_IPC (0x8000)
6984+
6985+/* Bit definitions and macros for MCF_PSC_IP */
6986+#define MCF_PSC_IP_CTS (0x01)
6987+#define MCF_PSC_IP_TGL (0x40)
6988+#define MCF_PSC_IP_LWPR_B (0x80)
6989+
6990+/* Bit definitions and macros for MCF_PSC_OPSET */
6991+#define MCF_PSC_OPSET_RTS (0x01)
6992+
6993+/* Bit definitions and macros for MCF_PSC_OPRESET */
6994+#define MCF_PSC_OPRESET_RTS (0x01)
6995+
6996+/* Bit definitions and macros for MCF_PSC_SICR */
6997+#define MCF_PSC_SICR_SIM(x) (((x)&0x07)<<0)
6998+#define MCF_PSC_SICR_SHDIR (0x10)
6999+#define MCF_PSC_SICR_DTS (0x20)
7000+#define MCF_PSC_SICR_AWR (0x40)
7001+#define MCF_PSC_SICR_ACRB (0x80)
7002+#define MCF_PSC_SICR_SIM_UART (0x00)
7003+#define MCF_PSC_SICR_SIM_MODEM8 (0x01)
7004+#define MCF_PSC_SICR_SIM_MODEM16 (0x02)
7005+#define MCF_PSC_SICR_SIM_AC97 (0x03)
7006+#define MCF_PSC_SICR_SIM_SIR (0x04)
7007+#define MCF_PSC_SICR_SIM_MIR (0x05)
7008+#define MCF_PSC_SICR_SIM_FIR (0x06)
7009+
7010+/* Bit definitions and macros for MCF_PSC_IRCR1 */
7011+#define MCF_PSC_IRCR1_SPUL (0x01)
7012+#define MCF_PSC_IRCR1_SIPEN (0x02)
7013+#define MCF_PSC_IRCR1_FD (0x04)
7014+
7015+/* Bit definitions and macros for MCF_PSC_IRCR2 */
7016+#define MCF_PSC_IRCR2_NXTEOF (0x01)
7017+#define MCF_PSC_IRCR2_ABORT (0x02)
7018+#define MCF_PSC_IRCR2_SIPREQ (0x04)
7019+
7020+/* Bit definitions and macros for MCF_PSC_IRMDR */
7021+#define MCF_PSC_IRMDR_M_FDIV(x) (((x)&0x7F)<<0)
7022+#define MCF_PSC_IRMDR_FREQ (0x80)
7023+
7024+/* Bit definitions and macros for MCF_PSC_IRFDR */
7025+#define MCF_PSC_IRFDR_F_FDIV(x) (((x)&0x0F)<<0)
7026+
7027+/* Bit definitions and macros for MCF_PSC_RFCNT */
7028+#define MCF_PSC_RFCNT_CNT(x) (((x)&0x01FF)<<0)
7029+
7030+/* Bit definitions and macros for MCF_PSC_TFCNT */
7031+#define MCF_PSC_TFCNT_CNT(x) (((x)&0x01FF)<<0)
7032+
7033+/* Bit definitions and macros for MCF_PSC_RFSR */
7034+#define MCF_PSC_RFSR_EMT (0x0001)
7035+#define MCF_PSC_RFSR_ALARM (0x0002)
7036+#define MCF_PSC_RFSR_FU (0x0004)
7037+#define MCF_PSC_RFSR_FRMRY (0x0008)
7038+#define MCF_PSC_RFSR_OF (0x0010)
7039+#define MCF_PSC_RFSR_UF (0x0020)
7040+#define MCF_PSC_RFSR_RXW (0x0040)
7041+#define MCF_PSC_RFSR_FAE (0x0080)
7042+#define MCF_PSC_RFSR_FRM(x) (((x)&0x000F)<<8)
7043+#define MCF_PSC_RFSR_TAG (0x1000)
7044+#define MCF_PSC_RFSR_TXW (0x4000)
7045+#define MCF_PSC_RFSR_IP (0x8000)
7046+#define MCF_PSC_RFSR_FRM_BYTE0 (0x0800)
7047+#define MCF_PSC_RFSR_FRM_BYTE1 (0x0400)
7048+#define MCF_PSC_RFSR_FRM_BYTE2 (0x0200)
7049+#define MCF_PSC_RFSR_FRM_BYTE3 (0x0100)
7050+
7051+/* Bit definitions and macros for MCF_PSC_TFSR */
7052+#define MCF_PSC_TFSR_EMT (0x0001)
7053+#define MCF_PSC_TFSR_ALARM (0x0002)
7054+#define MCF_PSC_TFSR_FU (0x0004)
7055+#define MCF_PSC_TFSR_FRMRY (0x0008)
7056+#define MCF_PSC_TFSR_OF (0x0010)
7057+#define MCF_PSC_TFSR_UF (0x0020)
7058+#define MCF_PSC_TFSR_RXW (0x0040)
7059+#define MCF_PSC_TFSR_FAE (0x0080)
7060+#define MCF_PSC_TFSR_FRM(x) (((x)&0x000F)<<8)
7061+#define MCF_PSC_TFSR_TAG (0x1000)
7062+#define MCF_PSC_TFSR_TXW (0x4000)
7063+#define MCF_PSC_TFSR_IP (0x8000)
7064+#define MCF_PSC_TFSR_FRM_BYTE0 (0x0800)
7065+#define MCF_PSC_TFSR_FRM_BYTE1 (0x0400)
7066+#define MCF_PSC_TFSR_FRM_BYTE2 (0x0200)
7067+#define MCF_PSC_TFSR_FRM_BYTE3 (0x0100)
7068+
7069+/* Bit definitions and macros for MCF_PSC_RFCR */
7070+#define MCF_PSC_RFCR_CNTR(x) (((x)&0x0000FFFF)<<0)
7071+#define MCF_PSC_RFCR_TXW_MSK (0x00040000)
7072+#define MCF_PSC_RFCR_OF_MSK (0x00080000)
7073+#define MCF_PSC_RFCR_UF_MSK (0x00100000)
7074+#define MCF_PSC_RFCR_RXW_MSK (0x00200000)
7075+#define MCF_PSC_RFCR_FAE_MSK (0x00400000)
7076+#define MCF_PSC_RFCR_IP_MSK (0x00800000)
7077+#define MCF_PSC_RFCR_GR(x) (((x)&0x00000007)<<24)
7078+#define MCF_PSC_RFCR_FRMEN (0x08000000)
7079+#define MCF_PSC_RFCR_TIMER (0x10000000)
7080+#define MCF_PSC_RFCR_WRITETAG (0x20000000)
7081+#define MCF_PSC_RFCR_SHADOW (0x80000000)
7082+
7083+/* Bit definitions and macros for MCF_PSC_TFCR */
7084+#define MCF_PSC_TFCR_CNTR(x) (((x)&0x0000FFFF)<<0)
7085+#define MCF_PSC_TFCR_TXW_MSK (0x00040000)
7086+#define MCF_PSC_TFCR_OF_MSK (0x00080000)
7087+#define MCF_PSC_TFCR_UF_MSK (0x00100000)
7088+#define MCF_PSC_TFCR_RXW_MSK (0x00200000)
7089+#define MCF_PSC_TFCR_FAE_MSK (0x00400000)
7090+#define MCF_PSC_TFCR_IP_MSK (0x00800000)
7091+#define MCF_PSC_TFCR_GR(x) (((x)&0x00000007)<<24)
7092+#define MCF_PSC_TFCR_FRMEN (0x08000000)
7093+#define MCF_PSC_TFCR_TIMER (0x10000000)
7094+#define MCF_PSC_TFCR_WRITETAG (0x20000000)
7095+#define MCF_PSC_TFCR_SHADOW (0x80000000)
7096+
7097+/* Bit definitions and macros for MCF_PSC_RFAR */
7098+#define MCF_PSC_RFAR_ALARM(x) (((x)&0x01FF)<<0)
7099+
7100+/* Bit definitions and macros for MCF_PSC_TFAR */
7101+#define MCF_PSC_TFAR_ALARM(x) (((x)&0x01FF)<<0)
7102+
7103+/* Bit definitions and macros for MCF_PSC_RFRP */
7104+#define MCF_PSC_RFRP_READ(x) (((x)&0x01FF)<<0)
7105+
7106+/* Bit definitions and macros for MCF_PSC_TFRP */
7107+#define MCF_PSC_TFRP_READ(x) (((x)&0x01FF)<<0)
7108+
7109+/* Bit definitions and macros for MCF_PSC_RFWP */
7110+#define MCF_PSC_RFWP_WRITE(x) (((x)&0x01FF)<<0)
7111+
7112+/* Bit definitions and macros for MCF_PSC_TFWP */
7113+#define MCF_PSC_TFWP_WRITE(x) (((x)&0x01FF)<<0)
7114+
7115+/* Bit definitions and macros for MCF_PSC_RLRFP */
7116+#define MCF_PSC_RLRFP_LFP(x) (((x)&0x01FF)<<0)
7117+
7118+/* Bit definitions and macros for MCF_PSC_TLRFP */
7119+#define MCF_PSC_TLRFP_LFP(x) (((x)&0x01FF)<<0)
7120+
7121+/* Bit definitions and macros for MCF_PSC_RLWFP */
7122+#define MCF_PSC_RLWFP_LFP(x) (((x)&0x01FF)<<0)
7123+
7124+/* Bit definitions and macros for MCF_PSC_TLWFP */
7125+#define MCF_PSC_TLWFP_LFP(x) (((x)&0x01FF)<<0)
7126+
7127+/********************************************************************/
7128+
7129+#endif /* __MCF548X_PSC_H__ */
7130--- /dev/null
7131+++ b/arch/m68k/include/asm/m5485sec.h
7132@@ -0,0 +1,177 @@
7133+/*
7134+ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
7135+ */
7136+
7137+#ifndef M5485SEC_H
7138+#define M5484SEC_H
7139+
7140+#define SEC_EUACR_U MCF_REG32(0x21000)
7141+#define SEC_EUACR_L MCF_REG32(0x21004)
7142+#define SEC_EUASR_U MCF_REG32(0x21028)
7143+#define SEC_EUASR_L MCF_REG32(0x2102C)
7144+#define SEC_SMCR MCF_REG32(0x21030)
7145+#define SEC_SISR_U MCF_REG32(0x21010)
7146+#define SEC_SISR_L MCF_REG32(0x21014)
7147+#define SEC_SICR_U MCF_REG32(0x21018)
7148+#define SEC_SICR_L MCF_REG32(0x2101C)
7149+#define SEC_SIMR_U MCF_REG32(0x21008)
7150+#define SEC_SIMR_L MCF_REG32(0x2100C)
7151+#define SEC_SID MCF_REG32(0x21020)
7152+
7153+#define SEC_SMCR_RESET 0x01000000
7154+#define SEC_SIMR_MASK_U 0x00000000
7155+#define SEC_SIMR_MASK_L 0x03333340
7156+
7157+#define SEC_CC0_FR MCF_REG32(0x2204C)
7158+#define SEC_CC0_CR MCF_REG32(0x2200C)
7159+#define SEC_CC0_CDPR MCF_REG32(0x22044)
7160+#define SEC_CC0_PSR_U MCF_REG32(0x22010)
7161+#define SEC_CC0_PSR_L MCF_REG32(0x22014)
7162+#define SEC_CC1_FR MCF_REG32(0x2304C)
7163+#define SEC_CC1_CR MCF_REG32(0x2300C)
7164+#define SEC_CC1_CDPR MCF_REG32(0x23044)
7165+#define SEC_CC1_PSR_U MCF_REG32(0x23010)
7166+#define SEC_CC1_PSR_L MCF_REG32(0x23014)
7167+
7168+#define SEC_CC_CR_RESET 0x00000001
7169+#define SEC_CC_CR_CONFIGURATION 0x0000001E
7170+#define SEC_CC_PSR_U_ERR_CH0 0x20000000
7171+#define SEC_CC_PSR_U_ERR_CH1 0x80000000
7172+#define SEC_CC_PSR_U_DN_CH0 0x10000000
7173+#define SEC_CC_PSR_U_DN_CH1 0x40000000
7174+
7175+#define SEC_DEU_DRCR MCF_REG32(0x2A018)
7176+#define SEC_DEU_DSR MCF_REG32(0x2A028)
7177+#define SEC_DEU_DISR MCF_REG32(0x2A030)
7178+#define SEC_DEU_DIMR MCF_REG32(0x2A038)
7179+
7180+#define SEC_DEU_DRCR_RESET 0x01000000
7181+#define SEC_DEU_DSR_RD 0x01000000
7182+#define SEC_DEU_DIMR_MASK 0xF63F0000
7183+
7184+#define SEC_AFEU_AFRCR MCF_REG32(0x28018)
7185+#define SEC_AFEU_AFSR MCF_REG32(0x28028)
7186+#define SEC_AFEU_AFISR MCF_REG32(0x28030)
7187+#define SEC_AFEU_AFIMR MCF_REG32(0x28038)
7188+
7189+#define SEC_AFEU_AFRCR_RESET 0x01000000
7190+#define SEC_AFEU_AFSR_RD 0x01000000
7191+#define SEC_AFEU_AFIMR_MASK 0xF61F0000
7192+
7193+
7194+#define SEC_MDEU_MDRCR MCF_REG32(0x2C018)
7195+#define SEC_MDEU_MDSR MCF_REG32(0x2C028)
7196+#define SEC_MDEU_MDISR MCF_REG32(0x2C030)
7197+#define SEC_MDEU_MDIMR MCF_REG32(0x2C038)
7198+
7199+#define SEC_MDEU_MDRCR_RESET 0x01000000
7200+#define SEC_MDEU_MDSR_RD 0x01000000
7201+#define SEC_MDEU_MDIMR_MASK 0xC41F0000
7202+
7203+
7204+#define SEC_RNG_RNGRCR MCF_REG32(0x2E018)
7205+#define SEC_RNG_RNGSR MCF_REG32(0x2E028)
7206+#define SEC_RNG_RNGISR MCF_REG32(0x2E030)
7207+#define SEC_RNG_RNGIMR MCF_REG32(0x2E038)
7208+
7209+#define SEC_RNG_RNGRCR_RESET 0x01000000
7210+#define SEC_RNG_RNGSR_RD 0x01000000
7211+#define SEC_RNG_RNGIMR_MASK 0xC2100000
7212+
7213+#define SEC_AESU_AESRCR MCF_REG32(0x32018)
7214+#define SEC_AESU_AESSR MCF_REG32(0x32028)
7215+#define SEC_AESU_AESISR MCF_REG32(0x32030)
7216+#define SEC_AESU_AESIMR MCF_REG32(0x32038)
7217+
7218+#define SEC_AESU_AESRCR_RESET 0x01000000
7219+#define SEC_AESU_AESSR_RD 0x01000000
7220+#define SEC_AESU_AESIMR_MASK 0xF61F0000
7221+
7222+
7223+#define SEC_DESC_NUM 20
7224+#define SEC_CHANNEL_NUMBER 2
7225+#define SEC_MAX_BUF_SIZE (32 * 1024)
7226+#define SEC_INIT_TIMEOUT (1 * HZ)
7227+#define SEC_INTERRUPT 37
7228+
7229+/* Header descriptor values*/
7230+#define SEC_ALG_ENCR_DES_ECB_SINGLE 0x20100010
7231+#define SEC_ALG_DECR_DES_ECB_SINGLE 0x20000010
7232+#define SEC_ALG_ENCR_DES_ECB_TRIPLE 0x20300010
7233+#define SEC_ALG_DECR_DES_ECB_TRIPLE 0x20200010
7234+#define SEC_ALG_ENCR_DES_CBC_SINGLE 0x20500010
7235+#define SEC_ALG_DECR_DES_CBC_SINGLE 0x20400010
7236+#define SEC_ALG_ENCR_DES_CBC_TRIPLE 0x20700010
7237+#define SEC_ALG_DECR_DES_CBC_TRIPLE 0x20600010
7238+
7239+#define SEC_ALG_MDEU_SHA256 0x30500010
7240+#define SEC_ALG_MDEU_MD5 0x30600010
7241+#define SEC_ALG_MDEU_SHA 0x30400010
7242+#define SEC_ALG_MDEU_SHA256_HMAC 0x31D00010
7243+#define SEC_ALG_MDEU_MD5_HMAC 0x31E00010
7244+#define SEC_ALG_MDEU_SHA_HMAC 0x31C00010
7245+
7246+#define SEC_ALG_RNG 0x40000010
7247+
7248+
7249+#define SEC_ALG_AFEU_KEY 0x10200050
7250+#define SEC_ALG_AFEU_CONTEXT 0x10700050
7251+
7252+#define SEC_ALG_ENCR_AESU_CBC 0x60300010
7253+#define SEC_ALG_DECR_AESU_CBC 0x60200010
7254+#define SEC_ALG_ENCR_AESU_ECB 0x60100010
7255+#define SEC_ALG_DECR_AESU_ECB 0x60000010
7256+#define SEC_ALG_AESU_CTR 0x60600010
7257+
7258+
7259+
7260+#define SEC_DESCHEAD_ERROR 0xFE000000
7261+#define SEC_DESCHEAD_COMPLETED 0xFF000000
7262+
7263+#define SEC_DEVICE_NAME "cfsec"
7264+
7265+/*!!! This number must be changed*/
7266+#define SEC_MAJOR 130
7267+
7268+#define SEC_DEV_BUF 1024
7269+#define SEC_DEV_KEY_LEN 64
7270+#define SEC_DEV_VECTOR_LEN 259
7271+
7272+#define SEC_AES_BLCK_LEN 16
7273+#define SEC_DES_BLCK_LEN 8
7274+
7275+
7276+/* Descriptor structure of SEC*/
7277+struct sec_descriptor {
7278+ volatile unsigned long secdesc_header;
7279+ unsigned long secdesc_len1;
7280+ void *secdesc_ptr1;
7281+ unsigned long secdesc_iv_in_len;
7282+ void *secdesc_iv_in_ptr;
7283+ unsigned long secdesc_key_len;
7284+ void *secdesc_key_ptr;
7285+ unsigned long secdesc_data_in_len;
7286+ void *secdesc_data_in_ptr;
7287+ unsigned long secdesc_data_out_len;
7288+ void *secdesc_data_out_ptr;
7289+ unsigned long secdesc_iv_out_len;
7290+ void *secdesc_iv_out_ptr;
7291+ unsigned long secdesc_len7;
7292+ void *secdesc_ptr7;
7293+ void *secdesc_ptrnext;
7294+};
7295+
7296+struct sec_device_data {
7297+ unsigned char secdev_inbuf[SEC_DEV_BUF];
7298+ unsigned char secdev_outbuf[SEC_DEV_BUF];
7299+ unsigned char secdev_key[SEC_DEV_KEY_LEN];
7300+ unsigned char secdev_iv[SEC_DEV_VECTOR_LEN];
7301+ unsigned char secdev_ov[SEC_DEV_VECTOR_LEN];
7302+ struct sec_descriptor *secdev_desc;
7303+};
7304+
7305+struct sec_descriptor *sec_desc_alloc(void);
7306+inline void sec_desc_free(struct sec_descriptor *desc);
7307+int sec_execute(int channel, struct sec_descriptor *desc, int timeout);
7308+int sec_nonblock_execute(struct sec_descriptor *desc);
7309+#endif
7310--- /dev/null
7311+++ b/arch/m68k/include/asm/m5485sim.h
7312@@ -0,0 +1,346 @@
7313+/*
7314+ * m5485sim.h -- ColdFire 547x/548x System Integration Unit support.
7315+ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
7316+ */
7317+#ifndef m5485sim_h
7318+#define m5485sim_h
7319+/*
7320+ * System Integration Unit Registers
7321+ */
7322+#define MCF_SDRAMDS MCF_REG32(0x000004)
7323+/* SDRAM Drive Strength */
7324+#define MCF_SBCR MCF_REG32(0x000010)
7325+/* System Breakpoint Control */
7326+#define MCF_CSnCFG(x) MCF_REG32(0x000020+(x*4))
7327+/* SDRAM Chip Select X */
7328+#define MCF_SECSACR MCF_REG32(0x000038)
7329+/* Sequential Access Control */
7330+#define MCF_RSR MCF_REG32(0x000044)
7331+/* Reset Status */
7332+#define MCF_JTAGID MCF_REG32(0x000050)
7333+/* JTAG Device Identification */
7334+#define MCF_XARB_PRIEN MCF_REG32(0x000264)
7335+/* Arbiter master pri enable */
7336+#define MCF_XARB_PRI MCF_REG32(0x000268)
7337+/* Arbiter master pri levels */
7338+#define MCF_SPCR MCF_REG32(0x000300)
7339+
7340+/*
7341+ * FlexBus Chip Selects Registers
7342+ */
7343+#define MCF_CSARn(x) MCF_REG32(0x000500+(x*0xC))
7344+#define MCF_CSMRn(x) MCF_REG32(0x000504+(x*0xC))
7345+#define MCF_CSCRn(x) MCF_REG32(0x000508+(x*0xC))
7346+
7347+/*
7348+ * Interrupt Controller Registers
7349+ */
7350+#define MCF_IPRH MCF_REG32(0x000700)
7351+#define MCF_IPRL MCF_REG32(0x000704)
7352+#define MCF_IMRH MCF_REG32(0x000708)
7353+#define MCF_IMRL MCF_REG32(0x00070C)
7354+#define MCF_INTFRCH MCF_REG32(0x000710)
7355+#define MCF_INTFRCL MCF_REG32(0x000714)
7356+#define MCF_IRLR MCF_REG08(0x000718)
7357+#define MCF_IACKLPR MCF_REG08(0x000719)
7358+#define MCF_SWIACK MCF_REG08(0x0007E0)
7359+#define MCF_LnIACK(x) MCF_REG08(0x0007E4+((x)*0x004))
7360+#define MCF_ICR(x) MCF_REG08(0x000740+((x)*0x001))
7361+
7362+/*
7363+ * Slice Timers Registers
7364+ */
7365+#define MCF_SLTCNT(x) MCF_REG32(0x000900+((x)*0x010))
7366+#define MCF_SCR(x) MCF_REG32(0x000904+((x)*0x010))
7367+#define MCF_SCNT(x) MCF_REG32(0x000908+((x)*0x010))
7368+#define MCF_SSR(x) MCF_REG32(0x00090C+((x)*0x010))
7369+
7370+/*
7371+ * Interrupt sources
7372+ */
7373+#define ISC_EPORT_Fn(x) (x)
7374+/* EPORT Interrupts */
7375+#define ISC_USB_EPn(x) (15+(x))
7376+/* USB Endopint */
7377+#define ISC_USB_ISR (22)
7378+/* USB General source */
7379+#define ISC_USB_AISR (22)
7380+/* USB core source */
7381+#define ISC_DSPI_OVRFW (25)
7382+/* DSPI overflow */
7383+#define ISC_DSPI_RFOF (26)
7384+#define ISC_DSPI_RFDF (27)
7385+#define ISC_DSPI_TFUF (28)
7386+#define ISC_DSPI_TCF (29)
7387+#define ISC_DSPI_TFFF (30)
7388+#define ISC_DSPI_EOQF (31)
7389+#define ISC_PSCn(x) (35-(x))
7390+#define ISC_COMM_TIM (36)
7391+#define ISC_SEC (37)
7392+#define ISC_FEC1 (38)
7393+#define ISC_FEC0 (39)
7394+#define ISC_I2C (40)
7395+#define ISC_PCI_ARB (41)
7396+#define ISC_PCI_CB (42)
7397+#define ISC_PCI_XLB (43)
7398+#define ISC_DMA (48)
7399+#define ISC_CANn_ERR(x) (49+(6*(x)))
7400+#define ISC_CANn_BUSOFF(x) (50+(6*(x)))
7401+#define ISC_CANn_MBOR(x) (51+(6*(x)))
7402+#define ISC_CAN0_WAKEIN (52)
7403+#define ISC_SLTn(x) (54-(x))
7404+#define ISC_GPTn(x) (62-(x))
7405+
7406+/*
7407+ * Interrupt level and priorities
7408+ */
7409+#define ILP_TOP (MCF_ICR_IL(5) | MCF_ICR_IP(3))
7410+#define ILP_SLT0 (MCF_ICR_IL(5) | MCF_ICR_IP(2))
7411+#define ILP_SLT1 (MCF_ICR_IL(5) | MCF_ICR_IP(1))
7412+#define ILP_DMA (MCF_ICR_IL(5) | MCF_ICR_IP(0))
7413+#define ILP_SEC (MCF_ICR_IL(4) | MCF_ICR_IP(7))
7414+#define ILP_FEC0 (MCF_ICR_IL(4) | MCF_ICR_IP(6))
7415+#define ILP_FEC1 (MCF_ICR_IL(4) | MCF_ICR_IP(5))
7416+#define ILP_PCI_XLB (MCF_ICR_IL(4) | MCF_ICR_IP(4))
7417+#define ILP_PCI_ARB (MCF_ICR_IL(4) | MCF_ICR_IP(3))
7418+#define ILP_PCI_CB (MCF_ICR_IL(4) | MCF_ICR_IP(2))
7419+#define ILP_I2C (MCF_ICR_IL(4) | MCF_ICR_IP(1))
7420+
7421+#define ILP_USB_EPn(x) (MCF_ICR_IL(3) | MCF_ICR_IP(7-(x)))
7422+#define ILP_USB_EP0 (MCF_ICR_IL(3) | MCF_ICR_IP(7))
7423+#define ILP_USB_EP1 (MCF_ICR_IL(3) | MCF_ICR_IP(6))
7424+#define ILP_USB_EP2 (MCF_ICR_IL(3) | MCF_ICR_IP(5))
7425+#define ILP_USB_EP3 (MCF_ICR_IL(3) | MCF_ICR_IP(4))
7426+#define ILP_USB_EP4 (MCF_ICR_IL(3) | MCF_ICR_IP(3))
7427+#define ILP_USB_EP5 (MCF_ICR_IL(3) | MCF_ICR_IP(2))
7428+#define ILP_USB_EP6 (MCF_ICR_IL(3) | MCF_ICR_IP(1))
7429+#define ILP_USB_ISR (MCF_ICR_IL(3) | MCF_ICR_IP(0))
7430+
7431+#define ILP_USB_AISR (MCF_ICR_IL(2) | MCF_ICR_IP(7))
7432+#define ILP_DSPI_OVRFW (MCF_ICR_IL(2) | MCF_ICR_IP(6))
7433+#define ILP_DSPI_RFOF (MCF_ICR_IL(2) | MCF_ICR_IP(5))
7434+#define ILP_DSPI_RFDF (MCF_ICR_IL(2) | MCF_ICR_IP(4))
7435+#define ILP_DSPI_TFUF (MCF_ICR_IL(2) | MCF_ICR_IP(3))
7436+#define ILP_DSPI_TCF (MCF_ICR_IL(2) | MCF_ICR_IP(2))
7437+#define ILP_DSPI_TFFF (MCF_ICR_IL(2) | MCF_ICR_IP(1))
7438+#define ILP_DSPI_EOQF (MCF_ICR_IL(2) | MCF_ICR_IP(0))
7439+
7440+#define ILP_COMM_TIM (MCF_ICR_IL(1) | MCF_ICR_IP(7))
7441+#define ILP_PSCn(x) (MCF_ICR_IL(1) | MCF_ICR_IP(3-((x)&3)))
7442+#define ILP_PSC0 (MCF_ICR_IL(1) | MCF_ICR_IP(3))
7443+#define ILP_PSC1 (MCF_ICR_IL(1) | MCF_ICR_IP(2))
7444+#define ILP_PSC2 (MCF_ICR_IL(1) | MCF_ICR_IP(1))
7445+#define ILP_PSC3 (MCF_ICR_IL(1) | MCF_ICR_IP(0))
7446+
7447+
7448+
7449+
7450+
7451+/********************************************************************/
7452+
7453+/*
7454+ * System Integration Unit Bitfields
7455+ */
7456+
7457+/* SBCR */
7458+#define MCF_SBCR_PIN2DSPI (0x08000000)
7459+#define MCF_SBCR_DMA2CPU (0x10000000)
7460+#define MCF_SBCR_CPU2DMA (0x20000000)
7461+#define MCF_SBCR_PIN2DMA (0x40000000)
7462+#define MCF_SBCR_PIN2CPU (0x80000000)
7463+
7464+/* SECSACR */
7465+#define MCF_SECSACR_SEQEN (0x00000001)
7466+
7467+/* RSR */
7468+#define MCF_RSR_RST (0x00000001)
7469+#define MCF_RSR_RSTWD (0x00000002)
7470+#define MCF_RSR_RSTJTG (0x00000008)
7471+
7472+/* JTAGID */
7473+#define MCF_JTAGID_REV (0xF0000000)
7474+#define MCF_JTAGID_PROCESSOR (0x0FFFFFFF)
7475+#define MCF_JTAGID_MCF5485 (0x0800C01D)
7476+#define MCF_JTAGID_MCF5484 (0x0800D01D)
7477+#define MCF_JTAGID_MCF5483 (0x0800E01D)
7478+#define MCF_JTAGID_MCF5482 (0x0800F01D)
7479+#define MCF_JTAGID_MCF5481 (0x0801001D)
7480+#define MCF_JTAGID_MCF5480 (0x0801101D)
7481+#define MCF_JTAGID_MCF5475 (0x0801201D)
7482+#define MCF_JTAGID_MCF5474 (0x0801301D)
7483+#define MCF_JTAGID_MCF5473 (0x0801401D)
7484+#define MCF_JTAGID_MCF5472 (0x0801501D)
7485+#define MCF_JTAGID_MCF5471 (0x0801601D)
7486+#define MCF_JTAGID_MCF5470 (0x0801701D)
7487+
7488+
7489+/*
7490+ * Interrupt Controller Bitfields
7491+ */
7492+#define MCF_IRLR_IRQ(x) (((x)&0x7F)<<1)
7493+#define MCF_IACKLPR_PRI(x) (((x)&0x0F)<<0)
7494+#define MCF_IACKLPR_LEVEL(x) (((x)&0x07)<<4)
7495+#define MCF_ICR_IP(x) (((x)&0x07)<<0)
7496+#define MCF_ICR_IL(x) (((x)&0x07)<<3)
7497+
7498+/*
7499+ * Slice Timers Bitfields
7500+ */
7501+#define MCF_SCR_TEN (0x01000000)
7502+#define MCF_SCR_IEN (0x02000000)
7503+#define MCF_SCR_RUN (0x04000000)
7504+#define MCF_SSR_ST (0x01000000)
7505+#define MCF_SSR_BE (0x02000000)
7506+
7507+
7508+/*
7509+ * Some needed coldfire registers
7510+ */
7511+#define MCF_PAR_PCIBG MCF_REG16(0x000A48)
7512+#define MCF_PAR_PCIBR MCF_REG16(0x000A4A)
7513+#define MCF_PAR_PSCn(x) MCF_REG08(0x000A4F-((x)&0x3))
7514+#define MCF_PAR_FECI2CIRQ MCF_REG16(0x000A44)
7515+#define MCF_PAR_DSPI MCF_REG16(0x000A50)
7516+#define MCF_PAR_TIMER MCF_REG08(0X000A52)
7517+#define MCF_EPPAR MCF_REG16(0x000F00)
7518+#define MCF_EPDDR MCF_REG08(0x000F04)
7519+#define MCF_EPIER MCF_REG08(0x000F05)
7520+#define MCF_EPFR MCF_REG08(0x000F0C)
7521+
7522+/*
7523+ * Some GPIO bitfields
7524+ */
7525+#define MCF_PAR_SDA (0x0008)
7526+#define MCF_PAR_SCL (0x0004)
7527+#define MCF_PAR_PSC_TXD (0x04)
7528+#define MCF_PAR_PSC_RXD (0x08)
7529+#define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4)
7530+#define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6)
7531+#define MCF_PAR_PSC_CTS_GPIO (0x00)
7532+#define MCF_PAR_PSC_CTS_BCLK (0x80)
7533+#define MCF_PAR_PSC_CTS_CTS (0xC0)
7534+#define MCF_PAR_PSC_RTS_GPIO (0x00)
7535+#define MCF_PAR_PSC_RTS_FSYNC (0x20)
7536+#define MCF_PAR_PSC_RTS_RTS (0x30)
7537+#define MCF_PAR_PSC_CANRX (0x40)
7538+
7539+/*
7540+ * FlexCAN Module Configuration Register
7541+ */
7542+#define CANMCR_MDIS (0x80000000)
7543+#define CANMCR_FRZ (0x40000000)
7544+#define CANMCR_HALT (0x10000000)
7545+#define CANMCR_SOFTRST (0x02000000)
7546+#define CANMCR_NOTRDY (0x08000000)
7547+#define CANMCR_FRZACK (0x01000000)
7548+#define CANMCR_SUPV (0x00800000)
7549+#define CANMCR_MAXMB (0x0F)
7550+/*
7551+ * FlexCAN Control Register
7552+ */
7553+#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)
7554+#define CANCTRL_RJW(x) (((x)&0x03)<<22)
7555+#define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
7556+#define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
7557+#define CANCTRL_BOFFMSK (0x00008000)
7558+#define CANCTRL_ERRMSK (0x00004000)
7559+#define CANCTRL_CLKSRC (0x00002000)
7560+#define CANCTRL_LPB (0x00001000)
7561+#define CANCTRL_SAMP(x) (((x)&0x01)<<7)
7562+#define CANCTRL_BOFFREC (0x00000040)
7563+#define CANCTRL_TSYNC (0x00000020)
7564+#define CANCTRL_LBUF (0x00000010)
7565+#define CANCTRL_LOM (0x00000008)
7566+#define CANCTRL_PROPSEG(x) ((x)&0x07)
7567+
7568+/*
7569+ * FlexCAN Error Counter Register
7570+ */
7571+#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)
7572+#define ERRCNT_TXECTR(x) ((x)&0xFF)
7573+
7574+/*
7575+ * FlexCAN Error and Status Register
7576+ */
7577+#define ERRSTAT_BITERR(x) (((x)&0x03)<<14)
7578+#define ERRSTAT_ACKERR (0x00002000)
7579+#define ERRSTAT_CRCERR (0x00001000)
7580+#define ERRSTAT_FRMERR (0x00000800)
7581+#define ERRSTAT_STFERR (0x00000400)
7582+#define ERRSTAT_TXWRN (0x00000200)
7583+#define ERRSTAT_RXWRN (0x00000100)
7584+#define ERRSTAT_IDLE (0x00000080)
7585+#define ERRSTAT_TXRX (0x00000040)
7586+#define ERRSTAT_FLTCONF(x) (((x)&0x03)<<4)
7587+#define ERRSTAT_BOFFINT (0x00000004)
7588+#define ERRSTAT_ERRINT (0x00000002)
7589+
7590+/*
7591+ * Interrupt Mask Register
7592+ */
7593+#define IMASK_BUF15M (0x8000)
7594+#define IMASK_BUF14M (0x4000)
7595+#define IMASK_BUF13M (0x2000)
7596+#define IMASK_BUF12M (0x1000)
7597+#define IMASK_BUF11M (0x0800)
7598+#define IMASK_BUF10M (0x0400)
7599+#define IMASK_BUF9M (0x0200)
7600+#define IMASK_BUF8M (0x0100)
7601+#define IMASK_BUF7M (0x0080)
7602+#define IMASK_BUF6M (0x0040)
7603+#define IMASK_BUF5M (0x0020)
7604+#define IMASK_BUF4M (0x0010)
7605+#define IMASK_BUF3M (0x0008)
7606+#define IMASK_BUF2M (0x0004)
7607+#define IMASK_BUF1M (0x0002)
7608+#define IMASK_BUF0M (0x0001)
7609+#define IMASK_BUFnM(x) (0x1<<(x))
7610+#define IMASK_BUFF_ENABLE_ALL (0xFFFF)
7611+#define IMASK_BUFF_DISABLE_ALL (0x0000)
7612+
7613+/*
7614+ * Interrupt Flag Register
7615+ */
7616+#define IFLAG_BUF15M (0x8000)
7617+#define IFLAG_BUF14M (0x4000)
7618+#define IFLAG_BUF13M (0x2000)
7619+#define IFLAG_BUF12M (0x1000)
7620+#define IFLAG_BUF11M (0x0800)
7621+#define IFLAG_BUF10M (0x0400)
7622+#define IFLAG_BUF9M (0x0200)
7623+#define IFLAG_BUF8M (0x0100)
7624+#define IFLAG_BUF7M (0x0080)
7625+#define IFLAG_BUF6M (0x0040)
7626+#define IFLAG_BUF5M (0x0020)
7627+#define IFLAG_BUF4M (0x0010)
7628+#define IFLAG_BUF3M (0x0008)
7629+#define IFLAG_BUF2M (0x0004)
7630+#define IFLAG_BUF1M (0x0002)
7631+#define IFLAG_BUF0M (0x0001)
7632+#define IFLAG_BUFF_SET_ALL (0xFFFF)
7633+#define IFLAG_BUFF_CLEAR_ALL (0x0000)
7634+#define IFLAG_BUFnM(x) (0x1<<(x))
7635+
7636+/*
7637+ * Message Buffers
7638+ */
7639+#define MB_CNT_CODE(x) (((x)&0x0F)<<24)
7640+#define MB_CNT_SRR (0x00400000)
7641+#define MB_CNT_IDE (0x00200000)
7642+#define MB_CNT_RTR (0x00100000)
7643+#define MB_CNT_TIMESTAMP(x) ((x)&0xFFFF)
7644+#define MB_ID_STD (0x07FF)
7645+#define MB_ID_EXT (0x1FFFFFFF)
7646+#define MB_CODE_MASK (0xF0FFFFFF)
7647+#define CAN_MB 16
7648+#define PDEV_MAX 2
7649+
7650+/*
7651+ * Some used coldfire values
7652+ */
7653+#define MCF_EPIER_EPIE(x) (0x01 << (x))
7654+#define MCF_EPPAR_EPPAx_FALLING (2)
7655+#define MCF_EPPAR_EPPA(n, x) (((x)&0x0003) << (2*n))
7656+
7657+
7658+#endif /* m5485sim_h */
7659--- /dev/null
7660+++ b/arch/m68k/include/asm/m5485sram.h
7661@@ -0,0 +1,12 @@
7662+#ifndef SYS_SRAM_H
7663+#define SYS_SRAM_H
7664+
7665+
7666+#define SYS_SRAM_DMA_START (MCF_MBAR + 0x10000)
7667+#define SYS_SRAM_DMA_SIZE 8192
7668+#define SYS_SRAM_FEC_START (SYS_SRAM_DMA_START + SYS_SRAM_DMA_SIZE)
7669+#define SYS_SRAM_FEC_SIZE 2048
7670+#define SYS_SRAM_SEC_START (SYS_SRAM_FEC_START + SYS_SRAM_FEC_SIZE)
7671+#define SYS_SRAM_SEC_SIZE 1280
7672+
7673+#endif /* SYS_SRAM_H */
7674

Archive Download this file

Branches:
backfire
history
master
release_2010-11-17
release_2010-12-14
release_2011-02-23
release_2011-05-28
release_2011-08-27
release_2011-11-13
release_2012-03-18
release_2012-04-09
release_2012-10-11
uclibc_nptl



interactive