Root/target/linux/coldfire/patches/029-Add-eSDHC-driver-for-MCF5441x.patch

1From 73c65ac21faf1b016f8f8ddfab2dc3e58a5618f9 Mon Sep 17 00:00:00 2001
2From: Alison Wang <b18965@freescale.com>
3Date: Thu, 4 Aug 2011 09:59:46 +0800
4Subject: [PATCH 29/52] Add eSDHC driver for MCF5441x
5
6Add eSDHC PIO mode(read and write) and DMA mode(read and write) support.
7Add card detect using extern irq.
8
9Signed-off-by: Alison Wang <b18965@freescale.com>
10---
11 drivers/mmc/host/Kconfig | 35 +
12 drivers/mmc/host/Makefile | 1 +
13 drivers/mmc/host/esdhc.c | 1826 +++++++++++++++++++++++++++++++++++++++++++++
14 drivers/mmc/host/esdhc.h | 310 ++++++++
15 4 files changed, 2172 insertions(+), 0 deletions(-)
16 create mode 100644 drivers/mmc/host/esdhc.c
17 create mode 100644 drivers/mmc/host/esdhc.h
18
19--- a/drivers/mmc/host/Kconfig
20+++ b/drivers/mmc/host/Kconfig
21@@ -403,6 +403,41 @@ config DETECT_USE_EXTERN_IRQ1
22 
23 endchoice
24 
25+config MMC_ESDHC
26+ tristate "Enhanced Secure Digital Host Controller Interface support"
27+ depends on M5441X
28+ help
29+ This select Freescale Enhanced SD Host Controller Interface.
30+ The controller is used in MCF5441x.
31+ If unsure, say N.
32+
33+config ESDHC_FORCE_PIO
34+ tristate "eSDHC force to use PIO (no DMA) mode"
35+ depends on MMC_ESDHC
36+ help
37+ This select Freescale Enhanced SD Host Controller Interface.
38+ The controller is used in MCF5441x.
39+ If unsure, say N.
40+
41+choice
42+ prompt "MMC/SD card detect "
43+ depends on MMC_ESDHC
44+
45+config ESDHC_DETECT_USE_EXTERN_IRQ7
46+ bool "based extern IRQ7"
47+ depends on MMC_ESDHC
48+ help
49+ MMC/SD cards using esdhc controller,
50+ we use the extern irq7 to detect card.
51+config ESDHC_DETECT_USE_EXTERN_IRQ1
52+ bool "based extern IRQ1"
53+ depends on MMC_ESDHC
54+ help
55+ MMC/SD cards using esdhc controller,
56+ we use the extern irq7 to detect card.
57+
58+endchoice
59+
60 config MMC_S3C
61     tristate "Samsung S3C SD/MMC Card Interface support"
62     depends on ARCH_S3C2410
63--- a/drivers/mmc/host/Makefile
64+++ b/drivers/mmc/host/Makefile
65@@ -28,6 +28,7 @@ endif
66 obj-$(CONFIG_MMC_S3C) += s3cmci.o
67 obj-$(CONFIG_MMC_SDRICOH_CS) += sdricoh_cs.o
68 obj-$(CONFIG_MMC_TMIO) += tmio_mmc.o
69+obj-$(CONFIG_MMC_ESDHC) += esdhc.o
70 obj-$(CONFIG_MMC_CB710) += cb710-mmc.o
71 obj-$(CONFIG_MMC_VIA_SDMMC) += via-sdmmc.o
72 obj-$(CONFIG_GPIOMMC) += gpiommc.o
73--- /dev/null
74+++ b/drivers/mmc/host/esdhc.c
75@@ -0,0 +1,1826 @@
76+/*
77+ * drivers/mmc/host/esdhc.c
78+ *
79+ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
80+ * Author: Chenghu Wu <b16972@freescale.com>
81+ * Xiaobo Xie <X.Xie@freescale.com>
82+ *
83+ * Freescale Enhanced Secure Digital Host Controller driver.
84+ * Based on mpc837x/driver/mmc/host/esdhc.c done by Xiaobo Xie
85+ * Ported to Coldfire platform by Chenghu Wu
86+ *
87+ * This program is free software; you can redistribute it and/or modify it
88+ * under the terms of the GNU General Public License as published by the
89+ * Free Software Foundation; either version 2 of the License, or (at your
90+ * option) any later version.
91+ */
92+
93+#include <linux/module.h>
94+#include <linux/init.h>
95+#include <linux/ioport.h>
96+#include <linux/interrupt.h>
97+#include <linux/delay.h>
98+#include <linux/highmem.h>
99+#include <linux/dma-mapping.h>
100+#include <linux/scatterlist.h>
101+#include <linux/uaccess.h>
102+#include <linux/irq.h>
103+#include <linux/io.h>
104+#include <linux/slab.h>
105+#include <linux/mmc/host.h>
106+
107+#include <asm/dma.h>
108+#include <asm/page.h>
109+
110+#include <linux/platform_device.h>
111+#include <asm/coldfire.h>
112+#include <asm/mcfsim.h>
113+
114+#include "esdhc.h"
115+#define DRIVER_NAME "esdhc"
116+
117+
118+#if defined(CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1)
119+#define card_detect_extern_irq (64 + 1)
120+#elif defined(CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ7)
121+#define card_detect_extern_irq (64 + 7)
122+#else
123+#define card_detect_extern_irq (64 + 7)
124+#endif
125+
126+#undef ESDHC_DMA_KMALLOC
127+
128+#define SYS_BUSCLOCK 80000000
129+#define ESDHC_DMA_SIZE 0x10000
130+
131+#undef MMC_ESDHC_DEBUG
132+#undef MMC_ESDHC_DEBUG_REG
133+
134+#ifdef MMC_ESDHC_DEBUG
135+#define DBG(fmt, args...) printk(KERN_INFO "[%s] " fmt "\n", __func__, ## args)
136+#else
137+#define DBG(fmt, args...) do {} while (0)
138+#endif
139+
140+#ifdef MMC_ESDHC_DEBUG_REG
141+static void esdhc_dumpregs(struct esdhc_host *host)
142+{
143+ printk(KERN_INFO "========= REGISTER DUMP ==========\n");
144+
145+ printk(KERN_INFO "Sysaddr: 0x%08x | Blkattr: 0x%08x\n",
146+ fsl_readl(host->ioaddr + ESDHC_DMA_ADDRESS),
147+ fsl_readl(host->ioaddr + ESDHC_BLOCK_ATTR));
148+ printk(KERN_INFO "Argument: 0x%08x | COMMAND: 0x%08x\n",
149+ fsl_readl(host->ioaddr + ESDHC_ARGUMENT),
150+ fsl_readl(host->ioaddr + ESDHC_COMMAND));
151+ printk(KERN_INFO "Present: 0x%08x | DMA ctl: 0x%08x\n",
152+ fsl_readl(host->ioaddr + ESDHC_PRESENT_STATE),
153+ fsl_readl(host->ioaddr + ESDHC_DMA_SYSCTL));
154+ printk(KERN_INFO "PROCTL: 0x%08x | SYSCTL: 0x%08x\n",
155+ fsl_readl(host->ioaddr + ESDHC_PROTOCOL_CONTROL),
156+ fsl_readl(host->ioaddr + ESDHC_SYSTEM_CONTROL));
157+ printk(KERN_INFO "Int stat: 0x%08x\n",
158+ fsl_readl(host->ioaddr + ESDHC_INT_STATUS));
159+ printk(KERN_INFO "Intenab: 0x%08x | Sigenab: 0x%08x\n",
160+ fsl_readl(host->ioaddr + ESDHC_INT_ENABLE),
161+ fsl_readl(host->ioaddr + ESDHC_SIGNAL_ENABLE));
162+ printk(KERN_INFO "AC12 err: 0x%08x | Version: 0x%08x\n",
163+ fsl_readl(host->ioaddr + ESDHC_ACMD12_ERR),
164+ fsl_readl(host->ioaddr + ESDHC_HOST_VERSION));
165+ printk(KERN_INFO "Caps: 0x%08x | Watermark: 0x%08x\n",
166+ fsl_readl(host->ioaddr + ESDHC_CAPABILITIES),
167+ fsl_readl(host->ioaddr + ESDHC_WML));
168+ printk(KERN_INFO "MCF_INTC1_IPRH: 0x%08x | MCF_INTC1_IPRL: 0x%08x\n",
169+ (unsigned int)MCF_INTC1_IPRH,
170+ (unsigned int)MCF_INTC1_IPRL);
171+ printk(KERN_INFO "MCF_INTC1_IMRH: 0x%08x | MCF_INTC1_IMRL: 0x%08x\n",
172+ (unsigned int)MCF_INTC1_IMRH,
173+ (unsigned int)MCF_INTC1_IMRL);
174+ printk(KERN_INFO "MCF_INTC1_INTFRCH: 0x%08x | MCF_INTC1_INTFRCL: 0x%08x\n",
175+ (unsigned int)MCF_INTC1_INTFRCH,
176+ (unsigned int)MCF_INTC1_INTFRCL);
177+ printk(KERN_INFO "MCF_INTC1_INTFRCH: 0x%08x | MCF_INTC1_INTFRCL: 0x%08x\n",
178+ (unsigned int)MCF_INTC1_INTFRCH,
179+ (unsigned int)MCF_INTC1_INTFRCL);
180+ printk(KERN_INFO "MCF_INTC1_ICR63: 0x%08x | MCF_INTC0_ICR36: 0x%08x\n",
181+ (unsigned int)MCF_INTC1_ICR63,
182+ (unsigned int)MCF_INTC0_ICR36);
183+
184+ printk(KERN_INFO "==================================\n");
185+}
186+#else
187+static void esdhc_dumpregs(struct esdhc_host *host)
188+{
189+ do {} while (0);
190+}
191+#endif
192+
193+
194+static unsigned int debug_nodma;
195+static unsigned int debug_forcedma;
196+static unsigned int debug_quirks;
197+
198+#define ESDHC_QUIRK_CLOCK_BEFORE_RESET (1<<0)
199+#define ESDHC_QUIRK_FORCE_DMA (1<<1)
200+#define ESDHC_QUIRK_NO_CARD_NO_RESET (1<<2)
201+#define ESDHC_QUIRK_SINGLE_POWER_WRITE (1<<3)
202+
203+static void esdhc_prepare_data(struct esdhc_host *, struct mmc_data *);
204+static void esdhc_finish_data(struct esdhc_host *);
205+static irqreturn_t esdhc_irq(int irq, void *dev_id);
206+static void esdhc_send_command(struct esdhc_host *, struct mmc_command *);
207+static void esdhc_finish_command(struct esdhc_host *);
208+
209+/*****************************************************************************\
210+ * *
211+ * Low level functions *
212+ * *
213+\*****************************************************************************/
214+
215+static void esdhc_reset(struct esdhc_host *host, u8 mask)
216+{
217+ unsigned long timeout;
218+ unsigned int sysctl;
219+
220+ if (host->chip->quirks & ESDHC_QUIRK_NO_CARD_NO_RESET) {
221+ if (!(fsl_readl(host->ioaddr + ESDHC_PRESENT_STATE) &
222+ ESDHC_CARD_PRESENT))
223+ return;
224+ }
225+
226+ timeout = fsl_readl(host->ioaddr + ESDHC_SYSTEM_CONTROL);
227+ timeout = timeout | (mask << ESDHC_RESET_SHIFT);
228+ fsl_writel(host->ioaddr + ESDHC_SYSTEM_CONTROL, timeout);
229+
230+ if (mask & ESDHC_RESET_ALL) {
231+ host->clock = 0;
232+ host->bus_width = 0;
233+ }
234+
235+ /* Wait max 100 ms */
236+ timeout = 100;
237+
238+ /* hw clears the bit when it's done */
239+ sysctl = (mask << ESDHC_RESET_SHIFT);
240+ while (fsl_readl(host->ioaddr + ESDHC_SYSTEM_CONTROL) & sysctl) {
241+ if (timeout == 0) {
242+ printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
243+ mmc_hostname(host->mmc), (int)mask);
244+ esdhc_dumpregs(host);
245+ return;
246+ }
247+ timeout--;
248+ mdelay(1);
249+ }
250+}
251+
252+static void esdhc_init(struct esdhc_host *host)
253+{
254+ u32 intmask;
255+ /*reset eSDHC chip*/
256+ esdhc_reset(host, ESDHC_RESET_ALL);
257+
258+ intmask = fsl_readl(host->ioaddr + ESDHC_PRESENT_STATE);
259+ intmask = intmask & 0xF7000000;
260+ fsl_writel(host->ioaddr + ESDHC_PRESENT_STATE, intmask);
261+
262+ intmask = fsl_readl(host->ioaddr + ESDHC_SYSTEM_CONTROL);
263+ intmask = intmask | ESDHC_CLOCK_INT_EN | ESDHC_CLOCK_INT_STABLE;
264+ fsl_writel(host->ioaddr + ESDHC_SYSTEM_CONTROL, intmask);
265+
266+ intmask = fsl_readl(host->ioaddr + ESDHC_INT_STATUS);
267+ fsl_writel(host->ioaddr + ESDHC_INT_STATUS, intmask);
268+
269+ intmask = fsl_readl(host->ioaddr + ESDHC_INT_ENABLE);
270+
271+ fsl_writel(host->ioaddr + ESDHC_INT_ENABLE, intmask);
272+ fsl_writel(host->ioaddr + ESDHC_SIGNAL_ENABLE, intmask);
273+ /* Modelo does not support */
274+ /*MCF_ESDHC_SCR = MCF_ESDHC_SCR | ESDHC_DMA_SNOOP | 0xC0;*/
275+
276+ intmask = fsl_readl(host->ioaddr + ESDHC_PROTOCOL_CONTROL);
277+ intmask &= ~ESDHC_CTRL_D3_DETEC;
278+
279+ fsl_writel(host->ioaddr + ESDHC_PROTOCOL_CONTROL, intmask);
280+ DBG(" init %x\n", fsl_readl(host->ioaddr + ESDHC_PROTOCOL_CONTROL));
281+}
282+
283+static void reset_regs(struct esdhc_host *host)
284+{
285+ u32 intmask;
286+
287+ intmask = fsl_readl(host->ioaddr + ESDHC_INT_STATUS);
288+ fsl_writel(host->ioaddr + ESDHC_INT_STATUS, intmask);
289+
290+ intmask = ESDHC_INT_DATA_END_BIT | ESDHC_INT_DATA_CRC |
291+ ESDHC_INT_DATA_TIMEOUT | ESDHC_INT_INDEX |
292+ ESDHC_INT_END_BIT | ESDHC_INT_CRC | ESDHC_INT_TIMEOUT |
293+ ESDHC_INT_DATA_AVAIL | ESDHC_INT_SPACE_AVAIL |
294+ ESDHC_INT_DMA_END | ESDHC_INT_DATA_END | ESDHC_INT_RESPONSE;
295+
296+ fsl_writel(host->ioaddr + ESDHC_INT_ENABLE, intmask);
297+ fsl_writel(host->ioaddr + ESDHC_SIGNAL_ENABLE, intmask);
298+
299+ if (host->bus_width == MMC_BUS_WIDTH_4) {
300+ intmask = fsl_readl(host->ioaddr + ESDHC_PROTOCOL_CONTROL);
301+ intmask |= ESDHC_CTRL_4BITBUS;
302+ fsl_writel(host->ioaddr + ESDHC_PROTOCOL_CONTROL, intmask);
303+ }
304+}
305+
306+/*****************************************************************************
307+ * *
308+ * Core functions *
309+ * *
310+ *****************************************************************************/
311+/* Return the SG's virtual address */
312+static inline char *esdhc_sg_to_buffer(struct esdhc_host *host)
313+{
314+ DBG("cur_sg %x virt %x\n", host->cur_sg, sg_virt(host->cur_sg));
315+ return sg_virt(host->cur_sg);
316+}
317+
318+static inline int esdhc_next_sg(struct esdhc_host *host)
319+{
320+ /*
321+ * Skip to next SG entry.
322+ */
323+ host->cur_sg = sg_next(host->cur_sg);
324+ host->num_sg--;
325+
326+ /*
327+ * Any entries left?
328+ */
329+ if (host->num_sg > 0) {
330+ host->offset = 0;
331+ host->remain = host->cur_sg->length;
332+ }
333+
334+ DBG("%s: host->remain %x %x\n", __func__, host->remain, host->num_sg);
335+ return host->num_sg;
336+}
337+
338+static void esdhc_read_block_pio(struct esdhc_host *host)
339+{
340+ int blksize, chunk_remain;
341+ u32 data;
342+ char *buffer;
343+ int size;
344+
345+ DBG("PIO reading\n");
346+
347+ /* Delay prevents data read error in big files */
348+ udelay(100);
349+
350+ blksize = host->data->blksz;
351+ chunk_remain = 0;
352+ data = 0;
353+
354+ buffer = esdhc_sg_to_buffer(host) + host->offset;
355+
356+ while (blksize) {
357+ if (chunk_remain == 0) {
358+ data = fsl_readl(host->ioaddr + ESDHC_BUFFER);
359+ chunk_remain = min(blksize, 4);
360+ }
361+
362+ size = min(host->remain, chunk_remain);
363+
364+ chunk_remain -= size;
365+ blksize -= size;
366+ host->offset += size;
367+ host->remain -= size;
368+
369+ while (size) {
370+ *buffer = data & 0xFF;
371+ buffer++;
372+ data >>= 8;
373+ size--;
374+ }
375+
376+ if (host->remain == 0) {
377+ if (esdhc_next_sg(host) == 0) {
378+ BUG_ON(blksize != 0);
379+ return;
380+ }
381+ buffer = esdhc_sg_to_buffer(host);
382+ }
383+ }
384+}
385+
386+static void esdhc_write_block_pio(struct esdhc_host *host)
387+{
388+ int blksize, chunk_remain;
389+ u32 data;
390+ char *buffer;
391+ int bytes, size;
392+
393+ DBG("PIO writing\n");
394+
395+ /* Delay necessary when writing large data blocks to SD card */
396+ udelay(100);
397+
398+ blksize = host->data->blksz;
399+ chunk_remain = 4;
400+ data = 0;
401+
402+ bytes = 0;
403+ buffer = esdhc_sg_to_buffer(host) + host->offset;
404+
405+ while (blksize) {
406+ size = min(host->remain, chunk_remain);
407+
408+ chunk_remain -= size;
409+ blksize -= size;
410+ host->offset += size;
411+ host->remain -= size;
412+
413+ while (size) {
414+ data >>= 8;
415+ data |= (u32)*buffer << 24;
416+ buffer++;
417+ size--;
418+ }
419+
420+ if (chunk_remain == 0) {
421+ fsl_writel(host->ioaddr + ESDHC_BUFFER, data);
422+ chunk_remain = min(blksize, 4);
423+ }
424+
425+ if (host->remain == 0) {
426+ if (esdhc_next_sg(host) == 0) {
427+ BUG_ON(blksize != 0);
428+ return;
429+ }
430+ buffer = esdhc_sg_to_buffer(host);
431+ }
432+ }
433+}
434+
435+static void esdhc_transfer_pio(struct esdhc_host *host)
436+{
437+ u32 mask;
438+
439+ BUG_ON(!host->data);
440+
441+ if (host->num_sg == 0)
442+ return;
443+
444+ if (host->data->flags & MMC_DATA_READ)
445+ mask = ESDHC_DATA_AVAILABLE;
446+ else
447+ mask = ESDHC_SPACE_AVAILABLE;
448+
449+ while (fsl_readl(host->ioaddr + ESDHC_PRESENT_STATE) & mask) {
450+ if (host->data->flags & MMC_DATA_READ)
451+ esdhc_read_block_pio(host);
452+ else
453+ esdhc_write_block_pio(host);
454+
455+ if (host->num_sg == 0)
456+ break;
457+ }
458+
459+ DBG("PIO transfer complete.\n");
460+ /* Delay necessary when writing large data blocks to SD card */
461+ udelay(100);
462+}
463+
464+static void esdhc_prepare_data(struct esdhc_host *host, struct mmc_data *data)
465+{
466+ u8 count;
467+ unsigned blkattr = 0;
468+ unsigned target_timeout, current_timeout;
469+ unsigned int sysctl;
470+
471+ WARN_ON(host->data);
472+
473+ if (data == NULL)
474+ return;
475+
476+ DBG("blksz %04x blks %04x flags %08x",
477+ data->blksz, data->blocks, data->flags);
478+ DBG("tsac %d ms nsac %d clk",
479+ data->timeout_ns / 1000000, data->timeout_clks);
480+
481+ /* Sanity checks */
482+ BUG_ON(data->blksz * data->blocks > 524288);
483+ BUG_ON(data->blksz > host->mmc->max_blk_size);
484+ BUG_ON(data->blocks > 65535);
485+
486+ if (host->clock == 0)
487+ return;
488+
489+ /* timeout in us */
490+ target_timeout = data->timeout_ns / 1000 +
491+ (data->timeout_clks * 1000000) / host->clock;
492+
493+ /*
494+ * Figure out needed cycles.
495+ * We do this in steps in order to fit inside a 32 bit int.
496+ * The first step is the minimum timeout, which will have a
497+ * minimum resolution of 6 bits:
498+ * (1) 2^13*1000 > 2^22,
499+ * (2) host->timeout_clk < 2^16
500+ * =>
501+ * (1) / (2) > 2^6
502+ */
503+ count = 0;
504+ host->timeout_clk = host->clock/1000;
505+ current_timeout = (1 << 13) * 1000 / host->timeout_clk;
506+ while (current_timeout < target_timeout) {
507+ count++;
508+ current_timeout <<= 1;
509+ if (count >= 0xF)
510+ break;
511+ }
512+
513+ if (count >= 0xF) {
514+ DBG("%s:Timeout requested is too large!\n",
515+ mmc_hostname(host->mmc));
516+ count = 0xE;
517+ }
518+
519+ if (data->blocks >= 0x50) {
520+ DBG("%s:Blocks %x are too large!\n",
521+ mmc_hostname(host->mmc),
522+ data->blocks);
523+ count = 0xE;
524+ }
525+
526+ if ((data->blocks == 1) && (data->blksz >= 0x200)) {
527+ DBG("%s:Blocksize %x is too large\n",
528+ mmc_hostname(host->mmc),
529+ data->blksz);
530+ count = 0xE;
531+ }
532+ count = 0xE;
533+
534+ sysctl = fsl_readl(host->ioaddr + ESDHC_SYSTEM_CONTROL);
535+ sysctl &= (~ESDHC_TIMEOUT_MASK);
536+ fsl_writel(host->ioaddr + ESDHC_SYSTEM_CONTROL,
537+ sysctl | (count<<ESDHC_TIMEOUT_SHIFT));
538+
539+ /* Data transfer*/
540+ if (host->flags & ESDHC_USE_DMA) {
541+ int sg_count;
542+ unsigned int wml;
543+ unsigned int wml_value;
544+ unsigned int timeout;
545+
546+ /* DMA address eSDHC in Modelo must be 4 bytes aligned */
547+ if ((data->sg->offset & 0x3) == 0)
548+ host->offset = 0;
549+ else
550+ host->offset = 0x4 - (data->sg->offset & 0x3);
551+
552+ sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg,
553+ data->sg_len,
554+ (data->flags & MMC_DATA_READ)
555+ ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
556+
557+ BUG_ON(sg_count != 1);
558+ /* The data in SD card is little endian,
559+ the SD controller is big endian */
560+ if ((data->flags & MMC_DATA_WRITE) == MMC_DATA_WRITE) {
561+ unsigned char *buffer = sg_virt(data->sg);
562+ unsigned char *buffer_tx =
563+ (unsigned char *)host->dma_tx_buf;
564+ int i;
565+ /* Each sector is 512 Bytes, write 0x200 sectors */
566+ memset(host->dma_tx_buf, 0, ESDHC_DMA_SIZE);
567+ for (i = 0; i < data->sg->length; i = i + 4) {
568+ *(buffer_tx + i + 3) = *(buffer + i);
569+ *(buffer_tx + i + 2) = *(buffer + i + 1);
570+ *(buffer_tx + i + 1) = *(buffer + i + 2);
571+ *(buffer_tx + i) = *(buffer + i + 3);
572+ }
573+
574+ fsl_writel(host->ioaddr + ESDHC_DMA_ADDRESS,
575+ (unsigned long)host->dma_tx_dmahandle);
576+ } else {
577+ fsl_writel(host->ioaddr + ESDHC_DMA_ADDRESS,
578+ sg_dma_address(data->sg) + host->offset);
579+ }
580+
581+ /* Disable the BRR and BWR interrupt */
582+ timeout = fsl_readl(host->ioaddr + ESDHC_INT_ENABLE);
583+ timeout = timeout & (~(ESDHC_INT_DATA_AVAIL |
584+ ESDHC_INT_SPACE_AVAIL));
585+ fsl_writel(host->ioaddr + ESDHC_INT_ENABLE, timeout);
586+
587+ timeout = fsl_readl(host->ioaddr + ESDHC_SIGNAL_ENABLE);
588+ timeout = timeout & (~(ESDHC_INT_DATA_AVAIL |
589+ ESDHC_INT_SPACE_AVAIL));
590+ fsl_writel(host->ioaddr + ESDHC_SIGNAL_ENABLE, timeout);
591+
592+ wml_value = data->blksz / 4;
593+ if (data->flags & MMC_DATA_READ) {
594+ /* Read watermask level, max is 0x10*/
595+ if (wml_value > 0x10)
596+ wml_value = 0x10;
597+ wml = (wml_value & ESDHC_WML_MASK) |
598+ ((0x10 & ESDHC_WML_MASK)
599+ << ESDHC_WML_WRITE_SHIFT);
600+ } else {
601+ if (wml_value > 0x80)
602+ wml_value = 0x80;
603+ wml = (0x10 & ESDHC_WML_MASK) |
604+ (((wml_value) & ESDHC_WML_MASK)
605+ << ESDHC_WML_WRITE_SHIFT);
606+ }
607+
608+ fsl_writel(host->ioaddr + ESDHC_WML, wml);
609+ } else {
610+ unsigned long timeout;
611+
612+ host->cur_sg = data->sg;
613+ host->num_sg = data->sg_len;
614+
615+ host->offset = 0;
616+ host->remain = host->cur_sg->length;
617+
618+ timeout = fsl_readl(host->ioaddr + ESDHC_INT_ENABLE);
619+ timeout = timeout | ESDHC_INT_DATA_AVAIL
620+ | ESDHC_INT_SPACE_AVAIL;
621+ fsl_writel(host->ioaddr + ESDHC_INT_ENABLE, timeout);
622+
623+ timeout = fsl_readl(host->ioaddr + ESDHC_SIGNAL_ENABLE);
624+ timeout = timeout | ESDHC_INT_DATA_AVAIL
625+ | ESDHC_INT_SPACE_AVAIL;
626+ fsl_writel(host->ioaddr + ESDHC_SIGNAL_ENABLE, timeout);
627+ }
628+
629+ /* We do not handle DMA boundaries */
630+ blkattr = data->blksz;
631+ blkattr |= (data->blocks << 16);
632+ fsl_writel(host->ioaddr + ESDHC_BLOCK_ATTR, blkattr);
633+ esdhc_dumpregs(host);
634+}
635+
636+static unsigned int esdhc_set_transfer_mode(struct esdhc_host *host,
637+ struct mmc_data *data)
638+{
639+ u32 mode = 0;
640+
641+ WARN_ON(host->data);
642+
643+ if (data == NULL)
644+ return 0;
645+
646+ mode = ESDHC_TRNS_BLK_CNT_EN;
647+ if (data->blocks > 1) {
648+ if (data->flags & MMC_DATA_READ)
649+ mode |= ESDHC_TRNS_MULTI | ESDHC_TRNS_ACMD12;
650+ else
651+ mode |= ESDHC_TRNS_MULTI;
652+ }
653+ if (data->flags & MMC_DATA_READ)
654+ mode |= ESDHC_TRNS_READ;
655+ if (host->flags & ESDHC_USE_DMA)
656+ mode |= ESDHC_TRNS_DMA;
657+
658+ return mode;
659+}
660+
661+static void esdhc_finish_data(struct esdhc_host *host)
662+{
663+ struct mmc_data *data;
664+ u16 blocks;
665+
666+ BUG_ON(!host->data);
667+
668+ data = host->data;
669+ host->data = NULL;
670+
671+ if (host->flags & ESDHC_USE_DMA) {
672+ unsigned char *buffer = sg_virt(data->sg);
673+ unsigned char C0, C1, C2, C3;
674+ int i;
675+ /* Data in SD card is little endian,
676+ SD controller is big endian */
677+
678+ dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
679+ (data->flags & MMC_DATA_READ)
680+ ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
681+ if (((data->flags & MMC_DATA_READ) == MMC_DATA_READ)) {
682+ for (i = 0; i < data->sg->length; i = i + 4) {
683+ C0 = *(buffer + host->offset + i);
684+ C1 = *(buffer + host->offset + i + 1);
685+ C2 = *(buffer + host->offset + i + 2);
686+ C3 = *(buffer + host->offset + i + 3);
687+ *(buffer+i) = C3;
688+ *(buffer+i+1) = C2;
689+ *(buffer+i+2) = C1;
690+ *(buffer+i+3) = C0;
691+ }
692+ }
693+ }
694+ /*
695+ * Controller doesn't count down when in single block mode.
696+ */
697+ if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
698+ blocks = 0;
699+ else {
700+ blocks = fsl_readl(host->ioaddr + ESDHC_BLOCK_ATTR) >> 16;
701+ blocks = 0;
702+ if (data->flags & MMC_DATA_READ)
703+ data->stop = 0;
704+ }
705+
706+ data->bytes_xfered = data->blksz * (data->blocks - blocks);
707+
708+ if ((data->error == MMC_ERR_NONE) && blocks) {
709+ printk(KERN_ERR"%s: Controller signaled completion even "
710+ "though there were blocks left.\n",
711+ mmc_hostname(host->mmc));
712+ data->error = MMC_ERR_FAILED;
713+ }
714+
715+ if ((blocks == 0) && (data->error & MMC_ERR_TIMEOUT)) {
716+ printk(KERN_ERR "Controller transmitted completion even "
717+ "though there was a timeout error.\n");
718+ data->error &= ~MMC_ERR_TIMEOUT;
719+ }
720+
721+ if (data->stop) {
722+ DBG("%s data->stop %x\n", __func__, data->stop);
723+ /*
724+ * The controller needs a reset of internal state machines
725+ * upon error conditions.
726+ */
727+ if (data->error != MMC_ERR_NONE) {
728+ printk("%s: The controller needs a "
729+ "reset of internal state machines\n",
730+ __func__);
731+ esdhc_reset(host, ESDHC_RESET_CMD);
732+ esdhc_reset(host, ESDHC_RESET_DATA);
733+ reset_regs(host);
734+ }
735+
736+ esdhc_send_command(host, data->stop);
737+ } else
738+ tasklet_schedule(&host->finish_tasklet);
739+}
740+
741+static void esdhc_send_command(struct esdhc_host *host, struct mmc_command *cmd)
742+{
743+ unsigned int flags;
744+ u32 mask;
745+ unsigned long timeout;
746+
747+ WARN_ON(host->cmd);
748+
749+ /* Wait max 10 ms */
750+ timeout = 10;
751+
752+ mask = ESDHC_CMD_INHIBIT;
753+ if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
754+ mask |= ESDHC_DATA_INHIBIT;
755+
756+ /* We shouldn't wait for data inihibit for stop commands, even
757+ though they might use busy signaling */
758+ if (host->mrq->data && (cmd == host->mrq->data->stop))
759+ mask &= ~ESDHC_DATA_INHIBIT;
760+
761+ while (fsl_readl(host->ioaddr + ESDHC_PRESENT_STATE) & mask) {
762+ if (timeout == 0) {
763+ printk(KERN_ERR "%s: Controller never released "
764+ "inhibit bit(s).\n", mmc_hostname(host->mmc));
765+ esdhc_dumpregs(host);
766+ cmd->error = MMC_ERR_FAILED;
767+ tasklet_schedule(&host->finish_tasklet);
768+ return;
769+ }
770+ timeout--;
771+ mdelay(1);
772+ }
773+
774+ mod_timer(&host->timer, jiffies + 15 * HZ);
775+
776+ host->cmd = cmd;
777+
778+ esdhc_prepare_data(host, cmd->data);
779+
780+ fsl_writel(host->ioaddr + ESDHC_ARGUMENT, cmd->arg);
781+
782+ flags = esdhc_set_transfer_mode(host, cmd->data);
783+
784+ if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
785+ printk(KERN_ERR "%s: Unsupported response type!\n",
786+ mmc_hostname(host->mmc));
787+ cmd->error = MMC_ERR_INVALID;
788+ tasklet_schedule(&host->finish_tasklet);
789+ return;
790+ }
791+
792+ if (!(cmd->flags & MMC_RSP_PRESENT))
793+ flags |= ESDHC_CMD_RESP_NONE;
794+ else if (cmd->flags & MMC_RSP_136)
795+ flags |= ESDHC_CMD_RESP_LONG;
796+ else if (cmd->flags & MMC_RSP_BUSY)
797+ flags |= ESDHC_CMD_RESP_SHORT_BUSY;
798+ else
799+ flags |= ESDHC_CMD_RESP_SHORT;
800+
801+ if (cmd->flags & MMC_RSP_CRC)
802+ flags |= ESDHC_CMD_CRC_EN;
803+ if (cmd->flags & MMC_RSP_OPCODE)
804+ flags |= ESDHC_CMD_INDEX_EN;
805+ if (cmd->data)
806+ flags |= ESDHC_CMD_DATA;
807+
808+ fsl_writel(host->ioaddr + ESDHC_COMMAND,
809+ ESDHC_MAKE_CMD(cmd->opcode, flags));
810+}
811+
812+static void esdhc_finish_command(struct esdhc_host *host)
813+{
814+ int i;
815+
816+ BUG_ON(host->cmd == NULL);
817+
818+ if (host->cmd->flags & MMC_RSP_PRESENT) {
819+ if (host->cmd->flags & MMC_RSP_136) {
820+ /* CRC is stripped so we need to do some shifting. */
821+ for (i = 0; i < 4; i++) {
822+ host->cmd->resp[i] = fsl_readl(host->ioaddr +
823+ ESDHC_RESPONSE + (3-i)*4) << 8;
824+ if (i != 3)
825+ host->cmd->resp[i] |=
826+ (fsl_readl(host->ioaddr
827+ + ESDHC_RESPONSE
828+ + (2-i)*4) >> 24);
829+ }
830+ } else
831+ host->cmd->resp[0] = fsl_readl(host->ioaddr +
832+ ESDHC_RESPONSE);
833+ }
834+
835+ host->cmd->error = MMC_ERR_NONE;
836+
837+ if (host->cmd->data)
838+ host->data = host->cmd->data;
839+ else
840+ tasklet_schedule(&host->finish_tasklet);
841+
842+ host->cmd = NULL;
843+}
844+
845+#define MYCLOCK 1
846+static void esdhc_set_clock(struct esdhc_host *host, unsigned int clock)
847+{
848+#if MYCLOCK
849+ unsigned long sdrefclk, vco, bestmatch = -1, temp, diff;
850+ int dvs, sdclkfs, outdiv;
851+ int best_dvs, best_sdclkfs, best_outdiv;
852+#else
853+ int div, pre_div;
854+ unsigned long sys_busclock = SYS_BUSCLOCK;
855+#endif
856+ unsigned long timeout;
857+ u16 clk;
858+
859+ DBG("esdhc_set_clock %x\n", clock);
860+ if (clock == host->clock)
861+ return;
862+
863+ timeout = fsl_readl(host->ioaddr + ESDHC_SYSTEM_CONTROL);
864+ timeout = timeout & (~ESDHC_CLOCK_MASK);
865+ fsl_writel(host->ioaddr + ESDHC_SYSTEM_CONTROL, timeout);
866+
867+ if (clock == 0)
868+ goto out;
869+
870+#if MYCLOCK
871+ /* TC: The VCO must obtain from u-boot */
872+ /*
873+ * First set the outdiv3 to min 1, then walk through all to
874+ * get closer value with SDCLKDIV and DIV combination
875+ */
876+ vco = 500000000;
877+ MCF_CLOCK_PLL_DR &= 0xFFFF83FF; /* Disable SD Clock */
878+
879+ for (outdiv = 2; outdiv <= 32; outdiv++) {
880+ sdrefclk = vco / outdiv;
881+
882+ for (sdclkfs = 2; sdclkfs < 257; sdclkfs <<= 1) {
883+ for (dvs = 1; dvs < 17; dvs++) {
884+ temp = sdrefclk / (sdclkfs * dvs);
885+
886+ if (temp > clock)
887+ diff = temp - clock;
888+ else
889+ diff = clock - temp;
890+
891+ if (diff <= bestmatch) {
892+ bestmatch = diff;
893+ best_outdiv = outdiv;
894+ best_sdclkfs = sdclkfs;
895+ best_dvs = dvs;
896+
897+ if (bestmatch == 0)
898+ goto end;
899+ }
900+ }
901+ }
902+ }
903+
904+end:
905+#ifdef CONFIG_M5441X
906+ best_outdiv = 3;
907+ best_sdclkfs = 2;
908+ best_dvs = 5;
909+#endif
910+ MCF_CLOCK_PLL_DR |= ((best_outdiv - 1) << 10);
911+ clk = ((best_sdclkfs >> 1) << 8) | ((best_dvs - 1) << 4);
912+#else
913+
914+ if (sys_busclock / 16 > clock) {
915+ for (pre_div = 1; pre_div < 256; pre_div *= 2) {
916+ if ((sys_busclock / pre_div) < (clock*16))
917+ break;
918+ }
919+ } else
920+ pre_div = 1;
921+
922+ for (div = 1; div <= 16; div++) {
923+ if ((sys_busclock / (div*pre_div)) <= clock)
924+ break;
925+ }
926+
927+ pre_div >>= 1;
928+ div -= 1;
929+
930+ clk = (div << ESDHC_DIVIDER_SHIFT) | (pre_div << ESDHC_PREDIV_SHIFT);
931+#endif
932+
933+ timeout = fsl_readl(host->ioaddr + ESDHC_SYSTEM_CONTROL);
934+ timeout = timeout | clk;
935+
936+ fsl_writel(host->ioaddr + ESDHC_SYSTEM_CONTROL, timeout);
937+
938+ /* Wait max 10 ms */
939+ timeout = 10;
940+ while (timeout) {
941+ timeout--;
942+ mdelay(1);
943+ }
944+
945+ timeout = fsl_readl(host->ioaddr + ESDHC_SYSTEM_CONTROL);
946+ timeout = timeout | ESDHC_CLOCK_CARD_EN;
947+ fsl_writel(host->ioaddr + ESDHC_SYSTEM_CONTROL, timeout);
948+
949+ esdhc_dumpregs(host);
950+
951+out:
952+ host->clock = clock;
953+ if (host->clock == 0) {
954+ timeout = fsl_readl(host->ioaddr + ESDHC_SYSTEM_CONTROL);
955+ timeout = timeout | ESDHC_CLOCK_DEFAULT;
956+ fsl_writel(host->ioaddr + ESDHC_SYSTEM_CONTROL, timeout);
957+ }
958+}
959+
960+static void esdhc_set_power(struct esdhc_host *host, unsigned short power)
961+{
962+ if (host->power == power)
963+ return;
964+
965+ if (power == (unsigned short)-1)
966+ host->power = power;
967+}
968+
969+/*****************************************************************************\
970+ * *
971+ * MMC callbacks *
972+ * *
973+\*****************************************************************************/
974+
975+static void esdhc_request(struct mmc_host *mmc, struct mmc_request *mrq)
976+{
977+ struct esdhc_host *host;
978+ unsigned long flags;
979+
980+ DBG("esdhc_request\n");
981+ host = mmc_priv(mmc);
982+
983+ spin_lock_irqsave(&host->lock, flags);
984+
985+ WARN_ON(host->mrq != NULL);
986+
987+ host->mrq = mrq;
988+
989+ esdhc_send_command(host, mrq->cmd);
990+
991+ mmiowb();
992+ spin_unlock_irqrestore(&host->lock, flags);
993+}
994+
995+static void esdhc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
996+{
997+ struct esdhc_host *host;
998+ unsigned long flags;
999+ u32 ctrl, irq_status_ena, irq_signal_ena;
1000+
1001+ DBG("ios->power_mode %x, ios->bus_width %x\n",
1002+ ios->power_mode, ios->bus_width);
1003+ host = mmc_priv(mmc);
1004+
1005+ spin_lock_irqsave(&host->lock, flags);
1006+
1007+ /*
1008+ * Reset the chip on each power off.
1009+ * Should clear out any weird states.
1010+ */
1011+
1012+ if (ios->power_mode == MMC_POWER_OFF) {
1013+ fsl_writel(host->ioaddr + ESDHC_SIGNAL_ENABLE, 0);
1014+ esdhc_init(host);
1015+ }
1016+
1017+ esdhc_set_clock(host, ios->clock);
1018+
1019+ if (ios->power_mode == MMC_POWER_OFF)
1020+ esdhc_set_power(host, -1);
1021+ else
1022+ esdhc_set_power(host, ios->vdd);
1023+
1024+ ctrl = fsl_readl(host->ioaddr + ESDHC_PROTOCOL_CONTROL);
1025+
1026+ if (ios->bus_width == MMC_BUS_WIDTH_4) {
1027+ ctrl |= ESDHC_CTRL_4BITBUS;
1028+ host->bus_width = MMC_BUS_WIDTH_4;
1029+
1030+ ctrl &= ~ESDHC_CTRL_D3_DETEC;
1031+
1032+ /*when change the config of the CD,
1033+ * will involve card remove interrupt
1034+ * So try disable the card remove interrupt.
1035+ */
1036+ irq_status_ena = fsl_readl(host->ioaddr + ESDHC_INT_ENABLE);
1037+ irq_status_ena &= ~ESDHC_INT_CARD_REMOVE;
1038+ fsl_writel(host->ioaddr + ESDHC_INT_ENABLE, irq_status_ena);
1039+
1040+ irq_signal_ena = fsl_readl(host->ioaddr + ESDHC_SIGNAL_ENABLE);
1041+ irq_signal_ena &= ~ESDHC_INT_CARD_REMOVE;
1042+ fsl_writel(host->ioaddr + ESDHC_SIGNAL_ENABLE, irq_signal_ena);
1043+
1044+ DBG("host->card_insert = 0x%x\n", host->card_insert);
1045+
1046+
1047+ } else {
1048+ ctrl &= ~ESDHC_CTRL_4BITBUS;
1049+ host->bus_width = MMC_BUS_WIDTH_1;
1050+ }
1051+
1052+ fsl_writel(host->ioaddr + ESDHC_PROTOCOL_CONTROL, ctrl);
1053+ mmiowb();
1054+ spin_unlock_irqrestore(&host->lock, flags);
1055+
1056+ esdhc_dumpregs(host);
1057+}
1058+
1059+static int esdhc_get_ro(struct mmc_host *mmc)
1060+{
1061+ return 0;
1062+}
1063+
1064+static const struct mmc_host_ops esdhc_ops = {
1065+ .request = esdhc_request,
1066+ .set_ios = esdhc_set_ios,
1067+ .get_ro = esdhc_get_ro,
1068+};
1069+
1070+/*****************************************************************************\
1071+ * *
1072+ * Tasklets *
1073+ * *
1074+\*****************************************************************************/
1075+
1076+static void esdhc_tasklet_card(unsigned long param)
1077+{
1078+ struct esdhc_host *host;
1079+
1080+ host = (struct esdhc_host *)param;
1081+
1082+ spin_lock(&host->lock);
1083+
1084+ DBG("esdhc_tasklet_card\n");
1085+ if (!(fsl_readl(host->ioaddr + ESDHC_PRESENT_STATE) &
1086+ ESDHC_CARD_PRESENT)) {
1087+ if (host->mrq) {
1088+ printk(KERN_ERR "%s: Card removed during transfer!\n",
1089+ mmc_hostname(host->mmc));
1090+ printk(KERN_ERR "%s: Resetting controller.\n",
1091+ mmc_hostname(host->mmc));
1092+
1093+ esdhc_reset(host, ESDHC_RESET_CMD);
1094+ esdhc_reset(host, ESDHC_RESET_DATA);
1095+
1096+ host->mrq->cmd->error = MMC_ERR_FAILED;
1097+ tasklet_schedule(&host->finish_tasklet);
1098+ }
1099+ host->card_insert = 0;
1100+ } else {
1101+ esdhc_reset(host, ESDHC_INIT_CARD);
1102+ host->card_insert = 1;
1103+ }
1104+
1105+ spin_unlock(&host->lock);
1106+
1107+ mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1108+}
1109+
1110+static void esdhc_tasklet_finish(unsigned long param)
1111+{
1112+ struct esdhc_host *host;
1113+ unsigned long flags;
1114+ struct mmc_request *mrq;
1115+
1116+ host = (struct esdhc_host *)param;
1117+ DBG("esdhc_tasklet_finish\n");
1118+
1119+ spin_lock_irqsave(&host->lock, flags);
1120+
1121+ del_timer(&host->timer);
1122+
1123+ mrq = host->mrq;
1124+
1125+ /*
1126+ * The controller needs a reset of internal state machines
1127+ * upon error conditions.
1128+ */
1129+ if ((mrq->cmd->error != MMC_ERR_NONE) ||
1130+ (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
1131+ (mrq->data->stop &&
1132+ (mrq->data->stop->error != MMC_ERR_NONE))))) {
1133+
1134+ /* Some controllers need this kick or reset won't work here */
1135+ if (host->chip->quirks & ESDHC_QUIRK_CLOCK_BEFORE_RESET) {
1136+ unsigned int clock;
1137+
1138+ /* This is to force an update */
1139+ clock = host->clock;
1140+ host->clock = 0;
1141+ esdhc_set_clock(host, clock);
1142+ }
1143+
1144+ if (mrq->cmd->error != MMC_ERR_TIMEOUT) {
1145+ esdhc_reset(host, ESDHC_RESET_CMD);
1146+ esdhc_reset(host, ESDHC_RESET_DATA);
1147+ reset_regs(host);
1148+ esdhc_dumpregs(host);
1149+ }
1150+ }
1151+
1152+ host->mrq = NULL;
1153+ host->cmd = NULL;
1154+ host->data = NULL;
1155+
1156+ spin_unlock_irqrestore(&host->lock, flags);
1157+
1158+ mmc_request_done(host->mmc, mrq);
1159+}
1160+
1161+static void esdhc_timeout_timer(unsigned long data)
1162+{
1163+ struct esdhc_host *host;
1164+ unsigned long flags;
1165+
1166+ host = (struct esdhc_host *)data;
1167+ printk(KERN_INFO "esdhc_timeout_timer\n");
1168+ spin_lock_irqsave(&host->lock, flags);
1169+
1170+ if (host->mrq) {
1171+ if (host->data) {
1172+ host->data->error = MMC_ERR_TIMEOUT;
1173+ esdhc_finish_data(host);
1174+ } else {
1175+ if (host->cmd)
1176+ host->cmd->error = MMC_ERR_TIMEOUT;
1177+ else
1178+ host->mrq->cmd->error = MMC_ERR_TIMEOUT;
1179+ tasklet_schedule(&host->finish_tasklet);
1180+ }
1181+ }
1182+
1183+ mmiowb();
1184+ fsl_writel(host->ioaddr + ESDHC_INT_STATUS, 0);
1185+ spin_unlock_irqrestore(&host->lock, flags);
1186+}
1187+
1188+/*****************************************************************************\
1189+ * *
1190+ * Interrupt handling *
1191+ * *
1192+\*****************************************************************************/
1193+
1194+static void esdhc_cmd_irq(struct esdhc_host *host, u32 intmask)
1195+{
1196+ BUG_ON(intmask == 0);
1197+
1198+ if (!host->cmd) {
1199+ printk(KERN_ERR "%s: Got command interrupt even though no "
1200+ "command operation was in progress.\n",
1201+ mmc_hostname(host->mmc));
1202+ esdhc_dumpregs(host);
1203+ return;
1204+ }
1205+
1206+ if (intmask & ESDHC_INT_TIMEOUT) {
1207+ host->cmd->error = MMC_ERR_TIMEOUT;
1208+ DBG("esdhc_cmd_irq MMC_ERR_TIMEOUT\n");
1209+ tasklet_schedule(&host->finish_tasklet);
1210+ } else if (intmask & ESDHC_INT_RESPONSE)
1211+ esdhc_finish_command(host);
1212+ else {
1213+ if (intmask & ESDHC_INT_CRC)
1214+ host->cmd->error = MMC_ERR_BADCRC;
1215+ else if (intmask & (ESDHC_INT_END_BIT | ESDHC_INT_INDEX))
1216+ host->cmd->error = MMC_ERR_FAILED;
1217+ else
1218+ host->cmd->error = MMC_ERR_INVALID;
1219+
1220+ tasklet_schedule(&host->finish_tasklet);
1221+ }
1222+}
1223+
1224+static void esdhc_data_irq(struct esdhc_host *host, u32 intmask)
1225+{
1226+ BUG_ON(intmask == 0);
1227+ if (!host->data) {
1228+ /*
1229+ * A data end interrupt is sent together with the response
1230+ * for the stop command.
1231+ */
1232+ if ((intmask & ESDHC_INT_DATA_END) ||
1233+ (intmask & ESDHC_INT_DMA_END)) {
1234+ return;
1235+ }
1236+ DBG("%s: Got data interrupt even though no "
1237+ "data operation was in progress.\n",
1238+ mmc_hostname(host->mmc));
1239+ esdhc_dumpregs(host);
1240+
1241+ return;
1242+ }
1243+
1244+ if (intmask & ESDHC_INT_DATA_TIMEOUT)
1245+ host->data->error = MMC_ERR_TIMEOUT;
1246+ else if (intmask & ESDHC_INT_DATA_CRC)
1247+ host->data->error = MMC_ERR_BADCRC;
1248+ else if (intmask & ESDHC_INT_DATA_END_BIT)
1249+ host->data->error = MMC_ERR_FAILED;
1250+
1251+ if (host->data->error != MMC_ERR_NONE) {
1252+ esdhc_finish_data(host);
1253+ } else {
1254+ if (intmask & (ESDHC_INT_DATA_AVAIL | ESDHC_INT_SPACE_AVAIL))
1255+ esdhc_transfer_pio(host);
1256+ /*
1257+ * We currently don't do anything fancy with DMA
1258+ * boundaries, but as we can't disable the feature
1259+ * we need to at least restart the transfer.
1260+ */
1261+ if (intmask & ESDHC_INT_DMA_END)
1262+ fsl_writel(host->ioaddr + ESDHC_DMA_ADDRESS,
1263+ fsl_readl(host->ioaddr + ESDHC_DMA_ADDRESS));
1264+ if (intmask & ESDHC_INT_DATA_END)
1265+ esdhc_finish_data(host);
1266+ }
1267+}
1268+
1269+static irqreturn_t esdhc_detect_irq(int irq, void *dev_id)
1270+{
1271+ irqreturn_t result;
1272+ struct esdhc_host *host = dev_id;
1273+ u8 irq_status = 0;
1274+
1275+ spin_lock(&host->lock);
1276+
1277+ irq_status = MCF_EPORT_EPPDR & 0x2;
1278+ DBG("***Extern IRQ %x %x %x %x %x %x\n", MCF_EPORT_EPPAR,
1279+ MCF_EPORT_EPDDR, MCF_EPORT_EPDR, MCF_EPORT_EPFR,
1280+ MCF_EPORT_EPIER, MCF_EPORT_EPPDR);
1281+#if defined(CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1)
1282+ MCF_EPORT_EPIER = MCF_EPORT_EPIER & (~MCF_EPORT_EPIER_EPIE1);
1283+#elif defined(CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ7)
1284+ MCF_EPORT_EPIER = MCF_EPORT_EPIER & (~MCF_EPORT_EPIER_EPIE7);
1285+#else
1286+ MCF_EPORT_EPIER = MCF_EPORT_EPIER & (~MCF_EPORT_EPIER_EPIE7);
1287+#endif
1288+ if (irq_status == 0x0) {
1289+ DBG("*** Card insert interrupt Extern IRQ\n");
1290+ esdhc_reset(host, ESDHC_INIT_CARD);
1291+ host->card_insert = 1;
1292+ } else /*irq_status == 0x2) */{
1293+ DBG("*** Card removed interrupt Extern IRQ\n");
1294+ if (host->mrq) {
1295+ printk(KERN_ERR "%s: Card removed during transfer!\n",
1296+ mmc_hostname(host->mmc));
1297+ printk(KERN_ERR "%s: Resetting controller.\n",
1298+ mmc_hostname(host->mmc));
1299+
1300+ esdhc_reset(host, ESDHC_RESET_CMD);
1301+ esdhc_reset(host, ESDHC_RESET_DATA);
1302+
1303+ host->mrq->cmd->error = MMC_ERR_FAILED;
1304+ tasklet_schedule(&host->finish_tasklet);
1305+ }
1306+ host->card_insert = 0;
1307+ }
1308+
1309+ mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1310+#if defined(CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1)
1311+ MCF_EPORT_EPPAR = MCF_EPORT_EPPAR | MCF_EPORT_EPPAR_EPPA1_BOTH;
1312+ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE1;
1313+ MCF_EPORT_EPFR = MCF_EPORT_EPFR | MCF_EPORT_EPFR_EPF1;
1314+#elif defined(CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ7)
1315+ MCF_EPORT_EPPAR = MCF_EPORT_EPPAR | MCF_EPORT_EPPAR_EPPA7_BOTH;
1316+ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE7;
1317+ MCF_EPORT_EPFR = MCF_EPORT_EPFR | MCF_EPORT_EPFR_EPF7;
1318+#else
1319+ MCF_EPORT_EPPAR = MCF_EPORT_EPPAR | MCF_EPORT_EPPAR_EPPA7_BOTH;
1320+ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE7;
1321+ MCF_EPORT_EPFR = MCF_EPORT_EPFR | MCF_EPORT_EPFR_EPF7;
1322+#endif
1323+ DBG("***Extern IRQ return %x %x %x %x %x %x\n", MCF_EPORT_EPPAR,
1324+ MCF_EPORT_EPDDR, MCF_EPORT_EPDR, MCF_EPORT_EPFR,
1325+ MCF_EPORT_EPIER, MCF_EPORT_EPPDR);
1326+
1327+ result = IRQ_HANDLED;
1328+ spin_unlock(&host->lock);
1329+
1330+ return result;
1331+}
1332+
1333+static irqreturn_t esdhc_irq(int irq, void *dev_id)
1334+{
1335+ irqreturn_t result;
1336+ struct esdhc_host *host = dev_id;
1337+ u32 status;
1338+
1339+ spin_lock(&host->lock);
1340+
1341+ status = fsl_readl(host->ioaddr + ESDHC_INT_STATUS);
1342+
1343+ if (!status || status == 0xffffffff) {
1344+ result = IRQ_NONE;
1345+ goto out;
1346+ }
1347+
1348+ if (status & ESDHC_INT_CMD_MASK) {
1349+ fsl_writel(host->ioaddr + ESDHC_INT_STATUS,
1350+ status & ESDHC_INT_CMD_MASK);
1351+ esdhc_cmd_irq(host, status & ESDHC_INT_CMD_MASK);
1352+ }
1353+
1354+ if (status & ESDHC_INT_DATA_MASK) {
1355+ fsl_writel(host->ioaddr + ESDHC_INT_STATUS,
1356+ status & ESDHC_INT_DATA_MASK);
1357+ esdhc_data_irq(host, status & ESDHC_INT_DATA_MASK);
1358+ }
1359+
1360+ status &= ~(ESDHC_INT_CMD_MASK | ESDHC_INT_DATA_MASK);
1361+
1362+ if (status) {
1363+ printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1364+ mmc_hostname(host->mmc), status);
1365+ esdhc_dumpregs(host);
1366+
1367+ fsl_writel(host->ioaddr + ESDHC_INT_STATUS, status);
1368+ }
1369+
1370+ result = IRQ_HANDLED;
1371+
1372+ mmiowb();
1373+out:
1374+ spin_unlock(&host->lock);
1375+
1376+ return result;
1377+}
1378+
1379+/*****************************************************************************\
1380+ * *
1381+ * Suspend/resume *
1382+ * *
1383+\*****************************************************************************/
1384+
1385+#ifdef CONFIG_PM
1386+
1387+static int esdhc_suspend(struct platform_device *pdev, pm_message_t state)
1388+{
1389+ struct esdhc_chip *chip;
1390+ int i, ret;
1391+
1392+ chip = platform_get_drvdata(pdev);
1393+ if (!chip)
1394+ return 0;
1395+
1396+ DBG("Suspending...");
1397+
1398+ for (i = 0; i < chip->num_slots; i++) {
1399+ if (!chip->hosts[i])
1400+ continue;
1401+ ret = mmc_suspend_host(chip->hosts[i]->mmc);
1402+ if (ret) {
1403+ for (i--; i >= 0; i--)
1404+ mmc_resume_host(chip->hosts[i]->mmc);
1405+ return ret;
1406+ }
1407+ }
1408+
1409+ for (i = 0; i < chip->num_slots; i++) {
1410+ if (!chip->hosts[i])
1411+ continue;
1412+ free_irq(chip->hosts[i]->irq, chip->hosts[i]);
1413+ }
1414+
1415+ return 0;
1416+}
1417+
1418+static int esdhc_resume(struct platform_device *pdev)
1419+{
1420+ struct esdhc_chip *chip;
1421+ int i, ret;
1422+
1423+ chip = platform_get_drvdata(pdev);
1424+ if (!chip)
1425+ return 0;
1426+
1427+ DBG("Resuming...");
1428+
1429+ for (i = 0; i < chip->num_slots; i++) {
1430+ if (!chip->hosts[i])
1431+ continue;
1432+ ret = request_irq(chip->hosts[i]->irq, esdhc_irq,
1433+ IRQF_SHARED, chip->hosts[i]->slot_descr,
1434+ chip->hosts[i]);
1435+ if (ret)
1436+ return ret;
1437+ esdhc_init(chip->hosts[i]);
1438+ mmiowb();
1439+ ret = mmc_resume_host(chip->hosts[i]->mmc);
1440+ if (ret)
1441+ return ret;
1442+ }
1443+
1444+ return 0;
1445+}
1446+
1447+#else
1448+
1449+#define esdhc_suspend NULL
1450+#define esdhc_resume NULL
1451+
1452+#endif
1453+
1454+/*****************************************************************************\
1455+ * *
1456+ * Device probing/removal *
1457+ * *
1458+\*****************************************************************************/
1459+
1460+static int esdhc_probe_slot(struct platform_device *pdev, int slot)
1461+{
1462+ int ret;
1463+ unsigned int version;
1464+ struct esdhc_chip *chip;
1465+ struct mmc_host *mmc;
1466+ struct esdhc_host *host;
1467+ struct resource *res;
1468+
1469+ unsigned int caps;
1470+
1471+ chip = platform_get_drvdata(pdev);
1472+ BUG_ON(!chip);
1473+
1474+ mmc = mmc_alloc_host(sizeof(struct esdhc_host), &(pdev->dev));
1475+ if (!mmc) {
1476+ printk(KERN_ERR "%s mmc_alloc_host failed %x\n",
1477+ __func__, (unsigned int)mmc);
1478+ return -ENOMEM;
1479+ }
1480+
1481+ host = mmc_priv(mmc);
1482+ host->mmc = mmc;
1483+
1484+ host->chip = chip;
1485+ chip->hosts[slot] = host;
1486+
1487+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1488+ if (res == NULL) {
1489+ printk(KERN_ERR "%s platform_get_resource MEM failed %x\n",
1490+ __func__, (unsigned int)res);
1491+ goto free;
1492+ }
1493+
1494+ host->addr = res->start;
1495+ host->size = res->end - res->start + 1;
1496+
1497+ host->irq = platform_get_irq(pdev, 0);
1498+ if (host->irq <= 0) {
1499+ printk(KERN_ERR "%s platform_get_irq failed %x\n",
1500+ __func__, host->irq);
1501+ goto free;
1502+ }
1503+
1504+ printk(KERN_INFO "slot %d at 0x%08lx, irq %d\n",
1505+ slot, host->addr, host->irq);
1506+
1507+ snprintf(host->slot_descr, 20, "esdhc:slot%d", slot);
1508+
1509+ ret = (int)request_mem_region(host->addr, host->size, DRIVER_NAME);
1510+ if (!ret) {
1511+ ret = -EBUSY;
1512+ printk(KERN_INFO "%s request_mem_region failed %x\n",
1513+ __func__, (unsigned int)res);
1514+ goto release;
1515+ }
1516+
1517+ host->ioaddr = ioremap_nocache(host->addr, host->size);
1518+ if (!host->ioaddr) {
1519+ ret = -ENOMEM;
1520+ printk(KERN_INFO "%s ioremap_nocache failed %x\n",
1521+ __func__, (unsigned int)host->ioaddr);
1522+ goto release;
1523+ }
1524+
1525+ esdhc_reset(host, ESDHC_RESET_ALL);
1526+
1527+ version = fsl_readl(host->ioaddr + ESDHC_HOST_VERSION);
1528+ if ((version & 1) != 0x01)
1529+ printk(KERN_INFO "%s: Unknown controller version (%d). "
1530+ "You may experience problems.\n", host->slot_descr,
1531+ version);
1532+
1533+ caps = fsl_readl(host->ioaddr + ESDHC_CAPABILITIES);
1534+ printk(KERN_INFO "%s caps %x %x\n",
1535+ __func__, caps, (unsigned int)MCF_ESDHC_HOSTCAPBLT);
1536+
1537+#if defined(CONFIG_ESDHC_FORCE_PIO)
1538+ debug_nodma = 1;
1539+#endif
1540+ if (debug_nodma)
1541+ DBG("DMA forced off\n");
1542+ else if (debug_forcedma) {
1543+ DBG("DMA forced on\n");
1544+ host->flags |= ESDHC_USE_DMA;
1545+ } else if (chip->quirks & ESDHC_QUIRK_FORCE_DMA) {
1546+ DBG("Controller force DMA capability\n");
1547+ host->flags |= ESDHC_USE_DMA;
1548+ } else if (!(caps & ESDHC_CAN_DO_DMA))
1549+ DBG("Controller doesn't have DMA capability\n");
1550+ else {
1551+ host->flags |= ESDHC_USE_DMA;
1552+ DBG("Controller have DMA capability\n");
1553+ }
1554+
1555+ /*
1556+ * Set host parameters.
1557+ */
1558+#ifdef CONFIG_MPC5441X
1559+ host->max_clk = 17000000;
1560+#else
1561+ host->max_clk = 25000000;
1562+#endif
1563+
1564+ /* if 4 bit , freq can be 50MHz */
1565+ mmc->ops = &esdhc_ops;
1566+ mmc->f_min = 400000;
1567+ mmc->f_max = min((int)host->max_clk, 50000000);
1568+
1569+ mmc->caps = MMC_CAP_4_BIT_DATA;
1570+
1571+ mmc->ocr_avail = 0;
1572+ if (caps & ESDHC_CAN_VDD_330)
1573+ mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1574+ if (caps & ESDHC_CAN_VDD_300)
1575+ mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1576+ if (caps & ESDHC_CAN_VDD_180)
1577+ mmc->ocr_avail |= MMC_VDD_165_195;
1578+
1579+ if (mmc->ocr_avail == 0) {
1580+ printk(KERN_INFO "%s: Hardware doesn't report any "
1581+ "support voltages.\n", host->slot_descr);
1582+ ret = -ENODEV;
1583+ goto unmap;
1584+ }
1585+
1586+ spin_lock_init(&host->lock);
1587+
1588+ /*
1589+ * Maximum number of segments. Hardware cannot do scatter lists.
1590+ */
1591+ if (host->flags & ESDHC_USE_DMA)
1592+ mmc->max_segs = 1;
1593+ else
1594+ mmc->max_segs = 16;
1595+
1596+ /*
1597+ * Maximum number of sectors in one transfer. Limited by DMA boundary
1598+ * size (512KiB).
1599+ */
1600+ mmc->max_req_size = 524288;
1601+
1602+ /*
1603+ * Maximum segment size. Could be one segment with the maximum number
1604+ * of bytes.
1605+ */
1606+ mmc->max_seg_size = mmc->max_req_size;
1607+
1608+ /*
1609+ * Maximum block size. This varies from controller to controller and
1610+ * is specified in the capabilities register.
1611+ */
1612+ mmc->max_blk_size = (caps & ESDHC_MAX_BLOCK_MASK) >>
1613+ ESDHC_MAX_BLOCK_SHIFT;
1614+ if (mmc->max_blk_size > 3) {
1615+ printk(KERN_INFO "%s: Invalid maximum block size.\n",
1616+ host->slot_descr);
1617+ ret = -ENODEV;
1618+ goto unmap;
1619+ }
1620+ mmc->max_blk_size = 512 << mmc->max_blk_size;
1621+
1622+ /*
1623+ * Maximum block count.
1624+ */
1625+ mmc->max_blk_count = /*65535*/0x80;
1626+
1627+ /*
1628+ * Init tasklets.
1629+ */
1630+ tasklet_init(&host->card_tasklet,
1631+ esdhc_tasklet_card, (unsigned long)host);
1632+ tasklet_init(&host->finish_tasklet,
1633+ esdhc_tasklet_finish, (unsigned long)host);
1634+
1635+ setup_timer(&host->timer, esdhc_timeout_timer, (unsigned long)host);
1636+
1637+ esdhc_init(host);
1638+
1639+ esdhc_dumpregs(host);
1640+
1641+ ret = request_irq(host->irq, esdhc_irq, IRQF_DISABLED,
1642+ host->slot_descr, host);
1643+ if (ret) {
1644+ printk(KERN_INFO "%s: request irq fail %x\n", __func__, ret);
1645+ goto untasklet;
1646+ }
1647+
1648+ ret = request_irq(card_detect_extern_irq,
1649+ esdhc_detect_irq, IRQF_DISABLED,
1650+ host->slot_descr, host);
1651+ if (ret) {
1652+ printk(KERN_INFO "%s: request irq fail %x\n", __func__, ret);
1653+ goto untasklet1;
1654+ }
1655+
1656+ mmiowb();
1657+
1658+ ret = mmc_add_host(mmc);
1659+ if (ret) {
1660+ printk(KERN_INFO "%s: mmc_add_host fail %x\n", __func__, ret);
1661+ goto unaddhost;
1662+ }
1663+
1664+ printk(KERN_INFO "%s: ESDHC at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
1665+ host->addr, host->irq,
1666+ (host->flags & ESDHC_USE_DMA) ? "DMA" : "PIO");
1667+
1668+#ifdef ESDHC_DMA_KMALLOC
1669+ host->dma_tx_buf = kmalloc(ESDHC_DMA_SIZE, GFP_DMA);
1670+ host->dma_tx_dmahandle = virt_to_phys(host->dma_tx_buf);
1671+#else
1672+ host->dma_tx_buf = dma_alloc_coherent(NULL, ESDHC_DMA_SIZE,
1673+ &host->dma_tx_dmahandle, GFP_DMA|GFP_KERNEL);
1674+#endif
1675+
1676+ if (((unsigned int)host->dma_tx_buf == 0) ||
1677+ ((unsigned int)host->dma_tx_dmahandle == 0))
1678+ printk(KERN_ERR "%s DMA alloc error\n", __func__);
1679+
1680+ return 0;
1681+
1682+unaddhost:
1683+ free_irq(card_detect_extern_irq, host);
1684+untasklet1:
1685+ free_irq(host->irq, host);
1686+untasklet:
1687+ tasklet_kill(&host->card_tasklet);
1688+ tasklet_kill(&host->finish_tasklet);
1689+unmap:
1690+ iounmap(host->ioaddr);
1691+release:
1692+ release_mem_region(host->addr, host->size);
1693+free:
1694+ mmc_free_host(mmc);
1695+
1696+ return ret;
1697+}
1698+
1699+static void esdhc_remove_slot(struct platform_device *pdev, int slot)
1700+{
1701+ struct esdhc_chip *chip;
1702+ struct mmc_host *mmc;
1703+ struct esdhc_host *host;
1704+
1705+ chip = platform_get_drvdata(pdev);
1706+ host = chip->hosts[slot];
1707+ mmc = host->mmc;
1708+
1709+ chip->hosts[slot] = NULL;
1710+
1711+ mmc_remove_host(mmc);
1712+
1713+ esdhc_reset(host, ESDHC_RESET_ALL);
1714+
1715+ free_irq(card_detect_extern_irq, host);
1716+
1717+ free_irq(host->irq, host);
1718+
1719+ del_timer_sync(&host->timer);
1720+
1721+ tasklet_kill(&host->card_tasklet);
1722+ tasklet_kill(&host->finish_tasklet);
1723+
1724+ iounmap(host->ioaddr);
1725+
1726+ release_mem_region(host->addr, host->size);
1727+
1728+ mmc_free_host(mmc);
1729+ DBG("%s: Exit....\n", __func__);
1730+}
1731+
1732+static int __init esdhc_probe(struct platform_device *pdev)
1733+{
1734+ int ret, i;
1735+ u8 slots;
1736+ struct esdhc_chip *chip;
1737+
1738+ BUG_ON(pdev == NULL);
1739+
1740+ /* Slew Rate */
1741+ MCF_GPIO_SRCR_SDHC = 3;
1742+ MCF_GPIO_SRCR_IRQ0 = 3;
1743+
1744+ /* Port Configuration */
1745+ MCF_GPIO_PAR_ESDHCH = 0xFF; /* DAT[3:0] */
1746+ MCF_GPIO_PAR_ESDHCL = 0x0F; /* CMD, CLK */
1747+
1748+ MCF_ESDHC_VSR = 2; /* disabled adma and set 3.0V */
1749+
1750+ MCF_INTC2_ICR31 = 2; /* SDHC irqstat */
1751+#if defined(CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1)
1752+ /*this is irq1 hardware work round*/
1753+ MCF_GPIO_PAR_IRQ0H |= 0x3;
1754+
1755+ MCF_EPORT_EPPAR = MCF_EPORT_EPPAR | MCF_EPORT_EPPAR_EPPA1_BOTH;
1756+ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE1;
1757+
1758+ MCF_INTC0_ICR1 = 7; /* IRQ1 */
1759+ DBG("MCF_INTC0_ICR1 %x MCF_EPORT_EPPAR %x "
1760+ "MCF_EPORT_EPFR %x MCF_EPORT_EPIER %x "
1761+ "MCF_INTC0_IMRL %x MCF_INTC0_INTFRCL %x "
1762+ "MCF_INTC0_IPRL %x\n",
1763+ MCF_INTC0_ICR1, MCF_EPORT_EPPAR, MCF_EPORT_EPFR,
1764+ MCF_EPORT_EPIER, MCF_INTC0_IMRL, MCF_INTC0_INTFRCL,
1765+ MCF_INTC0_IPRL);
1766+#elif defined(CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ7)
1767+ MCF_GPIO_PAR_IRQ0H |= MCF_GPIO_PAR_IRQH_IRQ7;
1768+
1769+ MCF_EPORT_EPPAR = MCF_EPORT_EPPAR | MCF_EPORT_EPPAR_EPPA7_BOTH;
1770+ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE7;
1771+
1772+ MCF_INTC0_ICR7 = 2; /* IRQ7 */
1773+ DBG("MCF_INTC0_ICR7 %x MCF_EPORT_EPPAR %x\n",
1774+ MCF_INTC0_ICR7, MCF_EPORT_EPPAR);
1775+#else
1776+ MCF_GPIO_PAR_IRQ0H |= MCF_GPIO_PAR_IRQH_IRQ7;
1777+
1778+ MCF_EPORT_EPPAR = MCF_EPORT_EPPAR | MCF_EPORT_EPPAR_EPPA7_BOTH;
1779+ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE7;
1780+
1781+ MCF_INTC0_ICR7 = 2; /* IRQ7 */
1782+ DBG("MCF_INTC0_ICR1 %x MCF_EPORT_EPPAR %x\n",
1783+ MCF_INTC0_ICR7, MCF_EPORT_EPPAR);
1784+#endif
1785+
1786+ slots = ESDHC_SLOTS_NUMBER;
1787+ DBG("found %d slot(s)\n", slots);
1788+ if (slots == 0) {
1789+ printk(KERN_INFO "%s: slot err %d\n", __func__, slots);
1790+ return -ENODEV;
1791+ }
1792+
1793+ chip = kmalloc(sizeof(struct esdhc_chip) +
1794+ sizeof(struct esdhc_host *) * slots, GFP_KERNEL);
1795+ if (!chip) {
1796+ ret = -ENOMEM;
1797+ printk(KERN_ERR "%s: kmalloc fail %x\n", __func__,
1798+ (unsigned int)chip);
1799+ goto err;
1800+ }
1801+
1802+ memset(chip, 0,
1803+ sizeof(struct esdhc_chip) +
1804+ sizeof(struct esdhc_host *) * slots);
1805+
1806+ chip->pdev = pdev;
1807+ chip->quirks = ESDHC_QUIRK_NO_CARD_NO_RESET;
1808+
1809+ if (debug_quirks)
1810+ chip->quirks = debug_quirks;
1811+
1812+ chip->num_slots = slots;
1813+ platform_set_drvdata(pdev, chip);
1814+
1815+ for (i = 0; i < slots; i++) {
1816+ ret = esdhc_probe_slot(pdev, i);
1817+ if (ret) {
1818+ for (i--; i >= 0; i--)
1819+ esdhc_remove_slot(pdev, i);
1820+ goto free;
1821+ }
1822+ }
1823+
1824+ return 0;
1825+
1826+free:
1827+ platform_set_drvdata(pdev, NULL);
1828+ kfree(chip);
1829+
1830+err:
1831+ return ret;
1832+}
1833+
1834+static int esdhc_remove(struct platform_device *pdev)
1835+{
1836+ int i;
1837+ struct esdhc_chip *chip;
1838+
1839+ chip = platform_get_drvdata(pdev);
1840+
1841+ if (chip) {
1842+ for (i = 0; i < chip->num_slots; i++)
1843+ esdhc_remove_slot(pdev, i);
1844+
1845+ platform_set_drvdata(pdev, NULL);
1846+
1847+ kfree(chip);
1848+ }
1849+
1850+ return 0;
1851+}
1852+
1853+/*-------------------------------------------------------------------------*/
1854+static struct platform_driver esdhc_driver = {
1855+ .probe = esdhc_probe,
1856+ .remove = esdhc_remove,
1857+ .suspend = esdhc_suspend,
1858+ .resume = esdhc_resume,
1859+ .driver = {
1860+ .name = DRIVER_NAME,
1861+ .owner = THIS_MODULE,
1862+ },
1863+};
1864+
1865+/*****************************************************************************\
1866+ * *
1867+ * Driver init/exit *
1868+ * *
1869+\*****************************************************************************/
1870+
1871+static int __init esdhc_drv_init(void)
1872+{
1873+ printk(KERN_INFO DRIVER_NAME
1874+ ": Freescale Enhanced Secure Digital Host"
1875+ " Controller driver\n");
1876+
1877+ return platform_driver_register(&esdhc_driver);
1878+}
1879+
1880+static void __exit esdhc_drv_exit(void)
1881+{
1882+ printk(KERN_INFO DRIVER_NAME
1883+ ": Freescale Enhanced Secure Digital Host"
1884+ " Controller driver exit\n");
1885+ platform_driver_unregister(&esdhc_driver);
1886+}
1887+
1888+module_init(esdhc_drv_init);
1889+module_exit(esdhc_drv_exit);
1890+
1891+module_param(debug_nodma, uint, 0444);
1892+module_param(debug_forcedma, uint, 0444);
1893+module_param(debug_quirks, uint, 0444);
1894+
1895+MODULE_AUTHOR("Chenghu Wu<b16972@freescale.com>");
1896+MODULE_DESCRIPTION("Enhanced Secure Digital Host Controller driver");
1897+MODULE_LICENSE("GPL");
1898+
1899+MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers.");
1900+MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers.");
1901+MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
1902--- /dev/null
1903+++ b/drivers/mmc/host/esdhc.h
1904@@ -0,0 +1,310 @@
1905+/*
1906+ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
1907+ * Author: Chenghu Wu <b16972@freescale.com>
1908+ * Xiaobo Xie <X.Xie@freescale.com>
1909+ *
1910+ * Based on mpc837x/driver/mmc/host/esdhc.c done by Xiaobo Xie
1911+ * Ported to Coldfire platform by Chenghu Wu
1912+ *
1913+ * This program is free software; you can redistribute it and/or modify
1914+ * it under the terms of the GNU General Public License as published by
1915+ * the Free Software Foundation; either version 2 of the License, or (at
1916+ * your option) any later version.
1917+ */
1918+#ifndef ESDHC_H
1919+#define ESDHC_H
1920+
1921+#define MMC_ERR_NONE 0
1922+#define MMC_ERR_TIMEOUT 1
1923+#define MMC_ERR_BADCRC 2
1924+#define MMC_ERR_FIFO 3
1925+#define MMC_ERR_FAILED 4
1926+#define MMC_ERR_INVALID 5
1927+
1928+#define MCF_CLOCK_PLL_DR (*(volatile unsigned long *)(0xFC0C0004))
1929+#define MCF_ESDHC_HOSTCAPBLT (*(volatile unsigned long *)(0xFC0CC040))
1930+#define MCF_ESDHC_ADMAESR (*(volatile unsigned long *)(0xFC0CC054))
1931+#define MCF_ESDHC_ADMASAR (*(volatile unsigned long *)(0xFC0CC058))
1932+#define MCF_ESDHC_VSR (*(volatile unsigned long *)(0xFC0CC0C0))
1933+#define MCF_ESDHC_HOSTVER (*(volatile unsigned long *)(0xFC0CC0FC))
1934+/*
1935+ * Controller registers (Big Endian)
1936+ */
1937+
1938+#define MCF_GPIO_PAR_SDHC_DATA3 0x20
1939+#define MCF_GPIO_PAR_SDHC_DATA2 0x10
1940+#define MCF_GPIO_PAR_SDHC_DATA1 0x08
1941+#define MCF_GPIO_PAR_SDHC_DATA0 0x04
1942+#define MCF_GPIO_PAR_SDHC_CMD 0x02
1943+#define MCF_GPIO_PAR_SDHC_CLK 0x01
1944+
1945+
1946+#define MCF_GPIO_SRCR_SDHC_LOWEST 0x00
1947+#define MCF_GPIO_SRCR_SDHC_LOWE 0x01
1948+#define MCF_GPIO_SRCR_SDHC_HIGH 0x02
1949+#define MCF_GPIO_SRCR_SDHC_HIGHEST 0x03
1950+
1951+
1952+#define MCF_GPIO_PCRL_SDHC_DATA3 0x80
1953+#define MCF_GPIO_PCRL_SDHC_DATA2 0x40
1954+#define MCF_GPIO_PCRL_SDHC_DATA1 0x20
1955+#define MCF_GPIO_PCRL_SDHC_DATA0 0x10
1956+#define MCF_GPIO_PCRL_SDHC_CMD 0x08
1957+#define MCF_GPIO_PCRL_SDHC_CLK 0x04
1958+
1959+#define MCF_INT_SDHC 63
1960+/* DMA System Address Register */
1961+#define ESDHC_DMA_ADDRESS 0x00
1962+
1963+/* Block Attributes Register */
1964+#define ESDHC_BLOCK_ATTR 0x04
1965+#define ESDHC_BLOCK_SIZE_MASK 0x00000fff
1966+#define ESDHC_BLCOK_CNT_MASK 0xffff0000
1967+#define ESDHC_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
1968+
1969+/* Command Argument */
1970+#define ESDHC_ARGUMENT 0x08
1971+
1972+/* Transfer Type Register */
1973+#define ESDHC_COMMAND 0x0C
1974+
1975+#define ESDHC_TRNS_DMA 0x00000001
1976+#define ESDHC_TRNS_BLK_CNT_EN 0x00000002
1977+#define ESDHC_TRNS_ACMD12 0x00000004
1978+#define ESDHC_TRNS_READ 0x00000010
1979+#define ESDHC_TRNS_MULTI 0x00000020
1980+
1981+#define ESDHC_CMD_RESP_MASK 0x00030000
1982+#define ESDHC_CMD_CRC_EN 0x00080000
1983+#define ESDHC_CMD_INDEX_EN 0x00100000
1984+#define ESDHC_CMD_DATA 0x00200000
1985+#define ESDHC_CMD_TYPE_MASK 0x00c00000
1986+#define ESDHC_CMD_INDEX 0x3f000000
1987+
1988+#define ESDHC_CMD_RESP_NONE 0x00000000
1989+#define ESDHC_CMD_RESP_LONG 0x00010000
1990+#define ESDHC_CMD_RESP_SHORT 0x00020000
1991+#define ESDHC_CMD_RESP_SHORT_BUSY 0x00030000
1992+
1993+#define ESDHC_MAKE_CMD(c, f) (((c & 0xff) << 24) | (f & 0xfb0037))
1994+
1995+/* Response Register */
1996+#define ESDHC_RESPONSE 0x10
1997+
1998+/* Buffer Data Port Register */
1999+#define ESDHC_BUFFER 0x20
2000+
2001+/* Present State Register */
2002+#define ESDHC_PRESENT_STATE 0x24
2003+#define ESDHC_CMD_INHIBIT 0x00000001
2004+#define ESDHC_DATA_INHIBIT 0x00000002
2005+#define ESDHC_DOING_WRITE 0x00000100
2006+#define ESDHC_DOING_READ 0x00000200
2007+#define ESDHC_SPACE_AVAILABLE 0x00000400
2008+#define ESDHC_DATA_AVAILABLE 0x00000800
2009+#define ESDHC_CARD_PRESENT 0x00010000
2010+#define ESDHC_WRITE_PROTECT 0x00080000
2011+
2012+/* Protocol control Register */
2013+#define ESDHC_PROTOCOL_CONTROL 0x28
2014+
2015+#define ESDHC_CTRL_BUS_MASK 0x00000006
2016+#define ESDHC_CTRL_4BITBUS 0x00000002
2017+#define ESDHC_CTRL_D3_DETEC 0x00000008
2018+#define ESDHC_CTRL_DTCT_EN 0x00000080
2019+#define ESDHC_CTRL_DTCT_STATUS 0x00000040
2020+#define ESDHC_CTRL_WU_CRM 0x04000000
2021+#define ESDHC_CTRL_WU_CINS 0x02000000
2022+#define ESDHC_CTRL_WU_CINT 0x01000000
2023+
2024+/* System Control Register */
2025+#define ESDHC_SYSTEM_CONTROL 0x2C
2026+
2027+#define ESDHC_CLOCK_MASK 0x0000fff0
2028+#define ESDHC_CLOCK_DEFAULT 0x00008000
2029+#define ESDHC_PREDIV_SHIFT 8
2030+#define ESDHC_DIVIDER_SHIFT 4
2031+#define ESDHC_CLOCK_CARD_EN 0x00000004
2032+#define ESDHC_CLOCK_INT_STABLE 0x00000002
2033+#define ESDHC_CLOCK_INT_EN 0x00000001
2034+
2035+#define ESDHC_TIMEOUT_MASK 0x000f0000
2036+#define ESDHC_TIMEOUT_SHIFT 16
2037+
2038+#define ESDHC_RESET_SHIFT 24
2039+#define ESDHC_RESET_ALL 0x01
2040+#define ESDHC_RESET_CMD 0x02
2041+#define ESDHC_RESET_DATA 0x04
2042+#define ESDHC_INIT_CARD 0x08
2043+
2044+/* Interrupt Register */
2045+#define ESDHC_INT_STATUS 0x30
2046+#define ESDHC_INT_ENABLE 0x34
2047+#define ESDHC_SIGNAL_ENABLE 0x38
2048+
2049+#define ESDHC_INT_RESPONSE 0x00000001
2050+#define ESDHC_INT_DATA_END 0x00000002
2051+#define ESDHC_INT_DMA_END 0x00000008
2052+#define ESDHC_INT_SPACE_AVAIL 0x00000010
2053+#define ESDHC_INT_DATA_AVAIL 0x00000020
2054+#define ESDHC_INT_CARD_INSERT 0x00000040
2055+#define ESDHC_INT_CARD_REMOVE 0x00000080
2056+#define ESDHC_INT_CARD_INT 0x00000100
2057+
2058+#define ESDHC_INT_TIMEOUT 0x00010000
2059+#define ESDHC_INT_CRC 0x00020000
2060+#define ESDHC_INT_END_BIT 0x00040000
2061+#define ESDHC_INT_INDEX 0x00080000
2062+#define ESDHC_INT_DATA_TIMEOUT 0x00100000
2063+#define ESDHC_INT_DATA_CRC 0x00200000
2064+#define ESDHC_INT_DATA_END_BIT 0x00400000
2065+#define ESDHC_INT_ACMD12ERR 0x01000000
2066+#define ESDHC_INT_DMAERR 0x10000000
2067+
2068+#define ESDHC_INT_NORMAL_MASK 0x00007FFF
2069+#define ESDHC_INT_ERROR_MASK 0xFFFF8000
2070+
2071+#define ESDHC_INT_CMD_MASK (ESDHC_INT_RESPONSE | ESDHC_INT_TIMEOUT | \
2072+ ESDHC_INT_CRC | ESDHC_INT_END_BIT | ESDHC_INT_INDEX)
2073+#define ESDHC_INT_DATA_MASK (ESDHC_INT_DATA_END | ESDHC_INT_DMA_END | \
2074+ ESDHC_INT_DATA_AVAIL | ESDHC_INT_SPACE_AVAIL | \
2075+ ESDHC_INT_DATA_TIMEOUT | ESDHC_INT_DATA_CRC | \
2076+ ESDHC_INT_DATA_END_BIT)
2077+
2078+#define ESDHC_INT_INSERT_MASK (ESDHC_INT_DATA_END_BIT | ESDHC_INT_DATA_CRC | \
2079+ ESDHC_INT_DATA_TIMEOUT | ESDHC_INT_INDEX | \
2080+ ESDHC_INT_END_BIT | ESDHC_INT_CRC | ESDHC_INT_TIMEOUT | \
2081+ ESDHC_INT_DATA_AVAIL | ESDHC_INT_SPACE_AVAIL | \
2082+ ESDHC_INT_DMA_END | ESDHC_INT_DATA_END | \
2083+ ESDHC_INT_RESPONSE | ESDHC_INT_CARD_REMOVE)
2084+
2085+#define ESDHC_INT_REMOVE_MASK (ESDHC_INT_DATA_END_BIT | ESDHC_INT_DATA_CRC | \
2086+ ESDHC_INT_DATA_TIMEOUT | ESDHC_INT_INDEX | \
2087+ ESDHC_INT_END_BIT | ESDHC_INT_CRC | ESDHC_INT_TIMEOUT | \
2088+ ESDHC_INT_DATA_AVAIL | ESDHC_INT_SPACE_AVAIL | \
2089+ ESDHC_INT_DMA_END | ESDHC_INT_DATA_END | \
2090+ ESDHC_INT_RESPONSE | ESDHC_INT_CARD_INSERT)
2091+
2092+/* Auto CMD12 Error Status Register */
2093+#define ESDHC_ACMD12_ERR 0x3C
2094+
2095+/* 3E-3F reserved */
2096+/* Host Controller Capabilities */
2097+#define ESDHC_CAPABILITIES 0x40
2098+
2099+#define ESDHC_MAX_BLOCK_MASK 0x00070000
2100+#define ESDHC_MAX_BLOCK_SHIFT 16
2101+#define ESDHC_CAN_DO_HISPD 0x00200000
2102+#define ESDHC_CAN_DO_DMA 0x00400000
2103+#define ESDHC_CAN_DO_SUSPEND 0x00800000
2104+#define ESDHC_CAN_VDD_330 0x01000000
2105+#define ESDHC_CAN_VDD_300 0x02000000
2106+#define ESDHC_CAN_VDD_180 0x04000000
2107+
2108+/* Watermark Level Register */
2109+#define ESDHC_WML 0x44
2110+#define ESDHC_WML_MASK 0xff
2111+#define ESDHC_WML_READ_SHIFT 0
2112+#define ESDHC_WML_WRITE_SHIFT 16
2113+
2114+/* 45-4F reserved for more caps and max curren*/
2115+
2116+/* Force Event Register */
2117+#define ESDHC_FORCE_EVENT 0x50
2118+
2119+/* 54-FB reserved */
2120+
2121+/* Host Controller Version Register */
2122+#define ESDHC_HOST_VERSION 0xFC
2123+
2124+#define ESDHC_VENDOR_VER_MASK 0xFF00
2125+#define ESDHC_VENDOR_VER_SHIFT 8
2126+#define ESDHC_SPEC_VER_MASK 0x00FF
2127+#define ESDHC_SPEC_VER_SHIFT 0
2128+
2129+#define ESDHC_DMA_SYSCTL 0x40C
2130+#define ESDHC_DMA_SNOOP 0x00000040
2131+
2132+#define ESDHC_SLOTS_NUMBER 1
2133+
2134+/* The SCCR[SDHCCM] Register */
2135+#define MPC837X_SCCR_OFFS 0xA08
2136+#define MPC837X_SDHCCM_MASK 0x0c000000
2137+#define MPC837X_SDHCCM_SHIFT 26
2138+
2139+#define esdhc_readl(addr) \
2140+ ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
2141+
2142+#define esdhc_writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b))
2143+
2144+static inline u32 fsl_readl(unsigned __iomem *addr)
2145+{
2146+ u32 val;
2147+ /*val = inl(addr);*/
2148+ val = esdhc_readl(addr);
2149+ return val;
2150+}
2151+
2152+static inline void fsl_writel(unsigned __iomem *addr, u32 val)
2153+{
2154+ /*outl(val, addr);*/
2155+ esdhc_writel(val, addr);
2156+}
2157+
2158+#define setbits32(_addr, _v) outl((_addr), inl(_addr) | (_v))
2159+#define clrbits32(_addr, _v) outl((_addr), inl(_addr) & ~(_v))
2160+
2161+struct esdhc_chip;
2162+
2163+struct esdhc_host {
2164+ struct esdhc_chip *chip;
2165+ struct mmc_host *mmc; /* MMC structure */
2166+
2167+ spinlock_t lock; /* Mutex */
2168+
2169+ int flags; /* Host attributes */
2170+#define ESDHC_USE_DMA (1<<0)
2171+
2172+ unsigned int max_clk; /* Max possible freq (MHz) */
2173+ unsigned int timeout_clk; /* Timeout freq (KHz) */
2174+
2175+ unsigned int clock; /* Current clock (MHz) */
2176+ unsigned short power; /* Current voltage */
2177+ unsigned short bus_width; /* current bus width */
2178+
2179+ struct mmc_request *mrq; /* Current request */
2180+ struct mmc_command *cmd; /* Current command */
2181+ struct mmc_data *data; /* Current data request */
2182+
2183+ struct scatterlist *cur_sg; /* We're working on this */
2184+ int num_sg; /* Entries left */
2185+ int offset; /* Offset into current sg */
2186+ int remain; /* Bytes left in current */
2187+
2188+ char slot_descr[20]; /* Name for reservations */
2189+
2190+ int card_insert;
2191+
2192+ int irq; /* Device IRQ */
2193+ unsigned long addr; /* Bus address */
2194+ unsigned int size; /* IO size */
2195+ void __iomem *ioaddr; /* Mapped address */
2196+
2197+ struct tasklet_struct card_tasklet; /* Tasklet structures */
2198+ struct tasklet_struct finish_tasklet;
2199+
2200+ struct timer_list timer; /* Timer for timeouts */
2201+ void *dma_tx_buf;
2202+ dma_addr_t dma_tx_dmahandle;
2203+};
2204+
2205+struct esdhc_chip {
2206+ struct platform_device *pdev;
2207+
2208+ unsigned long quirks;
2209+
2210+ int num_slots; /* Slots on controller */
2211+ struct esdhc_host *hosts[0]; /* Pointers to hosts */
2212+};
2213+
2214+#endif
2215

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