Root/target/linux/coldfire/patches/039-Add-PCI-bus-driver-for-M54455EVB-and-M547X_8X.patch

1From 3f21ef5f7b72937a1ae293e8ba6ebd0bb0b175e3 Mon Sep 17 00:00:00 2001
2From: Jingchang Lu <b35083@freescale.com>
3Date: Thu, 4 Aug 2011 09:59:49 +0800
4Subject: [PATCH 39/52] Add PCI bus driver for M54455EVB and M547X_8X
5
6Signed-off-by: Jingchang Lu <b35083@freescale.com>
7---
8 arch/m68k/coldfire/m5445x/devices.c | 9 +
9 arch/m68k/coldfire/m5445x/mcf5445x-pci.c | 721 +++++++++++++++++++++
10 arch/m68k/coldfire/m5445x/pci.c | 247 +++++++
11 arch/m68k/coldfire/m547x/pci.c | 1023 ++++++++++++++++++++++++++++++
12 arch/m68k/coldfire/m547x/pci_dummy.S | 45 ++
13 arch/m68k/include/asm/5445x_pci.h | 111 ++++
14 arch/m68k/include/asm/548x_pci.h | 99 +++
15 arch/m68k/include/asm/pci.h | 6 +
16 arch/m68k/kernel/bios32_mcf548x.c | 632 ++++++++++++++++++
17 drivers/pci/Makefile | 1 +
18 drivers/pci/access.c | 18 +
19 drivers/pci/setup-bus.c | 6 +
20 lib/iomap.c | 4 +
21 13 files changed, 2922 insertions(+), 0 deletions(-)
22 create mode 100644 arch/m68k/coldfire/m5445x/mcf5445x-pci.c
23 create mode 100644 arch/m68k/coldfire/m5445x/pci.c
24 create mode 100644 arch/m68k/coldfire/m547x/pci.c
25 create mode 100644 arch/m68k/coldfire/m547x/pci_dummy.S
26 create mode 100644 arch/m68k/include/asm/5445x_pci.h
27 create mode 100644 arch/m68k/include/asm/548x_pci.h
28 create mode 100644 arch/m68k/kernel/bios32_mcf548x.c
29
30--- a/arch/m68k/coldfire/m5445x/devices.c
31+++ b/arch/m68k/coldfire/m5445x/devices.c
32@@ -25,12 +25,15 @@
33 #include <linux/spi/mmc_spi.h>
34 #endif
35 
36+#include <linux/pci.h>
37+
38 #include <asm/coldfire.h>
39 #include <asm/mcfsim.h>
40 #include <asm/mcfuart.h>
41 #include <asm/mcfqspi.h>
42 #include <asm/mcfdspi.h>
43 #include <asm/cf_io.h>
44+#include <asm/pci.h>
45 
46 /* ATA Interrupt */
47 #define IRQ_ATA (64 + 64 + 54)
48@@ -517,6 +520,12 @@ void m5445x_uarts_init(void)
49 
50 static int __init init_BSP(void)
51 {
52+#ifndef CONFIG_M54455_PCI_initcall
53+#if defined(CONFIG_M54455) && defined(CONFIG_PCI)
54+ pci_init();
55+ pcibios_init();
56+#endif
57+#endif
58     m5445x_uarts_init();
59     platform_add_devices(m5445x_devices, ARRAY_SIZE(m5445x_devices));
60     return 0;
61--- /dev/null
62+++ b/arch/m68k/coldfire/m5445x/mcf5445x-pci.c
63@@ -0,0 +1,721 @@
64+/*
65+ * arch/m68k/coldfire/m5445x/mcf5445x-pci.c
66+ *
67+ * Coldfire M5445x specific PCI implementation.
68+ *
69+ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
70+ * Kurt Mahan <kmahan@freescale.com>
71+ */
72+
73+#include <linux/delay.h>
74+#include <linux/interrupt.h>
75+#include <linux/pci.h>
76+
77+#include <asm/mcfsim.h>
78+#include <asm/pci.h>
79+#include <asm/irq.h>
80+#include <asm/mcf5445x_pciarb.h>
81+#include <asm/mcf5445x_pci.h>
82+#include <asm/cf_io.h>
83+/*
84+ * Layout MCF5445x to PCI memory mappings:
85+ *
86+ * WIN MCF5445x PCI TYPE
87+ * --- -------- --- ----
88+ * [0] 0xA0000000 -> 0xACFFFFFF 0xA0000000 -> 0xACFFFFFF MEM
89+ * [1] 0xAC000000 -> 0xAEFFFFFF 0xAC000000 -> 0xAEFFFFFF IO
90+ * [2] 0xAF000000 -> 0xAFFFFFFF 0xAF000000 -> 0xAFFFFFFF CONFIG
91+ */
92+
93+void __iomem *pci_mem_map;
94+unsigned long pci_mem_mapsize = 256 * 1024 * 1024;
95+
96+#define MCF5445X_PCI_MEM_BASE ((unsigned int)pci_mem_map)
97+#define MCF5445X_PCI_MEM_BASE_PHY 0xA0000000
98+#define MCF5445X_PCI_MEM_SIZE 0x0C000000
99+
100+#define MCF5445X_PCI_IO_BASE \
101+ (MCF5445X_PCI_MEM_BASE + MCF5445X_PCI_MEM_SIZE)
102+#define MCF5445X_PCI_IO_SIZE 0x03000000
103+
104+#define MCF5445X_PCI_CONFIG_BASE \
105+ (MCF5445X_PCI_IO_BASE + MCF5445X_PCI_IO_SIZE)
106+#define MCF5445X_PCI_CONFIG_SIZE 0x01000000
107+
108+#define HOST_IO_BASE \
109+ (MCF5445X_PCI_MEM_BASE + MCF5445X_PCI_MEM_SIZE)
110+#define PCI_IO_MASK (MCF5445X_PCI_IO_SIZE - 1)
111+
112+#undef DEBUG
113+#ifdef DEBUG
114+# define DBG(x...) printk(x)
115+#else
116+# define DBG(x...)
117+#endif
118+
119+/* PCI Bus memory resource block */
120+struct resource pci_iomem_resource = {
121+ .name = "PCI memory space",
122+ .flags = IORESOURCE_MEM,
123+};
124+
125+/* PCI Bus ioport resource block */
126+struct resource pci_ioport_resource = {
127+ .name = "PCI I/O space",
128+ .flags = IORESOURCE_IO,
129+};
130+
131+/*
132+ * The M54455EVB multiplexes all the PCI interrupts via
133+ * the FPGA and routes them to a single interrupt. The
134+ * PCI spec requires all PCI interrupt routines be smart
135+ * enough to sort out their own interrupts.
136+ * The interrupt source from the FPGA is configured
137+ * to EPORT 3.
138+ */
139+#define MCF5445X_PCI_IRQ 0x43
140+
141+#define PCI_SLOTS 4
142+
143+/*
144+ * FPGA Info
145+ */
146+#define FPGA_PCI_IRQ_ENABLE (u32 *)0x09000000
147+#define FPGA_PCI_IRQ_STATUS (u32 *)0x09000004
148+#define FPGA_PCI_IRQ_ROUTE (u32 *)0x0900000c
149+#define FPGA_SEVEN_LED (u32 *)0x09000014
150+
151+
152+/*
153+ * mcf5445x_conf_device(struct pci_dev *dev)
154+ *
155+ * Machine dependent Configure the given device.
156+ *
157+ * Parameters:
158+ *
159+ * dev - the pci device.
160+ */
161+void
162+mcf5445x_conf_device(struct pci_dev *dev)
163+{
164+ set_fpga(FPGA_PCI_IRQ_ENABLE, 0x0f);
165+}
166+
167+/*
168+ * int mcf5445x_pci_config_read(unsigned int seg, unsigned int bus,
169+ * unsigned int devfn, int reg,
170+ * u32 *value)
171+ *
172+ * Read from PCI configuration space.
173+ *
174+ */
175+int mcf5445x_pci_config_read(unsigned int seg, unsigned int bus,
176+ unsigned int devfn, int reg, int len, u32 *value)
177+{
178+ u32 addr = MCF_PCI_PCICAR_BUSNUM(bus) |
179+ MCF_PCI_PCICAR_DEVNUM(PCI_SLOT(devfn)) |
180+ MCF_PCI_PCICAR_FUNCNUM(PCI_FUNC(devfn)) |
181+ MCF_PCI_PCICAR_DWORD(reg) |
182+ MCF_PCI_PCICAR_E;
183+
184+ if ((bus > 255) || (devfn > 255) || (reg > 255)) {
185+ *value = -1;
186+ return -EINVAL;
187+ }
188+
189+ /* setup for config mode */
190+ MCF_PCI_PCICAR = addr;
191+ __asm__ __volatile__("nop");
192+
193+ switch (len) {
194+ case 1:
195+ *value = *(volatile u8 *)(MCF5445X_PCI_CONFIG_BASE+(reg&3));
196+ break;
197+ case 2:
198+ *value = le16_to_cpu(*(volatile u16 *)
199+ (MCF5445X_PCI_CONFIG_BASE + (reg&2)));
200+ break;
201+ case 4:
202+ *value = le32_to_cpu(*(volatile u32 *)
203+ (MCF5445X_PCI_CONFIG_BASE));
204+ break;
205+ }
206+
207+ /* clear config mode */
208+ MCF_PCI_PCICAR = ~MCF_PCI_PCICAR_E;
209+ __asm__ __volatile__("nop");
210+
211+ return 0;
212+}
213+
214+/*
215+ * int mcf5445x_pci_config_write(unsigned int seg, unsigned int bus,
216+ * unsigned int devfn, int reg,
217+ * u32 *value)
218+ *
219+ * Write to PCI configuration space
220+ */
221+int mcf5445x_pci_config_write(unsigned int seg, unsigned int bus,
222+ unsigned int devfn, int reg, int len, u32 value)
223+{
224+ u32 addr = MCF_PCI_PCICAR_BUSNUM(bus) |
225+ MCF_PCI_PCICAR_DEVNUM(PCI_SLOT(devfn)) |
226+ MCF_PCI_PCICAR_FUNCNUM(PCI_FUNC(devfn)) |
227+ MCF_PCI_PCICAR_DWORD(reg) |
228+ MCF_PCI_PCICAR_E;
229+
230+ if ((bus > 255) || (devfn > 255) || (reg > 255))
231+ return -EINVAL;
232+
233+ /* setup for config mode */
234+ MCF_PCI_PCICAR = addr;
235+ __asm__ __volatile__("nop");
236+
237+ switch (len) {
238+ case 1:
239+ *(volatile u8 *)(MCF5445X_PCI_CONFIG_BASE+(reg&3)) = (u8)value;
240+ break;
241+ case 2:
242+ *(volatile u16 *)(MCF5445X_PCI_CONFIG_BASE+(reg&2)) =
243+ cpu_to_le16((u16)value);
244+ break;
245+ case 4:
246+ *(volatile u32 *)(MCF5445X_PCI_CONFIG_BASE) =
247+ cpu_to_le32(value);
248+ break;
249+ }
250+
251+ /* clear config mode */
252+ MCF_PCI_PCICAR = ~MCF_PCI_PCICAR_E;
253+ __asm__ __volatile__("nop");
254+
255+ return 0;
256+}
257+
258+/* hardware operations */
259+static struct pci_raw_ops mcf5445x_pci_ops = {
260+ .read = mcf5445x_pci_config_read,
261+ .write = mcf5445x_pci_config_write,
262+};
263+
264+/************************************************************************/
265+
266+/*
267+ * u8 pci_inb()
268+ *
269+ * Read a byte at specified address from I/O space
270+ */
271+unsigned char pci_inb(long addr)
272+{
273+ char value;
274+
275+ value = *(volatile unsigned char *) (HOST_IO_BASE |
276+ (addr & PCI_IO_MASK));
277+ DBG("PCI: inb addr=0x%08X, value=0x%02X\n", addr, value);
278+
279+ return (unsigned char) value;
280+}
281+
282+
283+/*
284+ * u16 pci_inw()
285+ *
286+ * Read a word at specified address from I/O space
287+ */
288+unsigned short pci_inw(long addr)
289+{
290+ short value;
291+ volatile unsigned short *ptr;
292+
293+ ptr = (volatile unsigned short *) (HOST_IO_BASE | (addr & PCI_IO_MASK));
294+ value = le16_to_cpu(*ptr);
295+
296+ DBG("PCI: inw addr=0x%08X, value=0x%04X\n", addr, value);
297+ return (unsigned short) value;
298+}
299+
300+/*
301+ * u16 pci_raw_inw()
302+ *
303+ * Read a raw word at specified address from I/O space
304+ */
305+unsigned short pci_raw_inw(long addr)
306+{
307+ short value;
308+ volatile unsigned short *ptr;
309+
310+ ptr = (volatile unsigned short *) (HOST_IO_BASE | (addr & PCI_IO_MASK));
311+ value = *ptr;
312+
313+ DBG("PCI: raw_inw addr=0x%08X, value=0x%04X\n", addr, value);
314+ return (unsigned short) value;
315+}
316+
317+/*
318+ * u32 pci_inl()
319+ *
320+ * Read a dword at specified address from I/O space
321+ */
322+unsigned long pci_inl(long addr)
323+{
324+ long value;
325+ volatile unsigned long *ptr;
326+
327+ ptr = (volatile unsigned long *) (HOST_IO_BASE | (addr & PCI_IO_MASK));
328+ value = le32_to_cpu(*ptr);
329+
330+ DBG("PCI: inl addr=0x%08X, value=0x%08X\n", addr, value);
331+ return (unsigned long) value;
332+}
333+
334+/*
335+ * u32 pci_raw_inl()
336+ *
337+ * Read a raw dword at specified address from I/O space
338+ */
339+unsigned long pci_raw_inl(long addr)
340+{
341+ long value;
342+ volatile unsigned long *ptr;
343+
344+ ptr = (volatile unsigned long *) (HOST_IO_BASE | (addr & PCI_IO_MASK));
345+ value = *ptr;
346+
347+ DBG("PCI: raw_inl addr=0x%08X, value=0x%08X\n", addr, value);
348+ return (unsigned long) value;
349+}
350+
351+/*
352+ * void pci_outb()
353+ *
354+ * Write a byte value at specified address to I/O space
355+ */
356+void pci_outb(unsigned char value, long addr)
357+{
358+
359+ *(volatile unsigned char *) (HOST_IO_BASE | (addr & PCI_IO_MASK)) \
360+ = value;
361+ DBG("PCI: outb addr=0x%08X, value=0x%02X\n", addr, value);
362+}
363+
364+
365+/*
366+ * void pci_outw()
367+ *
368+ * Write a word value at specified address to I/O space
369+ */
370+void pci_outw(volatile unsigned short value, volatile long addr)
371+{
372+ volatile unsigned short *ptr;
373+
374+ ptr = (volatile unsigned short *) (HOST_IO_BASE | (addr & PCI_IO_MASK));
375+ *ptr = cpu_to_le16(value);
376+ DBG("PCI: outw addr=0x%08X, value=0x%04X\n", addr, value);
377+}
378+
379+/*
380+ * void pci_raw_outw()
381+ *
382+ * Write a raw word value at specified address to I/O space
383+ */
384+void pci_raw_outw(volatile unsigned short value, volatile long addr)
385+{
386+ volatile unsigned short *ptr;
387+
388+ ptr = (volatile unsigned short *) (HOST_IO_BASE | (addr & PCI_IO_MASK));
389+ *ptr = value;
390+ DBG("PCI: raw_outw addr=0x%08X, value=0x%04X\n", addr, value);
391+}
392+
393+/*
394+ * void pci_outl()
395+ *
396+ * Write a long word value at specified address to I/O space
397+ */
398+void pci_outl(volatile unsigned long value, volatile long addr)
399+{
400+ volatile unsigned long *ptr;
401+
402+ ptr = (volatile unsigned long *)(HOST_IO_BASE | (addr & PCI_IO_MASK));
403+ *ptr = cpu_to_le32(value);
404+ DBG("PCI: outl addr=0x%08X, value=0x%08X\n", addr, value);
405+}
406+
407+/*
408+ * void pci_raw_outl()
409+ *
410+ * Write a raw long word value at specified address to I/O space
411+ */
412+void pci_raw_outl(volatile unsigned long value, volatile long addr)
413+{
414+ volatile unsigned long *ptr;
415+
416+ ptr = (volatile unsigned long *)(HOST_IO_BASE | (addr & PCI_IO_MASK));
417+ *ptr = value;
418+ DBG("PCI: raw_outl addr=0x%08X, value=0x%08X\n", addr, value);
419+}
420+
421+/*
422+ * void pci_insb()
423+ *
424+ * Read several byte values from specified I/O port
425+ */
426+void pci_insb(volatile unsigned char *addr, unsigned char *buf, int len)
427+{
428+ for (; len--; buf++)
429+ *buf = pci_inb((unsigned long)addr);
430+ DBG("PCI: pci_insb addr=0x%08X, buf=%p, len=%d\n", addr, buf, len);
431+}
432+
433+
434+/*
435+ * void pci_insw()
436+ *
437+ * Read several word values from specified I/O port
438+ */
439+void pci_insw(volatile unsigned short *addr, unsigned short *buf, int len)
440+{
441+ for (; len--; buf++)
442+ *buf = pci_inw((unsigned long)addr);
443+ DBG("PCI: pci_insw addr=0x%08X, buf=%p, len=%d\n", addr, buf, len);
444+}
445+
446+/*
447+ * void pci_insl()
448+ *
449+ * Read several dword values from specified I/O port
450+ */
451+void pci_insl(volatile unsigned long *addr, unsigned long *buf, int len)
452+{
453+ for (; len--; buf++)
454+ *buf = pci_inl((unsigned long)addr);
455+ DBG("PCI: pci_insl addr=0x%08X, buf=%p, len=%d\n", addr, buf, len);
456+}
457+
458+/*
459+ * void pci_outsb()
460+ *
461+ * Write several byte values to specified I/O port
462+ */
463+void pci_outsb(volatile unsigned char *addr, const unsigned char *buf, int len)
464+{
465+ for (; len--; buf++)
466+ pci_outb((unsigned long)addr, *buf);
467+ DBG("PCI: pci_outsb addr=0x%08X, buf=%p, len=%d\n", addr, buf, len);
468+}
469+
470+/*
471+ * void pci_outsw()
472+ *
473+ * Write several word values to specified I/O port
474+ */
475+void
476+pci_outsw(volatile unsigned short *addr, const unsigned short *buf, int len)
477+{
478+ for (; len--; buf++)
479+ pci_outw((unsigned long)addr, *buf);
480+ DBG("PCI: pci_outsw addr=0x%08X, buf=%p, len=%d\n", addr, buf, len);
481+}
482+
483+/*
484+ * void pci_outsl()
485+ *
486+ * Write several dword values to specified I/O port
487+ */
488+void pci_outsl(volatile unsigned long *addr, const unsigned long *buf, int len)
489+{
490+ for (; len--; buf++)
491+ pci_outl((unsigned long)addr, *buf);
492+ DBG("PCI: pci_outsl addr=0x%08X, buf=%p, len=%d\n", addr, buf, len);
493+}
494+/*
495+ * irqreturn_t mcf5445x_pci_interrupt( int irq, void *dev)
496+ *
497+ * PCI controller interrupt handler.
498+ */
499+static irqreturn_t
500+mcf5445x_pci_interrupt(int irq, void *dev)
501+{
502+ u32 status = MCF_PCI_PCIGSCR;
503+#ifdef DEBUG
504+ printk(KERN_INFO "PCI: Controller irq status=0x%08x\n", status);
505+#endif
506+ /* clear */
507+ MCF_PCI_PCIGSCR = status;
508+
509+ return IRQ_HANDLED;
510+}
511+
512+/*
513+ * irqreturn_t mcf5445x_pci_arb_interrupt( int irq, void *dev)
514+ *
515+ * PCI Arbiter interrupt handler.
516+ */
517+static irqreturn_t
518+mcf5445x_pci_arb_interrupt(int irq, void *dev)
519+{
520+ u32 status = MCF_PCIARB_PASR;
521+#ifdef DEBUG
522+ printk(KERN_INFO "PCI: Arbiter irq status=0x%08x\n", status);
523+#endif
524+ /* clear */
525+ MCF_PCIARB_PASR = status;
526+ return IRQ_HANDLED;
527+}
528+
529+/*
530+ * struct pci_bus_info *init_mcf5445x_pci(void)
531+ *
532+ * Machine specific initialisation:
533+ *
534+ * - Allocate and initialise a 'pci_bus_info' structure
535+ * - Initialize hardware
536+ *
537+ * Result: pointer to 'pci_bus_info' structure.
538+ */
539+int __init
540+init_mcf5445x_pci(void)
541+{
542+ /*
543+ * Initialize the PCI core
544+ */
545+ printk(KERN_INFO "init_mcf5445x_pci\n");
546+
547+ /* pci memory mapping */
548+ pci_mem_map = ioremap(MCF5445X_PCI_MEM_BASE_PHY, pci_mem_mapsize);
549+ if (!pci_mem_map) {
550+ printk(KERN_ERR "PCI memory map failed by ioremap!\n");
551+ return -ENOMEM;
552+ }
553+ printk(KERN_INFO "MCF5445X_PCI_MEM_BASE value is 0x%x\n", \
554+ MCF5445X_PCI_MEM_BASE);
555+
556+ /* Initialize pci resource */
557+ pci_iomem_resource.start = MCF5445X_PCI_MEM_BASE;
558+ pci_iomem_resource.end = MCF5445X_PCI_MEM_BASE + \
559+ MCF5445X_PCI_MEM_SIZE - 1;
560+
561+ pci_ioport_resource.start = MCF5445X_PCI_IO_BASE;
562+ pci_ioport_resource.end = MCF5445X_PCI_IO_BASE + \
563+ MCF5445X_PCI_IO_SIZE - 1;
564+
565+ /*
566+ * Must Reset!!! If bootloader has PCI enabled, it will cause
567+ * problem in linux when it tries to configure/find resources
568+ * for the pci devices
569+ */
570+ MCF_PCI_PCIGSCR = 1;
571+
572+ /* arbitration controller */
573+ MCF_PCIARB_PACR = MCF_PCIARB_PACR_INTMPRI |
574+ MCF_PCIARB_PACR_EXTMPRI(0x0f) |
575+ MCF_PCIARB_PACR_INTMINTEN |
576+ MCF_PCIARB_PACR_EXTMINTEN(0x0f);
577+
578+ /* pci pin assignment regs */
579+#if defined(CONFIG_PATA_FSL) || defined(CONFIG_PATA_FSL_MODULE)
580+ MCF_GPIO_PAR_PCI = MCF_GPIO_PAR_PCI_GNT0 |
581+ MCF_GPIO_PAR_PCI_GNT1 |
582+ MCF_GPIO_PAR_PCI_GNT2 |
583+ MCF_GPIO_PAR_PCI_GNT3_GNT3 |
584+ MCF_GPIO_PAR_PCI_REQ0 |
585+ MCF_GPIO_PAR_PCI_REQ1 |
586+ MCF_GPIO_PAR_PCI_REQ2 |
587+ MCF_GPIO_PAR_PCI_REQ3_REQ3;
588+
589+ MCF_GPIO_PAR_PCI = (MCF_GPIO_PAR_PCI &
590+ (MCF_GPIO_PAR_PCI_GNT3_MASK &
591+ MCF_GPIO_PAR_PCI_REQ3_MASK)) |
592+ MCF_GPIO_PAR_PCI_GNT3_ATA_DMACK |
593+ MCF_GPIO_PAR_PCI_REQ3_ATA_INTRQ;
594+#else
595+ MCF_GPIO_PAR_PCI = MCF_GPIO_PAR_PCI_GNT0 |
596+ MCF_GPIO_PAR_PCI_GNT1 |
597+ MCF_GPIO_PAR_PCI_GNT2 |
598+ MCF_GPIO_PAR_PCI_GNT3_GNT3 |
599+ MCF_GPIO_PAR_PCI_REQ0 |
600+ MCF_GPIO_PAR_PCI_REQ1 |
601+ MCF_GPIO_PAR_PCI_REQ2 |
602+ MCF_GPIO_PAR_PCI_REQ3_REQ3;
603+#endif
604+ /* target control reg */
605+ MCF_PCI_PCITCR = MCF_PCI_PCITCR_P |
606+ MCF_PCI_PCITCR_WCT(8);
607+
608+ /* PCI MEM address */
609+ MCF_PCI_PCIIW0BTAR = MCF5445X_PCI_MEM_BASE_PHY |
610+ (MCF5445X_PCI_MEM_BASE >> 16);
611+
612+ /* PCI MEM address */
613+ MCF_PCI_PCIIW1BTAR = (MCF5445X_PCI_MEM_BASE_PHY +
614+ MCF5445X_PCI_MEM_SIZE)
615+ | (MCF5445X_PCI_IO_BASE >> 16);
616+
617+ /* PCI IO address */
618+ MCF_PCI_PCIIW2BTAR = (MCF5445X_PCI_MEM_BASE_PHY +
619+ MCF5445X_PCI_MEM_SIZE + MCF5445X_PCI_IO_SIZE)
620+ | (MCF5445X_PCI_CONFIG_BASE >> 16);
621+
622+ /* window control */
623+ MCF_PCI_PCIIWCR = MCF_PCI_PCIIWCR_WINCTRL0_ENABLE |
624+ MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD |
625+ MCF_PCI_PCIIWCR_WINCTRL1_ENABLE |
626+ MCF_PCI_PCIIWCR_WINCTRL1_IO |
627+ MCF_PCI_PCIIWCR_WINCTRL2_ENABLE |
628+ MCF_PCI_PCIIWCR_WINCTRL2_IO;
629+
630+ /* initiator control reg */
631+ MCF_PCI_PCIICR = 0;
632+
633+ /* type 0 - command */
634+ MCF_PCI_PCISCR = MCF_PCI_PCISCR_MW | /* mem write/inval */
635+ MCF_PCI_PCISCR_B | /* bus master enable */
636+ MCF_PCI_PCISCR_MA | /* clear master abort error */
637+ MCF_PCI_PCISCR_M; /* mem access enable */
638+
639+ /* type 0 - config reg */
640+ MCF_PCI_PCICR1 = MCF_PCI_PCICR1_CACHELINESIZE(4) |
641+ MCF_PCI_PCICR1_LATTIMER(0xFF);
642+ /* type 0 - config 2 reg */
643+ MCF_PCI_PCICR2 = 0;
644+
645+ /* target control reg */
646+ MCF_PCI_PCITCR2 = MCF_PCI_PCITCR2_B0E | MCF_PCI_PCITCR2_B5E;
647+
648+ /* translate addresses from PCI[0] to CF[SDRAM] */
649+ MCF_PCI_PCITBATR0 = 0xFC000000 | MCF_PCI_PCITBATR5_EN;
650+ MCF_PCI_PCITBATR5 = MCF_RAMBAR1 | MCF_PCI_PCITBATR5_EN;
651+
652+ /* inbound window for memory */
653+ MCF_PCI_PCIBAR0 = 0xFC000000;
654+ MCF_PCI_PCIBAR5 = MCF_RAMBAR1;
655+
656+ /* setup controller interrupt handlers */
657+ if (request_irq(55+128, mcf5445x_pci_interrupt, IRQF_SHARED,
658+ "PCI Controller", NULL))
659+ printk(KERN_ERR "PCI: Unable to register controller irq\n");
660+
661+ if (request_irq(56+128, mcf5445x_pci_arb_interrupt, IRQF_SHARED,
662+ "PCI Arbiter", NULL))
663+ printk(KERN_ERR "PCI: Unable to register arbiter irq\n");
664+
665+ /* global control - clear reset bit */
666+ MCF_PCI_PCIGSCR = MCF_PCI_PCIGSCR_SEE |
667+ MCF_PCI_PCIGSCR_PEE;
668+
669+ /* let everything settle */
670+ udelay(1000);
671+
672+ /* allocate bus ioport resource */
673+ if (request_resource(&ioport_resource, &pci_ioport_resource) < 0)
674+ printk(KERN_ERR "PCI: Unable to alloc ioport resource\n");
675+
676+ /* allocate bus iomem resource */
677+ if (request_resource(&iomem_resource, &pci_iomem_resource) < 0)
678+ printk(KERN_ERR "PCI: Unable to alloc iomem resource\n");
679+
680+ /* setup FPGA to route PCI to IRQ3(67), SW7 to IRQ7, SW6 to IRQ4 */
681+ set_fpga(FPGA_PCI_IRQ_ENABLE, 0x00000000);
682+ set_fpga(FPGA_PCI_IRQ_ROUTE, 0x00000039);
683+ set_fpga(FPGA_SEVEN_LED, 0x000000FF);
684+
685+ raw_pci_ops = &mcf5445x_pci_ops;
686+#ifdef DEBUG
687+ mcf5445x_pci_dumpregs();
688+#endif
689+ return 0;
690+}
691+
692+/*
693+ * DEBUGGING
694+ */
695+
696+#ifdef DEBUG
697+struct regdump {
698+ u32 addr;
699+ char regname[16];
700+};
701+
702+struct regdump type0regs[] = {
703+ { 0xfc0a8000, "PCIIDR" },
704+ { 0xfc0a8004, "PCISCR" },
705+ { 0xfc0a8008, "PCICCRIR" },
706+ { 0xfc0a800c, "PCICR1" },
707+ { 0xfc0a8010, "PCIBAR0" },
708+ { 0xfc0a8014, "PCIBAR1" },
709+ { 0xfc0a8018, "PCIBAR2" },
710+ { 0xfc0a801c, "PCIBAR3" },
711+ { 0xfc0a8020, "PCIBAR4" },
712+ { 0xfc0a8024, "PCIBAR5" },
713+ { 0xfc0a8028, "PCICCPR" },
714+ { 0xfc0a802c, "PCISID" },
715+ { 0xfc0a8030, "PCIERBAR" },
716+ { 0xfc0a8034, "PCICPR" },
717+ { 0xfc0a803c, "PCICR2" },
718+ { 0, "" }
719+};
720+
721+struct regdump genregs[] = {
722+ { 0xfc0a8060, "PCIGSCR" },
723+ { 0xfc0a8064, "PCITBATR0" },
724+ { 0xfc0a8068, "PCITBATR1" },
725+ { 0xfc0a806c, "PCITCR1" },
726+ { 0xfc0a8070, "PCIIW0BTAR" },
727+ { 0xfc0a8074, "PCIIW1BTAR" },
728+ { 0xfc0a8078, "PCIIW2BTAR" },
729+ { 0xfc0a8080, "PCIIWCR" },
730+ { 0xfc0a8084, "PCIICR" },
731+ { 0xfc0a8088, "PCIISR" },
732+ { 0xfc0a808c, "PCITCR2" },
733+ { 0xfc0a8090, "PCITBATR0" },
734+ { 0xfc0a8094, "PCITBATR1" },
735+ { 0xfc0a8098, "PCITBATR2" },
736+ { 0xfc0a809c, "PCITBATR3" },
737+ { 0xfc0a80a0, "PCITBATR4" },
738+ { 0xfc0a80a4, "PCITBATR5" },
739+ { 0xfc0a80a8, "PCIINTR" },
740+ { 0xfc0a80f8, "PCICAR" },
741+ { 0, "" }
742+};
743+
744+struct regdump arbregs[] = {
745+ { 0xfc0ac000, "PACR" },
746+ { 0xfc0ac004, "PASR" }, /* documentation error */
747+ { 0, "" }
748+};
749+
750+/*
751+ * void mcf5445x_pci_dumpregs()
752+ *
753+ * Dump out all the PCI registers
754+ */
755+void
756+mcf5445x_pci_dumpregs(void)
757+{
758+ struct regdump *reg;
759+
760+ printk(KERN_INFO "*** MCF5445x PCI TARGET 0 REGISTERS ***\n");
761+
762+ reg = type0regs;
763+ while (reg->addr) {
764+ printk(KERN_INFO "0x%08x 0x%08x %s\n", reg->addr,
765+ *((u32 *)reg->addr), reg->regname);
766+ reg++;
767+ }
768+
769+ printk(KERN_INFO "\n*** MCF5445x PCI GENERAL REGISTERS ***\n");
770+ reg = genregs;
771+ while (reg->addr) {
772+ printk(KERN_INFO "0x%08x 0x%08x %s\n", reg->addr,
773+ *((u32 *)reg->addr), reg->regname);
774+ reg++;
775+ }
776+ printk(KERN_INFO "\n*** MCF5445x PCI ARBITER REGISTERS ***\n");
777+ reg = arbregs;
778+ while (reg->addr) {
779+ printk(KERN_INFO "0x%08x 0x%08x %s\n", reg->addr,
780+ *((u32 *)reg->addr), reg->regname);
781+ reg++;
782+ }
783+}
784+#endif /* DEBUG */
785--- /dev/null
786+++ b/arch/m68k/coldfire/m5445x/pci.c
787@@ -0,0 +1,247 @@
788+/*
789+ * linux/arch/m68k/coldfire/m5445x/pci.c
790+ *
791+ * PCI initialization for Coldfire architectures.
792+ *
793+ * Currently Supported:
794+ * M5445x
795+ *
796+ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
797+ * Kurt Mahan <kmahan@freescale.com>
798+ */
799+
800+#include <linux/kernel.h>
801+#include <linux/init.h>
802+#include <linux/pci.h>
803+
804+#include <asm/mcfsim.h>
805+#include <asm/pci.h>
806+
807+/* pci ops for reading/writing config */
808+struct pci_raw_ops *raw_pci_ops;
809+
810+/* pci debug flag */
811+static int debug_pci;
812+
813+static int
814+pci_read(struct pci_bus *bus, unsigned int devfn, int where,
815+ int size, u32 *value)
816+{
817+ return raw_pci_ops->read(0, bus->number, devfn, where, size, value);
818+}
819+
820+static int
821+pci_write(struct pci_bus *bus, unsigned int devfn, int where,
822+ int size, u32 value)
823+{
824+ return raw_pci_ops->write(0, bus->number, devfn, where, size, value);
825+}
826+
827+struct pci_ops pci_root_ops = {
828+ .read = pci_read,
829+ .write = pci_write,
830+};
831+
832+/*
833+ * pcibios_setup(char *)
834+ *
835+ * Initialize the pcibios based on cmd line params.
836+ */
837+char *
838+pcibios_setup(char *str)
839+{
840+ if (!strcmp(str, "debug")) {
841+ debug_pci = 1;
842+ return NULL;
843+ }
844+ return str;
845+}
846+
847+/*
848+ * We need to avoid collisions with `mirrored' VGA ports
849+ * and other strange ISA hardware, so we always want the
850+ * addresses to be allocated in the 0x000-0x0ff region
851+ * modulo 0x400.
852+ *
853+ * Why? Because some silly external IO cards only decode
854+ * the low 10 bits of the IO address. The 0x00-0xff region
855+ * is reserved for motherboard devices that decode all 16
856+ * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
857+ * but we want to try to avoid allocating at 0x2900-0x2bff
858+ * which might have be mirrored at 0x0100-0x03ff..
859+ */
860+resource_size_t
861+pcibios_align_resource(void *data, const struct resource *res,
862+ resource_size_t size, resource_size_t align)
863+{
864+ struct pci_dev *dev = data;
865+ resource_size_t start = res->start;
866+
867+ if (res->flags & IORESOURCE_IO) {
868+ if (size > 0x100)
869+ printk(KERN_ERR "PCI: I/O Region %s/%d too large"
870+ " (%ld bytes)\n", pci_name(dev),
871+ dev->resource - res, (long int)size);
872+
873+ if (start & 0x3ff)
874+ start = (start + 0x3ff) & ~0x3ff;
875+ }
876+
877+ return start;
878+}
879+EXPORT_SYMBOL(pcibios_align_resource);
880+
881+/*
882+ * Swizzle the device pin each time we cross a bridge
883+ * and return the slot number.
884+ */
885+static u8 __devinit
886+pcibios_swizzle(struct pci_dev *dev, u8 *pin)
887+{
888+ return 0;
889+}
890+
891+/*
892+ * Map a slot/pin to an IRQ.
893+ */
894+static int
895+pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
896+{
897+ return 0x43;
898+}
899+
900+/*
901+ * pcibios_update_irq(struct pci_dev *dev, int irq)
902+ *
903+ * Update a PCI interrupt.
904+ */
905+void
906+pcibios_update_irq(struct pci_dev *dev, int irq)
907+{
908+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
909+}
910+
911+/*
912+ * pcibios_enable_device(struct pci_dev *dev, int mask)
913+ *
914+ * Enable a device on the PCI bus.
915+ */
916+int
917+pcibios_enable_device(struct pci_dev *dev, int mask)
918+{
919+ u16 cmd, old_cmd;
920+ int idx;
921+ struct resource *r;
922+
923+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
924+ old_cmd = cmd;
925+ for (idx = 0; idx < DEVICE_COUNT_RESOURCE; idx++) {
926+ r = &dev->resource[idx];
927+ if (!r->start && r->end) {
928+ printk(KERN_ERR "PCI: Device %s not available because "
929+ "of resource collisions\n", pci_name(dev));
930+ return -EINVAL;
931+ }
932+ if (r->flags & IORESOURCE_IO)
933+ cmd |= PCI_COMMAND_IO;
934+ if (r->flags & IORESOURCE_MEM)
935+ cmd |= PCI_COMMAND_MEMORY;
936+ }
937+ if (cmd != old_cmd) {
938+ printk("PCI: Enabling device %s (%04x -> %04x)\n",
939+ pci_name(dev), old_cmd, cmd);
940+ pci_write_config_word(dev, PCI_COMMAND, cmd);
941+#ifdef CONFIG_M54455
942+ mcf5445x_conf_device(dev);
943+#endif
944+ }
945+
946+ return 0;
947+}
948+
949+/*
950+ * pcibios_fixup_bus(struct pci_bus *bus)
951+ */
952+void
953+pcibios_fixup_bus(struct pci_bus *bus)
954+{
955+ struct pci_dev *dev = bus->self;
956+
957+ if (!dev) {
958+ /* Root bus. */
959+#ifdef CONFIG_M54455
960+ bus->resource[0] = &pci_ioport_resource;
961+ bus->resource[1] = &pci_iomem_resource;
962+#endif
963+ }
964+}
965+
966+/*
967+ * pcibios_init(void)
968+ *
969+ * Allocate/initialize low level pci bus/devices.
970+ */
971+#ifdef CONFIG_M54455_PCI_initcall
972+static int __init
973+#else
974+int __init
975+#endif
976+pcibios_init(void)
977+{
978+ struct pci_bus *bus;
979+
980+ if (!raw_pci_ops) {
981+ printk(KERN_WARNING "PCIBIOS: FATAL: NO PCI Hardware found\n");
982+ return 0;
983+ }
984+
985+ /* allocate and scan the (only) bus */
986+ bus = pci_scan_bus_parented(NULL, 0, &pci_root_ops, NULL);
987+
988+ /* setup everything */
989+ if (bus) {
990+ /* compute the bridge window sizes */
991+ pci_bus_size_bridges(bus);
992+
993+ /* (re)assign device resources */
994+ pci_bus_assign_resources(bus);
995+
996+ /* add the bus to the system */
997+ pci_bus_add_devices(bus);
998+
999+ /* fixup irqs */
1000+ pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq);
1001+ }
1002+
1003+ return 0;
1004+}
1005+
1006+/*
1007+ * pci_init(void)
1008+ *
1009+ * Initialize the PCI Hardware.
1010+ */
1011+#ifdef CONFIG_M54455_PCI_initcall
1012+static int __init
1013+#else
1014+int __init
1015+#endif
1016+pci_init(void)
1017+{
1018+ printk(KERN_INFO "pci_init\n");
1019+#if defined(CONFIG_M54455)
1020+ init_mcf5445x_pci();
1021+#endif
1022+ if (!raw_pci_ops)
1023+ printk(KERN_ERR "PCI: FATAL: NO PCI Detected\n");
1024+
1025+ return 0;
1026+}
1027+
1028+#ifdef CONFIG_M54455_PCI_initcall
1029+/* low level hardware (first) */
1030+arch_initcall(pci_init);
1031+
1032+/* basic bios init (second) */
1033+subsys_initcall(pcibios_init);
1034+#endif
1035--- /dev/null
1036+++ b/arch/m68k/coldfire/m547x/pci.c
1037@@ -0,0 +1,1023 @@
1038+/*
1039+ * ColdFire 547x/548x PCI Host Controller functions
1040+ *
1041+ * Copyright (C) 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
1042+ * Shrek Wu b16972@freescale.com
1043+ * This code is based on the 2.6.10 version of pci.c
1044+ *
1045+ * This program is free software; you can redistribute it and/or modify
1046+ * it under the terms of the GNU General Public License as published by
1047+ * the Free Software Foundation; either version 2 of the License, or
1048+ * (at your option) any later version.
1049+ *
1050+ * This program is distributed in the hope that it will be useful,
1051+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1052+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1053+ * GNU General Public License for more details.
1054+ *
1055+ * You should have received a copy of the GNU General Public License
1056+ * along with this program; if not, write to the Free Software
1057+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
1058+ */
1059+#include <linux/kernel.h>
1060+#include <linux/types.h>
1061+#include <linux/init.h>
1062+#include <linux/mm.h>
1063+#include <linux/string.h>
1064+#include <linux/pci.h>
1065+#include <linux/ioport.h>
1066+#include <linux/slab.h>
1067+#include <linux/version.h>
1068+#include <linux/interrupt.h>
1069+#include <linux/delay.h>
1070+
1071+#include <linux/dma-mapping.h>
1072+#include <asm/coldfire.h>
1073+#include <linux/io.h>
1074+#include <asm/m5485sim.h>
1075+#include <asm/m5485pci.h>
1076+#include <asm/irq.h>
1077+#include <linux/pci.h>
1078+#include <asm/virtconvert.h>
1079+
1080+
1081+#undef DEBUG
1082+/*define DEBUG*/
1083+#ifdef DEBUG
1084+/*#define DBG(x...) printk(KERN_DEBUG x)*/
1085+#define DBG(x...) printk(x)
1086+#else
1087+#define DBG(x...)
1088+#endif
1089+
1090+/*
1091+ * Bridge configration dafaults
1092+ */
1093+#define PCI_RETRIES 0
1094+#define PCI_CACHE_LINE 8
1095+#define PCI_MINGNT 1
1096+#define PCI_MAXLAT 42
1097+
1098+
1099+/*
1100+ * Initiator windows setting
1101+ */
1102+#define HOST_MEM_BASE 0xD0000000
1103+/* ColdFire Memory window base */
1104+#define PCI_MEM_BASE 0xD0000000
1105+/* PCI Memory window base */
1106+#define PCI_MEM_SIZE 0x08000000
1107+/* Memory window size (128M) */
1108+#define HOST_IO_BASE 0xD8000000
1109+/* ColdFire I/O window base */
1110+#define PCI_IO_BASE_ADDR 0x00000000
1111+/* PCI I/O window base */
1112+#define PCI_IO_SIZE 0x00010000
1113+/* I/O window size (64K) */
1114+/*#define HOST_CFG_BASE 0xD8000000*/
1115+#define HOST_CFG_BASE 0xD8008000
1116+/* ColdFire config window base */
1117+#define HOST_DMA_BASE CONFIG_SDRAM_BASE
1118+/* ColdFire PCI-DMA window base */
1119+#define PCI_HDR_BASE (MCF_MBAR+0xB00)
1120+/* ColdFire config registers */
1121+
1122+#define PCI_MEM_MASK (PCI_MEM_SIZE-1)
1123+#define PCI_IO_MASK (PCI_IO_SIZE-1)
1124+
1125+/* Macro to set initiator window */
1126+#define WxBAR(host_address, pci_address, size) \
1127+ (((host_address) & 0xff000000) | \
1128+ ((((size)-1) & 0xff000000) >> 8) | \
1129+ ((pci_address) & 0xff000000) >> 16)
1130+
1131+/*
1132+ * BIOS internal data
1133+ */
1134+static u8 revision; /* controller revision */
1135+
1136+/*
1137+ * Board specific setting
1138+ */
1139+const unsigned int irq_lines[] = { 5, 7 };
1140+
1141+#define N_SLOTS (sizeof(board_info) / sizeof(board_info[0]))
1142+#define N_IRQS (sizeof(irq_lines) / sizeof(irq_lines[0]))
1143+#define BRIDGE_SLOT 0
1144+
1145+const struct slotinfo {
1146+ unsigned char idsel; /* device number */
1147+ unsigned char irq; /* external IRQ */
1148+ unsigned char req; /* REQ line number */
1149+ unsigned char gnt; /* GNT line number */
1150+} board_info[] = {
1151+ {0, 0, 0, 0}, /* Bridge */
1152+ {17, 5, 1, 1}, /* Slot #1 */
1153+ {18, 5, 2, 2}, /* Slot #2 */
1154+ {20, 7, 3, 3}, /* Slot #3 */
1155+ {21, 7, 4, 4}, /* Slot #4 */
1156+};
1157+
1158+/************************************************************************/
1159+
1160+/*
1161+ * static int mk_conf_addr()
1162+ *
1163+ * Return type0 or type1 configuration address
1164+ * by the means of device address and PCI dword location
1165+ * 0 - for not existing slots
1166+ */
1167+static int mk_conf_addr(/*struct pci_dev *dev*/
1168+ struct pci_bus *bus, unsigned int devfn, int where)
1169+{
1170+ int slot, func, address, idsel, dev_fn;
1171+
1172+ if (bus->number) {
1173+ address = MCF_PCICAR_E | (bus->number << 16) |
1174+ (devfn << 8) | (where & 0xfc);
1175+ } else {
1176+ slot = PCI_SLOT(devfn);
1177+ if (slot > N_SLOTS || slot == BRIDGE_SLOT)
1178+ return 0;
1179+ else {
1180+ func = PCI_FUNC(devfn);
1181+ idsel = board_info[slot].idsel;
1182+
1183+ dev_fn = PCI_DEVFN(idsel, func);
1184+ address = MCF_PCICAR_E | (bus->number << 16) |
1185+ (dev_fn << 8) | (where & 0xfc);
1186+ }
1187+ }
1188+
1189+ return address;
1190+}
1191+
1192+/*
1193+ * static int read_config_byte()
1194+ *
1195+ * Read a byte from configuration space of specified device
1196+ */
1197+static int read_config_byte(/*struct pci_dev *dev*/
1198+ struct pci_bus *bus, unsigned int devfn, int where, u8 *value)
1199+{
1200+ int slot;
1201+ int address;
1202+ int result;
1203+
1204+ *value = 0xff;
1205+ result = PCIBIOS_SUCCESSFUL;
1206+
1207+ slot = PCI_SLOT(devfn);
1208+ if (slot == BRIDGE_SLOT) {
1209+ if (where <= 0x40)
1210+ *value = *(volatile u8 *) (PCI_HDR_BASE +
1211+ (where & 0xfc) + (where & 3));
1212+ else
1213+ *value = 0;
1214+ } else {
1215+ address = mk_conf_addr(bus, devfn, where);
1216+ if (!address)
1217+ result = PCIBIOS_DEVICE_NOT_FOUND;
1218+ else {
1219+ MCF_PCICAR = address;
1220+ __asm__ __volatile__("nop");
1221+ *value = *(volatile u8 *) (HOST_CFG_BASE + (where & 3));
1222+ }
1223+ }
1224+ __asm("tpf");
1225+ MCF_PCICAR &= ~MCF_PCICAR_E;
1226+ DBG("PCI: read_config_byte bus=%d, dev=%d, fn=%d,"
1227+ " addr=0x%02X, val=0x%02X, ret=%02X\n",
1228+ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, *value, result);
1229+
1230+ return result;
1231+}
1232+
1233+/*
1234+ * static int read_config_word()
1235+ *
1236+ * Read a word from configuration space of specified device
1237+ */
1238+static int read_config_word(/*struct pci_dev *dev*/
1239+ struct pci_bus *bus, unsigned int devfn, int where, u16 *value)
1240+{
1241+ int slot;
1242+ int address;
1243+ int result;
1244+
1245+ *value = 0xffff;
1246+ result = PCIBIOS_SUCCESSFUL;
1247+
1248+ if (where & 0x1)
1249+ result = PCIBIOS_BAD_REGISTER_NUMBER;
1250+ else {
1251+ slot = PCI_SLOT(devfn);
1252+ if (slot == BRIDGE_SLOT) {
1253+ if (where <= 0x3f)
1254+ *value =
1255+ *(volatile u16 *) (PCI_HDR_BASE +
1256+ (where & 0xfc) + (where & 2));
1257+ else
1258+ *value = 0;
1259+ } else {
1260+ address = mk_conf_addr(bus, devfn, where);
1261+ if (!address)
1262+ result = PCIBIOS_DEVICE_NOT_FOUND;
1263+ else {
1264+ MCF_PCICAR = address;
1265+ __asm__ __volatile__("nop");
1266+ *value = le16_to_cpu(*(volatile u16 *)
1267+ (HOST_CFG_BASE +
1268+ (where & 2)));
1269+ }
1270+ }
1271+ }
1272+ __asm("tpf");
1273+ MCF_PCICAR &= ~MCF_PCICAR_E;
1274+ DBG("PCI: read_config_word bus=%d, dev=%d, fn=%d,"
1275+ " addr=0x%02X, val=0x%04X ret=%02X\n",
1276+ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, *value, result);
1277+
1278+ return result;
1279+}
1280+
1281+/*
1282+ * static int read_config_dword()
1283+ *
1284+ * Read a long word from configuration space of specified device
1285+ */
1286+static int read_config_dword(/*struct pci_dev *dev*/
1287+ struct pci_bus *bus, unsigned int devfn, int where, u32 *value)
1288+{
1289+ int slot;
1290+ int address;
1291+ int result;
1292+
1293+ *value = 0xffffffff;
1294+ result = PCIBIOS_SUCCESSFUL;
1295+
1296+ if (where & 0x3)
1297+ result = PCIBIOS_BAD_REGISTER_NUMBER;
1298+ else {
1299+ slot = PCI_SLOT(devfn);
1300+ if (slot == BRIDGE_SLOT) {
1301+ if (where <= 0x3d)
1302+ *value =
1303+ *(volatile u32 *) (PCI_HDR_BASE + where);
1304+ else
1305+ *value = 0;
1306+ __asm("tpf");
1307+ } else {
1308+ address = mk_conf_addr(bus, devfn, where);
1309+ if (!address)
1310+ result = PCIBIOS_DEVICE_NOT_FOUND;
1311+ else {
1312+ MCF_PCICAR = address;
1313+ __asm__ __volatile__("nop");
1314+ *value = le32_to_cpu(*(volatile u32 *)
1315+ (HOST_CFG_BASE));
1316+ __asm("tpf");
1317+ if (bus->number != 0 && revision < 1) {
1318+ volatile u32 temp;
1319+ MCF_PCICAR |= 0xff0000;
1320+ temp = *(volatile u32 *)
1321+ (HOST_CFG_BASE);
1322+ }
1323+ }
1324+ }
1325+ }
1326+
1327+ MCF_PCICAR &= ~MCF_PCICAR_E;
1328+ DBG("PCI: read_config_dword bus=%d, dev=%d, fn=%d, "
1329+ "addr=0x%02X, value=0x%08X ret=%02X\n",
1330+ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, *value, result);
1331+
1332+ return result;
1333+}
1334+
1335+
1336+
1337+/*
1338+ * static int write_config_byte()
1339+ *
1340+ * Write a byte to configuration space of specified device
1341+ */
1342+static int write_config_byte(/*struct pci_dev *dev*/
1343+ struct pci_bus *bus, unsigned int devfn, int where, u8 value)
1344+{
1345+ int slot;
1346+ int address;
1347+ int result;
1348+
1349+ result = PCIBIOS_SUCCESSFUL;
1350+
1351+ slot = PCI_SLOT(devfn);
1352+ if (slot == BRIDGE_SLOT) {
1353+ if (where <= 0x40)
1354+ *(volatile u8 *) (PCI_HDR_BASE + (where & 0xfc)
1355+ + (where & 3)) = value;
1356+ } else {
1357+ address = mk_conf_addr(bus, devfn, where);
1358+ if (!address)
1359+ result = PCIBIOS_DEVICE_NOT_FOUND;
1360+ else {
1361+ MCF_PCICAR = address;
1362+ __asm__ __volatile__("tpf");
1363+ *(volatile u8 *) (HOST_CFG_BASE + (where & 3)) = value;
1364+ }
1365+ }
1366+ __asm("tpf");
1367+ MCF_PCICAR &= ~MCF_PCICAR_E;
1368+ pci_dummy_function();
1369+
1370+ DBG("PCI: write_config_byte bus=%d, dev=%d, fn=%d, "
1371+ "addr=0x%02X, value=0x%02X ret=%02X\n",
1372+ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, value, result);
1373+
1374+ return result;
1375+}
1376+
1377+/*
1378+ * static int write_config_word()
1379+ *
1380+ * Write a word to configuration space of specified device
1381+ */
1382+static int write_config_word(/*struct pci_dev *dev*/
1383+ struct pci_bus *bus, unsigned int devfn, int where, u16 value)
1384+{
1385+ int slot;
1386+ int address;
1387+ int result;
1388+
1389+ result = PCIBIOS_SUCCESSFUL;
1390+
1391+ if (where & 0x1)
1392+ result = PCIBIOS_BAD_REGISTER_NUMBER;
1393+ else {
1394+ slot = PCI_SLOT(devfn);
1395+ if (slot == BRIDGE_SLOT) {
1396+ if (where <= 0x3f)
1397+ *(volatile u16 *) (PCI_HDR_BASE +
1398+ (where & 0xfc) + (where & 2)) = value;
1399+ } else {
1400+ address = mk_conf_addr(bus, devfn, where);
1401+ if (!address)
1402+ result = PCIBIOS_DEVICE_NOT_FOUND;
1403+ else {
1404+ MCF_PCICAR = address;
1405+ __asm__ __volatile__("tpf");
1406+ *(volatile u16 *) (HOST_CFG_BASE
1407+ + (where & 2)) =
1408+ cpu_to_le16(value);
1409+ }
1410+ }
1411+ }
1412+ __asm("tpf");
1413+ MCF_PCICAR &= ~MCF_PCICAR_E;
1414+ pci_dummy_function();
1415+
1416+ DBG("PCI: write_config_word bus=%d, dev=%d, fn=%d, "
1417+ "addr=0x%02X, value=0x%04X ret=%02X\n",
1418+ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, value, result);
1419+
1420+ return result;
1421+}
1422+
1423+/*
1424+ * static int write_config_dword()
1425+ *
1426+ * Write a long word to configuration space of specified device
1427+ */
1428+static int write_config_dword(/*struct pci_dev *dev*/
1429+ struct pci_bus *bus, unsigned int devfn, int where, u32 value)
1430+{
1431+ int slot;
1432+ int address;
1433+ int result;
1434+
1435+ result = PCIBIOS_SUCCESSFUL;
1436+
1437+ if (where & 0x3)
1438+ result = PCIBIOS_BAD_REGISTER_NUMBER;
1439+ else {
1440+ slot = PCI_SLOT(devfn);
1441+ if (slot == BRIDGE_SLOT) {
1442+ if (where <= 0x3d)
1443+ *(volatile u32 *) (PCI_HDR_BASE + where) =
1444+ value;
1445+ } else {
1446+ address = mk_conf_addr(bus, devfn, where);
1447+ if (!address)
1448+ result = PCIBIOS_DEVICE_NOT_FOUND;
1449+ else {
1450+ MCF_PCICAR = address;
1451+ __asm__ __volatile__("tpf");
1452+ *(volatile u32 *) (HOST_CFG_BASE) =
1453+ cpu_to_le32(value);
1454+ }
1455+ }
1456+ }
1457+ __asm("tpf");
1458+ MCF_PCICAR &= ~MCF_PCICAR_E;
1459+ pci_dummy_function();
1460+
1461+ DBG("PCI: write_config_dword dev=%d, fn=%d,"
1462+ "addr=0x%02X, value=0x%08X ret=%02X\n",
1463+ PCI_SLOT(devfn), PCI_FUNC(devfn), where, value, result);
1464+
1465+ return result;
1466+}
1467+
1468+static int config_read(struct pci_bus *bus, unsigned int devfn,
1469+ int where, int size, u32 *val)
1470+{
1471+ switch (size) {
1472+ case 1:
1473+ return read_config_byte(bus, devfn, where, (u8 *) val);
1474+ case 2:
1475+ return read_config_word(bus, devfn, where, (u16 *) val);
1476+ default:
1477+ return read_config_dword(bus, devfn, where, val);
1478+ }
1479+}
1480+
1481+static int config_write(struct pci_bus *bus, unsigned int devfn,
1482+ int where, int size, u32 val)
1483+{
1484+ switch (size) {
1485+ case 1:
1486+ return write_config_byte(bus, devfn, where, (u8) val);
1487+ case 2:
1488+ return write_config_word(bus, devfn, where, (u16) val);
1489+ default:
1490+ return write_config_dword(bus, devfn, where, val);
1491+ }
1492+}
1493+
1494+/*
1495+ * configuration routines entry points
1496+ */
1497+static struct pci_ops bus_ops = {
1498+ .read = config_read,
1499+ .write = config_write,
1500+};
1501+
1502+/************************************************************************/
1503+
1504+/*
1505+ * u8 pci_inb()
1506+ *
1507+ * Read a byte at specified address from I/O space
1508+ */
1509+unsigned char pci_inb(long addr)
1510+{
1511+ char value;
1512+
1513+ value = *(volatile unsigned char *)(HOST_IO_BASE |
1514+ (addr & PCI_IO_MASK));
1515+ DBG("PCI: inb addr=0x%08X, value=0x%02X\n", addr, value);
1516+
1517+ return (unsigned char) value;
1518+}
1519+
1520+
1521+/*
1522+ * u16 pci_inw()
1523+ *
1524+ * Read a word at specified address from I/O space
1525+ */
1526+unsigned short pci_inw(long addr)
1527+{
1528+ short value;
1529+ volatile unsigned short *ptr;
1530+
1531+ ptr = (volatile unsigned short *) (HOST_IO_BASE | (addr & PCI_IO_MASK));
1532+ value = le16_to_cpu(*ptr);
1533+
1534+ DBG("PCI: inw addr=0x%08X, value=0x%04X\n", addr, value);
1535+ return (unsigned short) value;
1536+}
1537+
1538+/*
1539+ * u16 pci_raw_inw()
1540+ *
1541+ * Read a raw word at specified address from I/O space
1542+ */
1543+unsigned short pci_raw_inw(long addr)
1544+{
1545+ short value;
1546+ volatile unsigned short *ptr;
1547+
1548+ ptr = (volatile unsigned short *) (HOST_IO_BASE | (addr & PCI_IO_MASK));
1549+ value = *ptr;
1550+
1551+ DBG("PCI: raw_inw addr=0x%08X, value=0x%04X\n", addr, value);
1552+ return (unsigned short) value;
1553+}
1554+
1555+/*
1556+ * u32 pci_inl()
1557+ *
1558+ * Read a dword at specified address from I/O space
1559+ */
1560+unsigned long pci_inl(long addr)
1561+{
1562+ long value;
1563+ volatile unsigned long *ptr;
1564+
1565+ ptr = (volatile unsigned long *) (HOST_IO_BASE | (addr & PCI_IO_MASK));
1566+ value = le32_to_cpu(*ptr);
1567+
1568+ DBG("PCI: inl addr=0x%08X, value=0x%08X\n", addr, value);
1569+ return (unsigned long) value;
1570+}
1571+
1572+/*
1573+ * u32 pci_raw_inl()
1574+ *
1575+ * Read a raw dword at specified address from I/O space
1576+ */
1577+unsigned long pci_raw_inl(long addr)
1578+{
1579+ long value;
1580+ volatile unsigned long *ptr;
1581+
1582+ ptr = (volatile unsigned long *) (HOST_IO_BASE | (addr & PCI_IO_MASK));
1583+ value = *ptr;
1584+
1585+ DBG("PCI: raw_inl addr=0x%08X, value=0x%08X\n", addr, value);
1586+ return (unsigned long) value;
1587+}
1588+
1589+/*
1590+ * void pci_outb()
1591+ *
1592+ * Write a byte value at specified address to I/O space
1593+ */
1594+void pci_outb(unsigned char value, long addr)
1595+{
1596+
1597+ *(volatile unsigned char *)(HOST_IO_BASE | (addr & PCI_IO_MASK))
1598+ = value;
1599+ DBG("PCI: outb addr=0x%08X, value=0x%02X\n", addr, value);
1600+}
1601+
1602+
1603+/*
1604+ * void pci_outw()
1605+ *
1606+ * Write a word value at specified address to I/O space
1607+ */
1608+void pci_outw(volatile unsigned short value, volatile long addr)
1609+{
1610+ volatile unsigned short *ptr;
1611+
1612+ ptr = (volatile unsigned short *) (HOST_IO_BASE | (addr & PCI_IO_MASK));
1613+ *ptr = cpu_to_le16(value);
1614+ DBG("PCI: outw addr=0x%08X, value=0x%04X\n", addr, value);
1615+}
1616+
1617+/*
1618+ * void pci_raw_outw()
1619+ *
1620+ * Write a raw word value at specified address to I/O space
1621+ */
1622+void pci_raw_outw(volatile unsigned short value, volatile long addr)
1623+{
1624+ volatile unsigned short *ptr;
1625+
1626+ ptr = (volatile unsigned short *) (HOST_IO_BASE | (addr & PCI_IO_MASK));
1627+ *ptr = value;
1628+ DBG("PCI: raw_outw addr=0x%08X, value=0x%04X\n", addr, value);
1629+}
1630+
1631+/*
1632+ * void pci_outl()
1633+ *
1634+ * Write a long word value at specified address to I/O space
1635+ */
1636+void pci_outl(volatile unsigned long value, volatile long addr)
1637+{
1638+ volatile unsigned long *ptr;
1639+
1640+ ptr = (volatile unsigned long *)(HOST_IO_BASE | (addr & PCI_IO_MASK));
1641+ *ptr = cpu_to_le32(value);
1642+ DBG("PCI: outl addr=0x%08X, value=0x%08X\n", addr, value);
1643+}
1644+
1645+/*
1646+ * void pci_raw_outl()
1647+ *
1648+ * Write a raw long word value at specified address to I/O space
1649+ */
1650+void pci_raw_outl(volatile unsigned long value, volatile long addr)
1651+{
1652+ volatile unsigned long *ptr;
1653+
1654+ ptr = (volatile unsigned long *)(HOST_IO_BASE | (addr & PCI_IO_MASK));
1655+ *ptr = value;
1656+ DBG("PCI: raw_outl addr=0x%08X, value=0x%08X\n", addr, value);
1657+}
1658+
1659+/*
1660+ * void pci_insb()
1661+ *
1662+ * Read several byte values from specified I/O port
1663+ */
1664+void pci_insb(volatile unsigned char *addr, unsigned char *buf, int len)
1665+{
1666+ for (; len--; buf++)
1667+ *buf = pci_inb((unsigned long)addr);
1668+ DBG("PCI: pci_insb addr=0x%08X, buf=%p, len=%d\n", addr, buf, len);
1669+}
1670+
1671+
1672+/*
1673+ * void pci_insw()
1674+ *
1675+ * Read several word values from specified I/O port
1676+ */
1677+void pci_insw(volatile unsigned short *addr, unsigned short *buf, int len)
1678+{
1679+ for (; len--; buf++)
1680+ *buf = pci_inw((unsigned long)addr);
1681+ DBG("PCI: pci_insw addr=0x%08X, buf=%p, len=%d\n", addr, buf, len);
1682+}
1683+
1684+/*
1685+ * void pci_insl()
1686+ *
1687+ * Read several dword values from specified I/O port
1688+ */
1689+void pci_insl(volatile unsigned long *addr, unsigned long *buf, int len)
1690+{
1691+ for (; len--; buf++)
1692+ *buf = pci_inl((unsigned long)addr);
1693+ DBG("PCI: pci_insl addr=0x%08X, buf=%p, len=%d\n", addr, buf, len);
1694+}
1695+
1696+/*
1697+ * void pci_outsb()
1698+ *
1699+ * Write several byte values to specified I/O port
1700+ */
1701+void pci_outsb(volatile unsigned char *addr, const unsigned char *buf, int len)
1702+{
1703+ for (; len--; buf++)
1704+ pci_outb((unsigned long)addr, *buf);
1705+ DBG("PCI: pci_outsb addr=0x%08X, buf=%p, len=%d\n", addr, buf, len);
1706+}
1707+
1708+/*
1709+ * void pci_outsw()
1710+ *
1711+ * Write several word values to specified I/O port
1712+ */
1713+void pci_outsw(volatile unsigned short *addr,
1714+ const unsigned short *buf, int len)
1715+{
1716+ for (; len--; buf++)
1717+ pci_outw((unsigned long)addr, *buf);
1718+ DBG("PCI: pci_outsw addr=0x%08X, buf=%p, len=%d\n", addr, buf, len);
1719+}
1720+
1721+/*
1722+ * void pci_outsl()
1723+ *
1724+ * Write several dword values to specified I/O port
1725+ */
1726+void pci_outsl(volatile unsigned long *addr, const unsigned long *buf, int len)
1727+{
1728+ for (; len--; buf++)
1729+ pci_outl((unsigned long)addr, *buf);
1730+ DBG("PCI: pci_outsl addr=0x%08X, buf=%p, len=%d\n", addr, buf, len);
1731+}
1732+
1733+/*
1734+ * void pci_xlb_handler()
1735+ *
1736+ * PCI XLB interrupt handler
1737+ */
1738+irqreturn_t xlb_interrupt(int irq, void *dev)
1739+{
1740+ volatile int xlb_error = MCF_PCIISR;
1741+
1742+ /* Acknowlege interrupt */
1743+ MCF_PCIISR = xlb_error;
1744+
1745+ /* Dump interrupt reason */
1746+ if (xlb_error & MCF_PCIISR_RE)
1747+ DBG("PCI: Retry Error Received\n");
1748+
1749+ if (xlb_error & MCF_PCIISR_IA)
1750+ DBG("PCI: Initiator Abort Received\n");
1751+
1752+ if (xlb_error & MCF_PCIISR_TA)
1753+ DBG("PCI: Target Abort Received\n");
1754+
1755+ return IRQ_HANDLED;
1756+}
1757+
1758+
1759+/*
1760+ * void pci_arbiter_handler()
1761+ *
1762+ * PCI arbiter interrupt handler
1763+ */
1764+irqreturn_t arb_interrupt(int irq, void *dev)
1765+{
1766+ volatile unsigned long arb_error = MCF_PCIARB_PASR;
1767+
1768+ /* Acknowlege interrupt */
1769+ printk(KERN_ERR "%s\n", __func__);
1770+ MCF_PCIARB_PASR = arb_error;
1771+
1772+ if (arb_error & MCF_PCIARB_PASR_ITLMBK) {
1773+ DBG("PCI: coldfire master time-out\n");
1774+
1775+ /* Set infinite number of retries */
1776+ MCF_PCIICR &= ~0xFF;
1777+ }
1778+
1779+ if (arb_error & MCF_PCIARB_PASR_EXTMBK(0x1F)) {
1780+ arb_error >>= 17;
1781+ DBG("PCI: external master time-out (mask = 0x%X)\n", arb_error);
1782+
1783+ /* raise arbitration priority level */
1784+ MCF_PCIARB_PACR = MCF_PCIARB_PACR_EXTMPRI(arb_error);
1785+ }
1786+
1787+ return IRQ_HANDLED;
1788+}
1789+
1790+
1791+/*
1792+ * void pci_eint_handler()
1793+ *
1794+ * Eport interrupt handler
1795+ */
1796+irqreturn_t eint_handler(int irq, void *dev)
1797+{
1798+ /* Just acknowlege interrupt and exit */
1799+ MCF_EPFR = 0x1 << (irq - 64);
1800+ return IRQ_HANDLED;
1801+}
1802+
1803+resource_size_t
1804+pcibios_align_resource(void *data, const struct resource *res,
1805+ resource_size_t size, resource_size_t align)
1806+{
1807+ struct pci_dev *dev = data;
1808+ resource_size_t start = res->start;
1809+
1810+ if (res->flags & IORESOURCE_IO) {
1811+ if (size > 0x100)
1812+ printk(KERN_ERR "PCI: I/O Region %s/%d too large"
1813+ " (%ld bytes)\n", pci_name(dev),
1814+ dev->resource - res, (long int)size);
1815+
1816+ if (start & 0x3ff)
1817+ start = (start + 0x3ff) & ~0x3ff;
1818+ }
1819+
1820+ return start;
1821+}
1822+EXPORT_SYMBOL(pcibios_align_resource);
1823+
1824+/*
1825+ * void __init coldfire_fixup(int pci_modify)
1826+ *
1827+ * Assign IRQ numbers as used by Linux to the interrupt pins
1828+ * of the PCI cards.
1829+ */
1830+static void __init coldfire_fixup(int pci_modify)
1831+{
1832+ struct pci_dev *dev;
1833+ unsigned char slot, pin;
1834+
1835+ DBG("%s\n", __func__);
1836+#ifdef NL_ORIGINAL
1837+ pci_for_each_dev(dev) {
1838+#else
1839+ dev = NULL;
1840+ while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1841+#endif
1842+ if (dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) {
1843+ slot = PCI_SLOT(dev->devfn);
1844+ dev->irq = 64 + board_info[slot].irq;
1845+
1846+ /* Check if device needs interrupt */
1847+#ifdef NL_ORIGINAL
1848+ pcibios_read_config_byte(
1849+ dev->bus->number, dev->devfn,
1850+ PCI_INTERRUPT_PIN, &pin);
1851+
1852+ if (pin) {
1853+ pcibios_write_config_byte(
1854+ dev->bus->number, dev->devfn,
1855+ PCI_INTERRUPT_LINE, dev->irq);
1856+ }
1857+#else
1858+ pci_read_config_byte(dev,
1859+ PCI_INTERRUPT_PIN, &pin);
1860+
1861+ if (pin) {
1862+ pci_write_config_byte(dev,
1863+ PCI_INTERRUPT_LINE, dev->irq);
1864+ }
1865+#endif
1866+ }
1867+ }
1868+}
1869+
1870+static void __init configure_device(struct pci_dev *dev)
1871+{
1872+ /* TODO: This should depend from disable_pci_burst setting */
1873+ DBG("%s\n", __func__);
1874+#ifdef NL_ORIGINAL
1875+ pcibios_write_config_byte(bus, devfn,
1876+ PCI_CACHE_LINE_SIZE, PCI_CACHE_LINE);
1877+#else
1878+ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, PCI_CACHE_LINE);
1879+
1880+ MCF_PCICR1 = MCF_PCICR1_LATTIMER(0xF8) |
1881+ MCF_PCICR1_CACHELINESIZE(PCI_CACHE_LINE);
1882+
1883+#endif
1884+}
1885+
1886+
1887+struct pci_bus_info *__init init_coldfire_pci(void)
1888+{
1889+ struct pci_bus_info *bus;
1890+ int i;
1891+ unsigned long pci_mem_va;
1892+ static char irq_name[N_IRQS][15];
1893+
1894+ MCF_SPCR |= 0x02; /*Enable the PCI clock*/
1895+
1896+ /* Get controller revision */
1897+ revision = MCF_PCICCRIR;
1898+ printk(KERN_INFO "ColdFire PCI Host Bridge "
1899+ "(Rev. %d) detected:"
1900+ "MEMBase %x,MEMLen %x,IOBase %x,IOLen %x\n",
1901+ revision, HOST_MEM_BASE,
1902+ PCI_MEM_SIZE - 1, 0, PCI_IO_SIZE - 1);
1903+
1904+ bus = (struct pci_bus_info *)kmalloc(sizeof(struct pci_bus_info),
1905+ GFP_KERNEL);
1906+ if (!bus) {
1907+ printk(KERN_ERR "can not alloc mem for pci bus!\n");
1908+ return NULL;
1909+ }
1910+
1911+ /* Setup bus info structure. */
1912+ memset(bus, 0, sizeof(struct pci_bus_info));
1913+
1914+ /* Request intiator memory resource */
1915+ bus->mem_space.start = PCI_MEM_BASE;/*HOST_MEM_BASE;*/
1916+ bus->mem_space.end = bus->mem_space.start + PCI_MEM_SIZE - 1;
1917+ bus->mem_space.name = "PCI Bus #0";
1918+ if (request_resource(&iomem_resource,
1919+ &(bus->mem_space)) != 0) {
1920+ printk(KERN_ERR "Failed to request bridge iomem resource\n");
1921+ return NULL;
1922+ }
1923+
1924+ /* Request intiator memory resource */
1925+ /*bus->io_space.start = 0;*/
1926+ bus->io_space.start = HOST_IO_BASE;
1927+ bus->io_space.end = bus->io_space.start + PCI_IO_SIZE - 1;
1928+ bus->io_space.name = "PCI Bus #0";
1929+ if (request_resource(&ioport_resource,
1930+ &(bus->io_space)) != 0) {
1931+ printk(KERN_ERR "Failed to request bridge "
1932+ "ioport resource\n");
1933+ return NULL;
1934+ }
1935+
1936+ /* Must Reset!!! If bootloader has PCI enabled, it will cause
1937+ * problem in linux when it tries to configure/find resources
1938+ * for the pci devices. Both registers need to be reset.
1939+ */
1940+ /*MCF_PCIGSCR |= 0x1;*/
1941+ MCF_PCIGSCR = 0x1;
1942+ MCF_PCITCR = 0x00000000;
1943+
1944+ /* Set up the arbiter */
1945+ MCF_PCIARB_PACR = 0; /*MCF_PCIARB_PACR_PKMD*/
1946+
1947+ /* GNT and REQ */
1948+ MCF_PAR_PCIBG = 0x3FF;
1949+ MCF_PAR_PCIBR = 0x3FF;
1950+
1951+ /* Enable bus mastering, memory access and MWI */
1952+ MCF_PCISCR = (MCF_PCISCR_B | MCF_PCISCR_M);
1953+
1954+ /* Setup burst parameters */
1955+ /*The offset 0x0e normally was header_type, set it to 0 and fix later*/
1956+ MCF_PCICR1 = MCF_PCICR1_LATTIMER(0x00) |
1957+ MCF_PCICR1_CACHELINESIZE(PCI_CACHE_LINE);
1958+
1959+ MCF_PCICR2 = 0;
1960+ /*MCF_PCICR2_MINGNT(PCI_MINGNT) |
1961+ MCF_PCICR2_MAXLAT(PCI_MAXLAT);
1962+ */
1963+ /* Turn on error signaling */
1964+ MCF_PCIICR = MCF_PCIICR_TAE | MCF_PCIICR_IAE | PCI_RETRIES;
1965+ MCF_PCIGSCR |= MCF_PCIGSCR_SEE;
1966+ /*
1967+ * Configure Initiator Windows
1968+ * Window 0: 128M PCI Memory @ HOST_MEM_BASE, 1:1 mapping
1969+ * Window 1: 64K I/O Memory @ HOST_IO_BASE, 1:0 mapping
1970+ */
1971+ MCF_PCIIW0BTAR = WxBAR(HOST_MEM_BASE, PCI_MEM_BASE, PCI_MEM_SIZE);
1972+ MCF_PCIIW1BTAR = WxBAR(HOST_IO_BASE, PCI_IO_BASE_ADDR, PCI_IO_SIZE);
1973+
1974+ MCF_PCIIWCR = MCF_PCIIWCR_WINCTRL1_IO |
1975+ MCF_PCIIWCR_WINCTRL0_MEMREAD;
1976+
1977+ /* Target PCI DMA Windows */
1978+ MCF_PCIBAR1 = PCI_DMA_BASE;
1979+ MCF_PCITBATR1 = HOST_DMA_BASE | MCF_PCITBATR1_EN;
1980+
1981+ /* Enable internal PCI controller interrupts */
1982+ MCF_ICR(ISC_PCI_XLB) = ILP_PCI_XLB;
1983+ /*request_irq(64+ISC_PCI_XLB, xlb_interrupt,
1984+ SA_INTERRUPT, "PCI XL Bus", (void*)-1);
1985+ enable_irq (64+ISC_PCI_XLB);
1986+ */
1987+ if (request_irq(64+ISC_PCI_XLB, xlb_interrupt,
1988+ IRQF_DISABLED, "PCI XL Bus", (void *)-1)) {
1989+ printk(KERN_ERR "Cannot allocate "
1990+ "ISC_PCI_XLB IRQ\n");
1991+ return (struct pci_bus_info *)-EBUSY;
1992+ }
1993+
1994+ MCF_ICR(ISC_PCI_ARB) = ILP_PCI_ARB;
1995+ /*request_irq(64+ISC_PCI_ARB, arb_interrupt,
1996+ SA_INTERRUPT, "PCI Arbiter", (void*)-1);
1997+ enable_irq (64+ISC_PCI_ARB);
1998+ */
1999+ if (request_irq(64 + ISC_PCI_ARB, arb_interrupt,
2000+ IRQF_DISABLED, "PCI Arbiter", (void *)-1)) {
2001+ printk(KERN_ERR "Cannot allocate "
2002+ "ISC_PCI_ARB IRQ\n");
2003+ return (struct pci_bus_info *)-EBUSY;
2004+ }
2005+
2006+ /* Set slots interrupt setting */
2007+ for (i = 0; i < N_IRQS; i++) {
2008+ /* Set trailing edge for PCI interrupts */
2009+ MCF_EPPAR &= ~MCF_EPPAR_EPPA(irq_lines[i], 0x3);
2010+ if (irq_lines[i] == 5)
2011+ MCF_EPPAR |= MCF_EPPAR_EPPA(irq_lines[i],
2012+ MCF_EPPAR_EPPAx_FALLING);
2013+ else
2014+ MCF_EPPAR |= MCF_EPPAR_EPPA(irq_lines[i],
2015+ 0/*MCF_EPPAR_EPPAx_FALLING*/);
2016+ /* Turn on irq line in eport */
2017+ MCF_EPIER |= MCF_EPIER_EPIE(irq_lines[i]);
2018+
2019+ /* Enable irq in gpio */
2020+ if (irq_lines[i] == 5)
2021+ MCF_PAR_FECI2CIRQ |= 1;
2022+
2023+ if (irq_lines[i] == 6)
2024+ MCF_PAR_FECI2CIRQ |= 2;
2025+
2026+ /* Register external interrupt handlers */
2027+ sprintf(irq_name[i], "PCI IRQ%d", irq_lines[i]);
2028+ /*request_irq(64 + irq_lines[i], eint_handler,
2029+ SA_SHIRQ, irq_name[i], (void*)-1);
2030+ enable_irq(64 + irq_lines[i]);*/
2031+ if (request_irq(64 + irq_lines[i], eint_handler,
2032+ IRQF_SHARED, irq_name[i], (void *)-1)) {
2033+ printk(KERN_ERR "Cannot allocate "
2034+ "irq_lines[%d] IRQ\n",
2035+ irq_lines[i]);
2036+ return (struct pci_bus_info *)-EBUSY;
2037+ }
2038+ }
2039+
2040+ /* Clear PCI Reset and wait for devices to reset */
2041+ MCF_PCIGSCR &= ~MCF_PCIGSCR_PR;
2042+ schedule_timeout((5 * HZ));
2043+ /* Remap initiator windows (should be 1:1 to the physical memory) */
2044+ pci_mem_va = (int) ioremap_nocache(HOST_MEM_BASE,
2045+ PCI_MEM_SIZE + PCI_IO_SIZE);
2046+ udelay(1000); /* let every thing effect */
2047+#if 1
2048+ printk(KERN_INFO "%s: MEMBase_phy %x, Virt %x, len %x\n",
2049+ __func__, HOST_MEM_BASE, pci_mem_va,
2050+ PCI_MEM_SIZE + PCI_IO_SIZE);
2051+#endif
2052+ BUG_ON(pci_mem_va != HOST_MEM_BASE);
2053+
2054+ /* Setup bios32 and pci bus driver callbacks */
2055+ bus->m68k_pci_ops = &bus_ops;
2056+ bus->fixup = coldfire_fixup;
2057+ bus->conf_device = configure_device;
2058+
2059+ return bus;
2060+}
2061--- /dev/null
2062+++ b/arch/m68k/coldfire/m547x/pci_dummy.S
2063@@ -0,0 +1,45 @@
2064+/*
2065+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
2066+ * Author: Jason Jin <Jason.jin@freescale.com>
2067+ *
2068+ * This routine is the dummy function for PCI errata
2069+ *
2070+ * This program is free software; you can redistribute it and/or
2071+ * modify it under the terms of the GNU General Public License as
2072+ * published by the Free Software Foundation; either version 2 of
2073+ * the License, or (at your option) any later version.
2074+ *
2075+ * This program is distributed in the hope that it will be useful,
2076+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
2077+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2078+ * GNU General Public License for more details.
2079+ *
2080+ * You should have received a copy of the GNU General Public License
2081+ * along with this program; if not, write to the Free Software
2082+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
2083+ * MA 02111-1307 USA
2084+ */
2085+
2086+.global _pci_dummy_function
2087+.global pci_dummy_function
2088+.text
2089+
2090+pci_dummy_function:
2091+_pci_dummy_function:
2092+
2093+/* force function start to 16-byte boundary.Can be done in linker file also */
2094+.align 16
2095+clr.l %d0
2096+move.l %d0, 0xF0000F0C
2097+/* Must use direct addressing. write to EPORT module
2098+* xlbus -> slavebus -> eport, writing '0' to register has no
2099+* effect
2100+*/
2101+
2102+rts
2103+tpf.l #0x0
2104+tpf.l #0x0
2105+tpf.l #0x0
2106+tpf.l #0x0
2107+tpf.l #0x0
2108+.end
2109--- /dev/null
2110+++ b/arch/m68k/include/asm/5445x_pci.h
2111@@ -0,0 +1,111 @@
2112+/*
2113+ * asm-m68k/pci.h - m68k specific PCI declarations.
2114+ *
2115+ * Copyright (C) 2007, 2009-2011 Freescale Semiconductor, Inc.
2116+ * All Rights Reserved.
2117+ * Kurt Mahan <kmahan@freescale.com>
2118+ */
2119+#ifndef _ASM_M68K_5445X_PCI_H
2120+#define _ASM_M68K_5445x_PCI_H
2121+
2122+#ifndef CONFIG_PCI
2123+/*
2124+ * The PCI address space does equal the physical memory
2125+ * address space. The networking and block device layers use
2126+ * this boolean for bounce buffer decisions.
2127+ */
2128+#define PCI_DMA_BUS_IS_PHYS (1)
2129+#else
2130+#include <asm-generic/pci-dma-compat.h>
2131+
2132+#define PCI_DMA_BASE 0 /* PCI-DMA window base */
2133+#define NL_ORIGINAL
2134+/*
2135+ * The PCI address space does equal the physical memory
2136+ * address space. The networking and block device layers use
2137+ * this boolean for bounce buffer decisions.
2138+ */
2139+#define PCI_DMA_BUS_IS_PHYS (1)
2140+
2141+#define PCIBIOS_MIN_IO 0x00004000
2142+#define PCIBIOS_MIN_MEM 0x02000000
2143+
2144+#define pcibios_assign_all_busses() 0
2145+#define pcibios_scan_all_fns(a, b) 0
2146+
2147+struct pci_raw_ops {
2148+ int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
2149+ int reg, int len, u32 *val);
2150+ int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
2151+ int reg, int len, u32 val);
2152+};
2153+
2154+extern struct pci_raw_ops *raw_pci_ops;
2155+
2156+static inline void
2157+pcibios_set_master(struct pci_dev *dev)
2158+{
2159+ /* no special bus mastering setup handling */
2160+}
2161+
2162+static inline void
2163+pcibios_penalize_isa_irq(int irq, int active)
2164+{
2165+ /* no dynamic PCI IRQ allocation */
2166+}
2167+
2168+#if 0
2169+static inline void
2170+pcibios_add_platform_entries(struct pci_dev *dev)
2171+{
2172+ /* no special handling */
2173+}
2174+#endif
2175+
2176+static inline void
2177+pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
2178+ struct resource *res)
2179+{
2180+ region->start = res->start;
2181+ region->end = res->end;
2182+}
2183+
2184+static inline void
2185+pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
2186+ struct pci_bus_region *region)
2187+{
2188+ res->start = region->start;
2189+ res->end = region->end;
2190+}
2191+
2192+static inline struct resource *
2193+pcibios_select_root(struct pci_dev *pdev, struct resource *res)
2194+{
2195+ struct resource *root = NULL;
2196+
2197+ if (res->flags & IORESOURCE_IO)
2198+ root = &ioport_resource;
2199+ if (res->flags & IORESOURCE_MEM)
2200+ root = &iomem_resource;
2201+
2202+ return root;
2203+}
2204+
2205+#ifndef CONFIG_M54455_PCI_initcall
2206+extern int pci_init(void);
2207+extern int pcibios_init(void);
2208+#endif
2209+
2210+extern void set_fpga(u32 *addr, u32 val);
2211+
2212+#ifdef CONFIG_M54455
2213+extern int init_mcf5445x_pci(void);
2214+extern void mcf5445x_conf_device(struct pci_dev *dev);
2215+extern void mcf5445x_pci_dumpregs(void);
2216+
2217+extern struct resource pci_ioport_resource;
2218+extern struct resource pci_iomem_resource;
2219+#endif
2220+
2221+#endif /* CONFIG_PCI */
2222+#endif /* _ASM_M68K_5445X_PCI_H */
2223--- /dev/null
2224+++ b/arch/m68k/include/asm/548x_pci.h
2225@@ -0,0 +1,99 @@
2226+/*
2227+ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved.
2228+ * Written by Wout Klaren.
2229+ */
2230+
2231+#ifndef _ASM_M68K_548X_PCI_H
2232+#define _ASM_M68K_548X_PCI_H
2233+
2234+#include <linux/mm.h>
2235+#include <asm/scatterlist.h>
2236+
2237+#include <asm-generic/pci.h>
2238+
2239+struct pci_ops;
2240+
2241+/*
2242+ * Structure with hardware dependent information and functions of the
2243+ * PCI bus.
2244+ */
2245+
2246+struct pci_bus_info {
2247+ /*
2248+ * Resources of the PCI bus.
2249+ */
2250+
2251+ struct resource mem_space;
2252+ struct resource io_space;
2253+
2254+ /*
2255+ * System dependent functions.
2256+ */
2257+
2258+ struct pci_ops *m68k_pci_ops;
2259+
2260+ void (*fixup)(int pci_modify);
2261+ void (*conf_device)(struct pci_dev *dev);
2262+};
2263+
2264+#define pcibios_assign_all_busses() 0
2265+#define pcibios_scan_all_fns(a, b) 0
2266+
2267+static inline void pcibios_set_master(struct pci_dev *dev)
2268+{
2269+ /* No special bus mastering setup handling */
2270+}
2271+
2272+static inline void pcibios_penalize_isa_irq(int irq)
2273+{
2274+ /* We don't do dynamic PCI IRQ allocation */
2275+}
2276+
2277+#ifndef CONFIG_COLDFIRE
2278+/* The PCI address space does equal the physical memory
2279+ * address space. The networking and block device layers use
2280+ * this boolean for bounce buffer decisions.
2281+ */
2282+#define PCI_DMA_BUS_IS_PHYS (1)
2283+
2284+#define PCIBIOS_MIN_IO 0x00004000
2285+#define PCIBIOS_MIN_MEM 0x04000000
2286+
2287+#else /* !CONFIG_COLDFIRE */
2288+#include <asm-generic/pci-dma-compat.h>
2289+#define PCI_DMA_BASE /*0x40000000*/0
2290+/* PCI-DMA window base */
2291+
2292+extern struct pci_bus_info *__init init_coldfire_pci(void);
2293+extern void *pci_alloc_son(struct pci_dev *, size_t,
2294+ dma_addr_t *, int);
2295+/*
2296+ * The PCI address space equal the virtual memory
2297+ * address space on m547X/m548X.
2298+ */
2299+#define PCI_DMA_BUS_IS_PHYS (1)
2300+
2301+#define PCIBIOS_MIN_IO 0x00000100
2302+#define PCIBIOS_MIN_MEM 0x02000000
2303+
2304+struct scatterlist;
2305+
2306+
2307+/* This is always fine. */
2308+#define pci_dac_dma_supported(pci_dev, mask) (1)
2309+
2310+
2311+/* These macros should be used after a pci_map_sg call has been done
2312+ * to get bus addresses of each of the SG entries and their lengths.
2313+ * You should only work with the number of sg entries pci_map_sg
2314+ * returns.
2315+ */
2316+#define sg_dma_address(sg) ((sg)->dma_address)
2317+#define sg_dma_len(sg) ((sg)->length)
2318+
2319+extern void pci_dummy_function(void);
2320+/*Declarations of hardware specific initialisation functions*/
2321+extern struct pci_bus_info *init_hades_pci(void);
2322+
2323+#endif /* !CONFIG_COLDFIRE*/
2324+#endif /* _ASM_M68K_548X_PCI_H */
2325--- a/arch/m68k/include/asm/pci.h
2326+++ b/arch/m68k/include/asm/pci.h
2327@@ -1,7 +1,13 @@
2328 #ifndef _ASM_M68K_PCI_H
2329 #define _ASM_M68K_PCI_H
2330 
2331+#if defined(CONFIG_M5445X)
2332+#include "5445x_pci.h"
2333+#elif defined(CONFIG_M547X_8X)
2334+#include "548x_pci.h"
2335+#else
2336 #include <asm-generic/pci-dma-compat.h>
2337+#endif
2338 
2339 /* The PCI address space does equal the physical memory
2340  * address space. The networking and block device layers use
2341--- /dev/null
2342+++ b/arch/m68k/kernel/bios32_mcf548x.c
2343@@ -0,0 +1,632 @@
2344+/*
2345+ * bios32.c - PCI BIOS functions for m68k systems.
2346+ *
2347+ * Written by Wout Klaren.
2348+ *
2349+ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
2350+ * Shrek Wu B16972@freescale.com
2351+ *
2352+ * Based on the DEC Alpha bios32.c by Dave Rusling and David Mosberger.
2353+ */
2354+#include <linux/init.h>
2355+#include <linux/kernel.h>
2356+#include <linux/device.h>
2357+#include <linux/delay.h>
2358+
2359+# define DBG_DEVS(args)
2360+
2361+#ifdef CONFIG_PCI
2362+
2363+/*
2364+ * PCI support for Linux/m68k. Currently only the Hades is supported.
2365+ *
2366+ * The support for PCI bridges in the DEC Alpha version has
2367+ * been removed in this version.
2368+ */
2369+
2370+#include <linux/pci.h>
2371+#include <linux/slab.h>
2372+#include <linux/mm.h>
2373+
2374+#include <asm/io.h>
2375+#include <asm/pci.h>
2376+#include <asm/uaccess.h>
2377+
2378+#define KB 1024
2379+#define MB (1024*KB)
2380+#define GB (1024*MB)
2381+
2382+#define MAJOR_REV 0
2383+#define MINOR_REV 5
2384+
2385+/*
2386+ * Align VAL to ALIGN, which must be a power of two.
2387+ */
2388+
2389+#define MAX(val1, val2) (((val1) > (val2)) ? val1 : val2)
2390+
2391+/*
2392+ * Offsets relative to the I/O and memory base addresses from where resources
2393+ * are allocated.
2394+ */
2395+
2396+#ifdef CONFIG_COLDFIRE
2397+#define IO_ALLOC_OFFSET 0x00000100
2398+#define MEM_ALLOC_OFFSET 0x00000000
2399+#else /* CONFIG_COLDFIRE */
2400+#define IO_ALLOC_OFFSET 0x00004000
2401+#define MEM_ALLOC_OFFSET 0x04000000
2402+#endif /* CONFIG_COLDFIRE */
2403+
2404+/*
2405+ * Bus info structure of the PCI bus. A pointer to this structure is
2406+ * put in the sysdata member of the pci_bus structure.
2407+ */
2408+
2409+static struct pci_bus_info *bus_info;
2410+
2411+static int pci_modify = 1;
2412+/* If set, layout the PCI bus ourself. */
2413+static int skip_vga;
2414+/* If set do not modify base addresses of vga cards.*/
2415+static int disable_pci_burst;
2416+/* If set do not allow PCI bursts. */
2417+
2418+static volatile unsigned int io_base;
2419+static volatile unsigned int mem_base;
2420+
2421+/*
2422+ * static void disable_dev(struct pci_dev *dev)
2423+ *
2424+ * Disable PCI device DEV so that it does not respond to I/O or memory
2425+ * accesses.
2426+ *
2427+ * Parameters:
2428+ *
2429+ * dev - device to disable.
2430+ */
2431+
2432+static void __init disable_dev(struct pci_dev *dev)
2433+{
2434+ unsigned short cmd;
2435+
2436+ if (((dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA) ||
2437+ (dev->class >> 8 == PCI_CLASS_DISPLAY_VGA) ||
2438+ (dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)) && skip_vga)
2439+ return;
2440+
2441+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
2442+
2443+ cmd &= (~PCI_COMMAND_IO & ~PCI_COMMAND_MEMORY & ~PCI_COMMAND_MASTER);
2444+ pci_write_config_word(dev, PCI_COMMAND, cmd);
2445+}
2446+
2447+/* Stolen from pcibios_enable_resources/i386 */
2448+int pcibios_enable_device(struct pci_dev *dev, int mask)
2449+{
2450+ u16 cmd, old_cmd;
2451+ int idx;
2452+ struct resource *r;
2453+
2454+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
2455+ old_cmd = cmd;
2456+ for (idx = 0; idx < 6; idx++) {
2457+ /* Only set up the requested stuff */
2458+ if (!(mask & (1<<idx)))
2459+ continue;
2460+
2461+ r = &dev->resource[idx];
2462+ if (!r->start && r->end) {
2463+ printk(KERN_ERR "PCI: Device %s not"
2464+ " available because"
2465+ " of resource collisions\n",
2466+ dev_name(&(dev->dev)));
2467+ return -EINVAL;
2468+ }
2469+ if (r->flags & IORESOURCE_IO)
2470+ cmd |= PCI_COMMAND_IO;
2471+ if (r->flags & IORESOURCE_MEM)
2472+ cmd |= PCI_COMMAND_MEMORY;
2473+ }
2474+ if (dev->resource[PCI_ROM_RESOURCE].start)
2475+ cmd |= PCI_COMMAND_MEMORY;
2476+ if (cmd != old_cmd) {
2477+ printk(KERN_ERR "PCI: Enabling device "
2478+ "%s (%04x -> %04x)\n",
2479+ dev_name(&(dev->dev)), old_cmd, cmd);
2480+ pci_write_config_word(dev, PCI_COMMAND, cmd);
2481+ }
2482+ return 0;
2483+}
2484+
2485+/*
2486+ * static void layout_dev(struct pci_dev *dev)
2487+ *
2488+ * Layout memory and I/O for a device.
2489+ *
2490+ * Parameters:
2491+ *
2492+ * device - device to layout memory and I/O for.
2493+ */
2494+
2495+static void __init layout_dev(struct pci_dev *dev)
2496+{
2497+ unsigned short cmd;
2498+ unsigned int base, mask, size, reg;
2499+ unsigned int alignto;
2500+ int i;
2501+
2502+ /*
2503+ * Skip video cards if requested.
2504+ */
2505+ if (((dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA) ||
2506+ (dev->class >> 8 == PCI_CLASS_DISPLAY_VGA) ||
2507+ (dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)) && skip_vga) {
2508+ printk(KERN_ERR "%s: VGA\n", __func__);
2509+ return;
2510+ }
2511+
2512+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
2513+
2514+ for (reg = PCI_BASE_ADDRESS_0, i = 0;
2515+ reg <= PCI_BASE_ADDRESS_5; reg += 4, i++) {
2516+ /*
2517+ * Figure out how much space and of what type this
2518+ * device wants.
2519+ */
2520+
2521+ pci_write_config_dword(dev, reg, 0xffffffff);
2522+ pci_read_config_dword(dev, reg, &base);
2523+ if (!base) {
2524+ /* this base-address register is unused */
2525+ dev->resource[i].start = 0;
2526+ dev->resource[i].end = 0;
2527+ dev->resource[i].flags = 0;
2528+ continue;
2529+ }
2530+
2531+ /*
2532+ * We've read the base address register back after
2533+ * writing all ones and so now we must decode it.
2534+ */
2535+ if (base & PCI_BASE_ADDRESS_SPACE_IO) {
2536+ /*
2537+ * I/O space base address register.
2538+ */
2539+
2540+ cmd |= PCI_COMMAND_IO;
2541+
2542+ base &= PCI_BASE_ADDRESS_IO_MASK;
2543+ mask = (~base << 1) | 0x1;
2544+ size = (mask & base) & 0xffffffff;
2545+
2546+ /*
2547+ * Align to multiple of size of minimum base.
2548+ */
2549+
2550+#ifdef CONFIG_COLDFIRE
2551+ alignto = MAX(PAGE_SIZE, size) ;
2552+#else /* !CONFIG_COLDFIRE */
2553+ alignto = MAX(0x040, size) ;
2554+#endif /* CONFIG_COLDFIRE */
2555+ base = ALIGN(io_base, alignto);
2556+ io_base = base + size;
2557+ pci_write_config_dword(dev, reg,
2558+ base | PCI_BASE_ADDRESS_SPACE_IO);
2559+ dev->resource[i].start = base;
2560+ dev->resource[i].end =
2561+ dev->resource[i].start + size - 1;
2562+ dev->resource[i].flags =
2563+ IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
2564+
2565+ DBG_DEVS(("layout_dev: IO address: %x\n", base));
2566+ } else {
2567+ unsigned int type;
2568+
2569+ /*
2570+ * Memory space base address register.
2571+ */
2572+ cmd |= PCI_COMMAND_MEMORY;
2573+
2574+ type = base & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
2575+ base &= PCI_BASE_ADDRESS_MEM_MASK;
2576+ mask = (~base << 1) | 0x1;
2577+ size = (mask & base) & 0xffffffff;
2578+ switch (type) {
2579+ case PCI_BASE_ADDRESS_MEM_TYPE_32:
2580+ case PCI_BASE_ADDRESS_MEM_TYPE_64:
2581+ break;
2582+
2583+ case PCI_BASE_ADDRESS_MEM_TYPE_1M:
2584+ printk(KERN_INFO "bios32 WARNING: slot %d,"
2585+ " function %d "
2586+ "requests memory below 1MB---don't "
2587+ "know how to do that.\n",
2588+ PCI_SLOT(dev->devfn),
2589+ PCI_FUNC(dev->devfn));
2590+ continue;
2591+ }
2592+ DBG_DEVS(("%s MEM: base %x,type %x,mask %x,size %x\n",
2593+ __func__, base, type, mask, size));
2594+ /*
2595+ * Align to multiple of size of minimum base.
2596+ */
2597+
2598+ alignto = max_t(unsigned int, 0x1000, size);
2599+ base = ALIGN(mem_base, alignto);
2600+ mem_base = base + size;
2601+ pci_write_config_dword(dev, reg, base);
2602+ dev->resource[i].start = base;
2603+ dev->resource[i].end =
2604+ dev->resource[i].start + size - 1;
2605+ dev->resource[i].flags = IORESOURCE_MEM;
2606+
2607+ DBG_DEVS(("%s MEM :base %x,size %x\n",
2608+ __func__, base, size));
2609+ if (type == PCI_BASE_ADDRESS_MEM_TYPE_64) {
2610+ /*
2611+ * 64-bit address, set the highest 32 bits
2612+ * to zero.
2613+ */
2614+
2615+ reg += 4;
2616+ pci_write_config_dword(dev, reg, 0);
2617+
2618+ i++;
2619+ dev->resource[i].start = 0;
2620+ dev->resource[i].end = 0;
2621+ dev->resource[i].flags = 0;
2622+ printk(KERN_ERR "%s:type == 64\n", __func__);
2623+ }
2624+ }
2625+ }
2626+ /*
2627+ * Enable device:
2628+ */
2629+ if (dev->class >> 8 == PCI_CLASS_NOT_DEFINED ||
2630+ dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA ||
2631+ dev->class >> 8 == PCI_CLASS_DISPLAY_VGA ||
2632+ dev->class >> 8 == PCI_CLASS_DISPLAY_XGA) {
2633+ /*
2634+ * All of these (may) have I/O scattered all around
2635+ * and may not use i/o-base address registers at all.
2636+ * So we just have to always enable I/O to these
2637+ * devices.
2638+ */
2639+ cmd |= PCI_COMMAND_IO;
2640+ pci_write_config_word(dev, PCI_COMMAND,
2641+ cmd | PCI_COMMAND_MASTER);
2642+ }
2643+
2644+ pci_write_config_byte(dev, PCI_LATENCY_TIMER,
2645+ (disable_pci_burst) ? 0 : 32);
2646+
2647+ if (bus_info != NULL)
2648+ bus_info->conf_device(dev);
2649+ /* Machine dependent configuration. */
2650+
2651+ printk(KERN_INFO "layout_dev: bus %d slot 0x%x "
2652+ "VID 0x%x DID 0x%x class 0x%x\n",
2653+ dev->bus->number, PCI_SLOT(dev->devfn),
2654+ dev->vendor, dev->device, dev->class);
2655+}
2656+
2657+/*
2658+ * static void layout_bus(struct pci_bus *bus)
2659+ *
2660+ * Layout memory and I/O for all devices on the given bus.
2661+ *
2662+ * Parameters:
2663+ *
2664+ * bus - bus.
2665+ */
2666+
2667+static void __init layout_bus(struct pci_bus *bus)
2668+{
2669+ unsigned int bio, bmem;
2670+ struct pci_dev *dev;
2671+
2672+ DBG_DEVS(("layout_bus: starting bus %d\n", bus->number));
2673+
2674+ if (list_empty(&bus->devices) && list_empty(&bus->children))
2675+ return;
2676+
2677+ /*
2678+ * Align the current bases on appropriate boundaries (4K for
2679+ * IO and 1MB for memory).
2680+ */
2681+
2682+ bio = io_base = ALIGN(io_base, 4*KB);
2683+ bmem = mem_base = ALIGN(mem_base, 1*MB);
2684+
2685+ /*
2686+ * PCI devices might have been setup by a PCI BIOS emulation
2687+ * running under TOS. In these cases there is a
2688+ * window during which two devices may have an overlapping
2689+ * address range. To avoid this causing trouble, we first
2690+ * turn off the I/O and memory address decoders for all PCI
2691+ * devices. They'll be re-enabled only once all address
2692+ * decoders are programmed consistently.
2693+ */
2694+
2695+ DBG_DEVS(("layout_bus: disable_dev for bus %d\n", bus->number));
2696+
2697+#ifdef NL_ORIGINAL
2698+ for (dev = bus->devices; dev; dev = dev->sibling) {
2699+#else
2700+ dev = NULL;
2701+ while ((dev = pci_get_device(
2702+ PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2703+#endif
2704+ if ((dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) ||
2705+ (dev->class >> 8 == PCI_CLASS_BRIDGE_PCMCIA))
2706+ disable_dev(dev);
2707+ }
2708+
2709+ /*
2710+ * Allocate space to each device:
2711+ */
2712+
2713+ DBG_DEVS(("layout_bus: starting bus %d devices\n", bus->number));
2714+
2715+#ifdef NL_ORIGINAL
2716+ for (dev = bus->devices; dev; dev = dev->sibling) {
2717+#else
2718+ dev = NULL;
2719+ while ((dev = pci_get_device(
2720+ PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2721+#endif
2722+
2723+ if ((dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) ||
2724+ (dev->class >> 8 == PCI_CLASS_BRIDGE_PCMCIA))
2725+ layout_dev(dev);
2726+ }
2727+
2728+ DBG_DEVS(("layout_bus: bus %d finished\n", bus->number));
2729+}
2730+
2731+/*
2732+ * static void pcibios_fixup(void)
2733+ *
2734+ * Layout memory and I/O of all devices on the PCI bus if 'pci_modify' is
2735+ * true. This might be necessary because not every m68k machine with a PCI
2736+ * bus has a PCI BIOS. This function should be called right after
2737+ * pci_scan_bus() in pcibios_init().
2738+ */
2739+
2740+static void __init pcibios_fixup(void)
2741+{
2742+ DBG_DEVS(("%s\n", __func__));
2743+ if (pci_modify) {
2744+ /*
2745+ * Set base addresses for allocation of I/O and memory space.
2746+ */
2747+
2748+ io_base = bus_info->io_space.start + IO_ALLOC_OFFSET;
2749+ mem_base = bus_info->mem_space.start + MEM_ALLOC_OFFSET;
2750+
2751+ /*
2752+ * Scan the tree, allocating PCI memory and I/O space.
2753+ */
2754+
2755+#ifdef NL_ORIGINAL
2756+ layout_bus(pci_bus_b(pci_root.next));
2757+#else
2758+ layout_bus(pci_bus_b(pci_root_buses.next));
2759+#endif
2760+ }
2761+
2762+ /*
2763+ * Fix interrupt assignments, etc.
2764+ */
2765+
2766+ bus_info->fixup(pci_modify);
2767+}
2768+
2769+/*
2770+ * static void pcibios_claim_resources(struct pci_bus *bus)
2771+ *
2772+ * Claim all resources that are assigned to devices on the given bus.
2773+ *
2774+ * Parameters:
2775+ *
2776+ * bus - bus.
2777+ */
2778+
2779+static void __init pcibios_claim_resources(struct pci_bus *bus)
2780+{
2781+ struct pci_dev *dev;
2782+ int i;
2783+ DBG_DEVS(("%s\n", __func__));
2784+#ifdef NL_ORIGINAL
2785+ while (bus) {
2786+#else
2787+ while ((bus = pci_find_next_bus(bus)) != NULL) {
2788+#endif
2789+
2790+#ifdef NL_ORIGINAL
2791+ for (dev = bus->devices; (dev != NULL);
2792+ dev = dev->sibling) {
2793+#else
2794+ dev = NULL;
2795+ while ((dev = pci_get_device(
2796+ PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2797+#endif
2798+ for (i = 0; i < PCI_NUM_RESOURCES; i++) {
2799+ struct resource *r = &dev->resource[i];
2800+ struct resource *pr;
2801+ struct pci_bus_info *bus_info =
2802+ (struct pci_bus_info *)dev->sysdata;
2803+
2804+ if ((r->start == 0) || (r->parent != NULL))
2805+ continue;
2806+
2807+#ifdef CONFIG_COLDFIRE
2808+ if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE)
2809+ continue;
2810+#endif /* CONFIG_COLDFIRE */
2811+#if 1
2812+ if (r->flags & IORESOURCE_IO)
2813+ pr = &bus_info->io_space;
2814+ else
2815+ pr = &bus_info->mem_space;
2816+#else
2817+ if (r->flags & IORESOURCE_IO)
2818+ pr = &ioport_resource;
2819+ else
2820+ pr = &iomem_resource;
2821+#endif
2822+ if (request_resource(pr, r) < 0) {
2823+#ifdef NL_ORIGINAL
2824+ DBG_DEVS(("PCI: Address space"
2825+ " collision on "
2826+ "region %d of device %s\n",
2827+ i, dev->name));
2828+#else
2829+ printk(KERN_INFO "PCI: Address space"
2830+ " collision on region %d of"
2831+ " device %s\n",
2832+ i, dev_name(&(dev->dev)));
2833+#endif
2834+ }
2835+ }
2836+
2837+#ifdef NL_ORIGINAL
2838+ }
2839+ if (bus->children)
2840+ pcibios_claim_resources(bus->children);
2841+#else
2842+ }
2843+ if (!list_empty(&bus->children))
2844+ pcibios_claim_resources(pci_bus_b(bus->children.next));
2845+#endif
2846+
2847+#ifdef NL_ORIGINAL
2848+ bus = bus->next;
2849+#endif
2850+ }
2851+}
2852+
2853+/*
2854+ * int pcibios_assign_resource(struct pci_dev *dev, int i)
2855+ *
2856+ * Assign a new address to a PCI resource.
2857+ *
2858+ * Parameters:
2859+ *
2860+ * dev - device.
2861+ * i - resource.
2862+ *
2863+ * Result: 0 if successful.
2864+ */
2865+
2866+int __init pcibios_assign_resource(struct pci_dev *dev, int i)
2867+{
2868+ struct resource *r = &dev->resource[i];
2869+ struct resource *pr = pci_find_parent_resource(dev, r);
2870+ unsigned long size = r->end + 1;
2871+ DBG_DEVS(("%s:IO_ALLOC_OFFSET %x\n", __func__, IO_ALLOC_OFFSET));
2872+ if (!pr)
2873+ return -EINVAL;
2874+
2875+ if (r->flags & IORESOURCE_IO) {
2876+ DBG_DEVS(("%s:IORESOURCE_IO:start %x, size %lx\n",
2877+ __func__, bus_info->io_space.start, size));
2878+ if (size > 0x100)
2879+ return -EFBIG;
2880+
2881+#ifdef NL_ORIGINAL
2882+ if (allocate_resource(pr, r, size, bus_info->io_space.start +
2883+ IO_ALLOC_OFFSET,
2884+ bus_info->io_space.end,
2885+ 1024))
2886+#else
2887+ if (allocate_resource(pr, r, size, bus_info->io_space.start +
2888+ IO_ALLOC_OFFSET,
2889+ bus_info->io_space.end,
2890+ 1024, NULL, NULL))
2891+#endif
2892+ return -EBUSY;
2893+ } else {
2894+ DBG_DEVS(("%s:IORESOURCE_MEM:start %x, size %lx\n",
2895+ __func__, bus_info->mem_space.start, size));
2896+#ifdef NL_ORIGINAL
2897+ if (allocate_resource(pr, r, size, bus_info->mem_space.start +
2898+ MEM_ALLOC_OFFSET,
2899+ bus_info->mem_space.end, size))
2900+#else
2901+ if (allocate_resource(pr, r, size, bus_info->io_space.start +
2902+ IO_ALLOC_OFFSET, bus_info->io_space.end,
2903+ 1024, NULL, NULL))
2904+#endif
2905+ return -EBUSY;
2906+ }
2907+
2908+ if (i < 6)
2909+ pci_write_config_dword(dev,
2910+ PCI_BASE_ADDRESS_0 + 4 * i, r->start);
2911+
2912+ return 0;
2913+}
2914+
2915+void pcibios_fixup_bus(struct pci_bus *bus)
2916+{
2917+ struct pci_dev *dev;
2918+ void *sysdata;
2919+
2920+ sysdata = (bus->parent) ? bus->parent->sysdata : bus->sysdata;
2921+
2922+#ifdef NL_ORIGINAL
2923+ for (dev = bus->devices; (dev != NULL); dev = dev->sibling)
2924+#else
2925+ dev = NULL;
2926+ while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL)
2927+#endif
2928+ dev->sysdata = sysdata;
2929+}
2930+
2931+int __init pcibios_init(void)
2932+{
2933+ printk(KERN_INFO "Linux/m68k PCI BIOS32 "
2934+ "revision %x.%02x\n", MAJOR_REV, MINOR_REV);
2935+
2936+ bus_info = NULL;
2937+#ifdef CONFIG_COLDFIRE
2938+ bus_info = init_coldfire_pci();
2939+#endif /* CONFIG_COLDFIRE */
2940+#ifdef CONFIG_HADES
2941+ if (MACH_IS_HADES)
2942+ bus_info = init_hades_pci();
2943+#endif
2944+ if (bus_info != NULL) {
2945+ printk(KERN_ERR "PCI: Probing PCI hardware\n");
2946+ pci_scan_bus(0, bus_info->m68k_pci_ops, bus_info);
2947+ pcibios_fixup();
2948+#ifdef NL_ORIGINAL
2949+ pcibios_claim_resources(pci_root);
2950+#else
2951+ pcibios_claim_resources(pci_bus_b(pci_root_buses.next));
2952+#endif
2953+ } else
2954+ printk(KERN_ERR "PCI: No PCI bus detected\n");
2955+ return 0;
2956+}
2957+
2958+subsys_initcall(pcibios_init);
2959+
2960+char *pcibios_setup(char *str)
2961+{
2962+ if (!strcmp(str, "nomodify")) {
2963+ pci_modify = 0;
2964+ return NULL;
2965+ } else if (!strcmp(str, "skipvga")) {
2966+ skip_vga = 1;
2967+ return NULL;
2968+ } else if (!strcmp(str, "noburst")) {
2969+ disable_pci_burst = 1;
2970+ return NULL;
2971+ }
2972+
2973+ return str;
2974+}
2975+#endif /* CONFIG_PCI */
2976--- a/drivers/pci/Makefile
2977+++ b/drivers/pci/Makefile
2978@@ -50,6 +50,7 @@ obj-$(CONFIG_X86_VISWS) += setup-irq.o
2979 obj-$(CONFIG_MN10300) += setup-bus.o
2980 obj-$(CONFIG_MICROBLAZE) += setup-bus.o
2981 obj-$(CONFIG_TILE) += setup-bus.o setup-irq.o
2982+obj-$(CONFIG_M54455) += setup-bus.o setup-irq.o
2983 
2984 #
2985 # ACPI Related PCI FW Functions
2986--- a/drivers/pci/access.c
2987+++ b/drivers/pci/access.c
2988@@ -25,6 +25,7 @@ static DEFINE_RAW_SPINLOCK(pci_lock);
2989 #define PCI_word_BAD (pos & 1)
2990 #define PCI_dword_BAD (pos & 3)
2991 
2992+#ifdef NL_ORIGINAL
2993 #define PCI_OP_READ(size,type,len) \
2994 int pci_bus_read_config_##size \
2995     (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
2996@@ -39,6 +40,23 @@ int pci_bus_read_config_##size \
2997     raw_spin_unlock_irqrestore(&pci_lock, flags); \
2998     return res; \
2999 }
3000+#else /* NL_ORIGINAL */
3001+#define PCI_OP_READ(size, type, len) \
3002+ int pci_bus_read_config_##size \
3003+ (struct pci_bus *bus, unsigned int devfn, \
3004+ int pos, type * value) \
3005+{ \
3006+ int res; \
3007+ unsigned long flags; \
3008+ if (PCI_##size##_BAD) \
3009+ return PCIBIOS_BAD_REGISTER_NUMBER; \
3010+ raw_spin_lock_irqsave(&pci_lock, flags); \
3011+ res = bus->ops->read( \
3012+ bus, devfn, pos, len, (u32 *)value); \
3013+ raw_spin_unlock_irqrestore(&pci_lock, flags); \
3014+ return res; \
3015+}
3016+#endif /* NL_ORIGINAL */
3017 
3018 #define PCI_OP_WRITE(size,type,len) \
3019 int pci_bus_write_config_##size \
3020--- a/drivers/pci/setup-bus.c
3021+++ b/drivers/pci/setup-bus.c
3022@@ -77,7 +77,13 @@ static void __dev_sort_resources(struct
3023     u16 class = dev->class >> 8;
3024 
3025     /* Don't touch classless devices or host bridges or ioapics. */
3026+#ifdef CONFIG_M5445X
3027+ if (class == PCI_CLASS_NOT_DEFINED || \
3028+ class == PCI_CLASS_BRIDGE_HOST || \
3029+ class == PCI_CLASS_BRIDGE_OTHER)
3030+#else
3031     if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
3032+#endif
3033         return;
3034 
3035     /* Don't touch ioapic devices already enabled by firmware */
3036--- a/lib/iomap.c
3037+++ b/lib/iomap.c
3038@@ -227,9 +227,13 @@ EXPORT_SYMBOL(iowrite32_rep);
3039 /* Create a virtual mapping cookie for an IO port range */
3040 void __iomem *ioport_map(unsigned long port, unsigned int nr)
3041 {
3042+#ifndef CONFIG_M54455
3043     if (port > PIO_MASK)
3044         return NULL;
3045     return (void __iomem *) (unsigned long) (port + PIO_OFFSET);
3046+#else
3047+ return (void __iomem *) (unsigned long) port;
3048+#endif
3049 }
3050 
3051 void ioport_unmap(void __iomem *addr)
3052

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