Root/target/linux/generic/files/drivers/net/phy/ar8216.c

1/*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/if.h>
19#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/list.h>
22#include <linux/if_ether.h>
23#include <linux/skbuff.h>
24#include <linux/netdevice.h>
25#include <linux/netlink.h>
26#include <linux/bitops.h>
27#include <net/genetlink.h>
28#include <linux/switch.h>
29#include <linux/delay.h>
30#include <linux/phy.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/lockdep.h>
34#include <linux/ar8216_platform.h>
35#include "ar8216.h"
36
37/* size of the vlan table */
38#define AR8X16_MAX_VLANS 128
39#define AR8X16_PROBE_RETRIES 10
40#define AR8X16_MAX_PORTS 8
41
42struct ar8216_priv;
43
44#define AR8XXX_CAP_GIGE BIT(0)
45
46enum {
47    AR8XXX_VER_AR8216 = 0x01,
48    AR8XXX_VER_AR8236 = 0x03,
49    AR8XXX_VER_AR8316 = 0x10,
50    AR8XXX_VER_AR8327 = 0x12,
51};
52
53struct ar8xxx_chip {
54    unsigned long caps;
55
56    int (*hw_init)(struct ar8216_priv *priv);
57    void (*init_globals)(struct ar8216_priv *priv);
58    void (*init_port)(struct ar8216_priv *priv, int port);
59    void (*setup_port)(struct ar8216_priv *priv, int port, u32 egress,
60               u32 ingress, u32 members, u32 pvid);
61    u32 (*read_port_status)(struct ar8216_priv *priv, int port);
62    int (*atu_flush)(struct ar8216_priv *priv);
63    void (*vtu_flush)(struct ar8216_priv *priv);
64    void (*vtu_load_vlan)(struct ar8216_priv *priv, u32 vid, u32 port_mask);
65};
66
67struct ar8216_priv {
68    struct switch_dev dev;
69    struct phy_device *phy;
70    u32 (*read)(struct ar8216_priv *priv, int reg);
71    void (*write)(struct ar8216_priv *priv, int reg, u32 val);
72    const struct net_device_ops *ndo_old;
73    struct net_device_ops ndo;
74    struct mutex reg_mutex;
75    u8 chip_ver;
76    u8 chip_rev;
77    const struct ar8xxx_chip *chip;
78    bool initialized;
79    bool port4_phy;
80    char buf[80];
81
82    bool init;
83    bool mii_lo_first;
84
85    /* all fields below are cleared on reset */
86    bool vlan;
87    u16 vlan_id[AR8X16_MAX_VLANS];
88    u8 vlan_table[AR8X16_MAX_VLANS];
89    u8 vlan_tagged;
90    u16 pvid[AR8X16_MAX_PORTS];
91};
92
93#define to_ar8216(_dev) container_of(_dev, struct ar8216_priv, dev)
94
95static inline bool ar8xxx_has_gige(struct ar8216_priv *priv)
96{
97    return priv->chip->caps & AR8XXX_CAP_GIGE;
98}
99
100static inline bool chip_is_ar8216(struct ar8216_priv *priv)
101{
102    return priv->chip_ver == AR8XXX_VER_AR8216;
103}
104
105static inline bool chip_is_ar8236(struct ar8216_priv *priv)
106{
107    return priv->chip_ver == AR8XXX_VER_AR8236;
108}
109
110static inline bool chip_is_ar8316(struct ar8216_priv *priv)
111{
112    return priv->chip_ver == AR8XXX_VER_AR8316;
113}
114
115static inline bool chip_is_ar8327(struct ar8216_priv *priv)
116{
117    return priv->chip_ver == AR8XXX_VER_AR8327;
118}
119
120static inline void
121split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
122{
123    regaddr >>= 1;
124    *r1 = regaddr & 0x1e;
125
126    regaddr >>= 5;
127    *r2 = regaddr & 0x7;
128
129    regaddr >>= 3;
130    *page = regaddr & 0x1ff;
131}
132
133static u32
134ar8216_mii_read(struct ar8216_priv *priv, int reg)
135{
136    struct phy_device *phy = priv->phy;
137    struct mii_bus *bus = phy->bus;
138    u16 r1, r2, page;
139    u16 lo, hi;
140
141    split_addr((u32) reg, &r1, &r2, &page);
142
143    mutex_lock(&bus->mdio_lock);
144
145    bus->write(bus, 0x18, 0, page);
146    usleep_range(1000, 2000); /* wait for the page switch to propagate */
147    lo = bus->read(bus, 0x10 | r2, r1);
148    hi = bus->read(bus, 0x10 | r2, r1 + 1);
149
150    mutex_unlock(&bus->mdio_lock);
151
152    return (hi << 16) | lo;
153}
154
155static void
156ar8216_mii_write(struct ar8216_priv *priv, int reg, u32 val)
157{
158    struct phy_device *phy = priv->phy;
159    struct mii_bus *bus = phy->bus;
160    u16 r1, r2, r3;
161    u16 lo, hi;
162
163    split_addr((u32) reg, &r1, &r2, &r3);
164    lo = val & 0xffff;
165    hi = (u16) (val >> 16);
166
167    mutex_lock(&bus->mdio_lock);
168
169    bus->write(bus, 0x18, 0, r3);
170    usleep_range(1000, 2000); /* wait for the page switch to propagate */
171    if (priv->mii_lo_first) {
172        bus->write(bus, 0x10 | r2, r1, lo);
173        bus->write(bus, 0x10 | r2, r1 + 1, hi);
174    } else {
175        bus->write(bus, 0x10 | r2, r1 + 1, hi);
176        bus->write(bus, 0x10 | r2, r1, lo);
177    }
178
179    mutex_unlock(&bus->mdio_lock);
180}
181
182static void
183ar8216_phy_dbg_write(struct ar8216_priv *priv, int phy_addr,
184             u16 dbg_addr, u16 dbg_data)
185{
186    struct mii_bus *bus = priv->phy->bus;
187
188    mutex_lock(&bus->mdio_lock);
189    bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
190    bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
191    mutex_unlock(&bus->mdio_lock);
192}
193
194static void
195ar8216_phy_mmd_write(struct ar8216_priv *priv, int phy_addr, u16 addr, u16 data)
196{
197    struct mii_bus *bus = priv->phy->bus;
198
199    mutex_lock(&bus->mdio_lock);
200    bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
201    bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
202    mutex_unlock(&bus->mdio_lock);
203}
204
205static u32
206ar8216_rmw(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
207{
208    u32 v;
209
210    lockdep_assert_held(&priv->reg_mutex);
211
212    v = priv->read(priv, reg);
213    v &= ~mask;
214    v |= val;
215    priv->write(priv, reg, v);
216
217    return v;
218}
219
220static void
221ar8216_read_port_link(struct ar8216_priv *priv, int port,
222              struct switch_port_link *link)
223{
224    u32 status;
225    u32 speed;
226
227    memset(link, '\0', sizeof(*link));
228
229    status = priv->chip->read_port_status(priv, port);
230
231    link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
232    if (link->aneg) {
233        link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
234        if (!link->link)
235            return;
236    } else {
237        link->link = true;
238    }
239
240    link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
241    link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
242    link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
243
244    speed = (status & AR8216_PORT_STATUS_SPEED) >>
245         AR8216_PORT_STATUS_SPEED_S;
246
247    switch (speed) {
248    case AR8216_PORT_SPEED_10M:
249        link->speed = SWITCH_PORT_SPEED_10;
250        break;
251    case AR8216_PORT_SPEED_100M:
252        link->speed = SWITCH_PORT_SPEED_100;
253        break;
254    case AR8216_PORT_SPEED_1000M:
255        link->speed = SWITCH_PORT_SPEED_1000;
256        break;
257    default:
258        link->speed = SWITCH_PORT_SPEED_UNKNOWN;
259        break;
260    }
261}
262
263static struct sk_buff *
264ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
265{
266    struct ar8216_priv *priv = dev->phy_ptr;
267    unsigned char *buf;
268
269    if (unlikely(!priv))
270        goto error;
271
272    if (!priv->vlan)
273        goto send;
274
275    if (unlikely(skb_headroom(skb) < 2)) {
276        if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
277            goto error;
278    }
279
280    buf = skb_push(skb, 2);
281    buf[0] = 0x10;
282    buf[1] = 0x80;
283
284send:
285    return skb;
286
287error:
288    dev_kfree_skb_any(skb);
289    return NULL;
290}
291
292static void
293ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
294{
295    struct ar8216_priv *priv;
296    unsigned char *buf;
297    int port, vlan;
298
299    priv = dev->phy_ptr;
300    if (!priv)
301        return;
302
303    /* don't strip the header if vlan mode is disabled */
304    if (!priv->vlan)
305        return;
306
307    /* strip header, get vlan id */
308    buf = skb->data;
309    skb_pull(skb, 2);
310
311    /* check for vlan header presence */
312    if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
313        return;
314
315    port = buf[0] & 0xf;
316
317    /* no need to fix up packets coming from a tagged source */
318    if (priv->vlan_tagged & (1 << port))
319        return;
320
321    /* lookup port vid from local table, the switch passes an invalid vlan id */
322    vlan = priv->vlan_id[priv->pvid[port]];
323
324    buf[14 + 2] &= 0xf0;
325    buf[14 + 2] |= vlan >> 8;
326    buf[15 + 2] = vlan & 0xff;
327}
328
329static int
330ar8216_wait_bit(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
331{
332    int timeout = 20;
333    u32 t = 0;
334
335    while (1) {
336        t = priv->read(priv, reg);
337        if ((t & mask) == val)
338            return 0;
339
340        if (timeout-- <= 0)
341            break;
342
343        udelay(10);
344    }
345
346    pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
347           (unsigned int) reg, t, mask, val);
348    return -ETIMEDOUT;
349}
350
351static void
352ar8216_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
353{
354    if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
355        return;
356    if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
357        val &= AR8216_VTUDATA_MEMBER;
358        val |= AR8216_VTUDATA_VALID;
359        priv->write(priv, AR8216_REG_VTU_DATA, val);
360    }
361    op |= AR8216_VTU_ACTIVE;
362    priv->write(priv, AR8216_REG_VTU, op);
363}
364
365static void
366ar8216_vtu_flush(struct ar8216_priv *priv)
367{
368    ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
369}
370
371static void
372ar8216_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
373{
374    u32 op;
375
376    op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
377    ar8216_vtu_op(priv, op, port_mask);
378}
379
380static int
381ar8216_atu_flush(struct ar8216_priv *priv)
382{
383    int ret;
384
385    ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
386    if (!ret)
387        priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
388
389    return ret;
390}
391
392static u32
393ar8216_read_port_status(struct ar8216_priv *priv, int port)
394{
395    return priv->read(priv, AR8216_REG_PORT_STATUS(port));
396}
397
398static void
399ar8216_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
400          u32 members, u32 pvid)
401{
402    u32 header;
403
404    if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
405        header = AR8216_PORT_CTRL_HEADER;
406    else
407        header = 0;
408
409    ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
410           AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
411           AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
412           AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
413           AR8216_PORT_CTRL_LEARN | header |
414           (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
415           (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
416
417    ar8216_rmw(priv, AR8216_REG_PORT_VLAN(port),
418           AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
419           AR8216_PORT_VLAN_DEFAULT_ID,
420           (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
421           (ingress << AR8216_PORT_VLAN_MODE_S) |
422           (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
423}
424
425static int
426ar8216_hw_init(struct ar8216_priv *priv)
427{
428    return 0;
429}
430
431static void
432ar8216_init_globals(struct ar8216_priv *priv)
433{
434    /* standard atheros magic */
435    priv->write(priv, 0x38, 0xc000050e);
436
437    ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
438           AR8216_GCTRL_MTU, 1518 + 8 + 2);
439}
440
441static void
442ar8216_init_port(struct ar8216_priv *priv, int port)
443{
444    /* Enable port learning and tx */
445    priv->write(priv, AR8216_REG_PORT_CTRL(port),
446        AR8216_PORT_CTRL_LEARN |
447        (4 << AR8216_PORT_CTRL_STATE_S));
448
449    priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
450
451    if (port == AR8216_PORT_CPU) {
452        priv->write(priv, AR8216_REG_PORT_STATUS(port),
453            AR8216_PORT_STATUS_LINK_UP |
454            (ar8xxx_has_gige(priv) ?
455                                AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
456            AR8216_PORT_STATUS_TXMAC |
457            AR8216_PORT_STATUS_RXMAC |
458            (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
459            (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
460            AR8216_PORT_STATUS_DUPLEX);
461    } else {
462        priv->write(priv, AR8216_REG_PORT_STATUS(port),
463            AR8216_PORT_STATUS_LINK_AUTO);
464    }
465}
466
467static const struct ar8xxx_chip ar8216_chip = {
468    .hw_init = ar8216_hw_init,
469    .init_globals = ar8216_init_globals,
470    .init_port = ar8216_init_port,
471    .setup_port = ar8216_setup_port,
472    .read_port_status = ar8216_read_port_status,
473    .atu_flush = ar8216_atu_flush,
474    .vtu_flush = ar8216_vtu_flush,
475    .vtu_load_vlan = ar8216_vtu_load_vlan,
476};
477
478static void
479ar8236_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
480          u32 members, u32 pvid)
481{
482    ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
483           AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
484           AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
485           AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
486           AR8216_PORT_CTRL_LEARN |
487           (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
488           (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
489
490    ar8216_rmw(priv, AR8236_REG_PORT_VLAN(port),
491           AR8236_PORT_VLAN_DEFAULT_ID,
492           (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
493
494    ar8216_rmw(priv, AR8236_REG_PORT_VLAN2(port),
495           AR8236_PORT_VLAN2_VLAN_MODE |
496           AR8236_PORT_VLAN2_MEMBER,
497           (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
498           (members << AR8236_PORT_VLAN2_MEMBER_S));
499}
500
501static int
502ar8236_hw_init(struct ar8216_priv *priv)
503{
504    int i;
505    struct mii_bus *bus;
506
507    if (priv->initialized)
508        return 0;
509
510    /* Initialize the PHYs */
511    bus = priv->phy->bus;
512    for (i = 0; i < 5; i++) {
513        mdiobus_write(bus, i, MII_ADVERTISE,
514                  ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
515                  ADVERTISE_PAUSE_ASYM);
516        mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
517    }
518    msleep(1000);
519
520    priv->initialized = true;
521    return 0;
522}
523
524static void
525ar8236_init_globals(struct ar8216_priv *priv)
526{
527    /* enable jumbo frames */
528    ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
529           AR8316_GCTRL_MTU, 9018 + 8 + 2);
530}
531
532static const struct ar8xxx_chip ar8236_chip = {
533    .hw_init = ar8236_hw_init,
534    .init_globals = ar8236_init_globals,
535    .init_port = ar8216_init_port,
536    .setup_port = ar8236_setup_port,
537    .read_port_status = ar8216_read_port_status,
538    .atu_flush = ar8216_atu_flush,
539    .vtu_flush = ar8216_vtu_flush,
540    .vtu_load_vlan = ar8216_vtu_load_vlan,
541};
542
543static int
544ar8316_hw_init(struct ar8216_priv *priv)
545{
546    int i;
547    u32 val, newval;
548    struct mii_bus *bus;
549
550    val = priv->read(priv, 0x8);
551
552    if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
553        if (priv->port4_phy) {
554            /* value taken from Ubiquiti RouterStation Pro */
555            newval = 0x81461bea;
556            printk(KERN_INFO "ar8316: Using port 4 as PHY\n");
557        } else {
558            newval = 0x01261be2;
559            printk(KERN_INFO "ar8316: Using port 4 as switch port\n");
560        }
561    } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
562        /* value taken from AVM Fritz!Box 7390 sources */
563        newval = 0x010e5b71;
564    } else {
565        /* no known value for phy interface */
566        printk(KERN_ERR "ar8316: unsupported mii mode: %d.\n",
567            priv->phy->interface);
568        return -EINVAL;
569    }
570
571    if (val == newval)
572        goto out;
573
574    priv->write(priv, 0x8, newval);
575
576    /* Initialize the ports */
577    bus = priv->phy->bus;
578    for (i = 0; i < 5; i++) {
579        if ((i == 4) && priv->port4_phy &&
580            priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
581            /* work around for phy4 rgmii mode */
582            ar8216_phy_dbg_write(priv, i, 0x12, 0x480c);
583            /* rx delay */
584            ar8216_phy_dbg_write(priv, i, 0x0, 0x824e);
585            /* tx delay */
586            ar8216_phy_dbg_write(priv, i, 0x5, 0x3d47);
587            msleep(1000);
588        }
589
590        /* initialize the port itself */
591        mdiobus_write(bus, i, MII_ADVERTISE,
592            ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
593        mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
594        mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
595        msleep(1000);
596    }
597
598out:
599    priv->initialized = true;
600    return 0;
601}
602
603static void
604ar8316_init_globals(struct ar8216_priv *priv)
605{
606    /* standard atheros magic */
607    priv->write(priv, 0x38, 0xc000050e);
608
609    /* enable cpu port to receive multicast and broadcast frames */
610    priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
611
612    /* enable jumbo frames */
613    ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
614           AR8316_GCTRL_MTU, 9018 + 8 + 2);
615}
616
617static const struct ar8xxx_chip ar8316_chip = {
618    .caps = AR8XXX_CAP_GIGE,
619    .hw_init = ar8316_hw_init,
620    .init_globals = ar8316_init_globals,
621    .init_port = ar8216_init_port,
622    .setup_port = ar8216_setup_port,
623    .read_port_status = ar8216_read_port_status,
624    .atu_flush = ar8216_atu_flush,
625    .vtu_flush = ar8216_vtu_flush,
626    .vtu_load_vlan = ar8216_vtu_load_vlan,
627};
628
629static u32
630ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
631{
632    u32 t;
633
634    if (!cfg)
635        return 0;
636
637    t = 0;
638    switch (cfg->mode) {
639    case AR8327_PAD_NC:
640        break;
641
642    case AR8327_PAD_MAC2MAC_MII:
643        t = AR8327_PAD_MAC_MII_EN;
644        if (cfg->rxclk_sel)
645            t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
646        if (cfg->txclk_sel)
647            t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
648        break;
649
650    case AR8327_PAD_MAC2MAC_GMII:
651        t = AR8327_PAD_MAC_GMII_EN;
652        if (cfg->rxclk_sel)
653            t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
654        if (cfg->txclk_sel)
655            t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
656        break;
657
658    case AR8327_PAD_MAC_SGMII:
659        t = AR8327_PAD_SGMII_EN;
660        break;
661
662    case AR8327_PAD_MAC2PHY_MII:
663        t = AR8327_PAD_PHY_MII_EN;
664        if (cfg->rxclk_sel)
665            t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
666        if (cfg->txclk_sel)
667            t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
668        break;
669
670    case AR8327_PAD_MAC2PHY_GMII:
671        t = AR8327_PAD_PHY_GMII_EN;
672        if (cfg->pipe_rxclk_sel)
673            t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
674        if (cfg->rxclk_sel)
675            t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
676        if (cfg->txclk_sel)
677            t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
678        break;
679
680    case AR8327_PAD_MAC_RGMII:
681        t = AR8327_PAD_RGMII_EN;
682        t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
683        t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
684        if (cfg->rxclk_delay_en)
685            t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
686        if (cfg->txclk_delay_en)
687            t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
688        break;
689
690    case AR8327_PAD_PHY_GMII:
691        t = AR8327_PAD_PHYX_GMII_EN;
692        break;
693
694    case AR8327_PAD_PHY_RGMII:
695        t = AR8327_PAD_PHYX_RGMII_EN;
696        break;
697
698    case AR8327_PAD_PHY_MII:
699        t = AR8327_PAD_PHYX_MII_EN;
700        break;
701    }
702
703    return t;
704}
705
706static void
707ar8327_phy_fixup(struct ar8216_priv *priv, int phy)
708{
709    switch (priv->chip_rev) {
710    case 1:
711        /* For 100M waveform */
712        ar8216_phy_dbg_write(priv, phy, 0, 0x02ea);
713        /* Turn on Gigabit clock */
714        ar8216_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
715        break;
716
717    case 2:
718        ar8216_phy_mmd_write(priv, phy, 0x7, 0x3c);
719        ar8216_phy_mmd_write(priv, phy, 0x4007, 0x0);
720        /* fallthrough */
721    case 4:
722        ar8216_phy_mmd_write(priv, phy, 0x3, 0x800d);
723        ar8216_phy_mmd_write(priv, phy, 0x4003, 0x803f);
724
725        ar8216_phy_dbg_write(priv, phy, 0x3d, 0x6860);
726        ar8216_phy_dbg_write(priv, phy, 0x5, 0x2c46);
727        ar8216_phy_dbg_write(priv, phy, 0x3c, 0x6000);
728        break;
729    }
730}
731
732static int
733ar8327_hw_init(struct ar8216_priv *priv)
734{
735    struct ar8327_platform_data *pdata;
736    struct ar8327_led_cfg *led_cfg;
737    struct mii_bus *bus;
738    u32 pos, new_pos;
739    u32 t;
740    int i;
741
742    pdata = priv->phy->dev.platform_data;
743    if (!pdata)
744        return -EINVAL;
745
746    t = ar8327_get_pad_cfg(pdata->pad0_cfg);
747    priv->write(priv, AR8327_REG_PAD0_MODE, t);
748    t = ar8327_get_pad_cfg(pdata->pad5_cfg);
749    priv->write(priv, AR8327_REG_PAD5_MODE, t);
750    t = ar8327_get_pad_cfg(pdata->pad6_cfg);
751    priv->write(priv, AR8327_REG_PAD6_MODE, t);
752
753    pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
754    new_pos = pos;
755
756    led_cfg = pdata->led_cfg;
757    if (led_cfg) {
758        if (led_cfg->open_drain)
759            new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
760        else
761            new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
762
763        priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
764        priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
765        priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
766        priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
767    }
768
769    if (new_pos != pos) {
770        new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
771        priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
772    }
773
774    bus = priv->phy->bus;
775    for (i = 0; i < AR8327_NUM_PHYS; i++) {
776        ar8327_phy_fixup(priv, i);
777
778        /* start aneg on the PHY */
779        mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
780                             ADVERTISE_PAUSE_CAP |
781                             ADVERTISE_PAUSE_ASYM);
782        mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
783        mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
784    }
785
786    msleep(1000);
787
788    return 0;
789}
790
791static void
792ar8327_init_globals(struct ar8216_priv *priv)
793{
794    u32 t;
795
796    /* enable CPU port and disable mirror port */
797    t = AR8327_FWD_CTRL0_CPU_PORT_EN |
798        AR8327_FWD_CTRL0_MIRROR_PORT;
799    priv->write(priv, AR8327_REG_FWD_CTRL0, t);
800
801    /* forward multicast and broadcast frames to CPU */
802    t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
803        (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
804        (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
805    priv->write(priv, AR8327_REG_FWD_CTRL1, t);
806
807    /* setup MTU */
808    ar8216_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
809           AR8327_MAX_FRAME_SIZE_MTU, 1518 + 8 + 2);
810}
811
812static void
813ar8327_init_cpuport(struct ar8216_priv *priv)
814{
815    struct ar8327_platform_data *pdata;
816    struct ar8327_port_cfg *cfg;
817    u32 t;
818
819    pdata = priv->phy->dev.platform_data;
820    if (!pdata)
821        return;
822
823    cfg = &pdata->cpuport_cfg;
824    if (!cfg->force_link) {
825        priv->write(priv, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU),
826                AR8216_PORT_STATUS_LINK_AUTO);
827        return;
828    }
829
830    t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
831    t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
832    t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
833    t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
834    switch (cfg->speed) {
835    case AR8327_PORT_SPEED_10:
836        t |= AR8216_PORT_SPEED_10M;
837        break;
838    case AR8327_PORT_SPEED_100:
839        t |= AR8216_PORT_SPEED_100M;
840        break;
841    case AR8327_PORT_SPEED_1000:
842        t |= AR8216_PORT_SPEED_1000M;
843        break;
844    }
845
846    priv->write(priv, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU), t);
847}
848
849static void
850ar8327_init_port(struct ar8216_priv *priv, int port)
851{
852    u32 t;
853
854    if (port == AR8216_PORT_CPU) {
855        ar8327_init_cpuport(priv);
856    } else {
857        t = AR8216_PORT_STATUS_LINK_AUTO;
858        priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
859    }
860
861    priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
862
863    priv->write(priv, AR8327_REG_PORT_VLAN0(port), 0);
864
865    t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
866    priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
867
868    t = AR8327_PORT_LOOKUP_LEARN;
869    t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
870    priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
871}
872
873static u32
874ar8327_read_port_status(struct ar8216_priv *priv, int port)
875{
876    return priv->read(priv, AR8327_REG_PORT_STATUS(port));
877}
878
879static int
880ar8327_atu_flush(struct ar8216_priv *priv)
881{
882    int ret;
883
884    ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
885                  AR8327_ATU_FUNC_BUSY, 0);
886    if (!ret)
887        priv->write(priv, AR8327_REG_ATU_FUNC,
888                AR8327_ATU_FUNC_OP_FLUSH);
889
890    return ret;
891}
892
893static void
894ar8327_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
895{
896    if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
897                AR8327_VTU_FUNC1_BUSY, 0))
898        return;
899
900    if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
901        priv->write(priv, AR8327_REG_VTU_FUNC0, val);
902
903    op |= AR8327_VTU_FUNC1_BUSY;
904    priv->write(priv, AR8327_REG_VTU_FUNC1, op);
905}
906
907static void
908ar8327_vtu_flush(struct ar8216_priv *priv)
909{
910    ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
911}
912
913static void
914ar8327_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
915{
916    u32 op;
917    u32 val;
918    int i;
919
920    op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
921    val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
922    for (i = 0; i < AR8327_NUM_PORTS; i++) {
923        u32 mode;
924
925        if ((port_mask & BIT(i)) == 0)
926            mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
927        else if (priv->vlan == 0)
928            mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
929        else if (priv->vlan_tagged & BIT(i))
930            mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
931        else
932            mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
933
934        val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
935    }
936    ar8327_vtu_op(priv, op, val);
937}
938
939static void
940ar8327_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
941          u32 members, u32 pvid)
942{
943    u32 t;
944    u32 mode;
945
946    t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
947    t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
948    priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
949
950    mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
951    switch (egress) {
952    case AR8216_OUT_KEEP:
953        mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
954        break;
955    case AR8216_OUT_STRIP_VLAN:
956        mode = AR8327_PORT_VLAN1_OUT_MODE_UNTAG;
957        break;
958    case AR8216_OUT_ADD_VLAN:
959        mode = AR8327_PORT_VLAN1_OUT_MODE_TAG;
960        break;
961    }
962
963    t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
964    t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
965    priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
966
967    t = members;
968    t |= AR8327_PORT_LOOKUP_LEARN;
969    t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
970    t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
971    priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
972}
973
974static const struct ar8xxx_chip ar8327_chip = {
975    .caps = AR8XXX_CAP_GIGE,
976    .hw_init = ar8327_hw_init,
977    .init_globals = ar8327_init_globals,
978    .init_port = ar8327_init_port,
979    .setup_port = ar8327_setup_port,
980    .read_port_status = ar8327_read_port_status,
981    .atu_flush = ar8327_atu_flush,
982    .vtu_flush = ar8327_vtu_flush,
983    .vtu_load_vlan = ar8327_vtu_load_vlan,
984};
985
986static int
987ar8216_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
988           struct switch_val *val)
989{
990    struct ar8216_priv *priv = to_ar8216(dev);
991    priv->vlan = !!val->value.i;
992    return 0;
993}
994
995static int
996ar8216_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
997           struct switch_val *val)
998{
999    struct ar8216_priv *priv = to_ar8216(dev);
1000    val->value.i = priv->vlan;
1001    return 0;
1002}
1003
1004
1005static int
1006ar8216_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1007{
1008    struct ar8216_priv *priv = to_ar8216(dev);
1009
1010    /* make sure no invalid PVIDs get set */
1011
1012    if (vlan >= dev->vlans)
1013        return -EINVAL;
1014
1015    priv->pvid[port] = vlan;
1016    return 0;
1017}
1018
1019static int
1020ar8216_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1021{
1022    struct ar8216_priv *priv = to_ar8216(dev);
1023    *vlan = priv->pvid[port];
1024    return 0;
1025}
1026
1027static int
1028ar8216_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1029          struct switch_val *val)
1030{
1031    struct ar8216_priv *priv = to_ar8216(dev);
1032    priv->vlan_id[val->port_vlan] = val->value.i;
1033    return 0;
1034}
1035
1036static int
1037ar8216_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1038          struct switch_val *val)
1039{
1040    struct ar8216_priv *priv = to_ar8216(dev);
1041    val->value.i = priv->vlan_id[val->port_vlan];
1042    return 0;
1043}
1044
1045static int
1046ar8216_sw_get_port_link(struct switch_dev *dev, int port,
1047            struct switch_port_link *link)
1048{
1049    struct ar8216_priv *priv = to_ar8216(dev);
1050
1051    ar8216_read_port_link(priv, port, link);
1052    return 0;
1053}
1054
1055static int
1056ar8216_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1057{
1058    struct ar8216_priv *priv = to_ar8216(dev);
1059    u8 ports = priv->vlan_table[val->port_vlan];
1060    int i;
1061
1062    val->len = 0;
1063    for (i = 0; i < dev->ports; i++) {
1064        struct switch_port *p;
1065
1066        if (!(ports & (1 << i)))
1067            continue;
1068
1069        p = &val->value.ports[val->len++];
1070        p->id = i;
1071        if (priv->vlan_tagged & (1 << i))
1072            p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1073        else
1074            p->flags = 0;
1075    }
1076    return 0;
1077}
1078
1079static int
1080ar8216_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1081{
1082    struct ar8216_priv *priv = to_ar8216(dev);
1083    u8 *vt = &priv->vlan_table[val->port_vlan];
1084    int i, j;
1085
1086    *vt = 0;
1087    for (i = 0; i < val->len; i++) {
1088        struct switch_port *p = &val->value.ports[i];
1089
1090        if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1091            priv->vlan_tagged |= (1 << p->id);
1092        } else {
1093            priv->vlan_tagged &= ~(1 << p->id);
1094            priv->pvid[p->id] = val->port_vlan;
1095
1096            /* make sure that an untagged port does not
1097             * appear in other vlans */
1098            for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1099                if (j == val->port_vlan)
1100                    continue;
1101                priv->vlan_table[j] &= ~(1 << p->id);
1102            }
1103        }
1104
1105        *vt |= 1 << p->id;
1106    }
1107    return 0;
1108}
1109
1110static int
1111ar8216_sw_hw_apply(struct switch_dev *dev)
1112{
1113    struct ar8216_priv *priv = to_ar8216(dev);
1114    u8 portmask[AR8X16_MAX_PORTS];
1115    int i, j;
1116
1117    mutex_lock(&priv->reg_mutex);
1118    /* flush all vlan translation unit entries */
1119    priv->chip->vtu_flush(priv);
1120
1121    memset(portmask, 0, sizeof(portmask));
1122    if (!priv->init) {
1123        /* calculate the port destination masks and load vlans
1124         * into the vlan translation unit */
1125        for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1126            u8 vp = priv->vlan_table[j];
1127
1128            if (!vp)
1129                continue;
1130
1131            for (i = 0; i < dev->ports; i++) {
1132                u8 mask = (1 << i);
1133                if (vp & mask)
1134                    portmask[i] |= vp & ~mask;
1135            }
1136
1137            priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1138                         priv->vlan_table[j]);
1139        }
1140    } else {
1141        /* vlan disabled:
1142         * isolate all ports, but connect them to the cpu port */
1143        for (i = 0; i < dev->ports; i++) {
1144            if (i == AR8216_PORT_CPU)
1145                continue;
1146
1147            portmask[i] = 1 << AR8216_PORT_CPU;
1148            portmask[AR8216_PORT_CPU] |= (1 << i);
1149        }
1150    }
1151
1152    /* update the port destination mask registers and tag settings */
1153    for (i = 0; i < dev->ports; i++) {
1154        int egress, ingress;
1155        int pvid;
1156
1157        if (priv->vlan) {
1158            pvid = priv->vlan_id[priv->pvid[i]];
1159            if (priv->vlan_tagged & (1 << i))
1160                egress = AR8216_OUT_ADD_VLAN;
1161            else
1162                egress = AR8216_OUT_STRIP_VLAN;
1163            ingress = AR8216_IN_SECURE;
1164        } else {
1165            pvid = i;
1166            egress = AR8216_OUT_KEEP;
1167            ingress = AR8216_IN_PORT_ONLY;
1168        }
1169
1170        priv->chip->setup_port(priv, i, egress, ingress, portmask[i],
1171                       pvid);
1172    }
1173    mutex_unlock(&priv->reg_mutex);
1174    return 0;
1175}
1176
1177static int
1178ar8216_sw_reset_switch(struct switch_dev *dev)
1179{
1180    struct ar8216_priv *priv = to_ar8216(dev);
1181    int i;
1182
1183    mutex_lock(&priv->reg_mutex);
1184    memset(&priv->vlan, 0, sizeof(struct ar8216_priv) -
1185        offsetof(struct ar8216_priv, vlan));
1186
1187    for (i = 0; i < AR8X16_MAX_VLANS; i++)
1188        priv->vlan_id[i] = i;
1189
1190    /* Configure all ports */
1191    for (i = 0; i < dev->ports; i++)
1192        priv->chip->init_port(priv, i);
1193
1194    priv->chip->init_globals(priv);
1195    mutex_unlock(&priv->reg_mutex);
1196
1197    return ar8216_sw_hw_apply(dev);
1198}
1199
1200static struct switch_attr ar8216_globals[] = {
1201    {
1202        .type = SWITCH_TYPE_INT,
1203        .name = "enable_vlan",
1204        .description = "Enable VLAN mode",
1205        .set = ar8216_sw_set_vlan,
1206        .get = ar8216_sw_get_vlan,
1207        .max = 1
1208    },
1209};
1210
1211static struct switch_attr ar8216_port[] = {
1212};
1213
1214static struct switch_attr ar8216_vlan[] = {
1215    {
1216        .type = SWITCH_TYPE_INT,
1217        .name = "vid",
1218        .description = "VLAN ID (0-4094)",
1219        .set = ar8216_sw_set_vid,
1220        .get = ar8216_sw_get_vid,
1221        .max = 4094,
1222    },
1223};
1224
1225static const struct switch_dev_ops ar8216_sw_ops = {
1226    .attr_global = {
1227        .attr = ar8216_globals,
1228        .n_attr = ARRAY_SIZE(ar8216_globals),
1229    },
1230    .attr_port = {
1231        .attr = ar8216_port,
1232        .n_attr = ARRAY_SIZE(ar8216_port),
1233    },
1234    .attr_vlan = {
1235        .attr = ar8216_vlan,
1236        .n_attr = ARRAY_SIZE(ar8216_vlan),
1237    },
1238    .get_port_pvid = ar8216_sw_get_pvid,
1239    .set_port_pvid = ar8216_sw_set_pvid,
1240    .get_vlan_ports = ar8216_sw_get_ports,
1241    .set_vlan_ports = ar8216_sw_set_ports,
1242    .apply_config = ar8216_sw_hw_apply,
1243    .reset_switch = ar8216_sw_reset_switch,
1244    .get_port_link = ar8216_sw_get_port_link,
1245};
1246
1247static int
1248ar8216_id_chip(struct ar8216_priv *priv)
1249{
1250    u32 val;
1251    u16 id;
1252    int i;
1253
1254    val = ar8216_mii_read(priv, AR8216_REG_CTRL);
1255    if (val == ~0)
1256        return -ENODEV;
1257
1258    id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1259    for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1260        u16 t;
1261
1262        val = ar8216_mii_read(priv, AR8216_REG_CTRL);
1263        if (val == ~0)
1264            return -ENODEV;
1265
1266        t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1267        if (t != id)
1268            return -ENODEV;
1269    }
1270
1271    priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1272    priv->chip_rev = (id & AR8216_CTRL_REVISION);
1273
1274    switch (priv->chip_ver) {
1275    case AR8XXX_VER_AR8216:
1276        priv->chip = &ar8216_chip;
1277        break;
1278    case AR8XXX_VER_AR8236:
1279        priv->chip = &ar8236_chip;
1280        break;
1281    case AR8XXX_VER_AR8316:
1282        priv->chip = &ar8316_chip;
1283        break;
1284    case AR8XXX_VER_AR8327:
1285        priv->mii_lo_first = true;
1286        priv->chip = &ar8327_chip;
1287        break;
1288    default:
1289        printk(KERN_DEBUG
1290            "ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n",
1291            priv->chip_ver, priv->chip_rev,
1292            mdiobus_read(priv->phy->bus, priv->phy->addr, 2),
1293            mdiobus_read(priv->phy->bus, priv->phy->addr, 3));
1294
1295        return -ENODEV;
1296    }
1297
1298    return 0;
1299}
1300
1301static int
1302ar8216_config_init(struct phy_device *pdev)
1303{
1304    struct ar8216_priv *priv = pdev->priv;
1305    struct net_device *dev = pdev->attached_dev;
1306    struct switch_dev *swdev;
1307    int ret;
1308
1309    if (!priv) {
1310        priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
1311        if (priv == NULL)
1312            return -ENOMEM;
1313    }
1314
1315    priv->phy = pdev;
1316
1317    ret = ar8216_id_chip(priv);
1318    if (ret)
1319        goto err_free_priv;
1320
1321    if (pdev->addr != 0) {
1322        if (ar8xxx_has_gige(priv)) {
1323            pdev->supported |= SUPPORTED_1000baseT_Full;
1324            pdev->advertising |= ADVERTISED_1000baseT_Full;
1325        }
1326
1327        if (chip_is_ar8316(priv)) {
1328            /* check if we're attaching to the switch twice */
1329            pdev = pdev->bus->phy_map[0];
1330            if (!pdev) {
1331                kfree(priv);
1332                return 0;
1333            }
1334
1335            /* switch device has not been initialized, reuse priv */
1336            if (!pdev->priv) {
1337                priv->port4_phy = true;
1338                pdev->priv = priv;
1339                return 0;
1340            }
1341
1342            kfree(priv);
1343
1344            /* switch device has been initialized, reinit */
1345            priv = pdev->priv;
1346            priv->dev.ports = (AR8216_NUM_PORTS - 1);
1347            priv->initialized = false;
1348            priv->port4_phy = true;
1349            ar8316_hw_init(priv);
1350            return 0;
1351        }
1352
1353        kfree(priv);
1354        return 0;
1355    }
1356
1357    if (ar8xxx_has_gige(priv))
1358        pdev->supported = SUPPORTED_1000baseT_Full;
1359    else
1360        pdev->supported = SUPPORTED_100baseT_Full;
1361    pdev->advertising = pdev->supported;
1362
1363    mutex_init(&priv->reg_mutex);
1364    priv->read = ar8216_mii_read;
1365    priv->write = ar8216_mii_write;
1366
1367    pdev->priv = priv;
1368
1369    swdev = &priv->dev;
1370    swdev->cpu_port = AR8216_PORT_CPU;
1371    swdev->ops = &ar8216_sw_ops;
1372    swdev->ports = AR8216_NUM_PORTS;
1373
1374    if (chip_is_ar8316(priv)) {
1375        swdev->name = "Atheros AR8316";
1376        swdev->vlans = AR8X16_MAX_VLANS;
1377
1378        if (priv->port4_phy) {
1379            /* port 5 connected to the other mac, therefore unusable */
1380            swdev->ports = (AR8216_NUM_PORTS - 1);
1381        }
1382    } else if (chip_is_ar8236(priv)) {
1383        swdev->name = "Atheros AR8236";
1384        swdev->vlans = AR8216_NUM_VLANS;
1385        swdev->ports = AR8216_NUM_PORTS;
1386    } else if (chip_is_ar8327(priv)) {
1387        swdev->name = "Atheros AR8327";
1388        swdev->vlans = AR8X16_MAX_VLANS;
1389        swdev->ports = AR8327_NUM_PORTS;
1390    } else {
1391        swdev->name = "Atheros AR8216";
1392        swdev->vlans = AR8216_NUM_VLANS;
1393    }
1394
1395    ret = register_switch(&priv->dev, pdev->attached_dev);
1396    if (ret)
1397        goto err_free_priv;
1398
1399    printk(KERN_INFO "%s: %s switch driver attached.\n",
1400        pdev->attached_dev->name, swdev->name);
1401
1402    priv->init = true;
1403
1404    ret = priv->chip->hw_init(priv);
1405    if (ret)
1406        goto err_free_priv;
1407
1408    ret = ar8216_sw_reset_switch(&priv->dev);
1409    if (ret)
1410        goto err_free_priv;
1411
1412    dev->phy_ptr = priv;
1413
1414    /* VID fixup only needed on ar8216 */
1415    if (chip_is_ar8216(priv) && pdev->addr == 0) {
1416        dev->priv_flags |= IFF_NO_IP_ALIGN;
1417        dev->eth_mangle_rx = ar8216_mangle_rx;
1418        dev->eth_mangle_tx = ar8216_mangle_tx;
1419    }
1420
1421    priv->init = false;
1422
1423    return 0;
1424
1425err_free_priv:
1426    kfree(priv);
1427    return ret;
1428}
1429
1430static int
1431ar8216_read_status(struct phy_device *phydev)
1432{
1433    struct ar8216_priv *priv = phydev->priv;
1434    struct switch_port_link link;
1435    int ret;
1436
1437    if (phydev->addr != 0)
1438        return genphy_read_status(phydev);
1439
1440    ar8216_read_port_link(priv, phydev->addr, &link);
1441    phydev->link = !!link.link;
1442    if (!phydev->link)
1443        return 0;
1444
1445    switch (link.speed) {
1446    case SWITCH_PORT_SPEED_10:
1447        phydev->speed = SPEED_10;
1448        break;
1449    case SWITCH_PORT_SPEED_100:
1450        phydev->speed = SPEED_100;
1451        break;
1452    case SWITCH_PORT_SPEED_1000:
1453        phydev->speed = SPEED_1000;
1454        break;
1455    default:
1456        phydev->speed = 0;
1457    }
1458    phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1459
1460    /* flush the address translation unit */
1461    mutex_lock(&priv->reg_mutex);
1462    ret = priv->chip->atu_flush(priv);
1463    mutex_unlock(&priv->reg_mutex);
1464
1465    phydev->state = PHY_RUNNING;
1466    netif_carrier_on(phydev->attached_dev);
1467    phydev->adjust_link(phydev->attached_dev);
1468
1469    return ret;
1470}
1471
1472static int
1473ar8216_config_aneg(struct phy_device *phydev)
1474{
1475    if (phydev->addr == 0)
1476        return 0;
1477
1478    return genphy_config_aneg(phydev);
1479}
1480
1481static int
1482ar8216_probe(struct phy_device *pdev)
1483{
1484    struct ar8216_priv priv;
1485
1486    priv.phy = pdev;
1487    return ar8216_id_chip(&priv);
1488}
1489
1490static void
1491ar8216_remove(struct phy_device *pdev)
1492{
1493    struct ar8216_priv *priv = pdev->priv;
1494    struct net_device *dev = pdev->attached_dev;
1495
1496    if (!priv)
1497        return;
1498
1499    dev->priv_flags &= ~IFF_NO_IP_ALIGN;
1500    dev->eth_mangle_rx = NULL;
1501    dev->eth_mangle_tx = NULL;
1502
1503    if (pdev->addr == 0)
1504        unregister_switch(&priv->dev);
1505    kfree(priv);
1506}
1507
1508static struct phy_driver ar8216_driver = {
1509    .phy_id = 0x004d0000,
1510    .name = "Atheros AR8216/AR8236/AR8316",
1511    .phy_id_mask = 0xffff0000,
1512    .features = PHY_BASIC_FEATURES,
1513    .probe = ar8216_probe,
1514    .remove = ar8216_remove,
1515    .config_init = &ar8216_config_init,
1516    .config_aneg = &ar8216_config_aneg,
1517    .read_status = &ar8216_read_status,
1518    .driver = { .owner = THIS_MODULE },
1519};
1520
1521int __init
1522ar8216_init(void)
1523{
1524    return phy_driver_register(&ar8216_driver);
1525}
1526
1527void __exit
1528ar8216_exit(void)
1529{
1530    phy_driver_unregister(&ar8216_driver);
1531}
1532
1533module_init(ar8216_init);
1534module_exit(ar8216_exit);
1535MODULE_LICENSE("GPL");
1536
1537

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