| 1 | /* |
| 2 | * ar8216.h: AR8216 switch driver |
| 3 | * |
| 4 | * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version 2 |
| 9 | * of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #ifndef __AR8216_H |
| 18 | #define __AR8216_H |
| 19 | |
| 20 | #define BITS(_s, _n) (((1UL << (_n)) - 1) << _s) |
| 21 | |
| 22 | #define AR8216_PORT_CPU 0 |
| 23 | #define AR8216_NUM_PORTS 6 |
| 24 | #define AR8216_NUM_VLANS 16 |
| 25 | #define AR8316_NUM_VLANS 4096 |
| 26 | |
| 27 | /* Atheros specific MII registers */ |
| 28 | #define MII_ATH_MMD_ADDR 0x0d |
| 29 | #define MII_ATH_MMD_DATA 0x0e |
| 30 | #define MII_ATH_DBG_ADDR 0x1d |
| 31 | #define MII_ATH_DBG_DATA 0x1e |
| 32 | |
| 33 | #define AR8216_REG_CTRL 0x0000 |
| 34 | #define AR8216_CTRL_REVISION BITS(0, 8) |
| 35 | #define AR8216_CTRL_REVISION_S 0 |
| 36 | #define AR8216_CTRL_VERSION BITS(8, 8) |
| 37 | #define AR8216_CTRL_VERSION_S 8 |
| 38 | #define AR8216_CTRL_RESET BIT(31) |
| 39 | |
| 40 | #define AR8216_REG_FLOOD_MASK 0x002C |
| 41 | #define AR8216_FM_UNI_DEST_PORTS BITS(0, 6) |
| 42 | #define AR8216_FM_MULTI_DEST_PORTS BITS(16, 6) |
| 43 | |
| 44 | #define AR8216_REG_GLOBAL_CTRL 0x0030 |
| 45 | #define AR8216_GCTRL_MTU BITS(0, 11) |
| 46 | #define AR8236_GCTRL_MTU BITS(0, 14) |
| 47 | #define AR8316_GCTRL_MTU BITS(0, 14) |
| 48 | |
| 49 | #define AR8216_REG_VTU 0x0040 |
| 50 | #define AR8216_VTU_OP BITS(0, 3) |
| 51 | #define AR8216_VTU_OP_NOOP 0x0 |
| 52 | #define AR8216_VTU_OP_FLUSH 0x1 |
| 53 | #define AR8216_VTU_OP_LOAD 0x2 |
| 54 | #define AR8216_VTU_OP_PURGE 0x3 |
| 55 | #define AR8216_VTU_OP_REMOVE_PORT 0x4 |
| 56 | #define AR8216_VTU_ACTIVE BIT(3) |
| 57 | #define AR8216_VTU_FULL BIT(4) |
| 58 | #define AR8216_VTU_PORT BITS(8, 4) |
| 59 | #define AR8216_VTU_PORT_S 8 |
| 60 | #define AR8216_VTU_VID BITS(16, 12) |
| 61 | #define AR8216_VTU_VID_S 16 |
| 62 | #define AR8216_VTU_PRIO BITS(28, 3) |
| 63 | #define AR8216_VTU_PRIO_S 28 |
| 64 | #define AR8216_VTU_PRIO_EN BIT(31) |
| 65 | |
| 66 | #define AR8216_REG_VTU_DATA 0x0044 |
| 67 | #define AR8216_VTUDATA_MEMBER BITS(0, 10) |
| 68 | #define AR8236_VTUDATA_MEMBER BITS(0, 7) |
| 69 | #define AR8216_VTUDATA_VALID BIT(11) |
| 70 | |
| 71 | #define AR8216_REG_ATU 0x0050 |
| 72 | #define AR8216_ATU_OP BITS(0, 3) |
| 73 | #define AR8216_ATU_OP_NOOP 0x0 |
| 74 | #define AR8216_ATU_OP_FLUSH 0x1 |
| 75 | #define AR8216_ATU_OP_LOAD 0x2 |
| 76 | #define AR8216_ATU_OP_PURGE 0x3 |
| 77 | #define AR8216_ATU_OP_FLUSH_LOCKED 0x4 |
| 78 | #define AR8216_ATU_OP_FLUSH_UNICAST 0x5 |
| 79 | #define AR8216_ATU_OP_GET_NEXT 0x6 |
| 80 | #define AR8216_ATU_ACTIVE BIT(3) |
| 81 | #define AR8216_ATU_PORT_NUM BITS(8, 4) |
| 82 | #define AR8216_ATU_FULL_VIO BIT(12) |
| 83 | #define AR8216_ATU_ADDR4 BITS(16, 8) |
| 84 | #define AR8216_ATU_ADDR5 BITS(24, 8) |
| 85 | |
| 86 | #define AR8216_REG_ATU_DATA 0x0054 |
| 87 | #define AR8216_ATU_ADDR3 BITS(0, 8) |
| 88 | #define AR8216_ATU_ADDR2 BITS(8, 8) |
| 89 | #define AR8216_ATU_ADDR1 BITS(16, 8) |
| 90 | #define AR8216_ATU_ADDR0 BITS(24, 8) |
| 91 | |
| 92 | #define AR8216_REG_ATU_CTRL 0x005C |
| 93 | #define AR8216_ATU_CTRL_AGE_EN BIT(17) |
| 94 | #define AR8216_ATU_CTRL_AGE_TIME BITS(0, 16) |
| 95 | #define AR8216_ATU_CTRL_AGE_TIME_S 0 |
| 96 | |
| 97 | #define AR8216_PORT_OFFSET(_i) (0x0100 * (_i + 1)) |
| 98 | #define AR8216_REG_PORT_STATUS(_i) (AR8216_PORT_OFFSET(_i) + 0x0000) |
| 99 | #define AR8216_PORT_STATUS_SPEED BITS(0,2) |
| 100 | #define AR8216_PORT_STATUS_SPEED_S 0 |
| 101 | #define AR8216_PORT_STATUS_TXMAC BIT(2) |
| 102 | #define AR8216_PORT_STATUS_RXMAC BIT(3) |
| 103 | #define AR8216_PORT_STATUS_TXFLOW BIT(4) |
| 104 | #define AR8216_PORT_STATUS_RXFLOW BIT(5) |
| 105 | #define AR8216_PORT_STATUS_DUPLEX BIT(6) |
| 106 | #define AR8216_PORT_STATUS_LINK_UP BIT(8) |
| 107 | #define AR8216_PORT_STATUS_LINK_AUTO BIT(9) |
| 108 | #define AR8216_PORT_STATUS_LINK_PAUSE BIT(10) |
| 109 | |
| 110 | #define AR8216_REG_PORT_CTRL(_i) (AR8216_PORT_OFFSET(_i) + 0x0004) |
| 111 | |
| 112 | /* port forwarding state */ |
| 113 | #define AR8216_PORT_CTRL_STATE BITS(0, 3) |
| 114 | #define AR8216_PORT_CTRL_STATE_S 0 |
| 115 | |
| 116 | #define AR8216_PORT_CTRL_LEARN_LOCK BIT(7) |
| 117 | |
| 118 | /* egress 802.1q mode */ |
| 119 | #define AR8216_PORT_CTRL_VLAN_MODE BITS(8, 2) |
| 120 | #define AR8216_PORT_CTRL_VLAN_MODE_S 8 |
| 121 | |
| 122 | #define AR8216_PORT_CTRL_IGMP_SNOOP BIT(10) |
| 123 | #define AR8216_PORT_CTRL_HEADER BIT(11) |
| 124 | #define AR8216_PORT_CTRL_MAC_LOOP BIT(12) |
| 125 | #define AR8216_PORT_CTRL_SINGLE_VLAN BIT(13) |
| 126 | #define AR8216_PORT_CTRL_LEARN BIT(14) |
| 127 | #define AR8216_PORT_CTRL_MIRROR_TX BIT(16) |
| 128 | #define AR8216_PORT_CTRL_MIRROR_RX BIT(17) |
| 129 | |
| 130 | #define AR8216_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET(_i) + 0x0008) |
| 131 | |
| 132 | #define AR8216_PORT_VLAN_DEFAULT_ID BITS(0, 12) |
| 133 | #define AR8216_PORT_VLAN_DEFAULT_ID_S 0 |
| 134 | |
| 135 | #define AR8216_PORT_VLAN_DEST_PORTS BITS(16, 9) |
| 136 | #define AR8216_PORT_VLAN_DEST_PORTS_S 16 |
| 137 | |
| 138 | /* bit0 added to the priority field of egress frames */ |
| 139 | #define AR8216_PORT_VLAN_TX_PRIO BIT(27) |
| 140 | |
| 141 | /* port default priority */ |
| 142 | #define AR8216_PORT_VLAN_PRIORITY BITS(28, 2) |
| 143 | #define AR8216_PORT_VLAN_PRIORITY_S 28 |
| 144 | |
| 145 | /* ingress 802.1q mode */ |
| 146 | #define AR8216_PORT_VLAN_MODE BITS(30, 2) |
| 147 | #define AR8216_PORT_VLAN_MODE_S 30 |
| 148 | |
| 149 | #define AR8216_REG_PORT_RATE(_i) (AR8216_PORT_OFFSET(_i) + 0x000c) |
| 150 | #define AR8216_REG_PORT_PRIO(_i) (AR8216_PORT_OFFSET(_i) + 0x0010) |
| 151 | |
| 152 | |
| 153 | #define AR8236_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET((_i)) + 0x0008) |
| 154 | #define AR8236_PORT_VLAN_DEFAULT_ID BITS(16, 12) |
| 155 | #define AR8236_PORT_VLAN_DEFAULT_ID_S 16 |
| 156 | #define AR8236_PORT_VLAN_PRIORITY BITS(29, 3) |
| 157 | #define AR8236_PORT_VLAN_PRIORITY_S 28 |
| 158 | |
| 159 | #define AR8236_REG_PORT_VLAN2(_i) (AR8216_PORT_OFFSET((_i)) + 0x000c) |
| 160 | #define AR8236_PORT_VLAN2_MEMBER BITS(16, 7) |
| 161 | #define AR8236_PORT_VLAN2_MEMBER_S 16 |
| 162 | #define AR8236_PORT_VLAN2_TX_PRIO BIT(23) |
| 163 | #define AR8236_PORT_VLAN2_VLAN_MODE BITS(30, 2) |
| 164 | #define AR8236_PORT_VLAN2_VLAN_MODE_S 30 |
| 165 | |
| 166 | #define AR8327_NUM_PORTS 7 |
| 167 | #define AR8327_NUM_PHYS 5 |
| 168 | #define AR8327_PORTS_ALL 0x7f |
| 169 | |
| 170 | #define AR8327_REG_MASK 0x000 |
| 171 | |
| 172 | #define AR8327_REG_PAD0_MODE 0x004 |
| 173 | #define AR8327_REG_PAD5_MODE 0x008 |
| 174 | #define AR8327_REG_PAD6_MODE 0x00c |
| 175 | #define AR8327_PAD_MAC_MII_RXCLK_SEL BIT(0) |
| 176 | #define AR8327_PAD_MAC_MII_TXCLK_SEL BIT(1) |
| 177 | #define AR8327_PAD_MAC_MII_EN BIT(2) |
| 178 | #define AR8327_PAD_MAC_GMII_RXCLK_SEL BIT(4) |
| 179 | #define AR8327_PAD_MAC_GMII_TXCLK_SEL BIT(5) |
| 180 | #define AR8327_PAD_MAC_GMII_EN BIT(6) |
| 181 | #define AR8327_PAD_SGMII_EN BIT(7) |
| 182 | #define AR8327_PAD_PHY_MII_RXCLK_SEL BIT(8) |
| 183 | #define AR8327_PAD_PHY_MII_TXCLK_SEL BIT(9) |
| 184 | #define AR8327_PAD_PHY_MII_EN BIT(10) |
| 185 | #define AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL BIT(11) |
| 186 | #define AR8327_PAD_PHY_GMII_RXCLK_SEL BIT(12) |
| 187 | #define AR8327_PAD_PHY_GMII_TXCLK_SEL BIT(13) |
| 188 | #define AR8327_PAD_PHY_GMII_EN BIT(14) |
| 189 | #define AR8327_PAD_PHYX_GMII_EN BIT(16) |
| 190 | #define AR8327_PAD_PHYX_RGMII_EN BIT(17) |
| 191 | #define AR8327_PAD_PHYX_MII_EN BIT(18) |
| 192 | #define AR8327_PAD_RGMII_RXCLK_DELAY_SEL BITS(20, 2) |
| 193 | #define AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S 20 |
| 194 | #define AR8327_PAD_RGMII_TXCLK_DELAY_SEL BITS(22, 2) |
| 195 | #define AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S 22 |
| 196 | #define AR8327_PAD_RGMII_RXCLK_DELAY_EN BIT(24) |
| 197 | #define AR8327_PAD_RGMII_TXCLK_DELAY_EN BIT(25) |
| 198 | #define AR8327_PAD_RGMII_EN BIT(26) |
| 199 | |
| 200 | #define AR8327_REG_POWER_ON_STRIP 0x010 |
| 201 | #define AR8327_POWER_ON_STRIP_POWER_ON_SEL BIT(31) |
| 202 | #define AR8327_POWER_ON_STRIP_LED_OPEN_EN BIT(24) |
| 203 | |
| 204 | #define AR8327_REG_INT_STATUS0 0x020 |
| 205 | #define AR8327_INT0_VT_DONE BIT(20) |
| 206 | |
| 207 | #define AR8327_REG_INT_STATUS1 0x024 |
| 208 | #define AR8327_REG_INT_MASK0 0x028 |
| 209 | #define AR8327_REG_INT_MASK1 0x02c |
| 210 | #define AR8327_REG_SERVICE_TAG 0x048 |
| 211 | #define AR8327_REG_LED_CTRL0 0x050 |
| 212 | #define AR8327_REG_LED_CTRL1 0x054 |
| 213 | #define AR8327_REG_LED_CTRL2 0x058 |
| 214 | #define AR8327_REG_LED_CTRL3 0x05c |
| 215 | #define AR8327_REG_MAC_ADDR0 0x060 |
| 216 | #define AR8327_REG_MAC_ADDR1 0x064 |
| 217 | |
| 218 | #define AR8327_REG_MAX_FRAME_SIZE 0x078 |
| 219 | #define AR8327_MAX_FRAME_SIZE_MTU BITS(0, 14) |
| 220 | |
| 221 | #define AR8327_REG_PORT_STATUS(_i) (0x07c + (_i) * 4) |
| 222 | |
| 223 | #define AR8327_REG_HEADER_CTRL 0x098 |
| 224 | #define AR8327_REG_PORT_HEADER(_i) (0x09c + (_i) * 4) |
| 225 | |
| 226 | #define AR8327_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8) |
| 227 | #define AR8327_PORT_VLAN0_DEF_SVID BITS(0, 12) |
| 228 | #define AR8327_PORT_VLAN0_DEF_SVID_S 0 |
| 229 | #define AR8327_PORT_VLAN0_DEF_CVID BITS(16, 12) |
| 230 | #define AR8327_PORT_VLAN0_DEF_CVID_S 16 |
| 231 | |
| 232 | #define AR8327_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8) |
| 233 | #define AR8327_PORT_VLAN1_PORT_VLAN_PROP BIT(6) |
| 234 | #define AR8327_PORT_VLAN1_OUT_MODE BITS(12, 2) |
| 235 | #define AR8327_PORT_VLAN1_OUT_MODE_S 12 |
| 236 | #define AR8327_PORT_VLAN1_OUT_MODE_UNMOD 0 |
| 237 | #define AR8327_PORT_VLAN1_OUT_MODE_UNTAG 1 |
| 238 | #define AR8327_PORT_VLAN1_OUT_MODE_TAG 2 |
| 239 | #define AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH 3 |
| 240 | |
| 241 | #define AR8327_REG_ATU_DATA0 0x600 |
| 242 | #define AR8327_REG_ATU_DATA1 0x604 |
| 243 | #define AR8327_REG_ATU_DATA2 0x608 |
| 244 | |
| 245 | #define AR8327_REG_ATU_FUNC 0x60c |
| 246 | #define AR8327_ATU_FUNC_OP BITS(0, 4) |
| 247 | #define AR8327_ATU_FUNC_OP_NOOP 0x0 |
| 248 | #define AR8327_ATU_FUNC_OP_FLUSH 0x1 |
| 249 | #define AR8327_ATU_FUNC_OP_LOAD 0x2 |
| 250 | #define AR8327_ATU_FUNC_OP_PURGE 0x3 |
| 251 | #define AR8327_ATU_FUNC_OP_FLUSH_LOCKED 0x4 |
| 252 | #define AR8327_ATU_FUNC_OP_FLUSH_UNICAST 0x5 |
| 253 | #define AR8327_ATU_FUNC_OP_GET_NEXT 0x6 |
| 254 | #define AR8327_ATU_FUNC_OP_SEARCH_MAC 0x7 |
| 255 | #define AR8327_ATU_FUNC_OP_CHANGE_TRUNK 0x8 |
| 256 | #define AR8327_ATU_FUNC_BUSY BIT(31) |
| 257 | |
| 258 | #define AR8327_REG_VTU_FUNC0 0x0610 |
| 259 | #define AR8327_VTU_FUNC0_EG_MODE BITS(4, 14) |
| 260 | #define AR8327_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2) |
| 261 | #define AR8327_VTU_FUNC0_EG_MODE_KEEP 0 |
| 262 | #define AR8327_VTU_FUNC0_EG_MODE_UNTAG 1 |
| 263 | #define AR8327_VTU_FUNC0_EG_MODE_TAG 2 |
| 264 | #define AR8327_VTU_FUNC0_EG_MODE_NOT 3 |
| 265 | #define AR8327_VTU_FUNC0_IVL BIT(19) |
| 266 | #define AR8327_VTU_FUNC0_VALID BIT(20) |
| 267 | |
| 268 | #define AR8327_REG_VTU_FUNC1 0x0614 |
| 269 | #define AR8327_VTU_FUNC1_OP BITS(0, 3) |
| 270 | #define AR8327_VTU_FUNC1_OP_NOOP 0 |
| 271 | #define AR8327_VTU_FUNC1_OP_FLUSH 1 |
| 272 | #define AR8327_VTU_FUNC1_OP_LOAD 2 |
| 273 | #define AR8327_VTU_FUNC1_OP_PURGE 3 |
| 274 | #define AR8327_VTU_FUNC1_OP_REMOVE_PORT 4 |
| 275 | #define AR8327_VTU_FUNC1_OP_GET_NEXT 5 |
| 276 | #define AR8327_VTU_FUNC1_OP_GET_ONE 6 |
| 277 | #define AR8327_VTU_FUNC1_FULL BIT(4) |
| 278 | #define AR8327_VTU_FUNC1_PORT BIT(8, 4) |
| 279 | #define AR8327_VTU_FUNC1_PORT_S 8 |
| 280 | #define AR8327_VTU_FUNC1_VID BIT(16, 12) |
| 281 | #define AR8327_VTU_FUNC1_VID_S 16 |
| 282 | #define AR8327_VTU_FUNC1_BUSY BIT(31) |
| 283 | |
| 284 | #define AR8327_REG_FWD_CTRL0 0x620 |
| 285 | #define AR8327_FWD_CTRL0_CPU_PORT_EN BIT(10) |
| 286 | #define AR8327_FWD_CTRL0_MIRROR_PORT BITS(4, 4) |
| 287 | #define AR8327_FWD_CTRL0_MIRROR_PORT_S 4 |
| 288 | |
| 289 | #define AR8327_REG_FWD_CTRL1 0x624 |
| 290 | #define AR8327_FWD_CTRL1_UC_FLOOD BITS(0, 7) |
| 291 | #define AR8327_FWD_CTRL1_UC_FLOOD_S 0 |
| 292 | #define AR8327_FWD_CTRL1_MC_FLOOD BITS(8, 7) |
| 293 | #define AR8327_FWD_CTRL1_MC_FLOOD_S 8 |
| 294 | #define AR8327_FWD_CTRL1_BC_FLOOD BITS(16, 7) |
| 295 | #define AR8327_FWD_CTRL1_BC_FLOOD_S 16 |
| 296 | #define AR8327_FWD_CTRL1_IGMP BITS(24, 7) |
| 297 | #define AR8327_FWD_CTRL1_IGMP_S 24 |
| 298 | |
| 299 | #define AR8327_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc) |
| 300 | #define AR8327_PORT_LOOKUP_MEMBER BITS(0, 7) |
| 301 | #define AR8327_PORT_LOOKUP_IN_MODE BITS(8, 2) |
| 302 | #define AR8327_PORT_LOOKUP_IN_MODE_S 8 |
| 303 | #define AR8327_PORT_LOOKUP_STATE BITS(16, 3) |
| 304 | #define AR8327_PORT_LOOKUP_STATE_S 16 |
| 305 | #define AR8327_PORT_LOOKUP_LEARN BIT(20) |
| 306 | |
| 307 | #define AR8327_REG_PORT_PRIO(_i) (0x664 + (_i) * 0xc) |
| 308 | |
| 309 | /* port speed */ |
| 310 | enum { |
| 311 | AR8216_PORT_SPEED_10M = 0, |
| 312 | AR8216_PORT_SPEED_100M = 1, |
| 313 | AR8216_PORT_SPEED_1000M = 2, |
| 314 | AR8216_PORT_SPEED_ERR = 3, |
| 315 | }; |
| 316 | |
| 317 | /* ingress 802.1q mode */ |
| 318 | enum { |
| 319 | AR8216_IN_PORT_ONLY = 0, |
| 320 | AR8216_IN_PORT_FALLBACK = 1, |
| 321 | AR8216_IN_VLAN_ONLY = 2, |
| 322 | AR8216_IN_SECURE = 3 |
| 323 | }; |
| 324 | |
| 325 | /* egress 802.1q mode */ |
| 326 | enum { |
| 327 | AR8216_OUT_KEEP = 0, |
| 328 | AR8216_OUT_STRIP_VLAN = 1, |
| 329 | AR8216_OUT_ADD_VLAN = 2 |
| 330 | }; |
| 331 | |
| 332 | /* port forwarding state */ |
| 333 | enum { |
| 334 | AR8216_PORT_STATE_DISABLED = 0, |
| 335 | AR8216_PORT_STATE_BLOCK = 1, |
| 336 | AR8216_PORT_STATE_LISTEN = 2, |
| 337 | AR8216_PORT_STATE_LEARN = 3, |
| 338 | AR8216_PORT_STATE_FORWARD = 4 |
| 339 | }; |
| 340 | |
| 341 | #endif |
| 342 | |
