Root/target/linux/generic/files/drivers/net/phy/rtl8366s.c

1/*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/delay.h>
17#include <linux/skbuff.h>
18#include <linux/rtl8366.h>
19
20#include "rtl8366_smi.h"
21
22#define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver"
23#define RTL8366S_DRIVER_VER "0.2.2"
24
25#define RTL8366S_PHY_NO_MAX 4
26#define RTL8366S_PHY_PAGE_MAX 7
27#define RTL8366S_PHY_ADDR_MAX 31
28
29/* Switch Global Configuration register */
30#define RTL8366S_SGCR 0x0000
31#define RTL8366S_SGCR_EN_BC_STORM_CTRL BIT(0)
32#define RTL8366S_SGCR_MAX_LENGTH(_x) (_x << 4)
33#define RTL8366S_SGCR_MAX_LENGTH_MASK RTL8366S_SGCR_MAX_LENGTH(0x3)
34#define RTL8366S_SGCR_MAX_LENGTH_1522 RTL8366S_SGCR_MAX_LENGTH(0x0)
35#define RTL8366S_SGCR_MAX_LENGTH_1536 RTL8366S_SGCR_MAX_LENGTH(0x1)
36#define RTL8366S_SGCR_MAX_LENGTH_1552 RTL8366S_SGCR_MAX_LENGTH(0x2)
37#define RTL8366S_SGCR_MAX_LENGTH_16000 RTL8366S_SGCR_MAX_LENGTH(0x3)
38#define RTL8366S_SGCR_EN_VLAN BIT(13)
39
40/* Port Enable Control register */
41#define RTL8366S_PECR 0x0001
42
43/* Switch Security Control registers */
44#define RTL8366S_SSCR0 0x0002
45#define RTL8366S_SSCR1 0x0003
46#define RTL8366S_SSCR2 0x0004
47#define RTL8366S_SSCR2_DROP_UNKNOWN_DA BIT(0)
48
49#define RTL8366S_RESET_CTRL_REG 0x0100
50#define RTL8366S_CHIP_CTRL_RESET_HW 1
51#define RTL8366S_CHIP_CTRL_RESET_SW (1 << 1)
52
53#define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
54#define RTL8366S_CHIP_VERSION_MASK 0xf
55#define RTL8366S_CHIP_ID_REG 0x0105
56#define RTL8366S_CHIP_ID_8366 0x8366
57
58/* PHY registers control */
59#define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
60#define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
61
62#define RTL8366S_PHY_CTRL_READ 1
63#define RTL8366S_PHY_CTRL_WRITE 0
64
65#define RTL8366S_PHY_REG_MASK 0x1f
66#define RTL8366S_PHY_PAGE_OFFSET 5
67#define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
68#define RTL8366S_PHY_NO_OFFSET 9
69#define RTL8366S_PHY_NO_MASK (0x1f << 9)
70
71/* LED control registers */
72#define RTL8366S_LED_BLINKRATE_REG 0x0420
73#define RTL8366S_LED_BLINKRATE_BIT 0
74#define RTL8366S_LED_BLINKRATE_MASK 0x0007
75
76#define RTL8366S_LED_CTRL_REG 0x0421
77#define RTL8366S_LED_0_1_CTRL_REG 0x0422
78#define RTL8366S_LED_2_3_CTRL_REG 0x0423
79
80#define RTL8366S_MIB_COUNT 33
81#define RTL8366S_GLOBAL_MIB_COUNT 1
82#define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
83#define RTL8366S_MIB_COUNTER_BASE 0x1000
84#define RTL8366S_MIB_COUNTER_PORT_OFFSET2 0x0008
85#define RTL8366S_MIB_COUNTER_BASE2 0x1180
86#define RTL8366S_MIB_CTRL_REG 0x11F0
87#define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
88#define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
89#define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
90
91#define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
92#define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
93#define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
94
95
96#define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
97#define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
98        (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
99#define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
100#define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
101
102
103#define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
104#define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
105
106#define RTL8366S_VLAN_TB_CTRL_REG 0x010F
107
108#define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
109#define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
110#define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
111
112#define RTL8366S_VLAN_MC_BASE(_x) (0x0016 + (_x) * 2)
113
114#define RTL8366S_VLAN_MEMBERINGRESS_REG 0x0379
115
116#define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
117#define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
118#define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
119#define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
120#define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
121#define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
122#define RTL8366S_PORT_STATUS_AN_MASK 0x0080
123
124
125#define RTL8366S_PORT_NUM_CPU 5
126#define RTL8366S_NUM_PORTS 6
127#define RTL8366S_NUM_VLANS 16
128#define RTL8366S_NUM_LEDGROUPS 4
129#define RTL8366S_NUM_VIDS 4096
130#define RTL8366S_PRIORITYMAX 7
131#define RTL8366S_FIDMAX 7
132
133
134#define RTL8366S_PORT_1 (1 << 0) /* In userspace port 0 */
135#define RTL8366S_PORT_2 (1 << 1) /* In userspace port 1 */
136#define RTL8366S_PORT_3 (1 << 2) /* In userspace port 2 */
137#define RTL8366S_PORT_4 (1 << 3) /* In userspace port 3 */
138
139#define RTL8366S_PORT_UNKNOWN (1 << 4) /* No known connection */
140#define RTL8366S_PORT_CPU (1 << 5) /* CPU port */
141
142#define RTL8366S_PORT_ALL (RTL8366S_PORT_1 | \
143                     RTL8366S_PORT_2 | \
144                     RTL8366S_PORT_3 | \
145                     RTL8366S_PORT_4 | \
146                     RTL8366S_PORT_UNKNOWN | \
147                     RTL8366S_PORT_CPU)
148
149#define RTL8366S_PORT_ALL_BUT_CPU (RTL8366S_PORT_1 | \
150                     RTL8366S_PORT_2 | \
151                     RTL8366S_PORT_3 | \
152                     RTL8366S_PORT_4 | \
153                     RTL8366S_PORT_UNKNOWN)
154
155#define RTL8366S_PORT_ALL_EXTERNAL (RTL8366S_PORT_1 | \
156                     RTL8366S_PORT_2 | \
157                     RTL8366S_PORT_3 | \
158                     RTL8366S_PORT_4)
159
160#define RTL8366S_PORT_ALL_INTERNAL (RTL8366S_PORT_UNKNOWN | \
161                     RTL8366S_PORT_CPU)
162
163#define RTL8366S_VLAN_VID_MASK 0xfff
164#define RTL8366S_VLAN_PRIORITY_SHIFT 12
165#define RTL8366S_VLAN_PRIORITY_MASK 0x7
166#define RTL8366S_VLAN_MEMBER_MASK 0x3f
167#define RTL8366S_VLAN_UNTAG_SHIFT 6
168#define RTL8366S_VLAN_UNTAG_MASK 0x3f
169#define RTL8366S_VLAN_FID_SHIFT 12
170#define RTL8366S_VLAN_FID_MASK 0x7
171
172static struct rtl8366_mib_counter rtl8366s_mib_counters[] = {
173    { 0, 0, 4, "IfInOctets" },
174    { 0, 4, 4, "EtherStatsOctets" },
175    { 0, 8, 2, "EtherStatsUnderSizePkts" },
176    { 0, 10, 2, "EtherFragments" },
177    { 0, 12, 2, "EtherStatsPkts64Octets" },
178    { 0, 14, 2, "EtherStatsPkts65to127Octets" },
179    { 0, 16, 2, "EtherStatsPkts128to255Octets" },
180    { 0, 18, 2, "EtherStatsPkts256to511Octets" },
181    { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
182    { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
183    { 0, 24, 2, "EtherOversizeStats" },
184    { 0, 26, 2, "EtherStatsJabbers" },
185    { 0, 28, 2, "IfInUcastPkts" },
186    { 0, 30, 2, "EtherStatsMulticastPkts" },
187    { 0, 32, 2, "EtherStatsBroadcastPkts" },
188    { 0, 34, 2, "EtherStatsDropEvents" },
189    { 0, 36, 2, "Dot3StatsFCSErrors" },
190    { 0, 38, 2, "Dot3StatsSymbolErrors" },
191    { 0, 40, 2, "Dot3InPauseFrames" },
192    { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
193    { 0, 44, 4, "IfOutOctets" },
194    { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
195    { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
196    { 0, 52, 2, "Dot3sDeferredTransmissions" },
197    { 0, 54, 2, "Dot3StatsLateCollisions" },
198    { 0, 56, 2, "EtherStatsCollisions" },
199    { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
200    { 0, 60, 2, "Dot3OutPauseFrames" },
201    { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
202
203    /*
204     * The following counters are accessible at a different
205     * base address.
206     */
207    { 1, 0, 2, "Dot1dTpPortInDiscards" },
208    { 1, 2, 2, "IfOutUcastPkts" },
209    { 1, 4, 2, "IfOutMulticastPkts" },
210    { 1, 6, 2, "IfOutBroadcastPkts" },
211};
212
213#define REG_WR(_smi, _reg, _val) \
214    do { \
215        err = rtl8366_smi_write_reg(_smi, _reg, _val); \
216        if (err) \
217            return err; \
218    } while (0)
219
220#define REG_RMW(_smi, _reg, _mask, _val) \
221    do { \
222        err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
223        if (err) \
224            return err; \
225    } while (0)
226
227static int rtl8366s_reset_chip(struct rtl8366_smi *smi)
228{
229    int timeout = 10;
230    u32 data;
231
232    rtl8366_smi_write_reg_noack(smi, RTL8366S_RESET_CTRL_REG,
233                    RTL8366S_CHIP_CTRL_RESET_HW);
234    do {
235        msleep(1);
236        if (rtl8366_smi_read_reg(smi, RTL8366S_RESET_CTRL_REG, &data))
237            return -EIO;
238
239        if (!(data & RTL8366S_CHIP_CTRL_RESET_HW))
240            break;
241    } while (--timeout);
242
243    if (!timeout) {
244        printk("Timeout waiting for the switch to reset\n");
245        return -EIO;
246    }
247
248    return 0;
249}
250
251static int rtl8366s_setup(struct rtl8366_smi *smi)
252{
253    struct rtl8366_platform_data *pdata;
254    int err;
255
256    pdata = smi->parent->platform_data;
257    if (pdata->num_initvals && pdata->initvals) {
258        unsigned i;
259
260        dev_info(smi->parent, "applying initvals\n");
261        for (i = 0; i < pdata->num_initvals; i++)
262            REG_WR(smi, pdata->initvals[i].reg,
263                   pdata->initvals[i].val);
264    }
265
266    /* set maximum packet length to 1536 bytes */
267    REG_RMW(smi, RTL8366S_SGCR, RTL8366S_SGCR_MAX_LENGTH_MASK,
268        RTL8366S_SGCR_MAX_LENGTH_1536);
269
270    /* enable learning for all ports */
271    REG_WR(smi, RTL8366S_SSCR0, 0);
272
273    /* enable auto ageing for all ports */
274    REG_WR(smi, RTL8366S_SSCR1, 0);
275
276    /*
277     * discard VLAN tagged packets if the port is not a member of
278     * the VLAN with which the packets is associated.
279     */
280    REG_WR(smi, RTL8366S_VLAN_MEMBERINGRESS_REG, RTL8366S_PORT_ALL);
281
282    /* don't drop packets whose DA has not been learned */
283    REG_RMW(smi, RTL8366S_SSCR2, RTL8366S_SSCR2_DROP_UNKNOWN_DA, 0);
284
285    return 0;
286}
287
288static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,
289                 u32 phy_no, u32 page, u32 addr, u32 *data)
290{
291    u32 reg;
292    int ret;
293
294    if (phy_no > RTL8366S_PHY_NO_MAX)
295        return -EINVAL;
296
297    if (page > RTL8366S_PHY_PAGE_MAX)
298        return -EINVAL;
299
300    if (addr > RTL8366S_PHY_ADDR_MAX)
301        return -EINVAL;
302
303    ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
304                    RTL8366S_PHY_CTRL_READ);
305    if (ret)
306        return ret;
307
308    reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
309          ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
310          (addr & RTL8366S_PHY_REG_MASK);
311
312    ret = rtl8366_smi_write_reg(smi, reg, 0);
313    if (ret)
314        return ret;
315
316    ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
317    if (ret)
318        return ret;
319
320    return 0;
321}
322
323static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,
324                  u32 phy_no, u32 page, u32 addr, u32 data)
325{
326    u32 reg;
327    int ret;
328
329    if (phy_no > RTL8366S_PHY_NO_MAX)
330        return -EINVAL;
331
332    if (page > RTL8366S_PHY_PAGE_MAX)
333        return -EINVAL;
334
335    if (addr > RTL8366S_PHY_ADDR_MAX)
336        return -EINVAL;
337
338    ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
339                    RTL8366S_PHY_CTRL_WRITE);
340    if (ret)
341        return ret;
342
343    reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
344          ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
345          (addr & RTL8366S_PHY_REG_MASK);
346
347    ret = rtl8366_smi_write_reg(smi, reg, data);
348    if (ret)
349        return ret;
350
351    return 0;
352}
353
354static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
355                   int port, unsigned long long *val)
356{
357    int i;
358    int err;
359    u32 addr, data;
360    u64 mibvalue;
361
362    if (port > RTL8366S_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
363        return -EINVAL;
364
365    switch (rtl8366s_mib_counters[counter].base) {
366    case 0:
367        addr = RTL8366S_MIB_COUNTER_BASE +
368               RTL8366S_MIB_COUNTER_PORT_OFFSET * port;
369        break;
370
371    case 1:
372        addr = RTL8366S_MIB_COUNTER_BASE2 +
373            RTL8366S_MIB_COUNTER_PORT_OFFSET2 * port;
374        break;
375
376    default:
377        return -EINVAL;
378    }
379
380    addr += rtl8366s_mib_counters[counter].offset;
381
382    /*
383     * Writing access counter address first
384     * then ASIC will prepare 64bits counter wait for being retrived
385     */
386    data = 0; /* writing data will be discard by ASIC */
387    err = rtl8366_smi_write_reg(smi, addr, data);
388    if (err)
389        return err;
390
391    /* read MIB control register */
392    err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
393    if (err)
394        return err;
395
396    if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
397        return -EBUSY;
398
399    if (data & RTL8366S_MIB_CTRL_RESET_MASK)
400        return -EIO;
401
402    mibvalue = 0;
403    for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
404        err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
405        if (err)
406            return err;
407
408        mibvalue = (mibvalue << 16) | (data & 0xFFFF);
409    }
410
411    *val = mibvalue;
412    return 0;
413}
414
415static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
416                struct rtl8366_vlan_4k *vlan4k)
417{
418    u32 data[2];
419    int err;
420    int i;
421
422    memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
423
424    if (vid >= RTL8366S_NUM_VIDS)
425        return -EINVAL;
426
427    /* write VID */
428    err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE,
429                    vid & RTL8366S_VLAN_VID_MASK);
430    if (err)
431        return err;
432
433    /* write table access control word */
434    err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
435                    RTL8366S_TABLE_VLAN_READ_CTRL);
436    if (err)
437        return err;
438
439    for (i = 0; i < 2; i++) {
440        err = rtl8366_smi_read_reg(smi,
441                       RTL8366S_VLAN_TABLE_READ_BASE + i,
442                       &data[i]);
443        if (err)
444            return err;
445    }
446
447    vlan4k->vid = vid;
448    vlan4k->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) &
449            RTL8366S_VLAN_UNTAG_MASK;
450    vlan4k->member = data[1] & RTL8366S_VLAN_MEMBER_MASK;
451    vlan4k->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) &
452            RTL8366S_VLAN_FID_MASK;
453
454    return 0;
455}
456
457static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi,
458                const struct rtl8366_vlan_4k *vlan4k)
459{
460    u32 data[2];
461    int err;
462    int i;
463
464    if (vlan4k->vid >= RTL8366S_NUM_VIDS ||
465        vlan4k->member > RTL8366S_VLAN_MEMBER_MASK ||
466        vlan4k->untag > RTL8366S_VLAN_UNTAG_MASK ||
467        vlan4k->fid > RTL8366S_FIDMAX)
468        return -EINVAL;
469
470    data[0] = vlan4k->vid & RTL8366S_VLAN_VID_MASK;
471    data[1] = (vlan4k->member & RTL8366S_VLAN_MEMBER_MASK) |
472          ((vlan4k->untag & RTL8366S_VLAN_UNTAG_MASK) <<
473            RTL8366S_VLAN_UNTAG_SHIFT) |
474          ((vlan4k->fid & RTL8366S_VLAN_FID_MASK) <<
475            RTL8366S_VLAN_FID_SHIFT);
476
477    for (i = 0; i < 2; i++) {
478        err = rtl8366_smi_write_reg(smi,
479                        RTL8366S_VLAN_TABLE_WRITE_BASE + i,
480                        data[i]);
481        if (err)
482            return err;
483    }
484
485    /* write table access control word */
486    err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
487                    RTL8366S_TABLE_VLAN_WRITE_CTRL);
488
489    return err;
490}
491
492static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
493                struct rtl8366_vlan_mc *vlanmc)
494{
495    u32 data[2];
496    int err;
497    int i;
498
499    memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
500
501    if (index >= RTL8366S_NUM_VLANS)
502        return -EINVAL;
503
504    for (i = 0; i < 2; i++) {
505        err = rtl8366_smi_read_reg(smi,
506                       RTL8366S_VLAN_MC_BASE(index) + i,
507                       &data[i]);
508        if (err)
509            return err;
510    }
511
512    vlanmc->vid = data[0] & RTL8366S_VLAN_VID_MASK;
513    vlanmc->priority = (data[0] >> RTL8366S_VLAN_PRIORITY_SHIFT) &
514               RTL8366S_VLAN_PRIORITY_MASK;
515    vlanmc->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) &
516            RTL8366S_VLAN_UNTAG_MASK;
517    vlanmc->member = data[1] & RTL8366S_VLAN_MEMBER_MASK;
518    vlanmc->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) &
519              RTL8366S_VLAN_FID_MASK;
520
521    return 0;
522}
523
524static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
525                const struct rtl8366_vlan_mc *vlanmc)
526{
527    u32 data[2];
528    int err;
529    int i;
530
531    if (index >= RTL8366S_NUM_VLANS ||
532        vlanmc->vid >= RTL8366S_NUM_VIDS ||
533        vlanmc->priority > RTL8366S_PRIORITYMAX ||
534        vlanmc->member > RTL8366S_VLAN_MEMBER_MASK ||
535        vlanmc->untag > RTL8366S_VLAN_UNTAG_MASK ||
536        vlanmc->fid > RTL8366S_FIDMAX)
537        return -EINVAL;
538
539    data[0] = (vlanmc->vid & RTL8366S_VLAN_VID_MASK) |
540          ((vlanmc->priority & RTL8366S_VLAN_PRIORITY_MASK) <<
541            RTL8366S_VLAN_PRIORITY_SHIFT);
542    data[1] = (vlanmc->member & RTL8366S_VLAN_MEMBER_MASK) |
543          ((vlanmc->untag & RTL8366S_VLAN_UNTAG_MASK) <<
544            RTL8366S_VLAN_UNTAG_SHIFT) |
545          ((vlanmc->fid & RTL8366S_VLAN_FID_MASK) <<
546            RTL8366S_VLAN_FID_SHIFT);
547
548    for (i = 0; i < 2; i++) {
549        err = rtl8366_smi_write_reg(smi,
550                        RTL8366S_VLAN_MC_BASE(index) + i,
551                        data[i]);
552        if (err)
553            return err;
554    }
555
556    return 0;
557}
558
559static int rtl8366s_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
560{
561    u32 data;
562    int err;
563
564    if (port >= RTL8366S_NUM_PORTS)
565        return -EINVAL;
566
567    err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
568                   &data);
569    if (err)
570        return err;
571
572    *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
573           RTL8366S_PORT_VLAN_CTRL_MASK;
574
575    return 0;
576}
577
578static int rtl8366s_set_mc_index(struct rtl8366_smi *smi, int port, int index)
579{
580    if (port >= RTL8366S_NUM_PORTS || index >= RTL8366S_NUM_VLANS)
581        return -EINVAL;
582
583    return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
584                RTL8366S_PORT_VLAN_CTRL_MASK <<
585                    RTL8366S_PORT_VLAN_CTRL_SHIFT(port),
586                (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
587                    RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
588}
589
590static int rtl8366s_enable_vlan(struct rtl8366_smi *smi, int enable)
591{
592    return rtl8366_smi_rmwr(smi, RTL8366S_SGCR, RTL8366S_SGCR_EN_VLAN,
593                (enable) ? RTL8366S_SGCR_EN_VLAN : 0);
594}
595
596static int rtl8366s_enable_vlan4k(struct rtl8366_smi *smi, int enable)
597{
598    return rtl8366_smi_rmwr(smi, RTL8366S_VLAN_TB_CTRL_REG,
599                1, (enable) ? 1 : 0);
600}
601
602static int rtl8366s_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
603{
604    unsigned max = RTL8366S_NUM_VLANS;
605
606    if (smi->vlan4k_enabled)
607        max = RTL8366S_NUM_VIDS - 1;
608
609    if (vlan == 0 || vlan >= max)
610        return 0;
611
612    return 1;
613}
614
615static int rtl8366s_enable_port(struct rtl8366_smi *smi, int port, int enable)
616{
617    return rtl8366_smi_rmwr(smi, RTL8366S_PECR, (1 << port),
618                (enable) ? 0 : (1 << port));
619}
620
621static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
622                  const struct switch_attr *attr,
623                  struct switch_val *val)
624{
625    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
626
627    return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2));
628}
629
630static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
631                     const struct switch_attr *attr,
632                     struct switch_val *val)
633{
634    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
635    u32 data;
636
637    rtl8366_smi_read_reg(smi, RTL8366S_LED_BLINKRATE_REG, &data);
638
639    val->value.i = (data & (RTL8366S_LED_BLINKRATE_MASK));
640
641    return 0;
642}
643
644static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
645                    const struct switch_attr *attr,
646                    struct switch_val *val)
647{
648    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
649
650    if (val->value.i >= 6)
651        return -EINVAL;
652
653    return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG,
654                RTL8366S_LED_BLINKRATE_MASK,
655                val->value.i);
656}
657
658static int rtl8366s_sw_get_max_length(struct switch_dev *dev,
659                    const struct switch_attr *attr,
660                    struct switch_val *val)
661{
662    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
663    u32 data;
664
665    rtl8366_smi_read_reg(smi, RTL8366S_SGCR, &data);
666
667    val->value.i = ((data & (RTL8366S_SGCR_MAX_LENGTH_MASK)) >> 4);
668
669    return 0;
670}
671
672static int rtl8366s_sw_set_max_length(struct switch_dev *dev,
673                    const struct switch_attr *attr,
674                    struct switch_val *val)
675{
676    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
677    char length_code;
678
679    switch (val->value.i) {
680        case 0:
681            length_code = RTL8366S_SGCR_MAX_LENGTH_1522;
682            break;
683        case 1:
684            length_code = RTL8366S_SGCR_MAX_LENGTH_1536;
685            break;
686        case 2:
687            length_code = RTL8366S_SGCR_MAX_LENGTH_1552;
688            break;
689        case 3:
690            length_code = RTL8366S_SGCR_MAX_LENGTH_16000;
691            break;
692        default:
693            return -EINVAL;
694    }
695
696    return rtl8366_smi_rmwr(smi, RTL8366S_SGCR,
697            RTL8366S_SGCR_MAX_LENGTH_MASK,
698            length_code);
699}
700
701static int rtl8366s_sw_get_learning_enable(struct switch_dev *dev,
702                       const struct switch_attr *attr,
703                       struct switch_val *val)
704{
705    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
706    u32 data;
707
708    rtl8366_smi_read_reg(smi,RTL8366S_SSCR0, &data);
709    val->value.i = !data;
710
711    return 0;
712}
713
714
715static int rtl8366s_sw_set_learning_enable(struct switch_dev *dev,
716                       const struct switch_attr *attr,
717                       struct switch_val *val)
718{
719    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
720    u32 portmask = 0;
721    int err = 0;
722
723    if (!val->value.i)
724        portmask = RTL8366S_PORT_ALL;
725
726    /* set learning for all ports */
727    REG_WR(smi, RTL8366S_SSCR0, portmask);
728
729    /* set auto ageing for all ports */
730    REG_WR(smi, RTL8366S_SSCR1, portmask);
731
732    return 0;
733}
734
735static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
736                     int port,
737                     struct switch_port_link *link)
738{
739    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
740    u32 data = 0;
741    u32 speed;
742
743    if (port >= RTL8366S_NUM_PORTS)
744        return -EINVAL;
745
746    rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE + (port / 2),
747                 &data);
748
749    if (port % 2)
750        data = data >> 8;
751
752    link->link = !!(data & RTL8366S_PORT_STATUS_LINK_MASK);
753    if (!link->link)
754        return 0;
755
756    link->duplex = !!(data & RTL8366S_PORT_STATUS_DUPLEX_MASK);
757    link->rx_flow = !!(data & RTL8366S_PORT_STATUS_RXPAUSE_MASK);
758    link->tx_flow = !!(data & RTL8366S_PORT_STATUS_TXPAUSE_MASK);
759    link->aneg = !!(data & RTL8366S_PORT_STATUS_AN_MASK);
760
761    speed = (data & RTL8366S_PORT_STATUS_SPEED_MASK);
762    switch (speed) {
763    case 0:
764        link->speed = SWITCH_PORT_SPEED_10;
765        break;
766    case 1:
767        link->speed = SWITCH_PORT_SPEED_100;
768        break;
769    case 2:
770        link->speed = SWITCH_PORT_SPEED_1000;
771        break;
772    default:
773        link->speed = SWITCH_PORT_SPEED_UNKNOWN;
774        break;
775    }
776
777    return 0;
778}
779
780static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
781                    const struct switch_attr *attr,
782                    struct switch_val *val)
783{
784    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
785    u32 data;
786    u32 mask;
787    u32 reg;
788
789    if (val->port_vlan >= RTL8366S_NUM_PORTS ||
790        (1 << val->port_vlan) == RTL8366S_PORT_UNKNOWN)
791        return -EINVAL;
792
793    if (val->port_vlan == RTL8366S_PORT_NUM_CPU) {
794        reg = RTL8366S_LED_BLINKRATE_REG;
795        mask = 0xF << 4;
796        data = val->value.i << 4;
797    } else {
798        reg = RTL8366S_LED_CTRL_REG;
799        mask = 0xF << (val->port_vlan * 4),
800        data = val->value.i << (val->port_vlan * 4);
801    }
802
803    return rtl8366_smi_rmwr(smi, reg, mask, data);
804}
805
806static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
807                    const struct switch_attr *attr,
808                    struct switch_val *val)
809{
810    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
811    u32 data = 0;
812
813    if (val->port_vlan >= RTL8366S_NUM_LEDGROUPS)
814        return -EINVAL;
815
816    rtl8366_smi_read_reg(smi, RTL8366S_LED_CTRL_REG, &data);
817    val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
818
819    return 0;
820}
821
822static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
823                       const struct switch_attr *attr,
824                       struct switch_val *val)
825{
826    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
827
828    if (val->port_vlan >= RTL8366S_NUM_PORTS)
829        return -EINVAL;
830
831
832    return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG,
833                0, (1 << (val->port_vlan + 3)));
834}
835
836static struct switch_attr rtl8366s_globals[] = {
837    {
838        .type = SWITCH_TYPE_INT,
839        .name = "enable_learning",
840        .description = "Enable learning, enable aging",
841        .set = rtl8366s_sw_set_learning_enable,
842        .get = rtl8366s_sw_get_learning_enable,
843        .max = 1,
844    }, {
845        .type = SWITCH_TYPE_INT,
846        .name = "enable_vlan",
847        .description = "Enable VLAN mode",
848        .set = rtl8366_sw_set_vlan_enable,
849        .get = rtl8366_sw_get_vlan_enable,
850        .max = 1,
851        .ofs = 1
852    }, {
853        .type = SWITCH_TYPE_INT,
854        .name = "enable_vlan4k",
855        .description = "Enable VLAN 4K mode",
856        .set = rtl8366_sw_set_vlan_enable,
857        .get = rtl8366_sw_get_vlan_enable,
858        .max = 1,
859        .ofs = 2
860    }, {
861        .type = SWITCH_TYPE_NOVAL,
862        .name = "reset_mibs",
863        .description = "Reset all MIB counters",
864        .set = rtl8366s_sw_reset_mibs,
865    }, {
866        .type = SWITCH_TYPE_INT,
867        .name = "blinkrate",
868        .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
869        " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
870        .set = rtl8366s_sw_set_blinkrate,
871        .get = rtl8366s_sw_get_blinkrate,
872        .max = 5
873    }, {
874        .type = SWITCH_TYPE_INT,
875        .name = "max_length",
876        .description = "Get/Set the maximum length of valid packets"
877        " (0 = 1522, 1 = 1536, 2 = 1552, 3 = 16000 (9216?))",
878        .set = rtl8366s_sw_set_max_length,
879        .get = rtl8366s_sw_get_max_length,
880        .max = 3,
881    },
882};
883
884static struct switch_attr rtl8366s_port[] = {
885    {
886        .type = SWITCH_TYPE_NOVAL,
887        .name = "reset_mib",
888        .description = "Reset single port MIB counters",
889        .set = rtl8366s_sw_reset_port_mibs,
890    }, {
891        .type = SWITCH_TYPE_STRING,
892        .name = "mib",
893        .description = "Get MIB counters for port",
894        .max = 33,
895        .set = NULL,
896        .get = rtl8366_sw_get_port_mib,
897    }, {
898        .type = SWITCH_TYPE_INT,
899        .name = "led",
900        .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
901        .max = 15,
902        .set = rtl8366s_sw_set_port_led,
903        .get = rtl8366s_sw_get_port_led,
904    },
905};
906
907static struct switch_attr rtl8366s_vlan[] = {
908    {
909        .type = SWITCH_TYPE_STRING,
910        .name = "info",
911        .description = "Get vlan information",
912        .max = 1,
913        .set = NULL,
914        .get = rtl8366_sw_get_vlan_info,
915    }, {
916        .type = SWITCH_TYPE_INT,
917        .name = "fid",
918        .description = "Get/Set vlan FID",
919        .max = RTL8366S_FIDMAX,
920        .set = rtl8366_sw_set_vlan_fid,
921        .get = rtl8366_sw_get_vlan_fid,
922    },
923};
924
925static const struct switch_dev_ops rtl8366_ops = {
926    .attr_global = {
927        .attr = rtl8366s_globals,
928        .n_attr = ARRAY_SIZE(rtl8366s_globals),
929    },
930    .attr_port = {
931        .attr = rtl8366s_port,
932        .n_attr = ARRAY_SIZE(rtl8366s_port),
933    },
934    .attr_vlan = {
935        .attr = rtl8366s_vlan,
936        .n_attr = ARRAY_SIZE(rtl8366s_vlan),
937    },
938
939    .get_vlan_ports = rtl8366_sw_get_vlan_ports,
940    .set_vlan_ports = rtl8366_sw_set_vlan_ports,
941    .get_port_pvid = rtl8366_sw_get_port_pvid,
942    .set_port_pvid = rtl8366_sw_set_port_pvid,
943    .reset_switch = rtl8366_sw_reset_switch,
944    .get_port_link = rtl8366s_sw_get_port_link,
945};
946
947static int rtl8366s_switch_init(struct rtl8366_smi *smi)
948{
949    struct switch_dev *dev = &smi->sw_dev;
950    int err;
951
952    dev->name = "RTL8366S";
953    dev->cpu_port = RTL8366S_PORT_NUM_CPU;
954    dev->ports = RTL8366S_NUM_PORTS;
955    dev->vlans = RTL8366S_NUM_VIDS;
956    dev->ops = &rtl8366_ops;
957    dev->alias = dev_name(smi->parent);
958
959    err = register_switch(dev, NULL);
960    if (err)
961        dev_err(smi->parent, "switch registration failed\n");
962
963    return err;
964}
965
966static void rtl8366s_switch_cleanup(struct rtl8366_smi *smi)
967{
968    unregister_switch(&smi->sw_dev);
969}
970
971static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
972{
973    struct rtl8366_smi *smi = bus->priv;
974    u32 val = 0;
975    int err;
976
977    err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);
978    if (err)
979        return 0xffff;
980
981    return val;
982}
983
984static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
985{
986    struct rtl8366_smi *smi = bus->priv;
987    u32 t;
988    int err;
989
990    err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);
991    /* flush write */
992    (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);
993
994    return err;
995}
996
997static int rtl8366s_detect(struct rtl8366_smi *smi)
998{
999    u32 chip_id = 0;
1000    u32 chip_ver = 0;
1001    int ret;
1002
1003    ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1004    if (ret) {
1005        dev_err(smi->parent, "unable to read chip id\n");
1006        return ret;
1007    }
1008
1009    switch (chip_id) {
1010    case RTL8366S_CHIP_ID_8366:
1011        break;
1012    default:
1013        dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1014        return -ENODEV;
1015    }
1016
1017    ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1018                   &chip_ver);
1019    if (ret) {
1020        dev_err(smi->parent, "unable to read chip version\n");
1021        return ret;
1022    }
1023
1024    dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1025         chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1026
1027    return 0;
1028}
1029
1030static struct rtl8366_smi_ops rtl8366s_smi_ops = {
1031    .detect = rtl8366s_detect,
1032    .reset_chip = rtl8366s_reset_chip,
1033    .setup = rtl8366s_setup,
1034
1035    .mii_read = rtl8366s_mii_read,
1036    .mii_write = rtl8366s_mii_write,
1037
1038    .get_vlan_mc = rtl8366s_get_vlan_mc,
1039    .set_vlan_mc = rtl8366s_set_vlan_mc,
1040    .get_vlan_4k = rtl8366s_get_vlan_4k,
1041    .set_vlan_4k = rtl8366s_set_vlan_4k,
1042    .get_mc_index = rtl8366s_get_mc_index,
1043    .set_mc_index = rtl8366s_set_mc_index,
1044    .get_mib_counter = rtl8366_get_mib_counter,
1045    .is_vlan_valid = rtl8366s_is_vlan_valid,
1046    .enable_vlan = rtl8366s_enable_vlan,
1047    .enable_vlan4k = rtl8366s_enable_vlan4k,
1048    .enable_port = rtl8366s_enable_port,
1049};
1050
1051static int __devinit rtl8366s_probe(struct platform_device *pdev)
1052{
1053    static int rtl8366_smi_version_printed;
1054    struct rtl8366_platform_data *pdata;
1055    struct rtl8366_smi *smi;
1056    int err;
1057
1058    if (!rtl8366_smi_version_printed++)
1059        printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1060               " version " RTL8366S_DRIVER_VER"\n");
1061
1062    pdata = pdev->dev.platform_data;
1063    if (!pdata) {
1064        dev_err(&pdev->dev, "no platform data specified\n");
1065        err = -EINVAL;
1066        goto err_out;
1067    }
1068
1069    smi = rtl8366_smi_alloc(&pdev->dev);
1070    if (!smi) {
1071        err = -ENOMEM;
1072        goto err_out;
1073    }
1074
1075    smi->gpio_sda = pdata->gpio_sda;
1076    smi->gpio_sck = pdata->gpio_sck;
1077    smi->hw_reset = pdata->hw_reset;
1078
1079    smi->clk_delay = 10;
1080    smi->cmd_read = 0xa9;
1081    smi->cmd_write = 0xa8;
1082    smi->ops = &rtl8366s_smi_ops;
1083    smi->cpu_port = RTL8366S_PORT_NUM_CPU;
1084    smi->num_ports = RTL8366S_NUM_PORTS;
1085    smi->num_vlan_mc = RTL8366S_NUM_VLANS;
1086    smi->mib_counters = rtl8366s_mib_counters;
1087    smi->num_mib_counters = ARRAY_SIZE(rtl8366s_mib_counters);
1088
1089    err = rtl8366_smi_init(smi);
1090    if (err)
1091        goto err_free_smi;
1092
1093    platform_set_drvdata(pdev, smi);
1094
1095    err = rtl8366s_switch_init(smi);
1096    if (err)
1097        goto err_clear_drvdata;
1098
1099    return 0;
1100
1101 err_clear_drvdata:
1102    platform_set_drvdata(pdev, NULL);
1103    rtl8366_smi_cleanup(smi);
1104 err_free_smi:
1105    kfree(smi);
1106 err_out:
1107    return err;
1108}
1109
1110static int __devexit rtl8366s_remove(struct platform_device *pdev)
1111{
1112    struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1113
1114    if (smi) {
1115        rtl8366s_switch_cleanup(smi);
1116        platform_set_drvdata(pdev, NULL);
1117        rtl8366_smi_cleanup(smi);
1118        kfree(smi);
1119    }
1120
1121    return 0;
1122}
1123
1124static struct platform_driver rtl8366s_driver = {
1125    .driver = {
1126        .name = RTL8366S_DRIVER_NAME,
1127        .owner = THIS_MODULE,
1128    },
1129    .probe = rtl8366s_probe,
1130    .remove = __devexit_p(rtl8366s_remove),
1131};
1132
1133static int __init rtl8366s_module_init(void)
1134{
1135    return platform_driver_register(&rtl8366s_driver);
1136}
1137module_init(rtl8366s_module_init);
1138
1139static void __exit rtl8366s_module_exit(void)
1140{
1141    platform_driver_unregister(&rtl8366s_driver);
1142}
1143module_exit(rtl8366s_module_exit);
1144
1145MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1146MODULE_VERSION(RTL8366S_DRIVER_VER);
1147MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1148MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1149MODULE_LICENSE("GPL v2");
1150MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);
1151

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