OpenWrt XBurst

OpenWrt XBurst Git Source Tree

Root/target/linux/generic/patches-3.3/025-bcma_backport.patch

1	--- a/drivers/bcma/Kconfig
2	+++ b/drivers/bcma/Kconfig
3	@@ -29,7 +29,7 @@ config BCMA_HOST_PCI
4
5	config BCMA_DRIVER_PCI_HOSTMODE
6	bool "Driver for PCI core working in hostmode"
7	- depends on BCMA && MIPS
8	+ depends on BCMA && MIPS && BCMA_HOST_PCI
9	help
10	PCI core hostmode operation (external PCI bus).
11
12	@@ -46,6 +46,15 @@ config BCMA_DRIVER_MIPS
13
14	If unsure, say N
15
16	+config BCMA_DRIVER_GMAC_CMN
17	+ bool "BCMA Broadcom GBIT MAC COMMON core driver"
18	+ depends on BCMA
19	+ help
20	+ Driver for the Broadcom GBIT MAC COMMON core attached to Broadcom
21	+ specific Advanced Microcontroller Bus.
22	+
23	+ If unsure, say N
24	+
25	config BCMA_DEBUG
26	bool "BCMA debugging"
27	depends on BCMA
28	--- a/drivers/bcma/Makefile
29	+++ b/drivers/bcma/Makefile
30	@@ -3,6 +3,7 @@ bcma-y += driver_chipcommon.o driver
31	bcma-y += driver_pci.o
32	bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
33	bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
34	+bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
35	bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o
36	bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o
37	obj-$(CONFIG_BCMA) += bcma.o
38	--- a/drivers/bcma/bcma_private.h
39	+++ b/drivers/bcma/bcma_private.h
40	@@ -10,10 +10,19 @@
41
42	#define BCMA_CORE_SIZE 0x1000
43
44	+#define bcma_err(bus, fmt, ...) \
45	+ pr_err("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
46	+#define bcma_warn(bus, fmt, ...) \
47	+ pr_warn("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
48	+#define bcma_info(bus, fmt, ...) \
49	+ pr_info("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
50	+#define bcma_debug(bus, fmt, ...) \
51	+ pr_debug("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
52	+
53	struct bcma_bus;
54
55	/* main.c */
56	-int bcma_bus_register(struct bcma_bus *bus);
57	+int __devinit bcma_bus_register(struct bcma_bus *bus);
58	void bcma_bus_unregister(struct bcma_bus *bus);
59	int __init bcma_bus_early_register(struct bcma_bus *bus,
60	struct bcma_device *core_cc,
61	@@ -48,8 +57,12 @@ extern int __init bcma_host_pci_init(voi
62	extern void __exit bcma_host_pci_exit(void);
63	#endif /* CONFIG_BCMA_HOST_PCI */
64
65	+/* driver_pci.c */
66	+u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
67	+
68	#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
69	-void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
70	+bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
71	+void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
72	#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
73
74	#endif
75	--- a/drivers/bcma/core.c
76	+++ b/drivers/bcma/core.c
77	@@ -30,6 +30,7 @@ void bcma_core_disable(struct bcma_devic
78	udelay(10);
79
80	bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
81	+ bcma_aread32(core, BCMA_RESET_CTL);
82	udelay(1);
83	}
84	EXPORT_SYMBOL_GPL(bcma_core_disable);
85	@@ -74,10 +75,10 @@ void bcma_core_set_clockmode(struct bcma
86	udelay(10);
87	}
88	if (i)
89	- pr_err("HT force timeout\n");
90	+ bcma_err(core->bus, "HT force timeout\n");
91	break;
92	case BCMA_CLKMODE_DYNAMIC:
93	- pr_warn("Dynamic clockmode not supported yet!\n");
94	+ bcma_set32(core, BCMA_CLKCTLST, ~BCMA_CLKCTLST_FORCEHT);
95	break;
96	}
97	}
98	@@ -101,9 +102,9 @@ void bcma_core_pll_ctl(struct bcma_devic
99	udelay(10);
100	}
101	if (i)
102	- pr_err("PLL enable timeout\n");
103	+ bcma_err(core->bus, "PLL enable timeout\n");
104	} else {
105	- pr_warn("Disabling PLL not supported yet!\n");
106	+ bcma_warn(core->bus, "Disabling PLL not supported yet!\n");
107	}
108	}
109	EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);
110	@@ -119,8 +120,8 @@ u32 bcma_core_dma_translation(struct bcm
111	else
112	return BCMA_DMA_TRANSLATION_DMA32_CMT;
113	default:
114	- pr_err("DMA translation unknown for host %d\n",
115	- core->bus->hosttype);
116	+ bcma_err(core->bus, "DMA translation unknown for host %d\n",
117	+ core->bus->hosttype);
118	}
119	return BCMA_DMA_TRANSLATION_NONE;
120	}
121	--- a/drivers/bcma/driver_chipcommon.c
122	+++ b/drivers/bcma/driver_chipcommon.c
123	@@ -44,7 +44,7 @@ void bcma_core_chipcommon_init(struct bc
124	if (cc->capabilities & BCMA_CC_CAP_PMU)
125	bcma_pmu_init(cc);
126	if (cc->capabilities & BCMA_CC_CAP_PCTL)
127	- pr_err("Power control not implemented!\n");
128	+ bcma_err(cc->core->bus, "Power control not implemented!\n");
129
130	if (cc->core->id.rev >= 16) {
131	if (cc->core->bus->sprom.leddc_on_time &&
132	@@ -137,8 +137,7 @@ void bcma_chipco_serial_init(struct bcma
133	\| BCMA_CC_CORECTL_UARTCLKEN);
134	}
135	} else {
136	- pr_err("serial not supported on this device ccrev: 0x%x\n",
137	- ccrev);
138	+ bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n", ccrev);
139	return;
140	}
141
142	--- a/drivers/bcma/driver_chipcommon_pmu.c
143	+++ b/drivers/bcma/driver_chipcommon_pmu.c
144	@@ -3,7 +3,8 @@
145	* ChipCommon Power Management Unit driver
146	*
147	* Copyright 2009, Michael Buesch <m@bues.ch>
148	- * Copyright 2007, Broadcom Corporation
149	+ * Copyright 2007, 2011, Broadcom Corporation
150	+ * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
151	*
152	* Licensed under the GNU/GPL. See COPYING for details.
153	*/
154	@@ -54,38 +55,19 @@ void bcma_chipco_regctl_maskset(struct b
155	}
156	EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
157
158	-static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
159	-{
160	- struct bcma_bus *bus = cc->core->bus;
161	-
162	- switch (bus->chipinfo.id) {
163	- case 0x4313:
164	- case 0x4331:
165	- case 43224:
166	- case 43225:
167	- break;
168	- default:
169	- pr_err("PLL init unknown for device 0x%04X\n",
170	- bus->chipinfo.id);
171	- }
172	-}
173	-
174	static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
175	{
176	struct bcma_bus *bus = cc->core->bus;
177	u32 min_msk = 0, max_msk = 0;
178
179	switch (bus->chipinfo.id) {
180	- case 0x4313:
181	+ case BCMA_CHIP_ID_BCM4313:
182	min_msk = 0x200D;
183	max_msk = 0xFFFF;
184	break;
185	- case 43224:
186	- case 43225:
187	- break;
188	default:
189	- pr_err("PMU resource config unknown for device 0x%04X\n",
190	- bus->chipinfo.id);
191	+ bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
192	+ bus->chipinfo.id);
193	}
194
195	/* Set the resource masks. */
196	@@ -93,22 +75,9 @@ static void bcma_pmu_resources_init(stru
197	bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
198	if (max_msk)
199	bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
200	-}
201	-
202	-void bcma_pmu_swreg_init(struct bcma_drv_cc *cc)
203	-{
204	- struct bcma_bus *bus = cc->core->bus;
205
206	- switch (bus->chipinfo.id) {
207	- case 0x4313:
208	- case 0x4331:
209	- case 43224:
210	- case 43225:
211	- break;
212	- default:
213	- pr_err("PMU switch/regulators init unknown for device "
214	- "0x%04X\n", bus->chipinfo.id);
215	- }
216	+ /* Add some delay; allow resources to come up and settle. */
217	+ mdelay(2);
218	}
219
220	/* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
221	@@ -122,8 +91,11 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
222	val \|= BCMA_CHIPCTL_4331_EXTPA_EN;
223	if (bus->chipinfo.pkg == 9 \|\| bus->chipinfo.pkg == 11)
224	val \|= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
225	+ else if (bus->chipinfo.rev > 0)
226	+ val \|= BCMA_CHIPCTL_4331_EXTPA_EN2;
227	} else {
228	val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
229	+ val &= ~BCMA_CHIPCTL_4331_EXTPA_EN2;
230	val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
231	}
232	bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
233	@@ -134,26 +106,38 @@ void bcma_pmu_workarounds(struct bcma_dr
234	struct bcma_bus *bus = cc->core->bus;
235
236	switch (bus->chipinfo.id) {
237	- case 0x4313:
238	- bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x7);
239	+ case BCMA_CHIP_ID_BCM4313:
240	+ /* enable 12 mA drive strenth for 4313 and set chipControl
241	+ register bit 1 */
242	+ bcma_chipco_chipctl_maskset(cc, 0,
243	+ BCMA_CCTRL_4313_12MA_LED_DRIVE,
244	+ BCMA_CCTRL_4313_12MA_LED_DRIVE);
245	break;
246	- case 0x4331:
247	- /* BCM4331 workaround is SPROM-related, we put it in sprom.c */
248	+ case BCMA_CHIP_ID_BCM4331:
249	+ case BCMA_CHIP_ID_BCM43431:
250	+ /* Ext PA lines must be enabled for tx on BCM4331 */
251	+ bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true);
252	break;
253	- case 43224:
254	+ case BCMA_CHIP_ID_BCM43224:
255	+ case BCMA_CHIP_ID_BCM43421:
256	+ /* enable 12 mA drive strenth for 43224 and set chipControl
257	+ register bit 15 */
258	if (bus->chipinfo.rev == 0) {
259	- pr_err("Workarounds for 43224 rev 0 not fully "
260	- "implemented\n");
261	- bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x00F000F0);
262	+ bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL,
263	+ BCMA_CCTRL_43224_GPIO_TOGGLE,
264	+ BCMA_CCTRL_43224_GPIO_TOGGLE);
265	+ bcma_chipco_chipctl_maskset(cc, 0,
266	+ BCMA_CCTRL_43224A0_12MA_LED_DRIVE,
267	+ BCMA_CCTRL_43224A0_12MA_LED_DRIVE);
268	} else {
269	- bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0);
270	+ bcma_chipco_chipctl_maskset(cc, 0,
271	+ BCMA_CCTRL_43224B0_12MA_LED_DRIVE,
272	+ BCMA_CCTRL_43224B0_12MA_LED_DRIVE);
273	}
274	break;
275	- case 43225:
276	- break;
277	default:
278	- pr_err("Workarounds unknown for device 0x%04X\n",
279	- bus->chipinfo.id);
280	+ bcma_debug(bus, "Workarounds unknown or not needed for device 0x%04X\n",
281	+ bus->chipinfo.id);
282	}
283	}
284
285	@@ -164,8 +148,8 @@ void bcma_pmu_init(struct bcma_drv_cc *c
286	pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
287	cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
288
289	- pr_debug("Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
290	- pmucap);
291	+ bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
292	+ cc->pmu.rev, pmucap);
293
294	if (cc->pmu.rev == 1)
295	bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
296	@@ -174,12 +158,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c
297	bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
298	BCMA_CC_PMU_CTL_NOILPONW);
299
300	- if (cc->core->id.id == 0x4329 && cc->core->id.rev == 2)
301	- pr_err("Fix for 4329b0 bad LPOM state not implemented!\n");
302	-
303	- bcma_pmu_pll_init(cc);
304	bcma_pmu_resources_init(cc);
305	- bcma_pmu_swreg_init(cc);
306	bcma_pmu_workarounds(cc);
307	}
308
309	@@ -188,23 +167,22 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
310	struct bcma_bus *bus = cc->core->bus;
311
312	switch (bus->chipinfo.id) {
313	- case 0x4716:
314	- case 0x4748:
315	- case 47162:
316	- case 0x4313:
317	- case 0x5357:
318	- case 0x4749:
319	- case 53572:
320	+ case BCMA_CHIP_ID_BCM4716:
321	+ case BCMA_CHIP_ID_BCM4748:
322	+ case BCMA_CHIP_ID_BCM47162:
323	+ case BCMA_CHIP_ID_BCM4313:
324	+ case BCMA_CHIP_ID_BCM5357:
325	+ case BCMA_CHIP_ID_BCM4749:
326	+ case BCMA_CHIP_ID_BCM53572:
327	/* always 20Mhz */
328	return 20000 * 1000;
329	- case 0x5356:
330	- case 0x5300:
331	+ case BCMA_CHIP_ID_BCM5356:
332	+ case BCMA_CHIP_ID_BCM4706:
333	/* always 25Mhz */
334	return 25000 * 1000;
335	default:
336	- pr_warn("No ALP clock specified for %04X device, "
337	- "pmu rev. %d, using default %d Hz\n",
338	- bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
339	+ bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
340	+ bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
341	}
342	return BCMA_CC_PMU_ALP_CLOCK;
343	}
344	@@ -221,7 +199,8 @@ static u32 bcma_pmu_clock(struct bcma_dr
345
346	BUG_ON(!m \|\| m > 4);
347
348	- if (bus->chipinfo.id == 0x5357 \|\| bus->chipinfo.id == 0x4749) {
349	+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 \|\|
350	+ bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) {
351	/* Detect failure in clock setting */
352	tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
353	if (tmp & 0x40000)
354	@@ -247,33 +226,62 @@ static u32 bcma_pmu_clock(struct bcma_dr
355	return (fc / div) * 1000000;
356	}
357
358	+static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
359	+{
360	+ u32 tmp, ndiv, p1div, p2div;
361	+ u32 clock;
362	+
363	+ BUG_ON(!m \|\| m > 4);
364	+
365	+ /* Get N, P1 and P2 dividers to determine CPU clock */
366	+ tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PMU6_4706_PROCPLL_OFF);
367	+ ndiv = (tmp & BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK)
368	+ >> BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT;
369	+ p1div = (tmp & BCMA_CC_PMU6_4706_PROC_P1DIV_MASK)
370	+ >> BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT;
371	+ p2div = (tmp & BCMA_CC_PMU6_4706_PROC_P2DIV_MASK)
372	+ >> BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT;
373	+
374	+ tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
375	+ if (tmp & BCMA_CC_CHIPST_4706_PKG_OPTION)
376	+ /* Low cost bonding: Fixed reference clock 25MHz and m = 4 */
377	+ clock = (25000000 / 4) * ndiv * p2div / p1div;
378	+ else
379	+ /* Fixed reference clock 25MHz and m = 2 */
380	+ clock = (25000000 / 2) * ndiv * p2div / p1div;
381	+
382	+ if (m == BCMA_CC_PMU5_MAINPLL_SSB)
383	+ clock = clock / 4;
384	+
385	+ return clock;
386	+}
387	+
388	/* query bus clock frequency for PMU-enabled chipcommon */
389	u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
390	{
391	struct bcma_bus *bus = cc->core->bus;
392
393	switch (bus->chipinfo.id) {
394	- case 0x4716:
395	- case 0x4748:
396	- case 47162:
397	+ case BCMA_CHIP_ID_BCM4716:
398	+ case BCMA_CHIP_ID_BCM4748:
399	+ case BCMA_CHIP_ID_BCM47162:
400	return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
401	BCMA_CC_PMU5_MAINPLL_SSB);
402	- case 0x5356:
403	+ case BCMA_CHIP_ID_BCM5356:
404	return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
405	BCMA_CC_PMU5_MAINPLL_SSB);
406	- case 0x5357:
407	- case 0x4749:
408	+ case BCMA_CHIP_ID_BCM5357:
409	+ case BCMA_CHIP_ID_BCM4749:
410	return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
411	BCMA_CC_PMU5_MAINPLL_SSB);
412	- case 0x5300:
413	- return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
414	- BCMA_CC_PMU5_MAINPLL_SSB);
415	- case 53572:
416	+ case BCMA_CHIP_ID_BCM4706:
417	+ return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
418	+ BCMA_CC_PMU5_MAINPLL_SSB);
419	+ case BCMA_CHIP_ID_BCM53572:
420	return 75000000;
421	default:
422	- pr_warn("No backplane clock specified for %04X device, "
423	- "pmu rev. %d, using default %d Hz\n",
424	- bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
425	+ bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
426	+ bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
427	}
428	return BCMA_CC_PMU_HT_CLOCK;
429	}
430	@@ -283,17 +291,21 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
431	{
432	struct bcma_bus *bus = cc->core->bus;
433
434	- if (bus->chipinfo.id == 53572)
435	+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
436	return 300000000;
437
438	if (cc->pmu.rev >= 5) {
439	u32 pll;
440	switch (bus->chipinfo.id) {
441	- case 0x5356:
442	+ case BCMA_CHIP_ID_BCM4706:
443	+ return bcma_pmu_clock_bcm4706(cc,
444	+ BCMA_CC_PMU4706_MAINPLL_PLL0,
445	+ BCMA_CC_PMU5_MAINPLL_CPU);
446	+ case BCMA_CHIP_ID_BCM5356:
447	pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
448	break;
449	- case 0x5357:
450	- case 0x4749:
451	+ case BCMA_CHIP_ID_BCM5357:
452	+ case BCMA_CHIP_ID_BCM4749:
453	pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
454	break;
455	default:
456	@@ -301,10 +313,188 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
457	break;
458	}
459
460	- /* TODO: if (bus->chipinfo.id == 0x5300)
461	- return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
462	return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
463	}
464
465	return bcma_pmu_get_clockcontrol(cc);
466	}
467	+
468	+static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
469	+ u32 value)
470	+{
471	+ bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
472	+ bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
473	+}
474	+
475	+void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
476	+{
477	+ u32 tmp = 0;
478	+ u8 phypll_offset = 0;
479	+ u8 bcm5357_bcm43236_p1div[] = {0x1, 0x5, 0x5};
480	+ u8 bcm5357_bcm43236_ndiv[] = {0x30, 0xf6, 0xfc};
481	+ struct bcma_bus *bus = cc->core->bus;
482	+
483	+ switch (bus->chipinfo.id) {
484	+ case BCMA_CHIP_ID_BCM5357:
485	+ case BCMA_CHIP_ID_BCM4749:
486	+ case BCMA_CHIP_ID_BCM53572:
487	+ /* 5357[ab]0, 43236[ab]0, and 6362b0 */
488	+
489	+ /* BCM5357 needs to touch PLL1_PLLCTL[02],
490	+ so offset PLL0_PLLCTL[02] by 6 */
491	+ phypll_offset = (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 \|\|
492	+ bus->chipinfo.id == BCMA_CHIP_ID_BCM4749 \|\|
493	+ bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;
494	+
495	+ /* RMW only the P1 divider */
496	+ bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
497	+ BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
498	+ tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
499	+ tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
500	+ tmp \|= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
501	+ bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
502	+
503	+ /* RMW only the int feedback divider */
504	+ bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
505	+ BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
506	+ tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
507	+ tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
508	+ tmp \|= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
509	+ bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
510	+
511	+ tmp = 1 << 10;
512	+ break;
513	+
514	+ case BCMA_CHIP_ID_BCM4331:
515	+ case BCMA_CHIP_ID_BCM43431:
516	+ if (spuravoid == 2) {
517	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
518	+ 0x11500014);
519	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
520	+ 0x0FC00a08);
521	+ } else if (spuravoid == 1) {
522	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
523	+ 0x11500014);
524	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
525	+ 0x0F600a08);
526	+ } else {
527	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
528	+ 0x11100014);
529	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
530	+ 0x03000a08);
531	+ }
532	+ tmp = 1 << 10;
533	+ break;
534	+
535	+ case BCMA_CHIP_ID_BCM43224:
536	+ case BCMA_CHIP_ID_BCM43225:
537	+ case BCMA_CHIP_ID_BCM43421:
538	+ if (spuravoid == 1) {
539	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
540	+ 0x11500010);
541	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
542	+ 0x000C0C06);
543	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
544	+ 0x0F600a08);
545	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
546	+ 0x00000000);
547	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
548	+ 0x2001E920);
549	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
550	+ 0x88888815);
551	+ } else {
552	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
553	+ 0x11100010);
554	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
555	+ 0x000c0c06);
556	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
557	+ 0x03000a08);
558	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
559	+ 0x00000000);
560	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
561	+ 0x200005c0);
562	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
563	+ 0x88888815);
564	+ }
565	+ tmp = 1 << 10;
566	+ break;
567	+
568	+ case BCMA_CHIP_ID_BCM4716:
569	+ case BCMA_CHIP_ID_BCM4748:
570	+ case BCMA_CHIP_ID_BCM47162:
571	+ if (spuravoid == 1) {
572	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
573	+ 0x11500060);
574	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
575	+ 0x080C0C06);
576	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
577	+ 0x0F600000);
578	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
579	+ 0x00000000);
580	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
581	+ 0x2001E924);
582	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
583	+ 0x88888815);
584	+ } else {
585	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
586	+ 0x11100060);
587	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
588	+ 0x080c0c06);
589	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
590	+ 0x03000000);
591	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
592	+ 0x00000000);
593	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
594	+ 0x200005c0);
595	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
596	+ 0x88888815);
597	+ }
598	+
599	+ tmp = 3 << 9;
600	+ break;
601	+
602	+ case BCMA_CHIP_ID_BCM43227:
603	+ case BCMA_CHIP_ID_BCM43228:
604	+ case BCMA_CHIP_ID_BCM43428:
605	+ /* LCNXN */
606	+ /* PLL Settings for spur avoidance on/off mode,
607	+ no on2 support for 43228A0 */
608	+ if (spuravoid == 1) {
609	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
610	+ 0x01100014);
611	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
612	+ 0x040C0C06);
613	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
614	+ 0x03140A08);
615	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
616	+ 0x00333333);
617	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
618	+ 0x202C2820);
619	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
620	+ 0x88888815);
621	+ } else {
622	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
623	+ 0x11100014);
624	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
625	+ 0x040c0c06);
626	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
627	+ 0x03000a08);
628	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
629	+ 0x00000000);
630	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
631	+ 0x200005c0);
632	+ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
633	+ 0x88888815);
634	+ }
635	+ tmp = 1 << 10;
636	+ break;
637	+ default:
638	+ bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
639	+ bus->chipinfo.id);
640	+ break;
641	+ }
642	+
643	+ tmp \|= bcma_cc_read32(cc, BCMA_CC_PMU_CTL);
644	+ bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp);
645	+}
646	+EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);
647	--- /dev/null
648	+++ b/drivers/bcma/driver_gmac_cmn.c
649	@@ -0,0 +1,14 @@
650	+/*
651	+ * Broadcom specific AMBA
652	+ * GBIT MAC COMMON Core
653	+ *
654	+ * Licensed under the GNU/GPL. See COPYING for details.
655	+ */
656	+
657	+#include "bcma_private.h"
658	+#include <linux/bcma/bcma.h>
659	+
660	+void __devinit bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc)
661	+{
662	+ mutex_init(&gc->phy_mutex);
663	+}
664	--- a/drivers/bcma/driver_mips.c
665	+++ b/drivers/bcma/driver_mips.c
666	@@ -22,15 +22,15 @@
667	/* The 47162a0 hangs when reading MIPS DMP registers registers */
668	static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
669	{
670	- return dev->bus->chipinfo.id == 47162 && dev->bus->chipinfo.rev == 0 &&
671	- dev->id.id == BCMA_CORE_MIPS_74K;
672	+ return dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM47162 &&
673	+ dev->bus->chipinfo.rev == 0 && dev->id.id == BCMA_CORE_MIPS_74K;
674	}
675
676	/* The 5357b0 hangs when reading USB20H DMP registers */
677	static inline bool bcma_core_mips_bcm5357b0_quirk(struct bcma_device *dev)
678	{
679	- return (dev->bus->chipinfo.id == 0x5357 \|\|
680	- dev->bus->chipinfo.id == 0x4749) &&
681	+ return (dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 \|\|
682	+ dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) &&
683	dev->bus->chipinfo.pkg == 11 &&
684	dev->id.id == BCMA_CORE_USB20_HOST;
685	}
686	@@ -143,8 +143,8 @@ static void bcma_core_mips_set_irq(struc
687	1 << irqflag);
688	}
689
690	- pr_info("set_irq: core 0x%04x, irq %d => %d\n",
691	- dev->id.id, oldirq + 2, irq + 2);
692	+ bcma_info(bus, "set_irq: core 0x%04x, irq %d => %d\n",
693	+ dev->id.id, oldirq + 2, irq + 2);
694	}
695
696	static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
697	@@ -173,7 +173,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
698	if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
699	return bcma_pmu_get_clockcpu(&bus->drv_cc);
700
701	- pr_err("No PMU available, need this to get the cpu clock\n");
702	+ bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
703	return 0;
704	}
705	EXPORT_SYMBOL(bcma_cpu_clock);
706	@@ -185,10 +185,10 @@ static void bcma_core_mips_flash_detect(
707	switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
708	case BCMA_CC_FLASHT_STSER:
709	case BCMA_CC_FLASHT_ATSER:
710	- pr_err("Serial flash not supported.\n");
711	+ bcma_err(bus, "Serial flash not supported.\n");
712	break;
713	case BCMA_CC_FLASHT_PARA:
714	- pr_info("found parallel flash.\n");
715	+ bcma_info(bus, "found parallel flash.\n");
716	bus->drv_cc.pflash.window = 0x1c000000;
717	bus->drv_cc.pflash.window_size = 0x02000000;
718
719	@@ -199,7 +199,7 @@ static void bcma_core_mips_flash_detect(
720	bus->drv_cc.pflash.buswidth = 2;
721	break;
722	default:
723	- pr_err("flash not supported.\n");
724	+ bcma_err(bus, "flash not supported.\n");
725	}
726	}
727
728	@@ -209,7 +209,7 @@ void bcma_core_mips_init(struct bcma_drv
729	struct bcma_device *core;
730	bus = mcore->core->bus;
731
732	- pr_info("Initializing MIPS core...\n");
733	+ bcma_info(bus, "Initializing MIPS core...\n");
734
735	if (!mcore->setup_done)
736	mcore->assigned_irqs = 1;
737	@@ -244,7 +244,7 @@ void bcma_core_mips_init(struct bcma_drv
738	break;
739	}
740	}
741	- pr_info("IRQ reconfiguration done\n");
742	+ bcma_info(bus, "IRQ reconfiguration done\n");
743	bcma_core_mips_dump_irq(bus);
744
745	if (mcore->setup_done)
746	--- a/drivers/bcma/driver_pci.c
747	+++ b/drivers/bcma/driver_pci.c
748	@@ -2,8 +2,9 @@
749	* Broadcom specific AMBA
750	* PCI Core
751	*
752	- * Copyright 2005, Broadcom Corporation
753	+ * Copyright 2005, 2011, Broadcom Corporation
754	* Copyright 2006, 2007, Michael Buesch <m@bues.ch>
755	+ * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
756	*
757	* Licensed under the GNU/GPL. See COPYING for details.
758	*/
759	@@ -16,40 +17,39 @@
760	* R/W ops.
761	**************************************************/
762
763	-static u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
764	+u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
765	{
766	- pcicore_write32(pc, 0x130, address);
767	- pcicore_read32(pc, 0x130);
768	- return pcicore_read32(pc, 0x134);
769	+ pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
770	+ pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
771	+ return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA);
772	}
773
774	-#if 0
775	static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
776	{
777	- pcicore_write32(pc, 0x130, address);
778	- pcicore_read32(pc, 0x130);
779	- pcicore_write32(pc, 0x134, data);
780	+ pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
781	+ pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
782	+ pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
783	}
784	-#endif
785
786	static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
787	{
788	- const u16 mdio_control = 0x128;
789	- const u16 mdio_data = 0x12C;
790	u32 v;
791	int i;
792
793	- v = (1 << 30); /* Start of Transaction */
794	- v \|= (1 << 28); /* Write Transaction */
795	- v \|= (1 << 17); /* Turnaround */
796	- v \|= (0x1F << 18);
797	+ v = BCMA_CORE_PCI_MDIODATA_START;
798	+ v \|= BCMA_CORE_PCI_MDIODATA_WRITE;
799	+ v \|= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
800	+ BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
801	+ v \|= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR <<
802	+ BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
803	+ v \|= BCMA_CORE_PCI_MDIODATA_TA;
804	v \|= (phy << 4);
805	- pcicore_write32(pc, mdio_data, v);
806	+ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
807
808	udelay(10);
809	for (i = 0; i < 200; i++) {
810	- v = pcicore_read32(pc, mdio_control);
811	- if (v & 0x100 /* Trans complete */)
812	+ v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
813	+ if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
814	break;
815	msleep(1);
816	}
817	@@ -57,79 +57,84 @@ static void bcma_pcie_mdio_set_phy(struc
818
819	static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
820	{
821	- const u16 mdio_control = 0x128;
822	- const u16 mdio_data = 0x12C;
823	int max_retries = 10;
824	u16 ret = 0;
825	u32 v;
826	int i;
827
828	- v = 0x80; /* Enable Preamble Sequence */
829	- v \|= 0x2; /* MDIO Clock Divisor */
830	- pcicore_write32(pc, mdio_control, v);
831	+ /* enable mdio access to SERDES */
832	+ v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
833	+ v \|= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
834	+ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
835
836	if (pc->core->id.rev >= 10) {
837	max_retries = 200;
838	bcma_pcie_mdio_set_phy(pc, device);
839	+ v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
840	+ BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
841	+ v \|= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
842	+ } else {
843	+ v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
844	+ v \|= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
845	}
846
847	- v = (1 << 30); /* Start of Transaction */
848	- v \|= (1 << 29); /* Read Transaction */
849	- v \|= (1 << 17); /* Turnaround */
850	- if (pc->core->id.rev < 10)
851	- v \|= (u32)device << 22;
852	- v \|= (u32)address << 18;
853	- pcicore_write32(pc, mdio_data, v);
854	+ v = BCMA_CORE_PCI_MDIODATA_START;
855	+ v \|= BCMA_CORE_PCI_MDIODATA_READ;
856	+ v \|= BCMA_CORE_PCI_MDIODATA_TA;
857	+
858	+ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
859	/* Wait for the device to complete the transaction */
860	udelay(10);
861	for (i = 0; i < max_retries; i++) {
862	- v = pcicore_read32(pc, mdio_control);
863	- if (v & 0x100 /* Trans complete */) {
864	+ v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
865	+ if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) {
866	udelay(10);
867	- ret = pcicore_read32(pc, mdio_data);
868	+ ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
869	break;
870	}
871	msleep(1);
872	}
873	- pcicore_write32(pc, mdio_control, 0);
874	+ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
875	return ret;
876	}
877
878	static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
879	u8 address, u16 data)
880	{
881	- const u16 mdio_control = 0x128;
882	- const u16 mdio_data = 0x12C;
883	int max_retries = 10;
884	u32 v;
885	int i;
886
887	- v = 0x80; /* Enable Preamble Sequence */
888	- v \|= 0x2; /* MDIO Clock Divisor */
889	- pcicore_write32(pc, mdio_control, v);
890	+ /* enable mdio access to SERDES */
891	+ v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
892	+ v \|= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
893	+ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
894
895	if (pc->core->id.rev >= 10) {
896	max_retries = 200;
897	bcma_pcie_mdio_set_phy(pc, device);
898	+ v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
899	+ BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
900	+ v \|= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
901	+ } else {
902	+ v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
903	+ v \|= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
904	}
905
906	- v = (1 << 30); /* Start of Transaction */
907	- v \|= (1 << 28); /* Write Transaction */
908	- v \|= (1 << 17); /* Turnaround */
909	- if (pc->core->id.rev < 10)
910	- v \|= (u32)device << 22;
911	- v \|= (u32)address << 18;
912	+ v = BCMA_CORE_PCI_MDIODATA_START;
913	+ v \|= BCMA_CORE_PCI_MDIODATA_WRITE;
914	+ v \|= BCMA_CORE_PCI_MDIODATA_TA;
915	v \|= data;
916	- pcicore_write32(pc, mdio_data, v);
917	+ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
918	/* Wait for the device to complete the transaction */
919	udelay(10);
920	for (i = 0; i < max_retries; i++) {
921	- v = pcicore_read32(pc, mdio_control);
922	- if (v & 0x100 /* Trans complete */)
923	+ v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
924	+ if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
925	break;
926	msleep(1);
927	}
928	- pcicore_write32(pc, mdio_control, 0);
929	+ pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
930	}
931
932	/**************************************************
933	@@ -138,88 +143,108 @@ static void bcma_pcie_mdio_write(struct
934
935	static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
936	{
937	- return (bcma_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
938	+ u32 tmp;
939	+
940	+ tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG);
941	+ if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT)
942	+ return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE \|
943	+ BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY;
944	+ else
945	+ return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE;
946	}
947
948	static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
949	{
950	- const u8 serdes_pll_device = 0x1D;
951	- const u8 serdes_rx_device = 0x1F;
952	u16 tmp;
953
954	- bcma_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
955	- bcma_pcicore_polarity_workaround(pc));
956	- tmp = bcma_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
957	- if (tmp & 0x4000)
958	- bcma_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
959	+ bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX,
960	+ BCMA_CORE_PCI_SERDES_RX_CTRL,
961	+ bcma_pcicore_polarity_workaround(pc));
962	+ tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
963	+ BCMA_CORE_PCI_SERDES_PLL_CTRL);
964	+ if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN)
965	+ bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
966	+ BCMA_CORE_PCI_SERDES_PLL_CTRL,
967	+ tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN);
968	+}
969	+
970	+static void bcma_core_pci_fixcfg(struct bcma_drv_pci *pc)
971	+{
972	+ struct bcma_device *core = pc->core;
973	+ u16 val16, core_index;
974	+ uint regoff;
975	+
976	+ regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_PI_OFFSET);
977	+ core_index = (u16)core->core_index;
978	+
979	+ val16 = pcicore_read16(pc, regoff);
980	+ if (((val16 & BCMA_CORE_PCI_SPROM_PI_MASK) >> BCMA_CORE_PCI_SPROM_PI_SHIFT)
981	+ != core_index) {
982	+ val16 = (core_index << BCMA_CORE_PCI_SPROM_PI_SHIFT) \|
983	+ (val16 & ~BCMA_CORE_PCI_SPROM_PI_MASK);
984	+ pcicore_write16(pc, regoff, val16);
985	+ }
986	+}
987	+
988	+/* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */
989	+/* Needs to happen when coming out of 'standby'/'hibernate' */
990	+static void bcma_core_pci_config_fixup(struct bcma_drv_pci *pc)
991	+{
992	+ u16 val16;
993	+ uint regoff;
994	+
995	+ regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_MISC_CONFIG);
996	+
997	+ val16 = pcicore_read16(pc, regoff);
998	+
999	+ if (!(val16 & BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST)) {
1000	+ val16 \|= BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST;
1001	+ pcicore_write16(pc, regoff, val16);
1002	+ }
1003	}
1004
1005	/**************************************************
1006	* Init.
1007	**************************************************/
1008
1009	-static void bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
1010	+static void __devinit bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
1011	{
1012	+ bcma_core_pci_fixcfg(pc);
1013	bcma_pcicore_serdes_workaround(pc);
1014	+ bcma_core_pci_config_fixup(pc);
1015	}
1016
1017	-static bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
1018	-{
1019	- struct bcma_bus *bus = pc->core->bus;
1020	- u16 chipid_top;
1021	-
1022	- chipid_top = (bus->chipinfo.id & 0xFF00);
1023	- if (chipid_top != 0x4700 &&
1024	- chipid_top != 0x5300)
1025	- return false;
1026	-
1027	-#ifdef CONFIG_SSB_DRIVER_PCICORE
1028	- if (bus->sprom.boardflags_lo & SSB_BFL_NOPCI)
1029	- return false;
1030	-#endif /* CONFIG_SSB_DRIVER_PCICORE */
1031	-
1032	-#if 0
1033	- /* TODO: on BCMA we use address from EROM instead of magic formula */
1034	- u32 tmp;
1035	- return !mips_busprobe32(tmp, (bus->mmio +
1036	- (pc->core->core_index * BCMA_CORE_SIZE)));
1037	-#endif
1038	-
1039	- return true;
1040	-}
1041	-
1042	-void bcma_core_pci_init(struct bcma_drv_pci *pc)
1043	+void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc)
1044	{
1045	if (pc->setup_done)
1046	return;
1047
1048	- if (bcma_core_pci_is_in_hostmode(pc)) {
1049	#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
1050	+ pc->hostmode = bcma_core_pci_is_in_hostmode(pc);
1051	+ if (pc->hostmode)
1052	bcma_core_pci_hostmode_init(pc);
1053	-#else
1054	- pr_err("Driver compiled without support for hostmode PCI\n");
1055	#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
1056	- } else {
1057	- bcma_core_pci_clientmode_init(pc);
1058	- }
1059
1060	- pc->setup_done = true;
1061	+ if (!pc->hostmode)
1062	+ bcma_core_pci_clientmode_init(pc);
1063	}
1064
1065	int bcma_core_pci_irq_ctl(struct bcma_drv_pci pc, struct bcma_device core,
1066	bool enable)
1067	{
1068	- struct pci_dev *pdev = pc->core->bus->host_pci;
1069	+ struct pci_dev *pdev;
1070	u32 coremask, tmp;
1071	int err = 0;
1072
1073	- if (core->bus->hosttype != BCMA_HOSTTYPE_PCI) {
1074	+ if (!pc \|\| core->bus->hosttype != BCMA_HOSTTYPE_PCI) {
1075	/* This bcma device is not on a PCI host-bus. So the IRQs are
1076	* not routed through the PCI core.
1077	* So we must not enable routing through the PCI core. */
1078	goto out;
1079	}
1080
1081	+ pdev = pc->core->bus->host_pci;
1082	+
1083	err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp);
1084	if (err)
1085	goto out;
1086	@@ -236,3 +261,17 @@ out:
1087	return err;
1088	}
1089	EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
1090	+
1091	+void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
1092	+{
1093	+ u32 w;
1094	+
1095	+ w = bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
1096	+ if (extend)
1097	+ w \|= BCMA_CORE_PCI_ASPMTIMER_EXTEND;
1098	+ else
1099	+ w &= ~BCMA_CORE_PCI_ASPMTIMER_EXTEND;
1100	+ bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w);
1101	+ bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
1102	+}
1103	+EXPORT_SYMBOL_GPL(bcma_core_pci_extend_L1timer);
1104	--- a/drivers/bcma/driver_pci_host.c
1105	+++ b/drivers/bcma/driver_pci_host.c
1106	@@ -2,13 +2,592 @@
1107	* Broadcom specific AMBA
1108	* PCI Core in hostmode
1109	*
1110	+ * Copyright 2005 - 2011, Broadcom Corporation
1111	+ * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1112	+ * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
1113	+ *
1114	* Licensed under the GNU/GPL. See COPYING for details.
1115	*/
1116
1117	#include "bcma_private.h"
1118	+#include <linux/pci.h>
1119	+#include <linux/export.h>
1120	#include <linux/bcma/bcma.h>
1121	+#include <asm/paccess.h>
1122	+
1123	+/* Probe a 32bit value on the bus and catch bus exceptions.
1124	+ * Returns nonzero on a bus exception.
1125	+ * This is MIPS specific */
1126	+#define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr)))
1127	+
1128	+/* Assume one-hot slot wiring */
1129	+#define BCMA_PCI_SLOT_MAX 16
1130	+#define PCI_CONFIG_SPACE_SIZE 256
1131	+
1132	+bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
1133	+{
1134	+ struct bcma_bus *bus = pc->core->bus;
1135	+ u16 chipid_top;
1136	+ u32 tmp;
1137	+
1138	+ chipid_top = (bus->chipinfo.id & 0xFF00);
1139	+ if (chipid_top != 0x4700 &&
1140	+ chipid_top != 0x5300)
1141	+ return false;
1142	+
1143	+ if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
1144	+ bcma_info(bus, "This PCI core is disabled and not working\n");
1145	+ return false;
1146	+ }
1147	+
1148	+ bcma_core_enable(pc->core, 0);
1149	+
1150	+ return !mips_busprobe32(tmp, pc->core->io_addr);
1151	+}
1152	+
1153	+static u32 bcma_pcie_read_config(struct bcma_drv_pci *pc, u32 address)
1154	+{
1155	+ pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
1156	+ pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
1157	+ return pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_DATA);
1158	+}
1159	+
1160	+static void bcma_pcie_write_config(struct bcma_drv_pci *pc, u32 address,
1161	+ u32 data)
1162	+{
1163	+ pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
1164	+ pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
1165	+ pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_DATA, data);
1166	+}
1167	+
1168	+static u32 bcma_get_cfgspace_addr(struct bcma_drv_pci *pc, unsigned int dev,
1169	+ unsigned int func, unsigned int off)
1170	+{
1171	+ u32 addr = 0;
1172	+
1173	+ /* Issue config commands only when the data link is up (atleast
1174	+ * one external pcie device is present).
1175	+ */
1176	+ if (dev >= 2 \|\| !(bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_LSREG)
1177	+ & BCMA_CORE_PCI_DLLP_LSREG_LINKUP))
1178	+ goto out;
1179	+
1180	+ /* Type 0 transaction */
1181	+ /* Slide the PCI window to the appropriate slot */
1182	+ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
1183	+ /* Calculate the address */
1184	+ addr = pc->host_controller->host_cfg_addr;
1185	+ addr \|= (dev << BCMA_CORE_PCI_CFG_SLOT_SHIFT);
1186	+ addr \|= (func << BCMA_CORE_PCI_CFG_FUN_SHIFT);
1187	+ addr \|= (off & ~3);
1188	+
1189	+out:
1190	+ return addr;
1191	+}
1192
1193	-void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
1194	+static int bcma_extpci_read_config(struct bcma_drv_pci *pc, unsigned int dev,
1195	+ unsigned int func, unsigned int off,
1196	+ void *buf, int len)
1197	{
1198	- pr_err("No support for PCI core in hostmode yet\n");
1199	+ int err = -EINVAL;
1200	+ u32 addr, val;
1201	+ void __iomem *mmio = 0;
1202	+
1203	+ WARN_ON(!pc->hostmode);
1204	+ if (unlikely(len != 1 && len != 2 && len != 4))
1205	+ goto out;
1206	+ if (dev == 0) {
1207	+ /* we support only two functions on device 0 */
1208	+ if (func > 1)
1209	+ return -EINVAL;
1210	+
1211	+ /* accesses to config registers with offsets >= 256
1212	+ * requires indirect access.
1213	+ */
1214	+ if (off >= PCI_CONFIG_SPACE_SIZE) {
1215	+ addr = (func << 12);
1216	+ addr \|= (off & 0x0FFF);
1217	+ val = bcma_pcie_read_config(pc, addr);
1218	+ } else {
1219	+ addr = BCMA_CORE_PCI_PCICFG0;
1220	+ addr \|= (func << 8);
1221	+ addr \|= (off & 0xfc);
1222	+ val = pcicore_read32(pc, addr);
1223	+ }
1224	+ } else {
1225	+ addr = bcma_get_cfgspace_addr(pc, dev, func, off);
1226	+ if (unlikely(!addr))
1227	+ goto out;
1228	+ err = -ENOMEM;
1229	+ mmio = ioremap_nocache(addr, sizeof(val));
1230	+ if (!mmio)
1231	+ goto out;
1232	+
1233	+ if (mips_busprobe32(val, mmio)) {
1234	+ val = 0xffffffff;
1235	+ goto unmap;
1236	+ }
1237	+
1238	+ val = readl(mmio);
1239	+ }
1240	+ val >>= (8 * (off & 3));
1241	+
1242	+ switch (len) {
1243	+ case 1:
1244	+ ((u8 )buf) = (u8)val;
1245	+ break;
1246	+ case 2:
1247	+ ((u16 )buf) = (u16)val;
1248	+ break;
1249	+ case 4:
1250	+ ((u32 )buf) = (u32)val;
1251	+ break;
1252	+ }
1253	+ err = 0;
1254	+unmap:
1255	+ if (mmio)
1256	+ iounmap(mmio);
1257	+out:
1258	+ return err;
1259	+}
1260	+
1261	+static int bcma_extpci_write_config(struct bcma_drv_pci *pc, unsigned int dev,
1262	+ unsigned int func, unsigned int off,
1263	+ const void *buf, int len)
1264	+{
1265	+ int err = -EINVAL;
1266	+ u32 addr = 0, val = 0;
1267	+ void __iomem *mmio = 0;
1268	+ u16 chipid = pc->core->bus->chipinfo.id;
1269	+
1270	+ WARN_ON(!pc->hostmode);
1271	+ if (unlikely(len != 1 && len != 2 && len != 4))
1272	+ goto out;
1273	+ if (dev == 0) {
1274	+ /* accesses to config registers with offsets >= 256
1275	+ * requires indirect access.
1276	+ */
1277	+ if (off < PCI_CONFIG_SPACE_SIZE) {
1278	+ addr = pc->core->addr + BCMA_CORE_PCI_PCICFG0;
1279	+ addr \|= (func << 8);
1280	+ addr \|= (off & 0xfc);
1281	+ mmio = ioremap_nocache(addr, sizeof(val));
1282	+ if (!mmio)
1283	+ goto out;
1284	+ }
1285	+ } else {
1286	+ addr = bcma_get_cfgspace_addr(pc, dev, func, off);
1287	+ if (unlikely(!addr))
1288	+ goto out;
1289	+ err = -ENOMEM;
1290	+ mmio = ioremap_nocache(addr, sizeof(val));
1291	+ if (!mmio)
1292	+ goto out;
1293	+
1294	+ if (mips_busprobe32(val, mmio)) {
1295	+ val = 0xffffffff;
1296	+ goto unmap;
1297	+ }
1298	+ }
1299	+
1300	+ switch (len) {
1301	+ case 1:
1302	+ val = readl(mmio);
1303	+ val &= ~(0xFF << (8 * (off & 3)));
1304	+ val \|= ((const u8 )buf) << (8 * (off & 3));
1305	+ break;
1306	+ case 2:
1307	+ val = readl(mmio);
1308	+ val &= ~(0xFFFF << (8 * (off & 3)));
1309	+ val \|= ((const u16 )buf) << (8 * (off & 3));
1310	+ break;
1311	+ case 4:
1312	+ val = ((const u32 )buf);
1313	+ break;
1314	+ }
1315	+ if (dev == 0 && !addr) {
1316	+ /* accesses to config registers with offsets >= 256
1317	+ * requires indirect access.
1318	+ */
1319	+ addr = (func << 12);
1320	+ addr \|= (off & 0x0FFF);
1321	+ bcma_pcie_write_config(pc, addr, val);
1322	+ } else {
1323	+ writel(val, mmio);
1324	+
1325	+ if (chipid == BCMA_CHIP_ID_BCM4716 \|\|
1326	+ chipid == BCMA_CHIP_ID_BCM4748)
1327	+ readl(mmio);
1328	+ }
1329	+
1330	+ err = 0;
1331	+unmap:
1332	+ if (mmio)
1333	+ iounmap(mmio);
1334	+out:
1335	+ return err;
1336	+}
1337	+
1338	+static int bcma_core_pci_hostmode_read_config(struct pci_bus *bus,
1339	+ unsigned int devfn,
1340	+ int reg, int size, u32 *val)
1341	+{
1342	+ unsigned long flags;
1343	+ int err;
1344	+ struct bcma_drv_pci *pc;
1345	+ struct bcma_drv_pci_host *pc_host;
1346	+
1347	+ pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
1348	+ pc = pc_host->pdev;
1349	+
1350	+ spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
1351	+ err = bcma_extpci_read_config(pc, PCI_SLOT(devfn),
1352	+ PCI_FUNC(devfn), reg, val, size);
1353	+ spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
1354	+
1355	+ return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
1356	+}
1357	+
1358	+static int bcma_core_pci_hostmode_write_config(struct pci_bus *bus,
1359	+ unsigned int devfn,
1360	+ int reg, int size, u32 val)
1361	+{
1362	+ unsigned long flags;
1363	+ int err;
1364	+ struct bcma_drv_pci *pc;
1365	+ struct bcma_drv_pci_host *pc_host;
1366	+
1367	+ pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
1368	+ pc = pc_host->pdev;
1369	+
1370	+ spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
1371	+ err = bcma_extpci_write_config(pc, PCI_SLOT(devfn),
1372	+ PCI_FUNC(devfn), reg, &val, size);
1373	+ spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
1374	+
1375	+ return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
1376	+}
1377	+
1378	+/* return cap_offset if requested capability exists in the PCI config space */
1379	+static u8 __devinit bcma_find_pci_capability(struct bcma_drv_pci *pc,
1380	+ unsigned int dev,
1381	+ unsigned int func, u8 req_cap_id,
1382	+ unsigned char buf, u32 buflen)
1383	+{
1384	+ u8 cap_id;
1385	+ u8 cap_ptr = 0;
1386	+ u32 bufsize;
1387	+ u8 byte_val;
1388	+
1389	+ /* check for Header type 0 */
1390	+ bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val,
1391	+ sizeof(u8));
1392	+ if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL)
1393	+ return cap_ptr;
1394	+
1395	+ /* check if the capability pointer field exists */
1396	+ bcma_extpci_read_config(pc, dev, func, PCI_STATUS, &byte_val,
1397	+ sizeof(u8));
1398	+ if (!(byte_val & PCI_STATUS_CAP_LIST))
1399	+ return cap_ptr;
1400	+
1401	+ /* check if the capability pointer is 0x00 */
1402	+ bcma_extpci_read_config(pc, dev, func, PCI_CAPABILITY_LIST, &cap_ptr,
1403	+ sizeof(u8));
1404	+ if (cap_ptr == 0x00)
1405	+ return cap_ptr;
1406	+
1407	+ /* loop thr'u the capability list and see if the requested capabilty
1408	+ * exists */
1409	+ bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id, sizeof(u8));
1410	+ while (cap_id != req_cap_id) {
1411	+ bcma_extpci_read_config(pc, dev, func, cap_ptr + 1, &cap_ptr,
1412	+ sizeof(u8));
1413	+ if (cap_ptr == 0x00)
1414	+ return cap_ptr;
1415	+ bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id,
1416	+ sizeof(u8));
1417	+ }
1418	+
1419	+ /* found the caller requested capability */
1420	+ if ((buf != NULL) && (buflen != NULL)) {
1421	+ u8 cap_data;
1422	+
1423	+ bufsize = *buflen;
1424	+ if (!bufsize)
1425	+ return cap_ptr;
1426	+
1427	+ *buflen = 0;
1428	+
1429	+ /* copy the cpability data excluding cap ID and next ptr */
1430	+ cap_data = cap_ptr + 2;
1431	+ if ((bufsize + cap_data) > PCI_CONFIG_SPACE_SIZE)
1432	+ bufsize = PCI_CONFIG_SPACE_SIZE - cap_data;
1433	+ *buflen = bufsize;
1434	+ while (bufsize--) {
1435	+ bcma_extpci_read_config(pc, dev, func, cap_data, buf,
1436	+ sizeof(u8));
1437	+ cap_data++;
1438	+ buf++;
1439	+ }
1440	+ }
1441	+
1442	+ return cap_ptr;
1443	+}
1444	+
1445	+/* If the root port is capable of returning Config Request
1446	+ * Retry Status (CRS) Completion Status to software then
1447	+ * enable the feature.
1448	+ */
1449	+static void __devinit bcma_core_pci_enable_crs(struct bcma_drv_pci *pc)
1450	+{
1451	+ struct bcma_bus *bus = pc->core->bus;
1452	+ u8 cap_ptr, root_ctrl, root_cap, dev;
1453	+ u16 val16;
1454	+ int i;
1455	+
1456	+ cap_ptr = bcma_find_pci_capability(pc, 0, 0, PCI_CAP_ID_EXP, NULL,
1457	+ NULL);
1458	+ root_cap = cap_ptr + PCI_EXP_RTCAP;
1459	+ bcma_extpci_read_config(pc, 0, 0, root_cap, &val16, sizeof(u16));
1460	+ if (val16 & BCMA_CORE_PCI_RC_CRS_VISIBILITY) {
1461	+ /* Enable CRS software visibility */
1462	+ root_ctrl = cap_ptr + PCI_EXP_RTCTL;
1463	+ val16 = PCI_EXP_RTCTL_CRSSVE;
1464	+ bcma_extpci_read_config(pc, 0, 0, root_ctrl, &val16,
1465	+ sizeof(u16));
1466	+
1467	+ /* Initiate a configuration request to read the vendor id
1468	+ * field of the device function's config space header after
1469	+ * 100 ms wait time from the end of Reset. If the device is
1470	+ * not done with its internal initialization, it must at
1471	+ * least return a completion TLP, with a completion status
1472	+ * of "Configuration Request Retry Status (CRS)". The root
1473	+ * complex must complete the request to the host by returning
1474	+ * a read-data value of 0001h for the Vendor ID field and
1475	+ * all 1s for any additional bytes included in the request.
1476	+ * Poll using the config reads for max wait time of 1 sec or
1477	+ * until we receive the successful completion status. Repeat
1478	+ * the procedure for all the devices.
1479	+ */
1480	+ for (dev = 1; dev < BCMA_PCI_SLOT_MAX; dev++) {
1481	+ for (i = 0; i < 100000; i++) {
1482	+ bcma_extpci_read_config(pc, dev, 0,
1483	+ PCI_VENDOR_ID, &val16,
1484	+ sizeof(val16));
1485	+ if (val16 != 0x1)
1486	+ break;
1487	+ udelay(10);
1488	+ }
1489	+ if (val16 == 0x1)
1490	+ bcma_err(bus, "PCI: Broken device in slot %d\n",
1491	+ dev);
1492	+ }
1493	+ }
1494	+}
1495	+
1496	+void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
1497	+{
1498	+ struct bcma_bus *bus = pc->core->bus;
1499	+ struct bcma_drv_pci_host *pc_host;
1500	+ u32 tmp;
1501	+ u32 pci_membase_1G;
1502	+ unsigned long io_map_base;
1503	+
1504	+ bcma_info(bus, "PCIEcore in host mode found\n");
1505	+
1506	+ pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
1507	+ if (!pc_host) {
1508	+ bcma_err(bus, "can not allocate memory");
1509	+ return;
1510	+ }
1511	+
1512	+ pc->host_controller = pc_host;
1513	+ pc_host->pci_controller.io_resource = &pc_host->io_resource;
1514	+ pc_host->pci_controller.mem_resource = &pc_host->mem_resource;
1515	+ pc_host->pci_controller.pci_ops = &pc_host->pci_ops;
1516	+ pc_host->pdev = pc;
1517	+
1518	+ pci_membase_1G = BCMA_SOC_PCI_DMA;
1519	+ pc_host->host_cfg_addr = BCMA_SOC_PCI_CFG;
1520	+
1521	+ pc_host->pci_ops.read = bcma_core_pci_hostmode_read_config;
1522	+ pc_host->pci_ops.write = bcma_core_pci_hostmode_write_config;
1523	+
1524	+ pc_host->mem_resource.name = "BCMA PCIcore external memory",
1525	+ pc_host->mem_resource.start = BCMA_SOC_PCI_DMA;
1526	+ pc_host->mem_resource.end = BCMA_SOC_PCI_DMA + BCMA_SOC_PCI_DMA_SZ - 1;
1527	+ pc_host->mem_resource.flags = IORESOURCE_MEM \| IORESOURCE_PCI_FIXED;
1528	+
1529	+ pc_host->io_resource.name = "BCMA PCIcore external I/O",
1530	+ pc_host->io_resource.start = 0x100;
1531	+ pc_host->io_resource.end = 0x7FF;
1532	+ pc_host->io_resource.flags = IORESOURCE_IO \| IORESOURCE_PCI_FIXED;
1533	+
1534	+ /* Reset RC */
1535	+ udelay(3000);
1536	+ pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
1537	+ udelay(1000);
1538	+ pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST \|
1539	+ BCMA_CORE_PCI_CTL_RST_OE);
1540	+
1541	+ /* 64 MB I/O access window. On 4716, use
1542	+ * sbtopcie0 to access the device registers. We
1543	+ * can't use address match 2 (1 GB window) region
1544	+ * as mips can't generate 64-bit address on the
1545	+ * backplane.
1546	+ */
1547	+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4716 \|\|
1548	+ bus->chipinfo.id == BCMA_CHIP_ID_BCM4748) {
1549	+ pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
1550	+ pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
1551	+ BCMA_SOC_PCI_MEM_SZ - 1;
1552	+ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1553	+ BCMA_CORE_PCI_SBTOPCI_MEM \| BCMA_SOC_PCI_MEM);
1554	+ } else if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
1555	+ tmp = BCMA_CORE_PCI_SBTOPCI_MEM;
1556	+ tmp \|= BCMA_CORE_PCI_SBTOPCI_PREF;
1557	+ tmp \|= BCMA_CORE_PCI_SBTOPCI_BURST;
1558	+ if (pc->core->core_unit == 0) {
1559	+ pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
1560	+ pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
1561	+ BCMA_SOC_PCI_MEM_SZ - 1;
1562	+ pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
1563	+ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1564	+ tmp \| BCMA_SOC_PCI_MEM);
1565	+ } else if (pc->core->core_unit == 1) {
1566	+ pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
1567	+ pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
1568	+ BCMA_SOC_PCI_MEM_SZ - 1;
1569	+ pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
1570	+ pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
1571	+ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1572	+ tmp \| BCMA_SOC_PCI1_MEM);
1573	+ }
1574	+ } else
1575	+ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1576	+ BCMA_CORE_PCI_SBTOPCI_IO);
1577	+
1578	+ /* 64 MB configuration access window */
1579	+ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
1580	+
1581	+ /* 1 GB memory access window */
1582	+ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI2,
1583	+ BCMA_CORE_PCI_SBTOPCI_MEM \| pci_membase_1G);
1584	+
1585	+
1586	+ /* As per PCI Express Base Spec 1.1 we need to wait for
1587	+ * at least 100 ms from the end of a reset (cold/warm/hot)
1588	+ * before issuing configuration requests to PCI Express
1589	+ * devices.
1590	+ */
1591	+ udelay(100000);
1592	+
1593	+ bcma_core_pci_enable_crs(pc);
1594	+
1595	+ /* Enable PCI bridge BAR0 memory & master access */
1596	+ tmp = PCI_COMMAND_MASTER \| PCI_COMMAND_MEMORY;
1597	+ bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));
1598	+
1599	+ /* Enable PCI interrupts */
1600	+ pcicore_write32(pc, BCMA_CORE_PCI_IMASK, BCMA_CORE_PCI_IMASK_INTA);
1601	+
1602	+ /* Ok, ready to run, register it to the system.
1603	+ * The following needs change, if we want to port hostmode
1604	+ * to non-MIPS platform. */
1605	+ io_map_base = (unsigned long)ioremap_nocache(pc_host->mem_resource.start,
1606	+ resource_size(&pc_host->mem_resource));
1607	+ pc_host->pci_controller.io_map_base = io_map_base;
1608	+ set_io_port_base(pc_host->pci_controller.io_map_base);
1609	+ /* Give some time to the PCI controller to configure itself with the new
1610	+ * values. Not waiting at this point causes crashes of the machine. */
1611	+ mdelay(10);
1612	+ register_pci_controller(&pc_host->pci_controller);
1613	+ return;
1614	+}
1615	+
1616	+/* Early PCI fixup for a device on the PCI-core bridge. */
1617	+static void bcma_core_pci_fixup_pcibridge(struct pci_dev *dev)
1618	+{
1619	+ if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
1620	+ /* This is not a device on the PCI-core bridge. */
1621	+ return;
1622	+ }
1623	+ if (PCI_SLOT(dev->devfn) != 0)
1624	+ return;
1625	+
1626	+ pr_info("PCI: Fixing up bridge %s\n", pci_name(dev));
1627	+
1628	+ /* Enable PCI bridge bus mastering and memory space */
1629	+ pci_set_master(dev);
1630	+ if (pcibios_enable_device(dev, ~0) < 0) {
1631	+ pr_err("PCI: BCMA bridge enable failed\n");
1632	+ return;
1633	+ }
1634	+
1635	+ /* Enable PCI bridge BAR1 prefetch and burst */
1636	+ pci_write_config_dword(dev, BCMA_PCI_BAR1_CONTROL, 3);
1637	+}
1638	+DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_pcibridge);
1639	+
1640	+/* Early PCI fixup for all PCI-cores to set the correct memory address. */
1641	+static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
1642	+{
1643	+ struct resource *res;
1644	+ int pos;
1645	+
1646	+ if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
1647	+ /* This is not a device on the PCI-core bridge. */
1648	+ return;
1649	+ }
1650	+ if (PCI_SLOT(dev->devfn) == 0)
1651	+ return;
1652	+
1653	+ pr_info("PCI: Fixing up addresses %s\n", pci_name(dev));
1654	+
1655	+ for (pos = 0; pos < 6; pos++) {
1656	+ res = &dev->resource[pos];
1657	+ if (res->flags & (IORESOURCE_IO \| IORESOURCE_MEM))
1658	+ pci_assign_resource(dev, pos);
1659	+ }
1660	+}
1661	+DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
1662	+
1663	+/* This function is called when doing a pci_enable_device().
1664	+ * We must first check if the device is a device on the PCI-core bridge. */
1665	+int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
1666	+{
1667	+ struct bcma_drv_pci_host *pc_host;
1668	+
1669	+ if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
1670	+ /* This is not a device on the PCI-core bridge. */
1671	+ return -ENODEV;
1672	+ }
1673	+ pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
1674	+ pci_ops);
1675	+
1676	+ pr_info("PCI: Fixing up device %s\n", pci_name(dev));
1677	+
1678	+ /* Fix up interrupt lines */
1679	+ dev->irq = bcma_core_mips_irq(pc_host->pdev->core) + 2;
1680	+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
1681	+
1682	+ return 0;
1683	+}
1684	+EXPORT_SYMBOL(bcma_core_pci_plat_dev_init);
1685	+
1686	+/* PCI device IRQ mapping. */
1687	+int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev)
1688	+{
1689	+ struct bcma_drv_pci_host *pc_host;
1690	+
1691	+ if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
1692	+ /* This is not a device on the PCI-core bridge. */
1693	+ return -ENODEV;
1694	+ }
1695	+
1696	+ pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
1697	+ pci_ops);
1698	+ return bcma_core_mips_irq(pc_host->pdev->core) + 2;
1699	}
1700	+EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq);
1701	--- a/drivers/bcma/host_pci.c
1702	+++ b/drivers/bcma/host_pci.c
1703	@@ -18,7 +18,7 @@ static void bcma_host_pci_switch_core(st
1704	pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN2,
1705	core->wrap);
1706	core->bus->mapped_core = core;
1707	- pr_debug("Switched to core: 0x%X\n", core->id.id);
1708	+ bcma_debug(core->bus, "Switched to core: 0x%X\n", core->id.id);
1709	}
1710
1711	/* Provides access to the requested core. Returns base offset that has to be
1712	@@ -154,8 +154,8 @@ const struct bcma_host_ops bcma_host_pci
1713	.awrite32 = bcma_host_pci_awrite32,
1714	};
1715
1716	-static int bcma_host_pci_probe(struct pci_dev *dev,
1717	- const struct pci_device_id *id)
1718	+static int __devinit bcma_host_pci_probe(struct pci_dev *dev,
1719	+ const struct pci_device_id *id)
1720	{
1721	struct bcma_bus *bus;
1722	int err = -ENOMEM;
1723	@@ -188,7 +188,7 @@ static int bcma_host_pci_probe(struct pc
1724
1725	/* SSB needed additional powering up, do we have any AMBA PCI cards? */
1726	if (!pci_is_pcie(dev))
1727	- pr_err("PCI card detected, report problems.\n");
1728	+ bcma_err(bus, "PCI card detected, report problems.\n");
1729
1730	/* Map MMIO */
1731	err = -ENOMEM;
1732	@@ -201,6 +201,9 @@ static int bcma_host_pci_probe(struct pc
1733	bus->hosttype = BCMA_HOSTTYPE_PCI;
1734	bus->ops = &bcma_host_pci_ops;
1735
1736	+ bus->boardinfo.vendor = bus->host_pci->subsystem_vendor;
1737	+ bus->boardinfo.type = bus->host_pci->subsystem_device;
1738	+
1739	/* Register */
1740	err = bcma_bus_register(bus);
1741	if (err)
1742	@@ -222,7 +225,7 @@ err_kfree_bus:
1743	return err;
1744	}
1745
1746	-static void bcma_host_pci_remove(struct pci_dev *dev)
1747	+static void __devexit bcma_host_pci_remove(struct pci_dev *dev)
1748	{
1749	struct bcma_bus *bus = pci_get_drvdata(dev);
1750
1751	@@ -265,6 +268,7 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
1752
1753	static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
1754	{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
1755	+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) },
1756	{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
1757	{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
1758	{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
1759	@@ -277,7 +281,7 @@ static struct pci_driver bcma_pci_bridge
1760	.name = "bcma-pci-bridge",
1761	.id_table = bcma_pci_bridge_tbl,
1762	.probe = bcma_host_pci_probe,
1763	- .remove = bcma_host_pci_remove,
1764	+ .remove = __devexit_p(bcma_host_pci_remove),
1765	.driver.pm = BCMA_PM_OPS,
1766	};
1767
1768	--- a/drivers/bcma/main.c
1769	+++ b/drivers/bcma/main.c
1770	@@ -13,6 +13,12 @@
1771	MODULE_DESCRIPTION("Broadcom's specific AMBA driver");
1772	MODULE_LICENSE("GPL");
1773
1774	+/* contains the number the next bus should get. */
1775	+static unsigned int bcma_bus_next_num = 0;
1776	+
1777	+/* bcma_buses_mutex locks the bcma_bus_next_num */
1778	+static DEFINE_MUTEX(bcma_buses_mutex);
1779	+
1780	static int bcma_bus_match(struct device dev, struct device_driver drv);
1781	static int bcma_device_probe(struct device *dev);
1782	static int bcma_device_remove(struct device *dev);
1783	@@ -55,7 +61,14 @@ static struct bus_type bcma_bus_type = {
1784	.dev_attrs = bcma_device_attrs,
1785	};
1786
1787	-static struct bcma_device bcma_find_core(struct bcma_bus bus, u16 coreid)
1788	+static u16 bcma_cc_core_id(struct bcma_bus *bus)
1789	+{
1790	+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
1791	+ return BCMA_CORE_4706_CHIPCOMMON;
1792	+ return BCMA_CORE_CHIPCOMMON;
1793	+}
1794	+
1795	+struct bcma_device bcma_find_core(struct bcma_bus bus, u16 coreid)
1796	{
1797	struct bcma_device *core;
1798
1799	@@ -65,6 +78,7 @@ static struct bcma_device *bcma_find_cor
1800	}
1801	return NULL;
1802	}
1803	+EXPORT_SYMBOL_GPL(bcma_find_core);
1804
1805	static void bcma_release_core_dev(struct device *dev)
1806	{
1807	@@ -84,16 +98,18 @@ static int bcma_register_cores(struct bc
1808	list_for_each_entry(core, &bus->cores, list) {
1809	/* We support that cores ourself */
1810	switch (core->id.id) {
1811	+ case BCMA_CORE_4706_CHIPCOMMON:
1812	case BCMA_CORE_CHIPCOMMON:
1813	case BCMA_CORE_PCI:
1814	case BCMA_CORE_PCIE:
1815	case BCMA_CORE_MIPS_74K:
1816	+ case BCMA_CORE_4706_MAC_GBIT_COMMON:
1817	continue;
1818	}
1819
1820	core->dev.release = bcma_release_core_dev;
1821	core->dev.bus = &bcma_bus_type;
1822	- dev_set_name(&core->dev, "bcma%d:%d", 0/bus->num/, dev_id);
1823	+ dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
1824
1825	switch (bus->hosttype) {
1826	case BCMA_HOSTTYPE_PCI:
1827	@@ -111,8 +127,9 @@ static int bcma_register_cores(struct bc
1828
1829	err = device_register(&core->dev);
1830	if (err) {
1831	- pr_err("Could not register dev for core 0x%03X\n",
1832	- core->id.id);
1833	+ bcma_err(bus,
1834	+ "Could not register dev for core 0x%03X\n",
1835	+ core->id.id);
1836	continue;
1837	}
1838	core->dev_registered = true;
1839	@@ -132,20 +149,24 @@ static void bcma_unregister_cores(struct
1840	}
1841	}
1842
1843	-int bcma_bus_register(struct bcma_bus *bus)
1844	+int __devinit bcma_bus_register(struct bcma_bus *bus)
1845	{
1846	int err;
1847	struct bcma_device *core;
1848
1849	+ mutex_lock(&bcma_buses_mutex);
1850	+ bus->num = bcma_bus_next_num++;
1851	+ mutex_unlock(&bcma_buses_mutex);
1852	+
1853	/* Scan for devices (cores) */
1854	err = bcma_bus_scan(bus);
1855	if (err) {
1856	- pr_err("Failed to scan: %d\n", err);
1857	+ bcma_err(bus, "Failed to scan: %d\n", err);
1858	return -1;
1859	}
1860
1861	/* Init CC core */
1862	- core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
1863	+ core = bcma_find_core(bus, bcma_cc_core_id(bus));
1864	if (core) {
1865	bus->drv_cc.core = core;
1866	bcma_core_chipcommon_init(&bus->drv_cc);
1867	@@ -165,17 +186,24 @@ int bcma_bus_register(struct bcma_bus *b
1868	bcma_core_pci_init(&bus->drv_pci);
1869	}
1870
1871	+ /* Init GBIT MAC COMMON core */
1872	+ core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
1873	+ if (core) {
1874	+ bus->drv_gmac_cmn.core = core;
1875	+ bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn);
1876	+ }
1877	+
1878	/* Try to get SPROM */
1879	err = bcma_sprom_get(bus);
1880	if (err == -ENOENT) {
1881	- pr_err("No SPROM available\n");
1882	+ bcma_err(bus, "No SPROM available\n");
1883	} else if (err)
1884	- pr_err("Failed to get SPROM: %d\n", err);
1885	+ bcma_err(bus, "Failed to get SPROM: %d\n", err);
1886
1887	/* Register found cores */
1888	bcma_register_cores(bus);
1889
1890	- pr_info("Bus registered\n");
1891	+ bcma_info(bus, "Bus registered\n");
1892
1893	return 0;
1894	}
1895	@@ -196,14 +224,14 @@ int __init bcma_bus_early_register(struc
1896	bcma_init_bus(bus);
1897
1898	match.manuf = BCMA_MANUF_BCM;
1899	- match.id = BCMA_CORE_CHIPCOMMON;
1900	+ match.id = bcma_cc_core_id(bus);
1901	match.class = BCMA_CL_SIM;
1902	match.rev = BCMA_ANY_REV;
1903
1904	/* Scan for chip common core */
1905	err = bcma_bus_scan_early(bus, &match, core_cc);
1906	if (err) {
1907	- pr_err("Failed to scan for common core: %d\n", err);
1908	+ bcma_err(bus, "Failed to scan for common core: %d\n", err);
1909	return -1;
1910	}
1911
1912	@@ -215,12 +243,12 @@ int __init bcma_bus_early_register(struc
1913	/* Scan for mips core */
1914	err = bcma_bus_scan_early(bus, &match, core_mips);
1915	if (err) {
1916	- pr_err("Failed to scan for mips core: %d\n", err);
1917	+ bcma_err(bus, "Failed to scan for mips core: %d\n", err);
1918	return -1;
1919	}
1920
1921	/* Init CC core */
1922	- core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
1923	+ core = bcma_find_core(bus, bcma_cc_core_id(bus));
1924	if (core) {
1925	bus->drv_cc.core = core;
1926	bcma_core_chipcommon_init(&bus->drv_cc);
1927	@@ -233,7 +261,7 @@ int __init bcma_bus_early_register(struc
1928	bcma_core_mips_init(&bus->drv_mips);
1929	}
1930
1931	- pr_info("Early bus registered\n");
1932	+ bcma_info(bus, "Early bus registered\n");
1933
1934	return 0;
1935	}
1936	@@ -259,8 +287,7 @@ int bcma_bus_resume(struct bcma_bus *bus
1937	struct bcma_device *core;
1938
1939	/* Init CC core */
1940	- core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
1941	- if (core) {
1942	+ if (bus->drv_cc.core) {
1943	bus->drv_cc.setup_done = false;
1944	bcma_core_chipcommon_init(&bus->drv_cc);
1945	}
1946	--- a/drivers/bcma/scan.c
1947	+++ b/drivers/bcma/scan.c
1948	@@ -19,15 +19,27 @@ struct bcma_device_id_name {
1949	u16 id;
1950	const char *name;
1951	};
1952	-struct bcma_device_id_name bcma_device_names[] = {
1953	+
1954	+static const struct bcma_device_id_name bcma_arm_device_names[] = {
1955	+ { BCMA_CORE_4706_MAC_GBIT_COMMON, "BCM4706 GBit MAC Common" },
1956	+ { BCMA_CORE_ARM_1176, "ARM 1176" },
1957	+ { BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" },
1958	+ { BCMA_CORE_ARM_CM3, "ARM CM3" },
1959	+};
1960	+
1961	+static const struct bcma_device_id_name bcma_bcm_device_names[] = {
1962	{ BCMA_CORE_OOB_ROUTER, "OOB Router" },
1963	+ { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
1964	+ { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
1965	+ { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
1966	+ { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
1967	+ { BCMA_CORE_ALTA, "ALTA (I2S)" },
1968	{ BCMA_CORE_INVALID, "Invalid" },
1969	{ BCMA_CORE_CHIPCOMMON, "ChipCommon" },
1970	{ BCMA_CORE_ILINE20, "ILine 20" },
1971	{ BCMA_CORE_SRAM, "SRAM" },
1972	{ BCMA_CORE_SDRAM, "SDRAM" },
1973	{ BCMA_CORE_PCI, "PCI" },
1974	- { BCMA_CORE_MIPS, "MIPS" },
1975	{ BCMA_CORE_ETHERNET, "Fast Ethernet" },
1976	{ BCMA_CORE_V90, "V90" },
1977	{ BCMA_CORE_USB11_HOSTDEV, "USB 1.1 Hostdev" },
1978	@@ -44,7 +56,6 @@ struct bcma_device_id_name bcma_device_n
1979	{ BCMA_CORE_PHY_A, "PHY A" },
1980	{ BCMA_CORE_PHY_B, "PHY B" },
1981	{ BCMA_CORE_PHY_G, "PHY G" },
1982	- { BCMA_CORE_MIPS_3302, "MIPS 3302" },
1983	{ BCMA_CORE_USB11_HOST, "USB 1.1 Host" },
1984	{ BCMA_CORE_USB11_DEV, "USB 1.1 Device" },
1985	{ BCMA_CORE_USB20_HOST, "USB 2.0 Host" },
1986	@@ -58,15 +69,11 @@ struct bcma_device_id_name bcma_device_n
1987	{ BCMA_CORE_PHY_N, "PHY N" },
1988	{ BCMA_CORE_SRAM_CTL, "SRAM Controller" },
1989	{ BCMA_CORE_MINI_MACPHY, "Mini MACPHY" },
1990	- { BCMA_CORE_ARM_1176, "ARM 1176" },
1991	- { BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" },
1992	{ BCMA_CORE_PHY_LP, "PHY LP" },
1993	{ BCMA_CORE_PMU, "PMU" },
1994	{ BCMA_CORE_PHY_SSN, "PHY SSN" },
1995	{ BCMA_CORE_SDIO_DEV, "SDIO Device" },
1996	- { BCMA_CORE_ARM_CM3, "ARM CM3" },
1997	{ BCMA_CORE_PHY_HT, "PHY HT" },
1998	- { BCMA_CORE_MIPS_74K, "MIPS 74K" },
1999	{ BCMA_CORE_MAC_GBIT, "GBit MAC" },
2000	{ BCMA_CORE_DDR12_MEM_CTL, "DDR1/DDR2 Memory Controller" },
2001	{ BCMA_CORE_PCIE_RC, "PCIe Root Complex" },
2002	@@ -79,16 +86,41 @@ struct bcma_device_id_name bcma_device_n
2003	{ BCMA_CORE_SHIM, "SHIM" },
2004	{ BCMA_CORE_DEFAULT, "Default" },
2005	};
2006	-const char bcma_device_name(struct bcma_device_id id)
2007	+
2008	+static const struct bcma_device_id_name bcma_mips_device_names[] = {
2009	+ { BCMA_CORE_MIPS, "MIPS" },
2010	+ { BCMA_CORE_MIPS_3302, "MIPS 3302" },
2011	+ { BCMA_CORE_MIPS_74K, "MIPS 74K" },
2012	+};
2013	+
2014	+static const char bcma_device_name(const struct bcma_device_id id)
2015	{
2016	- int i;
2017	+ const struct bcma_device_id_name *names;
2018	+ int size, i;
2019
2020	- if (id->manuf == BCMA_MANUF_BCM) {
2021	- for (i = 0; i < ARRAY_SIZE(bcma_device_names); i++) {
2022	- if (bcma_device_names[i].id == id->id)
2023	- return bcma_device_names[i].name;
2024	- }
2025	+ /* search manufacturer specific names */
2026	+ switch (id->manuf) {
2027	+ case BCMA_MANUF_ARM:
2028	+ names = bcma_arm_device_names;
2029	+ size = ARRAY_SIZE(bcma_arm_device_names);
2030	+ break;
2031	+ case BCMA_MANUF_BCM:
2032	+ names = bcma_bcm_device_names;
2033	+ size = ARRAY_SIZE(bcma_bcm_device_names);
2034	+ break;
2035	+ case BCMA_MANUF_MIPS:
2036	+ names = bcma_mips_device_names;
2037	+ size = ARRAY_SIZE(bcma_mips_device_names);
2038	+ break;
2039	+ default:
2040	+ return "UNKNOWN";
2041	+ }
2042	+
2043	+ for (i = 0; i < size; i++) {
2044	+ if (names[i].id == id->id)
2045	+ return names[i].name;
2046	}
2047	+
2048	return "UNKNOWN";
2049	}
2050
2051	@@ -212,6 +244,17 @@ static struct bcma_device *bcma_find_cor
2052	return NULL;
2053	}
2054
2055	+static struct bcma_device bcma_find_core_reverse(struct bcma_bus bus, u16 coreid)
2056	+{
2057	+ struct bcma_device *core;
2058	+
2059	+ list_for_each_entry_reverse(core, &bus->cores, list) {
2060	+ if (core->id.id == coreid)
2061	+ return core;
2062	+ }
2063	+ return NULL;
2064	+}
2065	+
2066	static int bcma_get_next_core(struct bcma_bus bus, u32 __iomem *eromptr,
2067	struct bcma_device_id *match, int core_num,
2068	struct bcma_device *core)
2069	@@ -252,11 +295,15 @@ static int bcma_get_next_core(struct bcm
2070
2071	/* check if component is a core at all */
2072	if (wrappers[0] + wrappers[1] == 0) {
2073	- /* we could save addrl of the router
2074	- if (cid == BCMA_CORE_OOB_ROUTER)
2075	- */
2076	- bcma_erom_skip_component(bus, eromptr);
2077	- return -ENXIO;
2078	+ /* Some specific cores don't need wrappers */
2079	+ switch (core->id.id) {
2080	+ case BCMA_CORE_4706_MAC_GBIT_COMMON:
2081	+ /* Not used yet: case BCMA_CORE_OOB_ROUTER: */
2082	+ break;
2083	+ default:
2084	+ bcma_erom_skip_component(bus, eromptr);
2085	+ return -ENXIO;
2086	+ }
2087	}
2088
2089	if (bcma_erom_is_bridge(bus, eromptr)) {
2090	@@ -286,6 +333,23 @@ static int bcma_get_next_core(struct bcm
2091	return -EILSEQ;
2092	}
2093
2094	+ /* First Slave Address Descriptor should be port 0:
2095	+ * the main register space for the core
2096	+ */
2097	+ tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0);
2098	+ if (tmp <= 0) {
2099	+ /* Try again to see if it is a bridge */
2100	+ tmp = bcma_erom_get_addr_desc(bus, eromptr,
2101	+ SCAN_ADDR_TYPE_BRIDGE, 0);
2102	+ if (tmp <= 0) {
2103	+ return -EILSEQ;
2104	+ } else {
2105	+ bcma_info(bus, "Bridge found\n");
2106	+ return -ENXIO;
2107	+ }
2108	+ }
2109	+ core->addr = tmp;
2110	+
2111	/* get & parse slave ports */
2112	for (i = 0; i < ports[1]; i++) {
2113	for (j = 0; ; j++) {
2114	@@ -298,7 +362,7 @@ static int bcma_get_next_core(struct bcm
2115	break;
2116	} else {
2117	if (i == 0 && j == 0)
2118	- core->addr = tmp;
2119	+ core->addr1 = tmp;
2120	}
2121	}
2122	}
2123	@@ -353,6 +417,7 @@ static int bcma_get_next_core(struct bcm
2124	void bcma_init_bus(struct bcma_bus *bus)
2125	{
2126	s32 tmp;
2127	+ struct bcma_chipinfo *chipinfo = &(bus->chipinfo);
2128
2129	if (bus->init_done)
2130	return;
2131	@@ -363,9 +428,12 @@ void bcma_init_bus(struct bcma_bus *bus)
2132	bcma_scan_switch_core(bus, BCMA_ADDR_BASE);
2133
2134	tmp = bcma_scan_read32(bus, 0, BCMA_CC_ID);
2135	- bus->chipinfo.id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
2136	- bus->chipinfo.rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
2137	- bus->chipinfo.pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
2138	+ chipinfo->id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
2139	+ chipinfo->rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
2140	+ chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
2141	+ bcma_info(bus, "Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
2142	+ chipinfo->id, chipinfo->rev, chipinfo->pkg);
2143	+
2144	bus->init_done = true;
2145	}
2146
2147	@@ -392,6 +460,7 @@ int bcma_bus_scan(struct bcma_bus *bus)
2148	bcma_scan_switch_core(bus, erombase);
2149
2150	while (eromptr < eromend) {
2151	+ struct bcma_device *other_core;
2152	struct bcma_device core = kzalloc(sizeof(core), GFP_KERNEL);
2153	if (!core)
2154	return -ENOMEM;
2155	@@ -414,14 +483,15 @@ int bcma_bus_scan(struct bcma_bus *bus)
2156
2157	core->core_index = core_num++;
2158	bus->nr_cores++;
2159	+ other_core = bcma_find_core_reverse(bus, core->id.id);
2160	+ core->core_unit = (other_core == NULL) ? 0 : other_core->core_unit + 1;
2161
2162	- pr_info("Core %d found: %s "
2163	- "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
2164	- core->core_index, bcma_device_name(&core->id),
2165	- core->id.manuf, core->id.id, core->id.rev,
2166	- core->id.class);
2167	+ bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
2168	+ core->core_index, bcma_device_name(&core->id),
2169	+ core->id.manuf, core->id.id, core->id.rev,
2170	+ core->id.class);
2171
2172	- list_add(&core->list, &bus->cores);
2173	+ list_add_tail(&core->list, &bus->cores);
2174	}
2175
2176	if (bus->hosttype == BCMA_HOSTTYPE_SOC)
2177	@@ -471,13 +541,12 @@ int __init bcma_bus_scan_early(struct bc
2178
2179	core->core_index = core_num++;
2180	bus->nr_cores++;
2181	- pr_info("Core %d found: %s "
2182	- "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
2183	- core->core_index, bcma_device_name(&core->id),
2184	- core->id.manuf, core->id.id, core->id.rev,
2185	- core->id.class);
2186	+ bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
2187	+ core->core_index, bcma_device_name(&core->id),
2188	+ core->id.manuf, core->id.id, core->id.rev,
2189	+ core->id.class);
2190
2191	- list_add(&core->list, &bus->cores);
2192	+ list_add_tail(&core->list, &bus->cores);
2193	err = 0;
2194	break;
2195	}
2196	--- a/drivers/bcma/scan.h
2197	+++ b/drivers/bcma/scan.h
2198	@@ -27,7 +27,7 @@
2199	#define SCAN_CIB_NMW 0x0007C000
2200	#define SCAN_CIB_NMW_SHIFT 14
2201	#define SCAN_CIB_NSW 0x00F80000
2202	-#define SCAN_CIB_NSW_SHIFT 17
2203	+#define SCAN_CIB_NSW_SHIFT 19
2204	#define SCAN_CIB_REV 0xFF000000
2205	#define SCAN_CIB_REV_SHIFT 24
2206
2207	--- a/drivers/bcma/sprom.c
2208	+++ b/drivers/bcma/sprom.c
2209	@@ -2,6 +2,8 @@
2210	* Broadcom specific AMBA
2211	* SPROM reading
2212	*
2213	+ * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
2214	+ *
2215	* Licensed under the GNU/GPL. See COPYING for details.
2216	*/
2217
2218	@@ -14,7 +16,57 @@
2219	#include <linux/dma-mapping.h>
2220	#include <linux/slab.h>
2221
2222	-#define SPOFF(offset) ((offset) / sizeof(u16))
2223	+static int(get_fallback_sprom)(struct bcma_bus dev, struct ssb_sprom *out);
2224	+
2225	+/**
2226	+ * bcma_arch_register_fallback_sprom - Registers a method providing a
2227	+ * fallback SPROM if no SPROM is found.
2228	+ *
2229	+ * @sprom_callback: The callback function.
2230	+ *
2231	+ * With this function the architecture implementation may register a
2232	+ * callback handler which fills the SPROM data structure. The fallback is
2233	+ * used for PCI based BCMA devices, where no valid SPROM can be found
2234	+ * in the shadow registers and to provide the SPROM for SoCs where BCMA is
2235	+ * to controll the system bus.
2236	+ *
2237	+ * This function is useful for weird architectures that have a half-assed
2238	+ * BCMA device hardwired to their PCI bus.
2239	+ *
2240	+ * This function is available for architecture code, only. So it is not
2241	+ * exported.
2242	+ */
2243	+int bcma_arch_register_fallback_sprom(int (sprom_callback)(struct bcma_bus bus,
2244	+ struct ssb_sprom *out))
2245	+{
2246	+ if (get_fallback_sprom)
2247	+ return -EEXIST;
2248	+ get_fallback_sprom = sprom_callback;
2249	+
2250	+ return 0;
2251	+}
2252	+
2253	+static int bcma_fill_sprom_with_fallback(struct bcma_bus *bus,
2254	+ struct ssb_sprom *out)
2255	+{
2256	+ int err;
2257	+
2258	+ if (!get_fallback_sprom) {
2259	+ err = -ENOENT;
2260	+ goto fail;
2261	+ }
2262	+
2263	+ err = get_fallback_sprom(bus, out);
2264	+ if (err)
2265	+ goto fail;
2266	+
2267	+ bcma_debug(bus, "Using SPROM revision %d provided by platform.\n",
2268	+ bus->sprom.revision);
2269	+ return 0;
2270	+fail:
2271	+ bcma_warn(bus, "Using fallback SPROM failed (err %d)\n", err);
2272	+ return err;
2273	+}
2274
2275	/**************************************************
2276	* R/W ops.
2277	@@ -124,10 +176,37 @@ static int bcma_sprom_valid(const u16 *s
2278	* SPROM extraction.
2279	**************************************************/
2280
2281	+#define SPOFF(offset) ((offset) / sizeof(u16))
2282	+
2283	+#define SPEX(_field, _offset, _mask, _shift) \
2284	+ bus->sprom._field = ((sprom[SPOFF(_offset)] & (_mask)) >> (_shift))
2285	+
2286	+#define SPEX32(_field, _offset, _mask, _shift) \
2287	+ bus->sprom._field = ((((u32)sprom[SPOFF((_offset)+2)] << 16 \| \
2288	+ sprom[SPOFF(_offset)]) & (_mask)) >> (_shift))
2289	+
2290	+#define SPEX_ARRAY8(_field, _offset, _mask, _shift) \
2291	+ do { \
2292	+ SPEX(_field[0], _offset + 0, _mask, _shift); \
2293	+ SPEX(_field[1], _offset + 2, _mask, _shift); \
2294	+ SPEX(_field[2], _offset + 4, _mask, _shift); \
2295	+ SPEX(_field[3], _offset + 6, _mask, _shift); \
2296	+ SPEX(_field[4], _offset + 8, _mask, _shift); \
2297	+ SPEX(_field[5], _offset + 10, _mask, _shift); \
2298	+ SPEX(_field[6], _offset + 12, _mask, _shift); \
2299	+ SPEX(_field[7], _offset + 14, _mask, _shift); \
2300	+ } while (0)
2301	+
2302	static void bcma_sprom_extract_r8(struct bcma_bus bus, const u16 sprom)
2303	{
2304	- u16 v;
2305	+ u16 v, o;
2306	int i;
2307	+ u16 pwr_info_offset[] = {
2308	+ SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
2309	+ SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
2310	+ };
2311	+ BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
2312	+ ARRAY_SIZE(bus->sprom.core_pwr_info));
2313
2314	bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
2315	SSB_SPROM_REVISION_REV;
2316	@@ -137,102 +216,378 @@ static void bcma_sprom_extract_r8(struct
2317	(((__be16 )bus->sprom.il0mac) + i) = cpu_to_be16(v);
2318	}
2319
2320	- bus->sprom.board_rev = sprom[SPOFF(SSB_SPROM8_BOARDREV)];
2321	+ SPEX(board_rev, SSB_SPROM8_BOARDREV, ~0, 0);
2322
2323	- bus->sprom.txpid2g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] &
2324	- SSB_SPROM4_TXPID2G0) >> SSB_SPROM4_TXPID2G0_SHIFT;
2325	- bus->sprom.txpid2g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] &
2326	- SSB_SPROM4_TXPID2G1) >> SSB_SPROM4_TXPID2G1_SHIFT;
2327	- bus->sprom.txpid2g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] &
2328	- SSB_SPROM4_TXPID2G2) >> SSB_SPROM4_TXPID2G2_SHIFT;
2329	- bus->sprom.txpid2g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] &
2330	- SSB_SPROM4_TXPID2G3) >> SSB_SPROM4_TXPID2G3_SHIFT;
2331	-
2332	- bus->sprom.txpid5gl[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] &
2333	- SSB_SPROM4_TXPID5GL0) >> SSB_SPROM4_TXPID5GL0_SHIFT;
2334	- bus->sprom.txpid5gl[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] &
2335	- SSB_SPROM4_TXPID5GL1) >> SSB_SPROM4_TXPID5GL1_SHIFT;
2336	- bus->sprom.txpid5gl[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] &
2337	- SSB_SPROM4_TXPID5GL2) >> SSB_SPROM4_TXPID5GL2_SHIFT;
2338	- bus->sprom.txpid5gl[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] &
2339	- SSB_SPROM4_TXPID5GL3) >> SSB_SPROM4_TXPID5GL3_SHIFT;
2340	-
2341	- bus->sprom.txpid5g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] &
2342	- SSB_SPROM4_TXPID5G0) >> SSB_SPROM4_TXPID5G0_SHIFT;
2343	- bus->sprom.txpid5g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] &
2344	- SSB_SPROM4_TXPID5G1) >> SSB_SPROM4_TXPID5G1_SHIFT;
2345	- bus->sprom.txpid5g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] &
2346	- SSB_SPROM4_TXPID5G2) >> SSB_SPROM4_TXPID5G2_SHIFT;
2347	- bus->sprom.txpid5g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] &
2348	- SSB_SPROM4_TXPID5G3) >> SSB_SPROM4_TXPID5G3_SHIFT;
2349	-
2350	- bus->sprom.txpid5gh[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] &
2351	- SSB_SPROM4_TXPID5GH0) >> SSB_SPROM4_TXPID5GH0_SHIFT;
2352	- bus->sprom.txpid5gh[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] &
2353	- SSB_SPROM4_TXPID5GH1) >> SSB_SPROM4_TXPID5GH1_SHIFT;
2354	- bus->sprom.txpid5gh[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] &
2355	- SSB_SPROM4_TXPID5GH2) >> SSB_SPROM4_TXPID5GH2_SHIFT;
2356	- bus->sprom.txpid5gh[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] &
2357	- SSB_SPROM4_TXPID5GH3) >> SSB_SPROM4_TXPID5GH3_SHIFT;
2358	-
2359	- bus->sprom.boardflags_lo = sprom[SPOFF(SSB_SPROM8_BFLLO)];
2360	- bus->sprom.boardflags_hi = sprom[SPOFF(SSB_SPROM8_BFLHI)];
2361	- bus->sprom.boardflags2_lo = sprom[SPOFF(SSB_SPROM8_BFL2LO)];
2362	- bus->sprom.boardflags2_hi = sprom[SPOFF(SSB_SPROM8_BFL2HI)];
2363	-
2364	- bus->sprom.country_code = sprom[SPOFF(SSB_SPROM8_CCODE)];
2365	-
2366	- bus->sprom.fem.ghz2.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
2367	- SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT;
2368	- bus->sprom.fem.ghz2.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
2369	- SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT;
2370	- bus->sprom.fem.ghz2.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
2371	- SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT;
2372	- bus->sprom.fem.ghz2.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
2373	- SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT;
2374	- bus->sprom.fem.ghz2.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
2375	- SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT;
2376	-
2377	- bus->sprom.fem.ghz5.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
2378	- SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT;
2379	- bus->sprom.fem.ghz5.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
2380	- SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT;
2381	- bus->sprom.fem.ghz5.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
2382	- SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT;
2383	- bus->sprom.fem.ghz5.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
2384	- SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT;
2385	- bus->sprom.fem.ghz5.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
2386	- SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT;
2387	+ SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G0,
2388	+ SSB_SPROM4_TXPID2G0_SHIFT);
2389	+ SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G1,
2390	+ SSB_SPROM4_TXPID2G1_SHIFT);
2391	+ SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23, SSB_SPROM4_TXPID2G2,
2392	+ SSB_SPROM4_TXPID2G2_SHIFT);
2393	+ SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23, SSB_SPROM4_TXPID2G3,
2394	+ SSB_SPROM4_TXPID2G3_SHIFT);
2395	+
2396	+ SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01, SSB_SPROM4_TXPID5GL0,
2397	+ SSB_SPROM4_TXPID5GL0_SHIFT);
2398	+ SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01, SSB_SPROM4_TXPID5GL1,
2399	+ SSB_SPROM4_TXPID5GL1_SHIFT);
2400	+ SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23, SSB_SPROM4_TXPID5GL2,
2401	+ SSB_SPROM4_TXPID5GL2_SHIFT);
2402	+ SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23, SSB_SPROM4_TXPID5GL3,
2403	+ SSB_SPROM4_TXPID5GL3_SHIFT);
2404	+
2405	+ SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01, SSB_SPROM4_TXPID5G0,
2406	+ SSB_SPROM4_TXPID5G0_SHIFT);
2407	+ SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01, SSB_SPROM4_TXPID5G1,
2408	+ SSB_SPROM4_TXPID5G1_SHIFT);
2409	+ SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23, SSB_SPROM4_TXPID5G2,
2410	+ SSB_SPROM4_TXPID5G2_SHIFT);
2411	+ SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23, SSB_SPROM4_TXPID5G3,
2412	+ SSB_SPROM4_TXPID5G3_SHIFT);
2413	+
2414	+ SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01, SSB_SPROM4_TXPID5GH0,
2415	+ SSB_SPROM4_TXPID5GH0_SHIFT);
2416	+ SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01, SSB_SPROM4_TXPID5GH1,
2417	+ SSB_SPROM4_TXPID5GH1_SHIFT);
2418	+ SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23, SSB_SPROM4_TXPID5GH2,
2419	+ SSB_SPROM4_TXPID5GH2_SHIFT);
2420	+ SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23, SSB_SPROM4_TXPID5GH3,
2421	+ SSB_SPROM4_TXPID5GH3_SHIFT);
2422	+
2423	+ SPEX(boardflags_lo, SSB_SPROM8_BFLLO, ~0, 0);
2424	+ SPEX(boardflags_hi, SSB_SPROM8_BFLHI, ~0, 0);
2425	+ SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, ~0, 0);
2426	+ SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, ~0, 0);
2427	+
2428	+ SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
2429	+ SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
2430	+
2431	+ /* Extract cores power info info */
2432	+ for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
2433	+ o = pwr_info_offset[i];
2434	+ SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
2435	+ SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
2436	+ SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
2437	+ SSB_SPROM8_2G_MAXP, 0);
2438	+
2439	+ SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
2440	+ SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
2441	+ SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
2442	+
2443	+ SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
2444	+ SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
2445	+ SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
2446	+ SSB_SPROM8_5G_MAXP, 0);
2447	+ SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
2448	+ SSB_SPROM8_5GH_MAXP, 0);
2449	+ SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
2450	+ SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
2451	+
2452	+ SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
2453	+ SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
2454	+ SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
2455	+ SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
2456	+ SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
2457	+ SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
2458	+ SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
2459	+ SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
2460	+ SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
2461	+ }
2462	+
2463	+ SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_TSSIPOS,
2464	+ SSB_SROM8_FEM_TSSIPOS_SHIFT);
2465	+ SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_EXTPA_GAIN,
2466	+ SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
2467	+ SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_PDET_RANGE,
2468	+ SSB_SROM8_FEM_PDET_RANGE_SHIFT);
2469	+ SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_TR_ISO,
2470	+ SSB_SROM8_FEM_TR_ISO_SHIFT);
2471	+ SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_ANTSWLUT,
2472	+ SSB_SROM8_FEM_ANTSWLUT_SHIFT);
2473	+
2474	+ SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_TSSIPOS,
2475	+ SSB_SROM8_FEM_TSSIPOS_SHIFT);
2476	+ SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_EXTPA_GAIN,
2477	+ SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
2478	+ SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_PDET_RANGE,
2479	+ SSB_SROM8_FEM_PDET_RANGE_SHIFT);
2480	+ SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_TR_ISO,
2481	+ SSB_SROM8_FEM_TR_ISO_SHIFT);
2482	+ SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_ANTSWLUT,
2483	+ SSB_SROM8_FEM_ANTSWLUT_SHIFT);
2484	+
2485	+ SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,
2486	+ SSB_SPROM8_ANTAVAIL_A_SHIFT);
2487	+ SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,
2488	+ SSB_SPROM8_ANTAVAIL_BG_SHIFT);
2489	+ SPEX(maxpwr_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_MAXP_BG_MASK, 0);
2490	+ SPEX(itssi_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_ITSSI_BG,
2491	+ SSB_SPROM8_ITSSI_BG_SHIFT);
2492	+ SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);
2493	+ SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,
2494	+ SSB_SPROM8_ITSSI_A_SHIFT);
2495	+ SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);
2496	+ SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,
2497	+ SSB_SPROM8_MAXP_AL_SHIFT);
2498	+ SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);
2499	+ SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,
2500	+ SSB_SPROM8_GPIOA_P1_SHIFT);
2501	+ SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);
2502	+ SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,
2503	+ SSB_SPROM8_GPIOB_P3_SHIFT);
2504	+ SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);
2505	+ SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,
2506	+ SSB_SPROM8_TRI5G_SHIFT);
2507	+ SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);
2508	+ SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,
2509	+ SSB_SPROM8_TRI5GH_SHIFT);
2510	+ SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G,
2511	+ SSB_SPROM8_RXPO2G_SHIFT);
2512	+ SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,
2513	+ SSB_SPROM8_RXPO5G_SHIFT);
2514	+ SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);
2515	+ SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,
2516	+ SSB_SPROM8_RSSISMC2G_SHIFT);
2517	+ SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,
2518	+ SSB_SPROM8_RSSISAV2G_SHIFT);
2519	+ SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,
2520	+ SSB_SPROM8_BXA2G_SHIFT);
2521	+ SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);
2522	+ SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,
2523	+ SSB_SPROM8_RSSISMC5G_SHIFT);
2524	+ SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,
2525	+ SSB_SPROM8_RSSISAV5G_SHIFT);
2526	+ SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,
2527	+ SSB_SPROM8_BXA5G_SHIFT);
2528	+
2529	+ SPEX(pa0b0, SSB_SPROM8_PA0B0, ~0, 0);
2530	+ SPEX(pa0b1, SSB_SPROM8_PA0B1, ~0, 0);
2531	+ SPEX(pa0b2, SSB_SPROM8_PA0B2, ~0, 0);
2532	+ SPEX(pa1b0, SSB_SPROM8_PA1B0, ~0, 0);
2533	+ SPEX(pa1b1, SSB_SPROM8_PA1B1, ~0, 0);
2534	+ SPEX(pa1b2, SSB_SPROM8_PA1B2, ~0, 0);
2535	+ SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, ~0, 0);
2536	+ SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, ~0, 0);
2537	+ SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, ~0, 0);
2538	+ SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, ~0, 0);
2539	+ SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, ~0, 0);
2540	+ SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, ~0, 0);
2541	+ SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, ~0, 0);
2542	+ SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, ~0, 0);
2543	+ SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, ~0, 0);
2544	+ SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, ~0, 0);
2545	+ SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, ~0, 0);
2546	+
2547	+ /* Extract the antenna gain values. */
2548	+ SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
2549	+ SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
2550	+ SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
2551	+ SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
2552	+ SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
2553	+ SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
2554	+ SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
2555	+ SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
2556	+
2557	+ SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
2558	+ SSB_SPROM8_LEDDC_ON_SHIFT);
2559	+ SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
2560	+ SSB_SPROM8_LEDDC_OFF_SHIFT);
2561	+
2562	+ SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
2563	+ SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
2564	+ SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
2565	+ SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
2566	+ SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
2567	+ SSB_SPROM8_TXRXC_SWITCH_SHIFT);
2568	+
2569	+ SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
2570	+
2571	+ SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
2572	+ SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
2573	+ SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
2574	+ SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
2575	+
2576	+ SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
2577	+ SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
2578	+ SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
2579	+ SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
2580	+ SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
2581	+ SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
2582	+ SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
2583	+ SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
2584	+ SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
2585	+ SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
2586	+ SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
2587	+ SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
2588	+ SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
2589	+ SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
2590	+ SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
2591	+ SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
2592	+ SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
2593	+ SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
2594	+ SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
2595	+ SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
2596	+
2597	+ SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
2598	+ SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
2599	+ SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
2600	+ SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
2601	+
2602	+ SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
2603	+ SSB_SPROM8_THERMAL_TRESH_SHIFT);
2604	+ SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
2605	+ SSB_SPROM8_THERMAL_OFFSET_SHIFT);
2606	+ SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
2607	+ SSB_SPROM8_TEMPDELTA_PHYCAL,
2608	+ SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
2609	+ SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
2610	+ SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
2611	+ SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
2612	+ SSB_SPROM8_TEMPDELTA_HYSTERESIS,
2613	+ SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
2614	+}
2615	+
2616	+/*
2617	+ * Indicates the presence of external SPROM.
2618	+ */
2619	+static bool bcma_sprom_ext_available(struct bcma_bus *bus)
2620	+{
2621	+ u32 chip_status;
2622	+ u32 srom_control;
2623	+ u32 present_mask;
2624	+
2625	+ if (bus->drv_cc.core->id.rev >= 31) {
2626	+ if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM))
2627	+ return false;
2628	+
2629	+ srom_control = bcma_read32(bus->drv_cc.core,
2630	+ BCMA_CC_SROM_CONTROL);
2631	+ return srom_control & BCMA_CC_SROM_CONTROL_PRESENT;
2632	+ }
2633	+
2634	+ /* older chipcommon revisions use chip status register */
2635	+ chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT);
2636	+ switch (bus->chipinfo.id) {
2637	+ case BCMA_CHIP_ID_BCM4313:
2638	+ present_mask = BCMA_CC_CHIPST_4313_SPROM_PRESENT;
2639	+ break;
2640	+
2641	+ case BCMA_CHIP_ID_BCM4331:
2642	+ present_mask = BCMA_CC_CHIPST_4331_SPROM_PRESENT;
2643	+ break;
2644	+
2645	+ default:
2646	+ return true;
2647	+ }
2648	+
2649	+ return chip_status & present_mask;
2650	+}
2651	+
2652	+/*
2653	+ * Indicates that on-chip OTP memory is present and enabled.
2654	+ */
2655	+static bool bcma_sprom_onchip_available(struct bcma_bus *bus)
2656	+{
2657	+ u32 chip_status;
2658	+ u32 otpsize = 0;
2659	+ bool present;
2660	+
2661	+ chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT);
2662	+ switch (bus->chipinfo.id) {
2663	+ case BCMA_CHIP_ID_BCM4313:
2664	+ present = chip_status & BCMA_CC_CHIPST_4313_OTP_PRESENT;
2665	+ break;
2666	+
2667	+ case BCMA_CHIP_ID_BCM4331:
2668	+ present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
2669	+ break;
2670	+
2671	+ case BCMA_CHIP_ID_BCM43224:
2672	+ case BCMA_CHIP_ID_BCM43225:
2673	+ /* for these chips OTP is always available */
2674	+ present = true;
2675	+ break;
2676	+
2677	+ default:
2678	+ present = false;
2679	+ break;
2680	+ }
2681	+
2682	+ if (present) {
2683	+ otpsize = bus->drv_cc.capabilities & BCMA_CC_CAP_OTPS;
2684	+ otpsize >>= BCMA_CC_CAP_OTPS_SHIFT;
2685	+ }
2686	+
2687	+ return otpsize != 0;
2688	+}
2689	+
2690	+/*
2691	+ * Verify OTP is filled and determine the byte
2692	+ * offset where SPROM data is located.
2693	+ *
2694	+ * On error, returns 0; byte offset otherwise.
2695	+ */
2696	+static int bcma_sprom_onchip_offset(struct bcma_bus *bus)
2697	+{
2698	+ struct bcma_device *cc = bus->drv_cc.core;
2699	+ u32 offset;
2700	+
2701	+ /* verify OTP status */
2702	+ if ((bcma_read32(cc, BCMA_CC_OTPS) & BCMA_CC_OTPS_GU_PROG_HW) == 0)
2703	+ return 0;
2704	+
2705	+ /* obtain bit offset from otplayout register */
2706	+ offset = (bcma_read32(cc, BCMA_CC_OTPL) & BCMA_CC_OTPL_GURGN_OFFSET);
2707	+ return BCMA_CC_SPROM + (offset >> 3);
2708	}
2709
2710	int bcma_sprom_get(struct bcma_bus *bus)
2711	{
2712	- u16 offset;
2713	+ u16 offset = BCMA_CC_SPROM;
2714	u16 *sprom;
2715	int err = 0;
2716
2717	if (!bus->drv_cc.core)
2718	return -EOPNOTSUPP;
2719
2720	- if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM))
2721	- return -ENOENT;
2722	+ if (!bcma_sprom_ext_available(bus)) {
2723	+ bool sprom_onchip;
2724	+
2725	+ /*
2726	+ * External SPROM takes precedence so check
2727	+ * on-chip OTP only when no external SPROM
2728	+ * is present.
2729	+ */
2730	+ sprom_onchip = bcma_sprom_onchip_available(bus);
2731	+ if (sprom_onchip) {
2732	+ /* determine offset */
2733	+ offset = bcma_sprom_onchip_offset(bus);
2734	+ }
2735	+ if (!offset \|\| !sprom_onchip) {
2736	+ /*
2737	+ * Maybe there is no SPROM on the device?
2738	+ * Now we ask the arch code if there is some sprom
2739	+ * available for this device in some other storage.
2740	+ */
2741	+ err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
2742	+ return err;
2743	+ }
2744	+ }
2745
2746	sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
2747	GFP_KERNEL);
2748	if (!sprom)
2749	return -ENOMEM;
2750
2751	- if (bus->chipinfo.id == 0x4331)
2752	+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 \|\|
2753	+ bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
2754	bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
2755
2756	- /* Most cards have SPROM moved by additional offset 0x30 (48 dwords).
2757	- * According to brcm80211 this applies to cards with PCIe rev >= 6
2758	- * TODO: understand this condition and use it */
2759	- offset = (bus->chipinfo.id == 0x4331) ? BCMA_CC_SPROM :
2760	- BCMA_CC_SPROM_PCIE6;
2761	+ bcma_debug(bus, "SPROM offset 0x%x\n", offset);
2762	bcma_sprom_read(bus, offset, sprom);
2763
2764	- if (bus->chipinfo.id == 0x4331)
2765	+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 \|\|
2766	+ bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
2767	bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
2768
2769	err = bcma_sprom_valid(sprom);
2770	--- a/include/linux/bcma/bcma.h
2771	+++ b/include/linux/bcma/bcma.h
2772	@@ -7,6 +7,7 @@
2773	#include <linux/bcma/bcma_driver_chipcommon.h>
2774	#include <linux/bcma/bcma_driver_pci.h>
2775	#include <linux/bcma/bcma_driver_mips.h>
2776	+#include <linux/bcma/bcma_driver_gmac_cmn.h>
2777	#include <linux/ssb/ssb.h> /* SPROM sharing */
2778
2779	#include "bcma_regs.h"
2780	@@ -26,6 +27,11 @@ struct bcma_chipinfo {
2781	u8 pkg;
2782	};
2783
2784	+struct bcma_boardinfo {
2785	+ u16 vendor;
2786	+ u16 type;
2787	+};
2788	+
2789	enum bcma_clkmode {
2790	BCMA_CLKMODE_FAST,
2791	BCMA_CLKMODE_DYNAMIC,
2792	@@ -65,6 +71,13 @@ struct bcma_host_ops {
2793
2794	/* Core-ID values. */
2795	#define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
2796	+#define BCMA_CORE_4706_CHIPCOMMON 0x500
2797	+#define BCMA_CORE_4706_SOC_RAM 0x50E
2798	+#define BCMA_CORE_4706_MAC_GBIT 0x52D
2799	+#define BCMA_CORE_AMEMC 0x52E /* DDR1/2 memory controller core */
2800	+#define BCMA_CORE_ALTA 0x534 /* I2S core */
2801	+#define BCMA_CORE_4706_MAC_GBIT_COMMON 0x5DC
2802	+#define BCMA_CORE_DDR23_PHY 0x5DD
2803	#define BCMA_CORE_INVALID 0x700
2804	#define BCMA_CORE_CHIPCOMMON 0x800
2805	#define BCMA_CORE_ILINE20 0x801
2806	@@ -125,6 +138,36 @@ struct bcma_host_ops {
2807
2808	#define BCMA_MAX_NR_CORES 16
2809
2810	+/* Chip IDs of PCIe devices */
2811	+#define BCMA_CHIP_ID_BCM4313 0x4313
2812	+#define BCMA_CHIP_ID_BCM43224 43224
2813	+#define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
2814	+#define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
2815	+#define BCMA_CHIP_ID_BCM43225 43225
2816	+#define BCMA_CHIP_ID_BCM43227 43227
2817	+#define BCMA_CHIP_ID_BCM43228 43228
2818	+#define BCMA_CHIP_ID_BCM43421 43421
2819	+#define BCMA_CHIP_ID_BCM43428 43428
2820	+#define BCMA_CHIP_ID_BCM43431 43431
2821	+#define BCMA_CHIP_ID_BCM43460 43460
2822	+#define BCMA_CHIP_ID_BCM4331 0x4331
2823	+#define BCMA_CHIP_ID_BCM6362 0x6362
2824	+#define BCMA_CHIP_ID_BCM4360 0x4360
2825	+#define BCMA_CHIP_ID_BCM4352 0x4352
2826	+
2827	+/* Chip IDs of SoCs */
2828	+#define BCMA_CHIP_ID_BCM4706 0x5300
2829	+#define BCMA_CHIP_ID_BCM4716 0x4716
2830	+#define BCMA_PKG_ID_BCM4716 8
2831	+#define BCMA_PKG_ID_BCM4717 9
2832	+#define BCMA_PKG_ID_BCM4718 10
2833	+#define BCMA_CHIP_ID_BCM47162 47162
2834	+#define BCMA_CHIP_ID_BCM4748 0x4748
2835	+#define BCMA_CHIP_ID_BCM4749 0x4749
2836	+#define BCMA_CHIP_ID_BCM5356 0x5356
2837	+#define BCMA_CHIP_ID_BCM5357 0x5357
2838	+#define BCMA_CHIP_ID_BCM53572 53572
2839	+
2840	struct bcma_device {
2841	struct bcma_bus *bus;
2842	struct bcma_device_id id;
2843	@@ -136,8 +179,10 @@ struct bcma_device {
2844	bool dev_registered;
2845
2846	u8 core_index;
2847	+ u8 core_unit;
2848
2849	u32 addr;
2850	+ u32 addr1;
2851	u32 wrap;
2852
2853	void __iomem *io_addr;
2854	@@ -175,6 +220,12 @@ int __bcma_driver_register(struct bcma_d
2855
2856	extern void bcma_driver_unregister(struct bcma_driver *drv);
2857
2858	+/* Set a fallback SPROM.
2859	+ * See kdoc at the function definition for complete documentation. */
2860	+extern int bcma_arch_register_fallback_sprom(
2861	+ int (sprom_callback)(struct bcma_bus bus,
2862	+ struct ssb_sprom *out));
2863	+
2864	struct bcma_bus {
2865	/* The MMIO area. */
2866	void __iomem *mmio;
2867	@@ -191,14 +242,18 @@ struct bcma_bus {
2868
2869	struct bcma_chipinfo chipinfo;
2870
2871	+ struct bcma_boardinfo boardinfo;
2872	+
2873	struct bcma_device *mapped_core;
2874	struct list_head cores;
2875	u8 nr_cores;
2876	u8 init_done:1;
2877	+ u8 num;
2878
2879	struct bcma_drv_cc drv_cc;
2880	struct bcma_drv_pci drv_pci;
2881	struct bcma_drv_mips drv_mips;
2882	+ struct bcma_drv_gmac_cmn drv_gmac_cmn;
2883
2884	/* We decided to share SPROM struct with SSB as long as we do not need
2885	* any hacks for BCMA. This simplifies drivers code. */
2886	@@ -282,6 +337,7 @@ static inline void bcma_maskset16(struct
2887	bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) \| set);
2888	}
2889
2890	+extern struct bcma_device bcma_find_core(struct bcma_bus bus, u16 coreid);
2891	extern bool bcma_core_is_enabled(struct bcma_device *core);
2892	extern void bcma_core_disable(struct bcma_device *core, u32 flags);
2893	extern int bcma_core_enable(struct bcma_device *core, u32 flags);
2894	--- a/include/linux/bcma/bcma_driver_chipcommon.h
2895	+++ b/include/linux/bcma/bcma_driver_chipcommon.h
2896	@@ -56,6 +56,9 @@
2897	#define BCMA_CC_OTPS_HW_PROTECT 0x00000001
2898	#define BCMA_CC_OTPS_SW_PROTECT 0x00000002
2899	#define BCMA_CC_OTPS_CID_PROTECT 0x00000004
2900	+#define BCMA_CC_OTPS_GU_PROG_IND 0x00000F00 /* General Use programmed indication */
2901	+#define BCMA_CC_OTPS_GU_PROG_IND_SHIFT 8
2902	+#define BCMA_CC_OTPS_GU_PROG_HW 0x00000100 /* HW region programmed */
2903	#define BCMA_CC_OTPC 0x0014 /* OTP control */
2904	#define BCMA_CC_OTPC_RECWAIT 0xFF000000
2905	#define BCMA_CC_OTPC_PROGWAIT 0x00FFFF00
2906	@@ -72,6 +75,8 @@
2907	#define BCMA_CC_OTPP_READ 0x40000000
2908	#define BCMA_CC_OTPP_START 0x80000000
2909	#define BCMA_CC_OTPP_BUSY 0x80000000
2910	+#define BCMA_CC_OTPL 0x001C /* OTP layout */
2911	+#define BCMA_CC_OTPL_GURGN_OFFSET 0x00000FFF /* offset of general use region */
2912	#define BCMA_CC_IRQSTAT 0x0020
2913	#define BCMA_CC_IRQMASK 0x0024
2914	#define BCMA_CC_IRQ_GPIO 0x00000001 /* gpio intr */
2915	@@ -79,6 +84,15 @@
2916	#define BCMA_CC_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */
2917	#define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */
2918	#define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */
2919	+#define BCMA_CC_CHIPST_4313_SPROM_PRESENT 1
2920	+#define BCMA_CC_CHIPST_4313_OTP_PRESENT 2
2921	+#define BCMA_CC_CHIPST_4331_SPROM_PRESENT 2
2922	+#define BCMA_CC_CHIPST_4331_OTP_PRESENT 4
2923	+#define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */
2924	+#define BCMA_CC_CHIPST_4706_SFLASH_PRESENT BIT(1) /* 0: parallel, 1: serial flash is present */
2925	+#define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
2926	+#define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
2927	+#define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
2928	#define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
2929	#define BCMA_CC_JCMD_START 0x80000000
2930	#define BCMA_CC_JCMD_BUSY 0x80000000
2931	@@ -181,6 +195,22 @@
2932	#define BCMA_CC_FLASH_CFG 0x0128
2933	#define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
2934	#define BCMA_CC_FLASH_WAITCNT 0x012C
2935	+#define BCMA_CC_SROM_CONTROL 0x0190
2936	+#define BCMA_CC_SROM_CONTROL_START 0x80000000
2937	+#define BCMA_CC_SROM_CONTROL_BUSY 0x80000000
2938	+#define BCMA_CC_SROM_CONTROL_OPCODE 0x60000000
2939	+#define BCMA_CC_SROM_CONTROL_OP_READ 0x00000000
2940	+#define BCMA_CC_SROM_CONTROL_OP_WRITE 0x20000000
2941	+#define BCMA_CC_SROM_CONTROL_OP_WRDIS 0x40000000
2942	+#define BCMA_CC_SROM_CONTROL_OP_WREN 0x60000000
2943	+#define BCMA_CC_SROM_CONTROL_OTPSEL 0x00000010
2944	+#define BCMA_CC_SROM_CONTROL_LOCK 0x00000008
2945	+#define BCMA_CC_SROM_CONTROL_SIZE_MASK 0x00000006
2946	+#define BCMA_CC_SROM_CONTROL_SIZE_1K 0x00000000
2947	+#define BCMA_CC_SROM_CONTROL_SIZE_4K 0x00000002
2948	+#define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004
2949	+#define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1
2950	+#define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001
2951	/* 0x1E0 is defined as shared BCMA_CLKCTLST */
2952	#define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
2953	#define BCMA_CC_UART0_DATA 0x0300
2954	@@ -240,7 +270,6 @@
2955	#define BCMA_CC_PLLCTL_ADDR 0x0660
2956	#define BCMA_CC_PLLCTL_DATA 0x0664
2957	#define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
2958	-#define BCMA_CC_SPROM_PCIE6 0x0830 /* SPROM beginning on PCIe rev >= 6 */
2959
2960	/* Divider allocation in 4716/47162/5356 */
2961	#define BCMA_CC_PMU5_MAINPLL_CPU 1
2962	@@ -256,6 +285,15 @@
2963
2964	/* 4706 PMU */
2965	#define BCMA_CC_PMU4706_MAINPLL_PLL0 0
2966	+#define BCMA_CC_PMU6_4706_PROCPLL_OFF 4 /* The CPU PLL */
2967	+#define BCMA_CC_PMU6_4706_PROC_P2DIV_MASK 0x000f0000
2968	+#define BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT 16
2969	+#define BCMA_CC_PMU6_4706_PROC_P1DIV_MASK 0x0000f000
2970	+#define BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT 12
2971	+#define BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK 0x00000ff8
2972	+#define BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT 3
2973	+#define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
2974	+#define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
2975
2976	/* ALP clock on pre-PMU chips */
2977	#define BCMA_CC_PMU_ALP_CLOCK 20000000
2978	@@ -284,6 +322,19 @@
2979	#define BCMA_CC_PPL_PCHI_OFF 5
2980	#define BCMA_CC_PPL_PCHI_MASK 0x0000003f
2981
2982	+#define BCMA_CC_PMU_PLL_CTL0 0
2983	+#define BCMA_CC_PMU_PLL_CTL1 1
2984	+#define BCMA_CC_PMU_PLL_CTL2 2
2985	+#define BCMA_CC_PMU_PLL_CTL3 3
2986	+#define BCMA_CC_PMU_PLL_CTL4 4
2987	+#define BCMA_CC_PMU_PLL_CTL5 5
2988	+
2989	+#define BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000
2990	+#define BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT 20
2991	+
2992	+#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
2993	+#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20
2994	+
2995	/* BCM4331 ChipControl numbers. */
2996	#define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */
2997	#define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */
2998	@@ -297,9 +348,18 @@
2999	#define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */
3000	#define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */
3001	#define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */
3002	+#define BCMA_CHIPCTL_4331_EXTPA_EN2 BIT(12) /* 0 ext pa disable, 1 ext pa enabled */
3003	#define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */
3004	#define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */
3005
3006	+/* 43224 chip-specific ChipControl register bits */
3007	+#define BCMA_CCTRL_43224_GPIO_TOGGLE 0x8000 /* gpio[3:0] pins as btcoex or s/w gpio */
3008	+#define BCMA_CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */
3009	+#define BCMA_CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */
3010	+
3011	+/* 4313 Chip specific ChipControl register bits */
3012	+#define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
3013	+
3014	/* Data for the PMU, if available.
3015	* Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
3016	*/
3017	@@ -387,5 +447,6 @@ extern void bcma_chipco_chipctl_maskset(
3018	u32 offset, u32 mask, u32 set);
3019	extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc,
3020	u32 offset, u32 mask, u32 set);
3021	+extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid);
3022
3023	#endif /* LINUX_BCMA_DRIVER_CC_H_ */
3024	--- /dev/null
3025	+++ b/include/linux/bcma/bcma_driver_gmac_cmn.h
3026	@@ -0,0 +1,100 @@
3027	+#ifndef LINUX_BCMA_DRIVER_GMAC_CMN_H_
3028	+#define LINUX_BCMA_DRIVER_GMAC_CMN_H_
3029	+
3030	+#include <linux/types.h>
3031	+
3032	+#define BCMA_GMAC_CMN_STAG0 0x000
3033	+#define BCMA_GMAC_CMN_STAG1 0x004
3034	+#define BCMA_GMAC_CMN_STAG2 0x008
3035	+#define BCMA_GMAC_CMN_STAG3 0x00C
3036	+#define BCMA_GMAC_CMN_PARSER_CTL 0x020
3037	+#define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
3038	+#define BCMA_GMAC_CMN_PHY_ACCESS 0x100
3039	+#define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
3040	+#define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
3041	+#define BCMA_GMAC_CMN_PA_ADDR_SHIFT 16
3042	+#define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
3043	+#define BCMA_GMAC_CMN_PA_REG_SHIFT 24
3044	+#define BCMA_GMAC_CMN_PA_WRITE 0x20000000
3045	+#define BCMA_GMAC_CMN_PA_START 0x40000000
3046	+#define BCMA_GMAC_CMN_PHY_CTL 0x104
3047	+#define BCMA_GMAC_CMN_PC_EPA_MASK 0x0000001f
3048	+#define BCMA_GMAC_CMN_PC_MCT_MASK 0x007f0000
3049	+#define BCMA_GMAC_CMN_PC_MCT_SHIFT 16
3050	+#define BCMA_GMAC_CMN_PC_MTE 0x00800000
3051	+#define BCMA_GMAC_CMN_GMAC0_RGMII_CTL 0x110
3052	+#define BCMA_GMAC_CMN_CFP_ACCESS 0x200
3053	+#define BCMA_GMAC_CMN_CFP_TCAM_DATA0 0x210
3054	+#define BCMA_GMAC_CMN_CFP_TCAM_DATA1 0x214
3055	+#define BCMA_GMAC_CMN_CFP_TCAM_DATA2 0x218
3056	+#define BCMA_GMAC_CMN_CFP_TCAM_DATA3 0x21C
3057	+#define BCMA_GMAC_CMN_CFP_TCAM_DATA4 0x220
3058	+#define BCMA_GMAC_CMN_CFP_TCAM_DATA5 0x224
3059	+#define BCMA_GMAC_CMN_CFP_TCAM_DATA6 0x228
3060	+#define BCMA_GMAC_CMN_CFP_TCAM_DATA7 0x22C
3061	+#define BCMA_GMAC_CMN_CFP_TCAM_MASK0 0x230
3062	+#define BCMA_GMAC_CMN_CFP_TCAM_MASK1 0x234
3063	+#define BCMA_GMAC_CMN_CFP_TCAM_MASK2 0x238
3064	+#define BCMA_GMAC_CMN_CFP_TCAM_MASK3 0x23C
3065	+#define BCMA_GMAC_CMN_CFP_TCAM_MASK4 0x240
3066	+#define BCMA_GMAC_CMN_CFP_TCAM_MASK5 0x244
3067	+#define BCMA_GMAC_CMN_CFP_TCAM_MASK6 0x248
3068	+#define BCMA_GMAC_CMN_CFP_TCAM_MASK7 0x24C
3069	+#define BCMA_GMAC_CMN_CFP_ACTION_DATA 0x250
3070	+#define BCMA_GMAC_CMN_TCAM_BIST_CTL 0x2A0
3071	+#define BCMA_GMAC_CMN_TCAM_BIST_STATUS 0x2A4
3072	+#define BCMA_GMAC_CMN_TCAM_CMP_STATUS 0x2A8
3073	+#define BCMA_GMAC_CMN_TCAM_DISABLE 0x2AC
3074	+#define BCMA_GMAC_CMN_TCAM_TEST_CTL 0x2F0
3075	+#define BCMA_GMAC_CMN_UDF_0_A3_A0 0x300
3076	+#define BCMA_GMAC_CMN_UDF_0_A7_A4 0x304
3077	+#define BCMA_GMAC_CMN_UDF_0_A8 0x308
3078	+#define BCMA_GMAC_CMN_UDF_1_A3_A0 0x310
3079	+#define BCMA_GMAC_CMN_UDF_1_A7_A4 0x314
3080	+#define BCMA_GMAC_CMN_UDF_1_A8 0x318
3081	+#define BCMA_GMAC_CMN_UDF_2_A3_A0 0x320
3082	+#define BCMA_GMAC_CMN_UDF_2_A7_A4 0x324
3083	+#define BCMA_GMAC_CMN_UDF_2_A8 0x328
3084	+#define BCMA_GMAC_CMN_UDF_0_B3_B0 0x330
3085	+#define BCMA_GMAC_CMN_UDF_0_B7_B4 0x334
3086	+#define BCMA_GMAC_CMN_UDF_0_B8 0x338
3087	+#define BCMA_GMAC_CMN_UDF_1_B3_B0 0x340
3088	+#define BCMA_GMAC_CMN_UDF_1_B7_B4 0x344
3089	+#define BCMA_GMAC_CMN_UDF_1_B8 0x348
3090	+#define BCMA_GMAC_CMN_UDF_2_B3_B0 0x350
3091	+#define BCMA_GMAC_CMN_UDF_2_B7_B4 0x354
3092	+#define BCMA_GMAC_CMN_UDF_2_B8 0x358
3093	+#define BCMA_GMAC_CMN_UDF_0_C3_C0 0x360
3094	+#define BCMA_GMAC_CMN_UDF_0_C7_C4 0x364
3095	+#define BCMA_GMAC_CMN_UDF_0_C8 0x368
3096	+#define BCMA_GMAC_CMN_UDF_1_C3_C0 0x370
3097	+#define BCMA_GMAC_CMN_UDF_1_C7_C4 0x374
3098	+#define BCMA_GMAC_CMN_UDF_1_C8 0x378
3099	+#define BCMA_GMAC_CMN_UDF_2_C3_C0 0x380
3100	+#define BCMA_GMAC_CMN_UDF_2_C7_C4 0x384
3101	+#define BCMA_GMAC_CMN_UDF_2_C8 0x388
3102	+#define BCMA_GMAC_CMN_UDF_0_D3_D0 0x390
3103	+#define BCMA_GMAC_CMN_UDF_0_D7_D4 0x394
3104	+#define BCMA_GMAC_CMN_UDF_0_D11_D8 0x394
3105	+
3106	+struct bcma_drv_gmac_cmn {
3107	+ struct bcma_device *core;
3108	+
3109	+ /* Drivers accessing BCMA_GMAC_CMN_PHY_ACCESS and
3110	+ * BCMA_GMAC_CMN_PHY_CTL need to take that mutex first. */
3111	+ struct mutex phy_mutex;
3112	+};
3113	+
3114	+/* Register access */
3115	+#define gmac_cmn_read16(gc, offset) bcma_read16((gc)->core, offset)
3116	+#define gmac_cmn_read32(gc, offset) bcma_read32((gc)->core, offset)
3117	+#define gmac_cmn_write16(gc, offset, val) bcma_write16((gc)->core, offset, val)
3118	+#define gmac_cmn_write32(gc, offset, val) bcma_write32((gc)->core, offset, val)
3119	+
3120	+#ifdef CONFIG_BCMA_DRIVER_GMAC_CMN
3121	+extern void __devinit bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc);
3122	+#else
3123	+static inline void bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc) { }
3124	+#endif
3125	+
3126	+#endif /* LINUX_BCMA_DRIVER_GMAC_CMN_H_ */
3127	--- a/include/linux/bcma/bcma_driver_pci.h
3128	+++ b/include/linux/bcma/bcma_driver_pci.h
3129	@@ -53,11 +53,47 @@ struct pci_dev;
3130	#define BCMA_CORE_PCI_SBTOPCI1_MASK 0xFC000000
3131	#define BCMA_CORE_PCI_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */
3132	#define BCMA_CORE_PCI_SBTOPCI2_MASK 0xC0000000
3133	+#define BCMA_CORE_PCI_CONFIG_ADDR 0x0120 /* pcie config space access */
3134	+#define BCMA_CORE_PCI_CONFIG_DATA 0x0124 /* pcie config space access */
3135	+#define BCMA_CORE_PCI_MDIO_CONTROL 0x0128 /* controls the mdio access */
3136	+#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
3137	+#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL 0x2
3138	+#define BCMA_CORE_PCI_MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
3139	+#define BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
3140	+#define BCMA_CORE_PCI_MDIO_DATA 0x012c /* Data to the mdio access */
3141	+#define BCMA_CORE_PCI_MDIODATA_MASK 0x0000ffff /* data 2 bytes */
3142	+#define BCMA_CORE_PCI_MDIODATA_TA 0x00020000 /* Turnaround */
3143	+#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */
3144	+#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */
3145	+#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */
3146	+#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */
3147	+#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
3148	+#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */
3149	+#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */
3150	+#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK 0x0f800000 /* Physmedia devaddr Mask */
3151	+#define BCMA_CORE_PCI_MDIODATA_WRITE 0x10000000 /* write Transaction */
3152	+#define BCMA_CORE_PCI_MDIODATA_READ 0x20000000 /* Read Transaction */
3153	+#define BCMA_CORE_PCI_MDIODATA_START 0x40000000 /* start of Transaction */
3154	+#define BCMA_CORE_PCI_MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */
3155	+#define BCMA_CORE_PCI_MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */
3156	+#define BCMA_CORE_PCI_MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
3157	+#define BCMA_CORE_PCI_MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
3158	+#define BCMA_CORE_PCI_MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
3159	+#define BCMA_CORE_PCI_PCIEIND_ADDR 0x0130 /* indirect access to the internal register */
3160	+#define BCMA_CORE_PCI_PCIEIND_DATA 0x0134 /* Data to/from the internal regsiter */
3161	+#define BCMA_CORE_PCI_CLKREQENCTRL 0x0138 /* >= rev 6, Clkreq rdma control */
3162	#define BCMA_CORE_PCI_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
3163	#define BCMA_CORE_PCI_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
3164	#define BCMA_CORE_PCI_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
3165	#define BCMA_CORE_PCI_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */
3166	#define BCMA_CORE_PCI_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
3167	+#define BCMA_CORE_PCI_SPROM_PI_OFFSET 0 /* first word */
3168	+#define BCMA_CORE_PCI_SPROM_PI_MASK 0xf000 /* bit 15:12 */
3169	+#define BCMA_CORE_PCI_SPROM_PI_SHIFT 12 /* bit 15:12 */
3170	+#define BCMA_CORE_PCI_SPROM_MISC_CONFIG 5 /* word 5 */
3171	+#define BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST 0x8000 /* bit 15 */
3172	+#define BCMA_CORE_PCI_SPROM_CLKREQ_OFFSET_REV5 20 /* word 20 for srom rev <= 5 */
3173	+#define BCMA_CORE_PCI_SPROM_CLKREQ_ENB 0x0800 /* bit 11 */
3174
3175	/* SBtoPCIx */
3176	#define BCMA_CORE_PCI_SBTOPCI_MEM 0x00000000
3177	@@ -72,20 +108,118 @@ struct pci_dev;
3178	#define BCMA_CORE_PCI_SBTOPCI_RC_READL 0x00000010 /* Memory read line */
3179	#define BCMA_CORE_PCI_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */
3180
3181	+/* PCIE protocol PHY diagnostic registers */
3182	+#define BCMA_CORE_PCI_PLP_MODEREG 0x200 /* Mode */
3183	+#define BCMA_CORE_PCI_PLP_STATUSREG 0x204 /* Status */
3184	+#define BCMA_CORE_PCI_PLP_POLARITYINV_STAT 0x10 /* Status reg PCIE_PLP_STATUSREG */
3185	+#define BCMA_CORE_PCI_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
3186	+#define BCMA_CORE_PCI_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */
3187	+#define BCMA_CORE_PCI_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */
3188	+#define BCMA_CORE_PCI_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
3189	+#define BCMA_CORE_PCI_PLP_ATTNREG 0x218 /* Attention */
3190	+#define BCMA_CORE_PCI_PLP_ATTNMASKREG 0x21C /* Attention Mask */
3191	+#define BCMA_CORE_PCI_PLP_RXERRCTR 0x220 /* Rx Error */
3192	+#define BCMA_CORE_PCI_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */
3193	+#define BCMA_CORE_PCI_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
3194	+#define BCMA_CORE_PCI_PLP_TESTCTRLREG 0x22C /* Test Control reg */
3195	+#define BCMA_CORE_PCI_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
3196	+#define BCMA_CORE_PCI_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
3197	+#define BCMA_CORE_PCI_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */
3198	+#define BCMA_CORE_PCI_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */
3199	+
3200	+/* PCIE protocol DLLP diagnostic registers */
3201	+#define BCMA_CORE_PCI_DLLP_LCREG 0x100 /* Link Control */
3202	+#define BCMA_CORE_PCI_DLLP_LSREG 0x104 /* Link Status */
3203	+#define BCMA_CORE_PCI_DLLP_LAREG 0x108 /* Link Attention */
3204	+#define BCMA_CORE_PCI_DLLP_LSREG_LINKUP (1 << 16)
3205	+#define BCMA_CORE_PCI_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
3206	+#define BCMA_CORE_PCI_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */
3207	+#define BCMA_CORE_PCI_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */
3208	+#define BCMA_CORE_PCI_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */
3209	+#define BCMA_CORE_PCI_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
3210	+#define BCMA_CORE_PCI_DLLP_LRREG 0x120 /* Link Replay */
3211	+#define BCMA_CORE_PCI_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */
3212	+#define BCMA_CORE_PCI_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
3213	+#define BCMA_CORE_PCI_ASPMTIMER_EXTEND 0x01000000 /* > rev7: enable extend ASPM timer */
3214	+#define BCMA_CORE_PCI_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */
3215	+#define BCMA_CORE_PCI_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */
3216	+#define BCMA_CORE_PCI_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */
3217	+#define BCMA_CORE_PCI_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */
3218	+#define BCMA_CORE_PCI_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
3219	+#define BCMA_CORE_PCI_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
3220	+#define BCMA_CORE_PCI_DLLP_ERRCTRREG 0x144 /* Error Counter */
3221	+#define BCMA_CORE_PCI_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */
3222	+#define BCMA_CORE_PCI_DLLP_TESTREG 0x14C /* Test */
3223	+#define BCMA_CORE_PCI_DLLP_PKTBIST 0x150 /* Packet BIST */
3224	+#define BCMA_CORE_PCI_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */
3225	+
3226	+/* SERDES RX registers */
3227	+#define BCMA_CORE_PCI_SERDES_RX_CTRL 1 /* Rx cntrl */
3228	+#define BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */
3229	+#define BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */
3230	+#define BCMA_CORE_PCI_SERDES_RX_TIMER1 2 /* Rx Timer1 */
3231	+#define BCMA_CORE_PCI_SERDES_RX_CDR 6 /* CDR */
3232	+#define BCMA_CORE_PCI_SERDES_RX_CDRBW 7 /* CDR BW */
3233	+
3234	+/* SERDES PLL registers */
3235	+#define BCMA_CORE_PCI_SERDES_PLL_CTRL 1 /* PLL control reg */
3236	+#define BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */
3237	+
3238	/* PCIcore specific boardflags */
3239	#define BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
3240
3241	+/* PCIE Config space accessing MACROS */
3242	+#define BCMA_CORE_PCI_CFG_BUS_SHIFT 24 /* Bus shift */
3243	+#define BCMA_CORE_PCI_CFG_SLOT_SHIFT 19 /* Slot/Device shift */
3244	+#define BCMA_CORE_PCI_CFG_FUN_SHIFT 16 /* Function shift */
3245	+#define BCMA_CORE_PCI_CFG_OFF_SHIFT 0 /* Register shift */
3246	+
3247	+#define BCMA_CORE_PCI_CFG_BUS_MASK 0xff /* Bus mask */
3248	+#define BCMA_CORE_PCI_CFG_SLOT_MASK 0x1f /* Slot/Device mask */
3249	+#define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */
3250	+#define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */
3251	+
3252	+/* PCIE Root Capability Register bits (Host mode only) */
3253	+#define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
3254	+
3255	+struct bcma_drv_pci;
3256	+
3257	+#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
3258	+struct bcma_drv_pci_host {
3259	+ struct bcma_drv_pci *pdev;
3260	+
3261	+ u32 host_cfg_addr;
3262	+ spinlock_t cfgspace_lock;
3263	+
3264	+ struct pci_controller pci_controller;
3265	+ struct pci_ops pci_ops;
3266	+ struct resource mem_resource;
3267	+ struct resource io_resource;
3268	+};
3269	+#endif
3270	+
3271	struct bcma_drv_pci {
3272	struct bcma_device *core;
3273	u8 setup_done:1;
3274	+ u8 hostmode:1;
3275	+
3276	+#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
3277	+ struct bcma_drv_pci_host *host_controller;
3278	+#endif
3279	};
3280
3281	/* Register access */
3282	+#define pcicore_read16(pc, offset) bcma_read16((pc)->core, offset)
3283	#define pcicore_read32(pc, offset) bcma_read32((pc)->core, offset)
3284	+#define pcicore_write16(pc, offset, val) bcma_write16((pc)->core, offset, val)
3285	#define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val)
3286
3287	-extern void bcma_core_pci_init(struct bcma_drv_pci *pc);
3288	+extern void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc);
3289	extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
3290	struct bcma_device *core, bool enable);
3291	+extern void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend);
3292	+
3293	+extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
3294	+extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
3295
3296	#endif /* LINUX_BCMA_DRIVER_PCI_H_ */
3297	--- a/include/linux/bcma/bcma_regs.h
3298	+++ b/include/linux/bcma/bcma_regs.h
3299	@@ -56,4 +56,31 @@
3300	#define BCMA_PCI_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
3301	#define BCMA_PCI_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
3302
3303	+/* SiliconBackplane Address Map.
3304	+ * All regions may not exist on all chips.
3305	+ */
3306	+#define BCMA_SOC_SDRAM_BASE 0x00000000U /* Physical SDRAM */
3307	+#define BCMA_SOC_PCI_MEM 0x08000000U /* Host Mode sb2pcitranslation0 (64 MB) */
3308	+#define BCMA_SOC_PCI_MEM_SZ (64 * 1024 * 1024)
3309	+#define BCMA_SOC_PCI_CFG 0x0c000000U /* Host Mode sb2pcitranslation1 (64 MB) */
3310	+#define BCMA_SOC_SDRAM_SWAPPED 0x10000000U /* Byteswapped Physical SDRAM */
3311	+#define BCMA_SOC_SDRAM_R2 0x80000000U /* Region 2 for sdram (512 MB) */
3312	+
3313	+
3314	+#define BCMA_SOC_PCI_DMA 0x40000000U /* Client Mode sb2pcitranslation2 (1 GB) */
3315	+#define BCMA_SOC_PCI_DMA2 0x80000000U /* Client Mode sb2pcitranslation2 (1 GB) */
3316	+#define BCMA_SOC_PCI_DMA_SZ 0x40000000U /* Client Mode sb2pcitranslation2 size in bytes */
3317	+#define BCMA_SOC_PCIE_DMA_L32 0x00000000U /* PCIE Client Mode sb2pcitranslation2
3318	+ * (2 ZettaBytes), low 32 bits
3319	+ */
3320	+#define BCMA_SOC_PCIE_DMA_H32 0x80000000U /* PCIE Client Mode sb2pcitranslation2
3321	+ * (2 ZettaBytes), high 32 bits
3322	+ */
3323	+
3324	+#define BCMA_SOC_PCI1_MEM 0x40000000U /* Host Mode sb2pcitranslation0 (64 MB) */
3325	+#define BCMA_SOC_PCI1_CFG 0x44000000U /* Host Mode sb2pcitranslation1 (64 MB) */
3326	+#define BCMA_SOC_PCIE1_DMA_H32 0xc0000000U /* PCIE Client Mode sb2pcitranslation2
3327	+ * (2 ZettaBytes), high 32 bits
3328	+ */
3329	+
3330	#endif /* LINUX_BCMA_REGS_H_ */
3331

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