Root/target/linux/ixp4xx/patches-3.3/185-mi424wr_support.patch

1--- /dev/null
2+++ b/arch/arm/mach-ixp4xx/mi424wr-pci.c
3@@ -0,0 +1,71 @@
4+/*
5+ * arch/arm/mach-ixp4xx/mi424wr-pci.c
6+ *
7+ * Actiontec MI424WR board-level PCI initialization
8+ *
9+ * Copyright (C) 2008 Jose Vasconcellos
10+ *
11+ * Maintainer: Jose Vasconcellos <jvasco@verizon.net>
12+ *
13+ * This program is free software; you can redistribute it and/or modify
14+ * it under the terms of the GNU General Public License version 2 as
15+ * published by the Free Software Foundation.
16+ *
17+ */
18+
19+#include <linux/kernel.h>
20+#include <linux/pci.h>
21+#include <linux/init.h>
22+#include <linux/irq.h>
23+
24+#include <asm/mach-types.h>
25+#include <asm/mach/pci.h>
26+
27+/* PCI controller GPIO to IRQ pin mappings
28+ * This information was obtained from Actiontec's GPL release.
29+ *
30+ * INTA INTB
31+ * SLOT 13 8 6
32+ * SLOT 14 7 8
33+ * SLOT 15 6 7
34+ */
35+
36+void __init mi424wr_pci_preinit(void)
37+{
38+ irq_set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW);
39+ irq_set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW);
40+ irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW);
41+
42+ ixp4xx_pci_preinit();
43+}
44+
45+static int __init mi424wr_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
46+{
47+ if (slot == 13)
48+ return IRQ_IXP4XX_GPIO8;
49+ if (slot == 14)
50+ return IRQ_IXP4XX_GPIO7;
51+ if (slot == 15)
52+ return IRQ_IXP4XX_GPIO6;
53+
54+ return -1;
55+}
56+
57+struct hw_pci mi424wr_pci __initdata = {
58+ .nr_controllers = 1,
59+ .preinit = mi424wr_pci_preinit,
60+ .swizzle = pci_std_swizzle,
61+ .setup = ixp4xx_setup,
62+ .scan = ixp4xx_scan_bus,
63+ .map_irq = mi424wr_map_irq,
64+};
65+
66+int __init mi424wr_pci_init(void)
67+{
68+ if (machine_is_mi424wr())
69+ pci_common_init(&mi424wr_pci);
70+ return 0;
71+}
72+
73+subsys_initcall(mi424wr_pci_init);
74+
75--- /dev/null
76+++ b/arch/arm/mach-ixp4xx/mi424wr-setup.c
77@@ -0,0 +1,381 @@
78+/*
79+ * arch/arm/mach-ixp4xx/mi424wr-setup.c
80+ *
81+ * Actiontec MI424-WR board setup
82+ * Copyright (c) 2008 Jose Vasconcellos
83+ *
84+ * Based on Gemtek GTWX5715 by
85+ * Copyright (C) 2004 George T. Joseph
86+ * Derived from Coyote
87+ *
88+ * This program is free software; you can redistribute it and/or
89+ * modify it under the terms of the GNU General Public License
90+ * as published by the Free Software Foundation; either version 2
91+ * of the License, or (at your option) any later version.
92+ *
93+ * This program is distributed in the hope that it will be useful,
94+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
95+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
96+ * GNU General Public License for more details.
97+ *
98+ * You should have received a copy of the GNU General Public License
99+ * along with this program; if not, write to the Free Software
100+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
101+ *
102+ */
103+
104+#include <linux/init.h>
105+#include <linux/device.h>
106+#include <linux/serial.h>
107+#include <linux/serial_8250.h>
108+#include <linux/types.h>
109+#include <linux/memory.h>
110+#include <linux/leds.h>
111+#include <linux/spi/spi_gpio_old.h>
112+
113+#include <asm/setup.h>
114+#include <asm/irq.h>
115+#include <asm/io.h>
116+#include <asm/mach-types.h>
117+#include <asm/mach/arch.h>
118+#include <asm/mach/flash.h>
119+
120+/*
121+ * GPIO 2,3,4 and 9 are hard wired to the Micrel/Kendin KS8995M Switch
122+ * and operate as an SPI type interface. The details of the interface
123+ * are available on Kendin/Micrel's web site.
124+ */
125+
126+#define MI424WR_KSSPI_SELECT 9
127+#define MI424WR_KSSPI_TXD 4
128+#define MI424WR_KSSPI_CLOCK 2
129+#define MI424WR_KSSPI_RXD 3
130+
131+/*
132+ * The "reset" button is wired to GPIO 10.
133+ * The GPIO is brought "low" when the button is pushed.
134+ */
135+
136+#define MI424WR_BUTTON_GPIO 10
137+#define MI424WR_BUTTON_IRQ IRQ_IXP4XX_GPIO10
138+
139+#define MI424WR_MOCA_WAN_LED 11
140+
141+/* Latch on CS1 - taken from Actiontec's 2.4 source code
142+ *
143+ * default latch value
144+ * 0 - power alarm led (red) 0 (off)
145+ * 1 - power led (green) 0 (off)
146+ * 2 - wireless led (green) 1 (off)
147+ * 3 - no internet led (red) 0 (off)
148+ * 4 - internet ok led (green) 0 (off)
149+ * 5 - moca LAN 0 (off)
150+ * 6 - WAN alarm led (red) 0 (off)
151+ * 7 - PCI reset 1 (not reset)
152+ * 8 - IP phone 1 led (green) 1 (off)
153+ * 9 - IP phone 2 led (green) 1 (off)
154+ * 10 - VOIP ready led (green) 1 (off)
155+ * 11 - PSTN relay 1 control 0 (PSTN)
156+ * 12 - PSTN relay 1 control 0 (PSTN)
157+ * 13 - N/A
158+ * 14 - N/A
159+ * 15 - N/A
160+ */
161+
162+#define MI424WR_LATCH_MASK 0x04
163+#define MI424WR_LATCH_DEFAULT 0x1f86
164+
165+#define MI424WR_LATCH_ALARM_LED 0x00
166+#define MI424WR_LATCH_POWER_LED 0x01
167+#define MI424WR_LATCH_WIRELESS_LED 0x02
168+#define MI424WR_LATCH_INET_DOWN_LED 0x03
169+#define MI424WR_LATCH_INET_OK_LED 0x04
170+#define MI424WR_LATCH_MOCA_LAN_LED 0x05
171+#define MI424WR_LATCH_WAN_ALARM_LED 0x06
172+#define MI424WR_LATCH_PCI_RESET 0x07
173+#define MI424WR_LATCH_PHONE1_LED 0x08
174+#define MI424WR_LATCH_PHONE2_LED 0x09
175+#define MI424WR_LATCH_VOIP_LED 0x10
176+#define MI424WR_LATCH_PSTN_RELAY1 0x11
177+#define MI424WR_LATCH_PSTN_RELAY2 0x12
178+
179+/* initialize CS1 to default timings, Intel style, 16-bit bus */
180+#define MI424WR_CS1_CONFIG 0x80000002
181+
182+/* Define both UARTs but they are not easily accessible.
183+ */
184+
185+static struct resource mi424wr_uart_resources[] = {
186+ {
187+ .start = IXP4XX_UART1_BASE_PHYS,
188+ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
189+ .flags = IORESOURCE_MEM,
190+ },
191+ {
192+ .start = IXP4XX_UART2_BASE_PHYS,
193+ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
194+ .flags = IORESOURCE_MEM,
195+ }
196+};
197+
198+
199+static struct plat_serial8250_port mi424wr_uart_platform_data[] = {
200+ {
201+ .mapbase = IXP4XX_UART1_BASE_PHYS,
202+ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
203+ .irq = IRQ_IXP4XX_UART1,
204+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
205+ .iotype = UPIO_MEM,
206+ .regshift = 2,
207+ .uartclk = IXP4XX_UART_XTAL,
208+ },
209+ {
210+ .mapbase = IXP4XX_UART2_BASE_PHYS,
211+ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
212+ .irq = IRQ_IXP4XX_UART2,
213+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
214+ .iotype = UPIO_MEM,
215+ .regshift = 2,
216+ .uartclk = IXP4XX_UART_XTAL,
217+ },
218+ { },
219+};
220+
221+static struct platform_device mi424wr_uart_device = {
222+ .name = "serial8250",
223+ .id = PLAT8250_DEV_PLATFORM,
224+ .dev.platform_data = mi424wr_uart_platform_data,
225+ .num_resources = ARRAY_SIZE(mi424wr_uart_resources),
226+ .resource = mi424wr_uart_resources,
227+};
228+
229+static struct flash_platform_data mi424wr_flash_data = {
230+ .map_name = "cfi_probe",
231+ .width = 2,
232+};
233+
234+static struct resource mi424wr_flash_resource = {
235+ .flags = IORESOURCE_MEM,
236+};
237+
238+static struct platform_device mi424wr_flash = {
239+ .name = "IXP4XX-Flash",
240+ .id = 0,
241+ .dev.platform_data = &mi424wr_flash_data,
242+ .num_resources = 1,
243+ .resource = &mi424wr_flash_resource,
244+};
245+
246+static int mi424wr_spi_boardinfo_setup(struct spi_board_info *bi,
247+ struct spi_master *master, void *data)
248+{
249+
250+ strlcpy(bi->modalias, "spi-ks8995", sizeof(bi->modalias));
251+
252+ bi->max_speed_hz = 5000000 /* Hz */;
253+ bi->bus_num = master->bus_num;
254+ bi->mode = SPI_MODE_0;
255+
256+ return 0;
257+}
258+
259+static struct spi_gpio_platform_data mi424wr_spi_bus_data = {
260+ .pin_cs = MI424WR_KSSPI_SELECT,
261+ .pin_clk = MI424WR_KSSPI_CLOCK,
262+ .pin_miso = MI424WR_KSSPI_RXD,
263+ .pin_mosi = MI424WR_KSSPI_TXD,
264+ .cs_activelow = 1,
265+ .no_spi_delay = 1,
266+ .boardinfo_setup = mi424wr_spi_boardinfo_setup,
267+};
268+
269+static struct gpio_led mi424wr_gpio_led[] = {
270+ {
271+ .name = "moca-wan", /* green led */
272+ .gpio = MI424WR_MOCA_WAN_LED,
273+ .active_low = 0,
274+ }
275+};
276+
277+static struct gpio_led_platform_data mi424wr_gpio_leds_data = {
278+ .num_leds = 1,
279+ .leds = mi424wr_gpio_led,
280+};
281+
282+static struct platform_device mi424wr_gpio_leds = {
283+ .name = "leds-gpio",
284+ .id = -1,
285+ .dev.platform_data = &mi424wr_gpio_leds_data,
286+};
287+
288+static uint16_t latch_value = MI424WR_LATCH_DEFAULT;
289+static uint16_t __iomem *iobase;
290+
291+static void mi424wr_latch_set_led(u8 bit, enum led_brightness value)
292+{
293+
294+ if (((MI424WR_LATCH_MASK >> bit) & 1) ^ (value == LED_OFF))
295+ latch_value &= ~(0x1 << bit);
296+ else
297+ latch_value |= (0x1 << bit);
298+
299+ __raw_writew(latch_value, iobase);
300+
301+}
302+
303+static struct latch_led mi424wr_latch_led[] = {
304+ {
305+ .name = "power-alarm",
306+ .bit = MI424WR_LATCH_ALARM_LED,
307+ },
308+ {
309+ .name = "power-ok",
310+ .bit = MI424WR_LATCH_POWER_LED,
311+ },
312+ {
313+ .name = "wireless", /* green led */
314+ .bit = MI424WR_LATCH_WIRELESS_LED,
315+ },
316+ {
317+ .name = "inet-down", /* red led */
318+ .bit = MI424WR_LATCH_INET_DOWN_LED,
319+ },
320+ {
321+ .name = "inet-up", /* green led */
322+ .bit = MI424WR_LATCH_INET_OK_LED,
323+ },
324+ {
325+ .name = "moca-lan", /* green led */
326+ .bit = MI424WR_LATCH_MOCA_LAN_LED,
327+ },
328+ {
329+ .name = "wan-alarm", /* red led */
330+ .bit = MI424WR_LATCH_WAN_ALARM_LED,
331+ }
332+};
333+
334+static struct latch_led_platform_data mi424wr_latch_leds_data = {
335+ .num_leds = ARRAY_SIZE(mi424wr_latch_led),
336+ .mem = 0x51000000,
337+ .leds = mi424wr_latch_led,
338+ .set_led = mi424wr_latch_set_led,
339+};
340+
341+static struct platform_device mi424wr_latch_leds = {
342+ .name = "leds-latch",
343+ .id = -1,
344+ .dev.platform_data = &mi424wr_latch_leds_data,
345+};
346+
347+static struct platform_device mi424wr_spi_bus = {
348+ .name = "spi-gpio",
349+ .id = 0,
350+ .dev.platform_data = &mi424wr_spi_bus_data,
351+};
352+
353+static struct eth_plat_info mi424wr_wan_data = {
354+ .phy = 17, /* KS8721 */
355+ .rxq = 3,
356+ .txreadyq = 20,
357+};
358+
359+static struct eth_plat_info mi424wr_lan_data = {
360+ .phy = IXP4XX_ETH_PHY_MAX_ADDR,
361+ .phy_mask = 0x1e, /* ports 1-4 of the KS8995 switch */
362+ .rxq = 4,
363+ .txreadyq = 21,
364+};
365+
366+static struct platform_device mi424wr_npe_devices[] = {
367+ {
368+ .name = "ixp4xx_eth",
369+ .id = IXP4XX_ETH_NPEC,
370+ .dev.platform_data = &mi424wr_lan_data,
371+ }, {
372+ .name = "ixp4xx_eth",
373+ .id = IXP4XX_ETH_NPEB,
374+ .dev.platform_data = &mi424wr_wan_data,
375+ }
376+};
377+
378+static struct eth_plat_info mi424wr_wanD_data = {
379+ .phy = 5,
380+ .rxq = 4,
381+ .txreadyq = 21,
382+};
383+
384+static struct eth_plat_info mi424wr_lanD_data = {
385+ .phy = IXP4XX_ETH_PHY_MAX_ADDR,
386+ .phy_mask = 0x1e, /* ports 1-4 of the KS8995 switch */
387+ .rxq = 3,
388+ .txreadyq = 20,
389+};
390+
391+static struct platform_device mi424wr_npeD_devices[] = {
392+ {
393+ .name = "ixp4xx_eth",
394+ .id = IXP4XX_ETH_NPEB,
395+ .dev.platform_data = &mi424wr_lanD_data,
396+ }, {
397+ .name = "ixp4xx_eth",
398+ .id = IXP4XX_ETH_NPEC,
399+ .dev.platform_data = &mi424wr_wanD_data,
400+ }
401+};
402+
403+static struct platform_device *mi424wr_devices[] __initdata = {
404+ &mi424wr_uart_device,
405+ &mi424wr_flash,
406+ &mi424wr_gpio_leds,
407+ &mi424wr_latch_leds,
408+ &mi424wr_spi_bus,
409+};
410+
411+static void __init mi424wr_init(void)
412+{
413+ ixp4xx_sys_init();
414+
415+ mi424wr_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
416+ mi424wr_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_8M - 1;
417+
418+ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
419+ *IXP4XX_EXP_CS1 = MI424WR_CS1_CONFIG;
420+
421+ /* configure button as input
422+ */
423+ gpio_line_config(MI424WR_BUTTON_GPIO, IXP4XX_GPIO_IN);
424+
425+ /* Initialize LEDs and enables PCI bus.
426+ */
427+ iobase = ioremap_nocache(IXP4XX_EXP_BUS_BASE(1), 0x1000);
428+ __raw_writew(latch_value, iobase);
429+
430+ platform_add_devices(mi424wr_devices, ARRAY_SIZE(mi424wr_devices));
431+
432+ /* Need to figure out how to detect revD.
433+ * Look for a revision argument sent by redboot.
434+ */
435+#define revD 4
436+ if (system_rev == revD) {
437+ platform_device_register(&mi424wr_npeD_devices[0]);
438+ platform_device_register(&mi424wr_npeD_devices[1]);
439+ } else {
440+ platform_device_register(&mi424wr_npe_devices[0]);
441+ platform_device_register(&mi424wr_npe_devices[1]);
442+ }
443+}
444+
445+
446+MACHINE_START(MI424WR, "Actiontec MI424WR")
447+ /* Maintainer: Jose Vasconcellos */
448+ .map_io = ixp4xx_map_io,
449+ .init_irq = ixp4xx_init_irq,
450+ .timer = &ixp4xx_timer,
451+ .atag_offset = 0x0100,
452+ .init_machine = mi424wr_init,
453+#if defined(CONFIG_PCI)
454+ .dma_zone_size = SZ_64M,
455+#endif
456+ .restart = ixp4xx_restart,
457+MACHINE_END
458+
459--- a/arch/arm/mach-ixp4xx/Makefile
460+++ b/arch/arm/mach-ixp4xx/Makefile
461@@ -25,6 +25,7 @@ obj-pci-$(CONFIG_MACH_COMPEX) += ixdp42
462 obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o
463 obj-pci-$(CONFIG_MACH_AP1000) += ixdp425-pci.o
464 obj-pci-$(CONFIG_MACH_TW5334) += tw5334-pci.o
465+obj-pci-$(CONFIG_MACH_MI424WR) += mi424wr-pci.o
466 
467 obj-y += common.o
468 
469@@ -51,6 +52,7 @@ obj-$(CONFIG_MACH_COMPEX) += compex-setu
470 obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o
471 obj-$(CONFIG_MACH_AP1000) += ap1000-setup.o
472 obj-$(CONFIG_MACH_TW5334) += tw5334-setup.o
473+obj-$(CONFIG_MACH_MI424WR) += mi424wr-setup.o
474 
475 obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
476 obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
477--- a/arch/arm/mach-ixp4xx/Kconfig
478+++ b/arch/arm/mach-ixp4xx/Kconfig
479@@ -262,6 +262,13 @@ config MACH_MIC256
480       Say 'Y' here if you want your kernel to support the MIC256
481       board from OMICRON electronics GmbH.
482 
483+config MACH_MI424WR
484+ bool "Actiontec MI424WR"
485+ depends on ARCH_IXP4XX
486+ select PCI
487+ help
488+ Add support for the Actiontec MI424-WR.
489+
490 comment "IXP4xx Options"
491 
492 config IXP4XX_INDIRECT_PCI
493--- a/arch/arm/configs/ixp4xx_defconfig
494+++ b/arch/arm/configs/ixp4xx_defconfig
495@@ -26,6 +26,7 @@ CONFIG_MACH_NAS100D=y
496 CONFIG_MACH_DSMG600=y
497 CONFIG_MACH_FSG=y
498 CONFIG_MACH_GTWX5715=y
499+CONFIG_MACH_MI424WR=y
500 CONFIG_IXP4XX_QMGR=y
501 CONFIG_IXP4XX_NPE=y
502 # CONFIG_ARM_THUMB is not set
503

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