| 1 | /* |
| 2 | * This program is free software; you can redistribute it and/or modify it |
| 3 | * under the terms of the GNU General Public License version 2 as published |
| 4 | * by the Free Software Foundation. |
| 5 | * |
| 6 | * Copyright (C) 2010 John Crispin <blogic@openwrt.org> |
| 7 | */ |
| 8 | |
| 9 | #ifndef _LTQ_FALCON_H__ |
| 10 | #define _LTQ_FALCON_H__ |
| 11 | |
| 12 | #ifdef CONFIG_SOC_FALCON |
| 13 | |
| 14 | #include <lantiq.h> |
| 15 | |
| 16 | /* Chip IDs */ |
| 17 | #define SOC_ID_FALCON 0x01B8 |
| 18 | |
| 19 | /* SoC Types */ |
| 20 | #define SOC_TYPE_FALCON 0x01 |
| 21 | |
| 22 | /* ASC0/1 - serial port */ |
| 23 | #define LTQ_ASC0_BASE_ADDR 0x1E100C00 |
| 24 | #define LTQ_ASC1_BASE_ADDR 0x1E100B00 |
| 25 | #define LTQ_ASC_SIZE 0x100 |
| 26 | |
| 27 | #define LTQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 8)) |
| 28 | #define LTQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 1) |
| 29 | #define LTQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 2) |
| 30 | |
| 31 | /* |
| 32 | * during early_printk no ioremap possible at this early stage |
| 33 | * lets use KSEG1 instead |
| 34 | */ |
| 35 | #define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR) |
| 36 | |
| 37 | /* ICU - interrupt control unit */ |
| 38 | #define LTQ_ICU_BASE_ADDR 0x1F880200 |
| 39 | #define LTQ_ICU_SIZE 0x100 |
| 40 | |
| 41 | /* WDT */ |
| 42 | #define LTQ_WDT_BASE_ADDR 0x1F8803F0 |
| 43 | #define LTQ_WDT_SIZE 0x10 |
| 44 | |
| 45 | #define LTQ_RST_CAUSE_WDTRST 0x0002 |
| 46 | |
| 47 | /* EBU - external bus unit */ |
| 48 | #define LTQ_EBU_BASE_ADDR 0x18000000 |
| 49 | #define LTQ_EBU_SIZE 0x0100 |
| 50 | |
| 51 | #define LTQ_EBU_MODCON 0x000C |
| 52 | |
| 53 | /* GPIO */ |
| 54 | #define LTQ_GPIO0_BASE_ADDR 0x1D810000 |
| 55 | #define LTQ_GPIO0_SIZE 0x0080 |
| 56 | #define LTQ_GPIO1_BASE_ADDR 0x1E800100 |
| 57 | #define LTQ_GPIO1_SIZE 0x0080 |
| 58 | #define LTQ_GPIO2_BASE_ADDR 0x1D810100 |
| 59 | #define LTQ_GPIO2_SIZE 0x0080 |
| 60 | #define LTQ_GPIO3_BASE_ADDR 0x1E800200 |
| 61 | #define LTQ_GPIO3_SIZE 0x0080 |
| 62 | #define LTQ_GPIO4_BASE_ADDR 0x1E800300 |
| 63 | #define LTQ_GPIO4_SIZE 0x0080 |
| 64 | #define LTQ_PADCTRL0_BASE_ADDR 0x1DB01000 |
| 65 | #define LTQ_PADCTRL0_SIZE 0x0100 |
| 66 | #define LTQ_PADCTRL1_BASE_ADDR 0x1E800400 |
| 67 | #define LTQ_PADCTRL1_SIZE 0x0100 |
| 68 | #define LTQ_PADCTRL2_BASE_ADDR 0x1DB02000 |
| 69 | #define LTQ_PADCTRL2_SIZE 0x0100 |
| 70 | #define LTQ_PADCTRL3_BASE_ADDR 0x1E800500 |
| 71 | #define LTQ_PADCTRL3_SIZE 0x0100 |
| 72 | #define LTQ_PADCTRL4_BASE_ADDR 0x1E800600 |
| 73 | #define LTQ_PADCTRL4_SIZE 0x0100 |
| 74 | |
| 75 | /* I2C */ |
| 76 | #define GPON_I2C_BASE 0x1E200000 |
| 77 | #define GPON_I2C_SIZE 0x00010000 |
| 78 | |
| 79 | /* CHIP ID */ |
| 80 | #define LTQ_STATUS_BASE_ADDR 0x1E802000 |
| 81 | |
| 82 | #define LTQ_FALCON_CHIPID ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c)) |
| 83 | #define LTQ_FALCON_CHIPTYPE ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38)) |
| 84 | #define LTQ_FALCON_CHIPCONF ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40)) |
| 85 | |
| 86 | /* SYSCTL - start/stop/restart/configure/... different parts of the Soc */ |
| 87 | #define LTQ_SYS1_BASE_ADDR 0x1EF00000 |
| 88 | #define LTQ_SYS1_SIZE 0x0100 |
| 89 | #define LTQ_STATUS_BASE_ADDR 0x1E802000 |
| 90 | #define LTQ_STATUS_SIZE 0x0080 |
| 91 | #define LTQ_SYS_ETH_BASE_ADDR 0x1DB00000 |
| 92 | #define LTQ_SYS_ETH_SIZE 0x0100 |
| 93 | #define LTQ_SYS_GPE_BASE_ADDR 0x1D700000 |
| 94 | #define LTQ_SYS_GPE_SIZE 0x0100 |
| 95 | |
| 96 | #define SYSCTL_SYS1 0 |
| 97 | #define SYSCTL_SYSETH 1 |
| 98 | #define SYSCTL_SYSGPE 2 |
| 99 | |
| 100 | /* Activation Status Register */ |
| 101 | #define ACTS_ASC1_ACT 0x00000800 |
| 102 | #define ACTS_I2C_ACT 0x00004000 |
| 103 | #define ACTS_P0 0x00010000 |
| 104 | #define ACTS_P1 0x00010000 |
| 105 | #define ACTS_P2 0x00020000 |
| 106 | #define ACTS_P3 0x00020000 |
| 107 | #define ACTS_P4 0x00040000 |
| 108 | #define ACTS_PADCTRL0 0x00100000 |
| 109 | #define ACTS_PADCTRL1 0x00100000 |
| 110 | #define ACTS_PADCTRL2 0x00200000 |
| 111 | #define ACTS_PADCTRL3 0x00200000 |
| 112 | #define ACTS_PADCTRL4 0x00400000 |
| 113 | #define ACTS_I2C_ACT 0x00004000 |
| 114 | |
| 115 | /* global register ranges */ |
| 116 | extern __iomem void *ltq_ebu_membase; |
| 117 | extern __iomem void *ltq_sys1_membase; |
| 118 | #define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y)) |
| 119 | #define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x)) |
| 120 | #define ltq_ebu_w32_mask(clear, set, reg) \ |
| 121 | ltq_ebu_w32((ltq_ebu_r32(reg) & ~(clear)) | (set), reg) |
| 122 | |
| 123 | #define ltq_sys1_w32(x, y) ltq_w32((x), ltq_sys1_membase + (y)) |
| 124 | #define ltq_sys1_r32(x) ltq_r32(ltq_sys1_membase + (x)) |
| 125 | #define ltq_sys1_w32_mask(clear, set, reg) \ |
| 126 | ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg) |
| 127 | |
| 128 | /* gpio wrapper to help configure the pin muxing */ |
| 129 | extern int ltq_gpio_mux_set(unsigned int pin, unsigned int mux); |
| 130 | |
| 131 | /* to keep the irq code generic we need to define these to 0 as falcon |
| 132 | has no EIU/EBU */ |
| 133 | #define LTQ_EIU_BASE_ADDR 0 |
| 134 | #define LTQ_EBU_PCC_ISTAT 0 |
| 135 | |
| 136 | static inline int ltq_is_ar9(void) |
| 137 | { |
| 138 | return 0; |
| 139 | } |
| 140 | |
| 141 | static inline int ltq_is_vr9(void) |
| 142 | { |
| 143 | return 0; |
| 144 | } |
| 145 | |
| 146 | static inline int ltq_is_falcon(void) |
| 147 | { |
| 148 | return 1; |
| 149 | } |
| 150 | |
| 151 | #endif /* CONFIG_SOC_FALCON */ |
| 152 | #endif /* _LTQ_XWAY_H__ */ |
| 153 | |
