Root/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/base_reg.h

1/******************************************************************************
2
3  Copyright (c) 2007
4  Infineon Technologies AG
5  St. Martin Strasse 53; 81669 Munich, Germany
6
7  Any use of this Software is subject to the conclusion of a respective
8  License Agreement. Without such a License Agreement no rights to the
9  Software are granted.
10
11 ******************************************************************************/
12
13#ifndef __BASE_REG_H
14#define __BASE_REG_H
15
16#ifndef KSEG1
17#define KSEG1 0xA0000000
18#endif
19
20#define LTQ_EBU_SEG1_BASE (KSEG1 + 0x10000000)
21#define LTQ_EBU_SEG2_BASE (KSEG1 + 0x11000000)
22#define LTQ_EBU_SEG3_BASE (KSEG1 + 0x12000000)
23#define LTQ_EBU_SEG4_BASE (KSEG1 + 0x13000000)
24
25#define LTQ_ASC0_BASE (KSEG1 + 0x14100100)
26#define LTQ_ASC1_BASE (KSEG1 + 0x14100200)
27
28#define LTQ_SSC0_BASE (0x14100300)
29#define LTQ_SSC1_BASE (0x14100400)
30
31#define LTQ_PORT_P0_BASE (KSEG1 + 0x14100600)
32#define LTQ_PORT_P1_BASE (KSEG1 + 0x14108100)
33#define LTQ_PORT_P2_BASE (KSEG1 + 0x14100800)
34#define LTQ_PORT_P3_BASE (KSEG1 + 0x14100900)
35#define LTQ_PORT_P4_BASE (KSEG1 + 0x1E000400)
36
37#define LTQ_EBU_BASE (KSEG1 + 0x14102000)
38#define LTQ_DMA_BASE (KSEG1 + 0x14104000)
39
40#define LTQ_ICU0_IM3_IM2_BASE (KSEG1 + 0x1E016000)
41#define LTQ_ICU0_IM5_IM4_IM1_IM0_BASE (KSEG1 + 0x14106000)
42
43#define LTQ_ES_BASE (KSEG1 + 0x18000000)
44
45#define LTQ_SYS0_BASE (KSEG1 + 0x1C000000)
46#define LTQ_SYS1_BASE (KSEG1 + 0x1C000800)
47#define LTQ_SYS2_BASE (KSEG1 + 0x1E400000)
48
49#define LTQ_L2_SPRAM_BASE (KSEG1 + 0x1F1E8000)
50
51#define LTQ_SWINT_BASE (KSEG1 + 0x1E000100)
52#define LTQ_MBS_BASE (KSEG1 + 0x1E000200)
53
54#define LTQ_STATUS_BASE (KSEG1 + 0x1E000500)
55
56#endif
57

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