| 1 | /****************************************************************************** |
| 2 | |
| 3 | Copyright (c) 2007 |
| 4 | Infineon Technologies AG |
| 5 | St. Martin Strasse 53; 81669 Munich, Germany |
| 6 | |
| 7 | Any use of this Software is subject to the conclusion of a respective |
| 8 | License Agreement. Without such a License Agreement no rights to the |
| 9 | Software are granted. |
| 10 | |
| 11 | ******************************************************************************/ |
| 12 | |
| 13 | #ifndef __DMA_REG_H |
| 14 | #define __DMA_REG_H |
| 15 | |
| 16 | #define dma_r32(reg) ltq_r32(&dma->reg) |
| 17 | #define dma_w32(val, reg) ltq_w32(val, &dma->reg) |
| 18 | #define dma_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &dma->reg) |
| 19 | |
| 20 | /** DMA register structure */ |
| 21 | struct svip_reg_dma { |
| 22 | volatile unsigned long clc; /* 0x00 */ |
| 23 | volatile unsigned long reserved0; /* 0x04 */ |
| 24 | volatile unsigned long id; /* 0x08 */ |
| 25 | volatile unsigned long reserved1; /* 0x0c */ |
| 26 | volatile unsigned long ctrl; /* 0x10 */ |
| 27 | volatile unsigned long cpoll; /* 0x14 */ |
| 28 | volatile unsigned long cs; /* 0x18 */ |
| 29 | volatile unsigned long cctrl; /* 0x1C */ |
| 30 | volatile unsigned long cdba; /* 0x20 */ |
| 31 | volatile unsigned long cdlen; /* 0x24 */ |
| 32 | volatile unsigned long cis; /* 0x28 */ |
| 33 | volatile unsigned long cie; /* 0x2C */ |
| 34 | volatile unsigned long cgbl; /* 0x30 */ |
| 35 | volatile unsigned long reserved2[3]; /* 0x34 */ |
| 36 | volatile unsigned long ps; /* 0x40 */ |
| 37 | volatile unsigned long pctrl; /* 0x44 */ |
| 38 | volatile unsigned long reserved3[43]; /* 0x48 */ |
| 39 | volatile unsigned long irnen; /* 0xF4 */ |
| 40 | volatile unsigned long irncr; /* 0xF8 */ |
| 41 | volatile unsigned long irnicr; /* 0xFC */ |
| 42 | }; |
| 43 | |
| 44 | /******************************************************************************* |
| 45 | * CLC Register |
| 46 | ******************************************************************************/ |
| 47 | |
| 48 | /* Fast Shut-Off Enable Bit (5) */ |
| 49 | #define DMA_CLC_FSOE (0x1 << 5) |
| 50 | #define DMA_CLC_FSOE_VAL(val) (((val) & 0x1) << 5) |
| 51 | #define DMA_CLC_FSOE_GET(val) ((((val) & DMA_CLC_FSOE) >> 5) & 0x1) |
| 52 | #define DMA_CLC_FSOE_SET(reg,val) (reg) = ((reg & ~DMA_CLC_FSOE) | (((val) & 0x1) << 5)) |
| 53 | /* Suspend Bit Write Enable for OCDS (4) */ |
| 54 | #define DMA_CLC_SBWE (0x1 << 4) |
| 55 | #define DMA_CLC_SBWE_VAL(val) (((val) & 0x1) << 4) |
| 56 | #define DMA_CLC_SBWE_SET(reg,val) (reg) = (((reg & ~DMA_CLC_SBWE) | (val) & 1) << 4) |
| 57 | /* External Request Disable (3) */ |
| 58 | #define DMA_CLC_EDIS (0x1 << 3) |
| 59 | #define DMA_CLC_EDIS_VAL(val) (((val) & 0x1) << 3) |
| 60 | #define DMA_CLC_EDIS_GET(val) ((((val) & DMA_CLC_EDIS) >> 3) & 0x1) |
| 61 | #define DMA_CLC_EDIS_SET(reg,val) (reg) = ((reg & ~DMA_CLC_EDIS) | (((val) & 0x1) << 3)) |
| 62 | /* Suspend Enable Bit for OCDS (2) */ |
| 63 | #define DMA_CLC_SPEN (0x1 << 2) |
| 64 | #define DMA_CLC_SPEN_VAL(val) (((val) & 0x1) << 2) |
| 65 | #define DMA_CLC_SPEN_GET(val) ((((val) & DMA_CLC_SPEN) >> 2) & 0x1) |
| 66 | #define DMA_CLC_SPEN_SET(reg,val) (reg) = ((reg & ~DMA_CLC_SPEN) | (((val) & 0x1) << 2)) |
| 67 | /* Disable Status Bit (1) */ |
| 68 | #define DMA_CLC_DISS (0x1 << 1) |
| 69 | #define DMA_CLC_DISS_GET(val) ((((val) & DMA_CLC_DISS) >> 1) & 0x1) |
| 70 | /* Disable Request Bit (0) */ |
| 71 | #define DMA_CLC_DISR (0x1) |
| 72 | #define DMA_CLC_DISR_VAL(val) (((val) & 0x1) << 0) |
| 73 | #define DMA_CLC_DISR_GET(val) ((((val) & DMA_CLC_DISR) >> 0) & 0x1) |
| 74 | #define DMA_CLC_DISR_SET(reg,val) (reg) = ((reg & ~DMA_CLC_DISR) | (((val) & 0x1) << 0)) |
| 75 | |
| 76 | /******************************************************************************* |
| 77 | * ID Register |
| 78 | ******************************************************************************/ |
| 79 | |
| 80 | /* Number of Channels (25:20) */ |
| 81 | #define DMA_ID_CHNR (0x3f << 20) |
| 82 | #define DMA_ID_CHNR_GET(val) ((((val) & DMA_ID_CHNR) >> 20) & 0x3f) |
| 83 | /* Number of Ports (19:16) */ |
| 84 | #define DMA_ID_PRTNR (0xf << 16) |
| 85 | #define DMA_ID_PRTNR_GET(val) ((((val) & DMA_ID_PRTNR) >> 16) & 0xf) |
| 86 | /* Module ID (15:8) */ |
| 87 | #define DMA_ID_ID (0xff << 8) |
| 88 | #define DMA_ID_ID_GET(val) ((((val) & DMA_ID_ID) >> 8) & 0xff) |
| 89 | /* Revision (4:0) */ |
| 90 | #define DMA_ID_REV (0x1f) |
| 91 | #define DMA_ID_REV_GET(val) ((((val) & DMA_ID_REV) >> 0) & 0x1f) |
| 92 | |
| 93 | /******************************************************************************* |
| 94 | * Control Register |
| 95 | ******************************************************************************/ |
| 96 | |
| 97 | /* Global Software Reset (0) */ |
| 98 | #define DMA_CTRL_RST (0x1) |
| 99 | #define DMA_CTRL_RST_GET(val) ((((val) & DMA_CTRL_RST) >> 0) & 0x1) |
| 100 | |
| 101 | /******************************************************************************* |
| 102 | * Channel Polling Register |
| 103 | ******************************************************************************/ |
| 104 | |
| 105 | /* Enable (31) */ |
| 106 | #define DMA_CPOLL_EN (0x1 << 31) |
| 107 | #define DMA_CPOLL_EN_VAL(val) (((val) & 0x1) << 31) |
| 108 | #define DMA_CPOLL_EN_GET(val) ((((val) & DMA_CPOLL_EN) >> 31) & 0x1) |
| 109 | #define DMA_CPOLL_EN_SET(reg,val) (reg) = ((reg & ~DMA_CPOLL_EN) | (((val) & 0x1) << 31)) |
| 110 | /* Counter (15:4) */ |
| 111 | #define DMA_CPOLL_CNT (0xfff << 4) |
| 112 | #define DMA_CPOLL_CNT_VAL(val) (((val) & 0xfff) << 4) |
| 113 | #define DMA_CPOLL_CNT_GET(val) ((((val) & DMA_CPOLL_CNT) >> 4) & 0xfff) |
| 114 | #define DMA_CPOLL_CNT_SET(reg,val) (reg) = ((reg & ~DMA_CPOLL_CNT) | (((val) & 0xfff) << 4)) |
| 115 | |
| 116 | /******************************************************************************* |
| 117 | * Global Buffer Length Register |
| 118 | ******************************************************************************/ |
| 119 | |
| 120 | /* Global Buffer Length (15:0) */ |
| 121 | #define DMA_CGBL_GBL (0xffff) |
| 122 | #define DMA_CGBL_GBL_VAL(val) (((val) & 0xffff) << 0) |
| 123 | #define DMA_CGBL_GBL_GET(val) ((((val) & DMA_CGBL_GBL) >> 0) & 0xffff) |
| 124 | #define DMA_CGBL_GBL_SET(reg,val) (reg) = ((reg & ~DMA_CGBL_GBL) | (((val) & 0xffff) << 0)) |
| 125 | |
| 126 | /******************************************************************************* |
| 127 | * Channel Select Register |
| 128 | ******************************************************************************/ |
| 129 | |
| 130 | /* Channel Selection (4:0) */ |
| 131 | #define DMA_CS_CS (0x1f) |
| 132 | #define DMA_CS_CS_VAL(val) (((val) & 0x1f) << 0) |
| 133 | #define DMA_CS_CS_GET(val) ((((val) & DMA_CS_CS) >> 0) & 0x1f) |
| 134 | #define DMA_CS_CS_SET(reg,val) (reg) = ((reg & ~DMA_CS_CS) | (((val) & 0x1f) << 0)) |
| 135 | |
| 136 | /******************************************************************************* |
| 137 | * Channel Control Register |
| 138 | ******************************************************************************/ |
| 139 | |
| 140 | /* Peripheral to Peripheral Copy (24) */ |
| 141 | #define DMA_CCTRL_P2PCPY (0x1 << 24) |
| 142 | #define DMA_CCTRL_P2PCPY_VAL(val) (((val) & 0x1) << 24) |
| 143 | #define DMA_CCTRL_P2PCPY_GET(val) ((((val) & DMA_CCTRL_P2PCPY) >> 24) & 0x1) |
| 144 | #define DMA_CCTRL_P2PCPY_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_P2PCPY) | (((val) & 0x1) << 24)) |
| 145 | /* Channel Weight for Transmit Direction (17:16) */ |
| 146 | #define DMA_CCTRL_TXWGT (0x3 << 16) |
| 147 | #define DMA_CCTRL_TXWGT_VAL(val) (((val) & 0x3) << 16) |
| 148 | #define DMA_CCTRL_TXWGT_GET(val) ((((val) & DMA_CCTRL_TXWGT) >> 16) & 0x3) |
| 149 | #define DMA_CCTRL_TXWGT_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_TXWGT) | (((val) & 0x3) << 16)) |
| 150 | /* Port Assignment (13:11) */ |
| 151 | #define DMA_CCTRL_PRTNR (0x7 << 11) |
| 152 | #define DMA_CCTRL_PRTNR_GET(val) ((((val) & DMA_CCTRL_PRTNR) >> 11) & 0x7) |
| 153 | /* Class (10:9) */ |
| 154 | #define DMA_CCTRL_CLASS (0x3 << 9) |
| 155 | #define DMA_CCTRL_CLASS_VAL(val) (((val) & 0x3) << 9) |
| 156 | #define DMA_CCTRL_CLASS_GET(val) ((((val) & DMA_CCTRL_CLASS) >> 9) & 0x3) |
| 157 | #define DMA_CCTRL_CLASS_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_CLASS) | (((val) & 0x3) << 9)) |
| 158 | /* Direction (8) */ |
| 159 | #define DMA_CCTRL_DIR (0x1 << 8) |
| 160 | #define DMA_CCTRL_DIR_GET(val) ((((val) & DMA_CCTRL_DIR) >> 8) & 0x1) |
| 161 | /* Reset (1) */ |
| 162 | #define DMA_CCTRL_RST (0x1 << 1) |
| 163 | #define DMA_CCTRL_RST_VAL(val) (((val) & 0x1) << 1) |
| 164 | #define DMA_CCTRL_RST_GET(val) ((((val) & DMA_CCTRL_RST) >> 1) & 0x1) |
| 165 | #define DMA_CCTRL_RST_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_RST) | (((val) & 0x1) << 1)) |
| 166 | /* Channel On or Off (0) */ |
| 167 | #define DMA_CCTRL_ON_OFF (0x1) |
| 168 | #define DMA_CCTRL_ON_OFF_VAL(val) (((val) & 0x1) << 0) |
| 169 | #define DMA_CCTRL_ON_OFF_GET(val) ((((val) & DMA_CCTRL_ON_OFF) >> 0) & 0x1) |
| 170 | #define DMA_CCTRL_ON_OFF_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_ON_OFF) | (((val) & 0x1) << 0)) |
| 171 | |
| 172 | /******************************************************************************* |
| 173 | * Channel Descriptor Base Address Register |
| 174 | ******************************************************************************/ |
| 175 | |
| 176 | /* Channel Descriptor Base Address (29:3) */ |
| 177 | #define DMA_CDBA_CDBA (0x7ffffff << 3) |
| 178 | #define DMA_CDBA_CDBA_VAL(val) (((val) & 0x7ffffff) << 3) |
| 179 | #define DMA_CDBA_CDBA_GET(val) ((((val) & DMA_CDBA_CDBA) >> 3) & 0x7ffffff) |
| 180 | #define DMA_CDBA_CDBA_SET(reg,val) (reg) = ((reg & ~DMA_CDBA_CDBA) | (((val) & 0x7ffffff) << 3)) |
| 181 | |
| 182 | /******************************************************************************* |
| 183 | * Channel Descriptor Length Register |
| 184 | ******************************************************************************/ |
| 185 | |
| 186 | /* Channel Descriptor Length (7:0) */ |
| 187 | #define DMA_CDLEN_CDLEN (0xff) |
| 188 | #define DMA_CDLEN_CDLEN_VAL(val) (((val) & 0xff) << 0) |
| 189 | #define DMA_CDLEN_CDLEN_GET(val) ((((val) & DMA_CDLEN_CDLEN) >> 0) & 0xff) |
| 190 | #define DMA_CDLEN_CDLEN_SET(reg,val) (reg) = ((reg & ~DMA_CDLEN_CDLEN) | (((val) & 0xff) << 0)) |
| 191 | |
| 192 | /******************************************************************************* |
| 193 | * Channel Interrupt Status Register |
| 194 | ******************************************************************************/ |
| 195 | |
| 196 | /* SAI Read Error Interrupt (5) */ |
| 197 | #define DMA_CIS_RDERR (0x1 << 5) |
| 198 | #define DMA_CIS_RDERR_GET(val) ((((val) & DMA_CIS_RDERR) >> 5) & 0x1) |
| 199 | /* Channel Off Interrupt (4) */ |
| 200 | #define DMA_CIS_CHOFF (0x1 << 4) |
| 201 | #define DMA_CIS_CHOFF_GET(val) ((((val) & DMA_CIS_CHOFF) >> 4) & 0x1) |
| 202 | /* Descriptor Complete Interrupt (3) */ |
| 203 | #define DMA_CIS_DESCPT (0x1 << 3) |
| 204 | #define DMA_CIS_DESCPT_GET(val) ((((val) & DMA_CIS_DESCPT) >> 3) & 0x1) |
| 205 | /* Descriptor Under-Run Interrupt (2) */ |
| 206 | #define DMA_CIS_DUR (0x1 << 2) |
| 207 | #define DMA_CIS_DUR_GET(val) ((((val) & DMA_CIS_DUR) >> 2) & 0x1) |
| 208 | /* End of Packet Interrupt (1) */ |
| 209 | #define DMA_CIS_EOP (0x1 << 1) |
| 210 | #define DMA_CIS_EOP_GET(val) ((((val) & DMA_CIS_EOP) >> 1) & 0x1) |
| 211 | |
| 212 | /******************************************************************************* |
| 213 | * Channel Interrupt Enable Register |
| 214 | ******************************************************************************/ |
| 215 | |
| 216 | /* SAI Read Error Interrupt (5) */ |
| 217 | #define DMA_CIE_RDERR (0x1 << 5) |
| 218 | #define DMA_CIE_RDERR_GET(val) ((((val) & DMA_CIE_RDERR) >> 5) & 0x1) |
| 219 | /* Channel Off Interrupt (4) */ |
| 220 | #define DMA_CIE_CHOFF (0x1 << 4) |
| 221 | #define DMA_CIE_CHOFF_GET(val) ((((val) & DMA_CIE_CHOFF) >> 4) & 0x1) |
| 222 | /* Descriptor Complete Interrupt Enable (3) */ |
| 223 | #define DMA_CIE_DESCPT (0x1 << 3) |
| 224 | #define DMA_CIE_DESCPT_GET(val) ((((val) & DMA_CIE_DESCPT) >> 3) & 0x1) |
| 225 | /* Descriptor Under Run Interrupt Enable (2) */ |
| 226 | #define DMA_CIE_DUR (0x1 << 2) |
| 227 | #define DMA_CIE_DUR_GET(val) ((((val) & DMA_CIE_DUR) >> 2) & 0x1) |
| 228 | /* End of Packet Interrupt Enable (1) */ |
| 229 | #define DMA_CIE_EOP (0x1 << 1) |
| 230 | #define DMA_CIE_EOP_GET(val) ((((val) & DMA_CIE_EOP) >> 1) & 0x1) |
| 231 | |
| 232 | /******************************************************************************* |
| 233 | * Port Select Register |
| 234 | ******************************************************************************/ |
| 235 | |
| 236 | /* Port Selection (2:0) */ |
| 237 | #define DMA_PS_PS (0x7) |
| 238 | #define DMA_PS_PS_VAL(val) (((val) & 0x7) << 0) |
| 239 | #define DMA_PS_PS_GET(val) ((((val) & DMA_PS_PS) >> 0) & 0x7) |
| 240 | #define DMA_PS_PS_SET(reg,val) (reg) = ((reg & ~DMA_PS_PS) | (((val) & 0x7) << 0)) |
| 241 | |
| 242 | /******************************************************************************* |
| 243 | * Port Control Register |
| 244 | ******************************************************************************/ |
| 245 | |
| 246 | /* General Purpose Control (16) */ |
| 247 | #define DMA_PCTRL_GPC (0x1 << 16) |
| 248 | #define DMA_PCTRL_GPC_VAL(val) (((val) & 0x1) << 16) |
| 249 | #define DMA_PCTRL_GPC_GET(val) ((((val) & DMA_PCTRL_GPC) >> 16) & 0x1) |
| 250 | #define DMA_PCTRL_GPC_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_GPC) | (((val) & 0x1) << 16)) |
| 251 | /* Port Weight for Transmit Direction (14:12) */ |
| 252 | #define DMA_PCTRL_TXWGT (0x7 << 12) |
| 253 | #define DMA_PCTRL_TXWGT_VAL(val) (((val) & 0x7) << 12) |
| 254 | #define DMA_PCTRL_TXWGT_GET(val) ((((val) & DMA_PCTRL_TXWGT) >> 12) & 0x7) |
| 255 | #define DMA_PCTRL_TXWGT_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_TXWGT) | (((val) & 0x7) << 12)) |
| 256 | /* Endianness for Transmit Direction (11:10) */ |
| 257 | #define DMA_PCTRL_TXENDI (0x3 << 10) |
| 258 | #define DMA_PCTRL_TXENDI_VAL(val) (((val) & 0x3) << 10) |
| 259 | #define DMA_PCTRL_TXENDI_GET(val) ((((val) & DMA_PCTRL_TXENDI) >> 10) & 0x3) |
| 260 | #define DMA_PCTRL_TXENDI_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_TXENDI) | (((val) & 0x3) << 10)) |
| 261 | /* Endianness for Receive Direction (9:8) */ |
| 262 | #define DMA_PCTRL_RXENDI (0x3 << 8) |
| 263 | #define DMA_PCTRL_RXENDI_VAL(val) (((val) & 0x3) << 8) |
| 264 | #define DMA_PCTRL_RXENDI_GET(val) ((((val) & DMA_PCTRL_RXENDI) >> 8) & 0x3) |
| 265 | #define DMA_PCTRL_RXENDI_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_RXENDI) | (((val) & 0x3) << 8)) |
| 266 | /* Packet Drop Enable (6) */ |
| 267 | #define DMA_PCTRL_PDEN (0x1 << 6) |
| 268 | #define DMA_PCTRL_PDEN_VAL(val) (((val) & 0x1) << 6) |
| 269 | #define DMA_PCTRL_PDEN_GET(val) ((((val) & DMA_PCTRL_PDEN) >> 6) & 0x1) |
| 270 | #define DMA_PCTRL_PDEN_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_PDEN) | (((val) & 0x1) << 6)) |
| 271 | /* Burst Length for Transmit Direction (5:4) */ |
| 272 | #define DMA_PCTRL_TXBL (0x3 << 4) |
| 273 | #define DMA_PCTRL_TXBL_VAL(val) (((val) & 0x3) << 4) |
| 274 | #define DMA_PCTRL_TXBL_GET(val) ((((val) & DMA_PCTRL_TXBL) >> 4) & 0x3) |
| 275 | #define DMA_PCTRL_TXBL_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_TXBL) | (((val) & 0x3) << 4)) |
| 276 | /* Burst Length for Receive Direction (3:2) */ |
| 277 | #define DMA_PCTRL_RXBL (0x3 << 2) |
| 278 | #define DMA_PCTRL_RXBL_VAL(val) (((val) & 0x3) << 2) |
| 279 | #define DMA_PCTRL_RXBL_GET(val) ((((val) & DMA_PCTRL_RXBL) >> 2) & 0x3) |
| 280 | #define DMA_PCTRL_RXBL_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_RXBL) | (((val) & 0x3) << 2)) |
| 281 | |
| 282 | /******************************************************************************* |
| 283 | * DMA_IRNEN Register |
| 284 | ******************************************************************************/ |
| 285 | |
| 286 | /* Channel x Interrupt Request Enable (23) */ |
| 287 | #define DMA_IRNEN_CH23 (0x1 << 23) |
| 288 | #define DMA_IRNEN_CH23_VAL(val) (((val) & 0x1) << 23) |
| 289 | #define DMA_IRNEN_CH23_GET(val) ((((val) & DMA_IRNEN_CH23) >> 23) & 0x1) |
| 290 | #define DMA_IRNEN_CH23_SET(reg,val) (reg) = ((reg & ~DMA_IRNEN_CH23) | (((val) & 0x1) << 23)) |
| 291 | |
| 292 | /******************************************************************************* |
| 293 | * DMA_IRNCR Register |
| 294 | ******************************************************************************/ |
| 295 | |
| 296 | /* Channel x Interrupt (23) */ |
| 297 | #define DMA_IRNCR_CH23 (0x1 << 23) |
| 298 | #define DMA_IRNCR_CH23_GET(val) ((((val) & DMA_IRNCR_CH23) >> 23) & 0x1) |
| 299 | |
| 300 | /******************************************************************************* |
| 301 | * DMA_IRNICR Register |
| 302 | ******************************************************************************/ |
| 303 | |
| 304 | /* Channel x Interrupt Request (23) */ |
| 305 | #define DMA_IRNICR_CH23 (0x1 << 23) |
| 306 | #define DMA_IRNICR_CH23_GET(val) ((((val) & DMA_IRNICR_CH23) >> 23) & 0x1) |
| 307 | |
| 308 | #endif |
| 309 | |
