| 1 | /****************************************************************************** |
| 2 | |
| 3 | Copyright (c) 2007 |
| 4 | Infineon Technologies AG |
| 5 | St. Martin Strasse 53; 81669 Munich, Germany |
| 6 | |
| 7 | Any use of this Software is subject to the conclusion of a respective |
| 8 | License Agreement. Without such a License Agreement no rights to the |
| 9 | Software are granted. |
| 10 | |
| 11 | ******************************************************************************/ |
| 12 | |
| 13 | #ifndef __ES_REG_H |
| 14 | #define __ES_REG_H |
| 15 | |
| 16 | #define es_r32(reg) ltq_r32(&es->reg) |
| 17 | #define es_w32(val, reg) ltq_w32(val, &es->reg) |
| 18 | #define es_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &es->reg) |
| 19 | |
| 20 | /** ES register structure */ |
| 21 | struct svip_reg_es { |
| 22 | volatile unsigned long ps; /* 0x0000 */ |
| 23 | volatile unsigned long p0_ctl; /* 0x0004 */ |
| 24 | volatile unsigned long p1_ctl; /* 0x0008 */ |
| 25 | volatile unsigned long p2_ctl; /* 0x000C */ |
| 26 | volatile unsigned long p0_vlan; /* 0x0010 */ |
| 27 | volatile unsigned long p1_vlan; /* 0x0014 */ |
| 28 | volatile unsigned long p2_vlan; /* 0x0018 */ |
| 29 | volatile unsigned long reserved1[1]; /* 0x001C */ |
| 30 | volatile unsigned long p0_inctl; /* 0x0020 */ |
| 31 | volatile unsigned long p1_inctl; /* 0x0024 */ |
| 32 | volatile unsigned long p2_inctl; /* 0x0028 */ |
| 33 | volatile unsigned long reserved2[1]; /* 0x002C */ |
| 34 | volatile unsigned long p0_ecs_q32; /* 0x0030 */ |
| 35 | volatile unsigned long p0_ecs_q10; /* 0x0034 */ |
| 36 | volatile unsigned long p0_ecw_q32; /* 0x0038 */ |
| 37 | volatile unsigned long p0_ecw_q10; /* 0x003C */ |
| 38 | volatile unsigned long p1_ecs_q32; /* 0x0040 */ |
| 39 | volatile unsigned long p1_ecs_q10; /* 0x0044 */ |
| 40 | volatile unsigned long p1_ecw_q32; /* 0x0048 */ |
| 41 | volatile unsigned long p1_ecw_q10; /* 0x004C */ |
| 42 | volatile unsigned long p2_ecs_q32; /* 0x0050 */ |
| 43 | volatile unsigned long p2_ecs_q10; /* 0x0054 */ |
| 44 | volatile unsigned long p2_ecw_q32; /* 0x0058 */ |
| 45 | volatile unsigned long p2_ecw_q10; /* 0x005C */ |
| 46 | volatile unsigned long int_ena; /* 0x0060 */ |
| 47 | volatile unsigned long int_st; /* 0x0064 */ |
| 48 | volatile unsigned long sw_gctl0; /* 0x0068 */ |
| 49 | volatile unsigned long sw_gctl1; /* 0x006C */ |
| 50 | volatile unsigned long arp; /* 0x0070 */ |
| 51 | volatile unsigned long strm_ctl; /* 0x0074 */ |
| 52 | volatile unsigned long rgmii_ctl; /* 0x0078 */ |
| 53 | volatile unsigned long prt_1p; /* 0x007C */ |
| 54 | volatile unsigned long gbkt_szbs; /* 0x0080 */ |
| 55 | volatile unsigned long gbkt_szebs; /* 0x0084 */ |
| 56 | volatile unsigned long bf_th; /* 0x0088 */ |
| 57 | volatile unsigned long pmac_hd_ctl; /* 0x008C */ |
| 58 | volatile unsigned long pmac_sa1; /* 0x0090 */ |
| 59 | volatile unsigned long pmac_sa2; /* 0x0094 */ |
| 60 | volatile unsigned long pmac_da1; /* 0x0098 */ |
| 61 | volatile unsigned long pmac_da2; /* 0x009C */ |
| 62 | volatile unsigned long pmac_vlan; /* 0x00A0 */ |
| 63 | volatile unsigned long pmac_tx_ipg; /* 0x00A4 */ |
| 64 | volatile unsigned long pmac_rx_ipg; /* 0x00A8 */ |
| 65 | volatile unsigned long adr_tb_ctl0; /* 0x00AC */ |
| 66 | volatile unsigned long adr_tb_ctl1; /* 0x00B0 */ |
| 67 | volatile unsigned long adr_tb_ctl2; /* 0x00B4 */ |
| 68 | volatile unsigned long adr_tb_st0; /* 0x00B8 */ |
| 69 | volatile unsigned long adr_tb_st1; /* 0x00BC */ |
| 70 | volatile unsigned long adr_tb_st2; /* 0x00C0 */ |
| 71 | volatile unsigned long rmon_ctl; /* 0x00C4 */ |
| 72 | volatile unsigned long rmon_st; /* 0x00C8 */ |
| 73 | volatile unsigned long mdio_ctl; /* 0x00CC */ |
| 74 | volatile unsigned long mdio_data; /* 0x00D0 */ |
| 75 | volatile unsigned long tp_flt_act; /* 0x00D4 */ |
| 76 | volatile unsigned long prtcl_flt_act; /* 0x00D8 */ |
| 77 | volatile unsigned long reserved4[9]; /* 0xdc */ |
| 78 | volatile unsigned long vlan_flt0; /* 0x0100 */ |
| 79 | volatile unsigned long vlan_flt1; /* 0x0104 */ |
| 80 | volatile unsigned long vlan_flt2; /* 0x0108 */ |
| 81 | volatile unsigned long vlan_flt3; /* 0x010C */ |
| 82 | volatile unsigned long vlan_flt4; /* 0x0110 */ |
| 83 | volatile unsigned long vlan_flt5; /* 0x0114 */ |
| 84 | volatile unsigned long vlan_flt6; /* 0x0118 */ |
| 85 | volatile unsigned long vlan_flt7; /* 0x011C */ |
| 86 | volatile unsigned long vlan_flt8; /* 0x0120 */ |
| 87 | volatile unsigned long vlan_flt9; /* 0x0124 */ |
| 88 | volatile unsigned long vlan_flt10; /* 0x0128 */ |
| 89 | volatile unsigned long vlan_flt11; /* 0x012C */ |
| 90 | volatile unsigned long vlan_flt12; /* 0x0130 */ |
| 91 | volatile unsigned long vlan_flt13; /* 0x0134 */ |
| 92 | volatile unsigned long vlan_flt14; /* 0x0138 */ |
| 93 | volatile unsigned long vlan_flt15; /* 0x013C */ |
| 94 | volatile unsigned long tp_flt10; /* 0x0140 */ |
| 95 | volatile unsigned long tp_flt32; /* 0x0144 */ |
| 96 | volatile unsigned long tp_flt54; /* 0x0148 */ |
| 97 | volatile unsigned long tp_flt76; /* 0x014C */ |
| 98 | volatile unsigned long dfsrv_map0; /* 0x0150 */ |
| 99 | volatile unsigned long dfsrv_map1; /* 0x0154 */ |
| 100 | volatile unsigned long dfsrv_map2; /* 0x0158 */ |
| 101 | volatile unsigned long dfsrv_map3; /* 0x015C */ |
| 102 | volatile unsigned long tcp_pf0; /* 0x0160 */ |
| 103 | volatile unsigned long tcp_pf1; /* 0x0164 */ |
| 104 | volatile unsigned long tcp_pf2; /* 0x0168 */ |
| 105 | volatile unsigned long tcp_pf3; /* 0x016C */ |
| 106 | volatile unsigned long tcp_pf4; /* 0x0170 */ |
| 107 | volatile unsigned long tcp_pf5; /* 0x0174 */ |
| 108 | volatile unsigned long tcp_pf6; /* 0x0178 */ |
| 109 | volatile unsigned long tcp_pf7; /* 0x017C */ |
| 110 | volatile unsigned long ra_03_00; /* 0x0180 */ |
| 111 | volatile unsigned long ra_07_04; /* 0x0184 */ |
| 112 | volatile unsigned long ra_0b_08; /* 0x0188 */ |
| 113 | volatile unsigned long ra_0f_0c; /* 0x018C */ |
| 114 | volatile unsigned long ra_13_10; /* 0x0190 */ |
| 115 | volatile unsigned long ra_17_14; /* 0x0194 */ |
| 116 | volatile unsigned long ra_1b_18; /* 0x0198 */ |
| 117 | volatile unsigned long ra_1f_1c; /* 0x019C */ |
| 118 | volatile unsigned long ra_23_20; /* 0x01A0 */ |
| 119 | volatile unsigned long ra_27_24; /* 0x01A4 */ |
| 120 | volatile unsigned long ra_2b_28; /* 0x01A8 */ |
| 121 | volatile unsigned long ra_2f_2c; /* 0x01AC */ |
| 122 | volatile unsigned long prtcl_f0; /* 0x01B0 */ |
| 123 | volatile unsigned long prtcl_f1; /* 0x01B4 */ |
| 124 | }; |
| 125 | |
| 126 | /******************************************************************************* |
| 127 | * ES |
| 128 | ******************************************************************************/ |
| 129 | #define LTQ_ES_PS_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0000)) |
| 130 | #define LTQ_ES_P0_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0004)) |
| 131 | #define LTQ_ES_P1_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0008)) |
| 132 | #define LTQ_ES_P2_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x000C)) |
| 133 | #define LTQ_ES_P0_VLAN_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0010)) |
| 134 | #define LTQ_ES_P1_VLAN_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0014)) |
| 135 | #define LTQ_ES_P2_VLAN_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0010)) |
| 136 | #define LTQ_ES_P0_INCTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0020)) |
| 137 | #define LTQ_ES_P1_INCTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0024)) |
| 138 | #define LTQ_ES_P2_INCTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0028)) |
| 139 | #define LTQ_ES_P0_ECS_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0030)) |
| 140 | #define LTQ_ES_P0_ECS_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0034)) |
| 141 | #define LTQ_ES_P0_ECW_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0038)) |
| 142 | #define LTQ_ES_P0_ECW_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x003C)) |
| 143 | #define LTQ_ES_P1_ECS_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0030)) |
| 144 | #define LTQ_ES_P1_ECS_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0034)) |
| 145 | #define LTQ_ES_P1_ECW_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0038)) |
| 146 | #define LTQ_ES_P1_ECW_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x003C)) |
| 147 | #define LTQ_ES_P2_ECS_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0030)) |
| 148 | #define LTQ_ES_P2_ECS_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0034)) |
| 149 | #define LTQ_ES_P2_ECW_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0038)) |
| 150 | #define LTQ_ES_P2_ECW_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x003C)) |
| 151 | #define LTQ_ES_INT_ENA_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0060)) |
| 152 | #define LTQ_ES_INT_ST_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0064)) |
| 153 | #define LTQ_ES_SW_GCTL0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0068)) |
| 154 | #define LTQ_ES_SW_GCTL1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x006C)) |
| 155 | #define LTQ_ES_ARP_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0070)) |
| 156 | #define LTQ_ES_STRM_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0074)) |
| 157 | #define LTQ_ES_RGMII_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0078)) |
| 158 | #define LTQ_ES_PRT_1P_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x007C)) |
| 159 | #define LTQ_ES_GBKT_SZBS_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0080)) |
| 160 | #define LTQ_ES_GBKT_SZEBS_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0084)) |
| 161 | #define LTQ_ES_BF_TH_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0088)) |
| 162 | #define LTQ_ES_PMAC_HD_CTL ((volatile unsigned int*)(LTQ_ES_BASE + 0x008C)) |
| 163 | #define LTQ_ES_PMAC_SA1 ((volatile unsigned int*)(LTQ_ES_BASE + 0x0090)) |
| 164 | #define LTQ_ES_PMAC_SA2 ((volatile unsigned int*)(LTQ_ES_BASE + 0x0094)) |
| 165 | #define LTQ_ES_PMAC_DA1 ((volatile unsigned int*)(LTQ_ES_BASE + 0x0098)) |
| 166 | #define LTQ_ES_PMAC_DA2 ((volatile unsigned int*)(LTQ_ES_BASE + 0x009C)) |
| 167 | #define LTQ_ES_PMAC_VLAN ((volatile unsigned int*)(LTQ_ES_BASE + 0x00A0)) |
| 168 | #define LTQ_ES_PMAC_TX_IPG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00A4)) |
| 169 | #define LTQ_ES_PMAC_RX_IPG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00A8)) |
| 170 | #define LTQ_ES_ADR_TB_CTL0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00AC)) |
| 171 | #define LTQ_ES_ADR_TB_CTL1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00B0)) |
| 172 | #define LTQ_ES_ADR_TB_CTL2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00B4)) |
| 173 | #define LTQ_ES_ADR_TB_ST0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00B8)) |
| 174 | #define LTQ_ES_ADR_TB_ST1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00BC)) |
| 175 | #define LTQ_ES_ADR_TB_ST2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00C0)) |
| 176 | #define LTQ_ES_RMON_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00C4)) |
| 177 | #define LTQ_ES_RMON_ST_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00C8)) |
| 178 | #define LTQ_ES_MDIO_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00CC)) |
| 179 | #define LTQ_ES_MDIO_DATA_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00D0)) |
| 180 | #define LTQ_ES_TP_FLT_ACT_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00D4)) |
| 181 | #define LTQ_ES_PRTCL_FLT_ACT_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00D8)) |
| 182 | #define LTQ_ES_VLAN_FLT0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0100)) |
| 183 | #define LTQ_ES_VLAN_FLT1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0104)) |
| 184 | #define LTQ_ES_VLAN_FLT2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0108)) |
| 185 | #define LTQ_ES_VLAN_FLT3_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x010C)) |
| 186 | #define LTQ_ES_VLAN_FLT4_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0110)) |
| 187 | #define LTQ_ES_VLAN_FLT5_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0114)) |
| 188 | #define LTQ_ES_VLAN_FLT6_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0118)) |
| 189 | #define LTQ_ES_VLAN_FLT7_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x011C)) |
| 190 | #define LTQ_ES_VLAN_FLT8_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0120)) |
| 191 | #define LTQ_ES_VLAN_FLT9_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0124)) |
| 192 | #define LTQ_ES_VLAN_FLT10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0128)) |
| 193 | #define LTQ_ES_VLAN_FLT11_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x012C)) |
| 194 | #define LTQ_ES_VLAN_FLT12_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0130)) |
| 195 | #define LTQ_ES_VLAN_FLT13_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0134)) |
| 196 | #define LTQ_ES_VLAN_FLT14_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0138)) |
| 197 | #define LTQ_ES_VLAN_FLT15_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x013C)) |
| 198 | #define LTQ_ES_TP_FLT10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0140)) |
| 199 | #define LTQ_ES_TP_FLT32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0144)) |
| 200 | #define LTQ_ES_TP_FLT54_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0148)) |
| 201 | #define LTQ_ES_TP_FLT76_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x014C)) |
| 202 | #define LTQ_ES_DFSRV_MAP0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0150)) |
| 203 | #define LTQ_ES_DFSRV_MAP1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0154)) |
| 204 | #define LTQ_ES_DFSRV_MAP2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0158)) |
| 205 | #define LTQ_ES_DFSRV_MAP3_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x015C)) |
| 206 | #define LTQ_ES_TCP_PF0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0160)) |
| 207 | #define LTQ_ES_TCP_PF1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0164)) |
| 208 | #define LTQ_ES_TCP_PF2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0168)) |
| 209 | #define LTQ_ES_TCP_PF3_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x016C)) |
| 210 | #define LTQ_ES_TCP_PF4_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0170)) |
| 211 | #define LTQ_ES_TCP_PF5_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0174)) |
| 212 | #define LTQ_ES_TCP_PF6_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0178)) |
| 213 | #define LTQ_ES_TCP_PF7_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x017C)) |
| 214 | #define LTQ_ES_RA_03_00_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0180)) |
| 215 | #define LTQ_ES_RA_07_04_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0184)) |
| 216 | #define LTQ_ES_RA_0B_08_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0188)) |
| 217 | #define LTQ_ES_RA_0F_0C_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x018C)) |
| 218 | #define LTQ_ES_RA_13_10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0190)) |
| 219 | #define LTQ_ES_RA_17_14_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0194)) |
| 220 | #define LTQ_ES_RA_1B_18_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0198)) |
| 221 | #define LTQ_ES_RA_1F_1C_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x019C)) |
| 222 | #define LTQ_ES_RA_23_20_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01A0)) |
| 223 | #define LTQ_ES_RA_27_24_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01A4)) |
| 224 | #define LTQ_ES_RA_2B_28_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01A8)) |
| 225 | #define LTQ_ES_RA_2F_2C_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01AC)) |
| 226 | #define LTQ_ES_PRTCL_F0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01B0)) |
| 227 | #define LTQ_ES_PRTCL_F1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01B4)) |
| 228 | |
| 229 | /******************************************************************************* |
| 230 | * Port Status Register |
| 231 | ******************************************************************************/ |
| 232 | |
| 233 | /* Port 1 Flow Control Status (12) */ |
| 234 | #define LTQ_ES_PS_REG_P1FCS (0x1 << 12) |
| 235 | #define LTQ_ES_PS_REG_P1FCS_GET(val) ((((val) & LTQ_ES_PS_REG_P1FCS) >> 12) & 0x1) |
| 236 | /* Port 1 Duplex Status (11) */ |
| 237 | #define LTQ_ES_PS_REG_P1DS (0x1 << 11) |
| 238 | #define LTQ_ES_PS_REG_P1DS_GET(val) ((((val) & LTQ_ES_PS_REG_P1DS) >> 11) & 0x1) |
| 239 | /* Port 1 Speed High Status (10) */ |
| 240 | #define LTQ_ES_PS_REG_P1SHS (0x1 << 10) |
| 241 | #define LTQ_ES_PS_REG_P1SHS_GET(val) ((((val) & LTQ_ES_PS_REG_P1SHS) >> 10) & 0x1) |
| 242 | /* Port 1 Speed Status (9) */ |
| 243 | #define LTQ_ES_PS_REG_P1SS (0x1 << 9) |
| 244 | #define LTQ_ES_PS_REG_P1SS_GET(val) ((((val) & LTQ_ES_PS_REG_P1SS) >> 9) & 0x1) |
| 245 | /* Port 1 Link Status (8) */ |
| 246 | #define LTQ_ES_PS_REG_P1LS (0x1 << 8) |
| 247 | #define LTQ_ES_PS_REG_P1LS_GET(val) ((((val) & LTQ_ES_PS_REG_P1LS) >> 8) & 0x1) |
| 248 | /* Port 0 Flow Control Status (4) */ |
| 249 | #define LTQ_ES_PS_REG_P0FCS (0x1 << 4) |
| 250 | #define LTQ_ES_PS_REG_P0FCS_GET(val) ((((val) & LTQ_ES_PS_REG_P0FCS) >> 4) & 0x1) |
| 251 | /* Port 0 Duplex Status (3) */ |
| 252 | #define LTQ_ES_PS_REG_P0DS (0x1 << 3) |
| 253 | #define LTQ_ES_PS_REG_P0DS_GET(val) ((((val) & LTQ_ES_PS_REG_P0DS) >> 3) & 0x1) |
| 254 | /* Port 0 Speed High Status (2) */ |
| 255 | #define LTQ_ES_PS_REG_P0SHS (0x1 << 2) |
| 256 | #define LTQ_ES_PS_REG_P0SHS_GET(val) ((((val) & LTQ_ES_PS_REG_P0SHS) >> 2) & 0x1) |
| 257 | /* Port 0 Speed Status (1) */ |
| 258 | #define LTQ_ES_PS_REG_P0SS (0x1 << 1) |
| 259 | #define LTQ_ES_PS_REG_P0SS_GET(val) ((((val) & LTQ_ES_PS_REG_P0SS) >> 1) & 0x1) |
| 260 | /* Port 0 Link Status (0) */ |
| 261 | #define LTQ_ES_PS_REG_P0LS (0x1) |
| 262 | #define LTQ_ES_PS_REG_P0LS_GET(val) ((((val) & LTQ_ES_PS_REG_P0LS) >> 0) & 0x1) |
| 263 | |
| 264 | /******************************************************************************* |
| 265 | * P0 Control Register |
| 266 | ******************************************************************************/ |
| 267 | |
| 268 | /* STP/RSTP port state (31:30) */ |
| 269 | #define LTQ_ES_P0_CTL_REG_SPS (0x3 << 30) |
| 270 | #define LTQ_ES_P0_CTL_REG_SPS_VAL(val) (((val) & 0x3) << 30) |
| 271 | #define LTQ_ES_P0_CTL_REG_SPS_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_SPS) >> 30) & 0x3) |
| 272 | #define LTQ_ES_P0_CTL_REG_SPS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_SPS) | (((val) & 0x3) << 30)) |
| 273 | /* TCP/UDP PRIEN (29) */ |
| 274 | #define LTQ_ES_P0_CTL_REG_TCPE (0x1 << 29) |
| 275 | #define LTQ_ES_P0_CTL_REG_TCPE_VAL(val) (((val) & 0x1) << 29) |
| 276 | #define LTQ_ES_P0_CTL_REG_TCPE_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_TCPE) >> 29) & 0x1) |
| 277 | #define LTQ_ES_P0_CTL_REG_TCPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_TCPE) | (((val) & 0x1) << 29)) |
| 278 | /* IP over TCP/UDP (28) */ |
| 279 | #define LTQ_ES_P0_CTL_REG_IPOVTU (0x1 << 28) |
| 280 | #define LTQ_ES_P0_CTL_REG_IPOVTU_VAL(val) (((val) & 0x1) << 28) |
| 281 | #define LTQ_ES_P0_CTL_REG_IPOVTU_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_IPOVTU) >> 28) & 0x1) |
| 282 | #define LTQ_ES_P0_CTL_REG_IPOVTU_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_IPOVTU) | (((val) & 0x1) << 28)) |
| 283 | /* VLAN Priority Enable (27) */ |
| 284 | #define LTQ_ES_P0_CTL_REG_VPE (0x1 << 27) |
| 285 | #define LTQ_ES_P0_CTL_REG_VPE_VAL(val) (((val) & 0x1) << 27) |
| 286 | #define LTQ_ES_P0_CTL_REG_VPE_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_VPE) >> 27) & 0x1) |
| 287 | #define LTQ_ES_P0_CTL_REG_VPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_VPE) | (((val) & 0x1) << 27)) |
| 288 | /* Service Priority Enable (26) */ |
| 289 | #define LTQ_ES_P0_CTL_REG_SPE (0x1 << 26) |
| 290 | #define LTQ_ES_P0_CTL_REG_SPE_VAL(val) (((val) & 0x1) << 26) |
| 291 | #define LTQ_ES_P0_CTL_REG_SPE_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_SPE) >> 26) & 0x1) |
| 292 | #define LTQ_ES_P0_CTL_REG_SPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_SPE) | (((val) & 0x1) << 26)) |
| 293 | /* IP over VLAN PRI (25) */ |
| 294 | #define LTQ_ES_P0_CTL_REG_IPVLAN (0x1 << 25) |
| 295 | #define LTQ_ES_P0_CTL_REG_IPVLAN_VAL(val) (((val) & 0x1) << 25) |
| 296 | #define LTQ_ES_P0_CTL_REG_IPVLAN_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_IPVLAN) >> 25) & 0x1) |
| 297 | #define LTQ_ES_P0_CTL_REG_IPVLAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_IPVLAN) | (((val) & 0x1) << 25)) |
| 298 | /* Ether Type Priority Enable (24) */ |
| 299 | #define LTQ_ES_P0_CTL_REG_TPE (0x1 << 24) |
| 300 | #define LTQ_ES_P0_CTL_REG_TPE_VAL(val) (((val) & 0x1) << 24) |
| 301 | #define LTQ_ES_P0_CTL_REG_TPE_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_TPE) >> 24) & 0x1) |
| 302 | #define LTQ_ES_P0_CTL_REG_TPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_TPE) | (((val) & 0x1) << 24)) |
| 303 | /* Force Link Up (18) */ |
| 304 | #define LTQ_ES_P0_CTL_REG_FLP (0x1 << 18) |
| 305 | #define LTQ_ES_P0_CTL_REG_FLP_VAL(val) (((val) & 0x1) << 18) |
| 306 | #define LTQ_ES_P0_CTL_REG_FLP_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_FLP) >> 18) & 0x1) |
| 307 | #define LTQ_ES_P0_CTL_REG_FLP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_FLP) | (((val) & 0x1) << 18)) |
| 308 | /* Force Link Down (17) */ |
| 309 | #define LTQ_ES_P0_CTL_REG_FLD (0x1 << 17) |
| 310 | #define LTQ_ES_P0_CTL_REG_FLD_VAL(val) (((val) & 0x1) << 17) |
| 311 | #define LTQ_ES_P0_CTL_REG_FLD_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_FLD) >> 17) & 0x1) |
| 312 | #define LTQ_ES_P0_CTL_REG_FLD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_FLD) | (((val) & 0x1) << 17)) |
| 313 | /* Ratio Mode for WFQ (16) */ |
| 314 | #define LTQ_ES_P0_CTL_REG_RMWFQ (0x1 << 16) |
| 315 | #define LTQ_ES_P0_CTL_REG_RMWFQ_VAL(val) (((val) & 0x1) << 16) |
| 316 | #define LTQ_ES_P0_CTL_REG_RMWFQ_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_RMWFQ) >> 16) & 0x1) |
| 317 | #define LTQ_ES_P0_CTL_REG_RMWFQ_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_RMWFQ) | (((val) & 0x1) << 16)) |
| 318 | /* Aging Disable (15) */ |
| 319 | #define LTQ_ES_P0_CTL_REG_AD (0x1 << 15) |
| 320 | #define LTQ_ES_P0_CTL_REG_AD_VAL(val) (((val) & 0x1) << 15) |
| 321 | #define LTQ_ES_P0_CTL_REG_AD_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_AD) >> 15) & 0x1) |
| 322 | #define LTQ_ES_P0_CTL_REG_AD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_AD) | (((val) & 0x1) << 15)) |
| 323 | /* Learning Disable (14) */ |
| 324 | #define LTQ_ES_P0_CTL_REG_LD (0x1 << 14) |
| 325 | #define LTQ_ES_P0_CTL_REG_LD_VAL(val) (((val) & 0x1) << 14) |
| 326 | #define LTQ_ES_P0_CTL_REG_LD_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_LD) >> 14) & 0x1) |
| 327 | #define LTQ_ES_P0_CTL_REG_LD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_LD) | (((val) & 0x1) << 14)) |
| 328 | /* Maximum Number of Addresses (12:8) */ |
| 329 | #define LTQ_ES_P0_CTL_REG_MNA024 (0x1f << 8) |
| 330 | #define LTQ_ES_P0_CTL_REG_MNA024_VAL(val) (((val) & 0x1f) << 8) |
| 331 | #define LTQ_ES_P0_CTL_REG_MNA024_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_MNA024) >> 8) & 0x1f) |
| 332 | #define LTQ_ES_P0_CTL_REG_MNA024_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_MNA024) | (((val) & 0x1f) << 8)) |
| 333 | /* PPPOE Port Only (7) */ |
| 334 | #define LTQ_ES_P0_CTL_REG_PPPOEP (0x1 << 7) |
| 335 | #define LTQ_ES_P0_CTL_REG_PPPOEP_VAL(val) (((val) & 0x1) << 7) |
| 336 | #define LTQ_ES_P0_CTL_REG_PPPOEP_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_PPPOEP) >> 7) & 0x1) |
| 337 | #define LTQ_ES_P0_CTL_REG_PPPOEP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_PPPOEP) | (((val) & 0x1) << 7)) |
| 338 | /* PPPOE Manage (6) */ |
| 339 | #define LTQ_ES_P0_CTL_REG_PM (0x1 << 6) |
| 340 | #define LTQ_ES_P0_CTL_REG_PM_VAL(val) (((val) & 0x1) << 6) |
| 341 | #define LTQ_ES_P0_CTL_REG_PM_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_PM) >> 6) & 0x1) |
| 342 | #define LTQ_ES_P0_CTL_REG_PM_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_PM) | (((val) & 0x1) << 6)) |
| 343 | /* Port Mirror Option (5:4) */ |
| 344 | #define LTQ_ES_P0_CTL_REG_IPMO (0x3 << 4) |
| 345 | #define LTQ_ES_P0_CTL_REG_IPMO_VAL(val) (((val) & 0x3) << 4) |
| 346 | #define LTQ_ES_P0_CTL_REG_IPMO_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_IPMO) >> 4) & 0x3) |
| 347 | #define LTQ_ES_P0_CTL_REG_IPMO_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_IPMO) | (((val) & 0x3) << 4)) |
| 348 | /* 802.1x Port Authorized state (3:2) */ |
| 349 | #define LTQ_ES_P0_CTL_REG_PAS (0x3 << 2) |
| 350 | #define LTQ_ES_P0_CTL_REG_PAS_VAL(val) (((val) & 0x3) << 2) |
| 351 | #define LTQ_ES_P0_CTL_REG_PAS_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_PAS) >> 2) & 0x3) |
| 352 | #define LTQ_ES_P0_CTL_REG_PAS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_PAS) | (((val) & 0x3) << 2)) |
| 353 | /* Drop Scheme for voilation 802.1x (1) */ |
| 354 | #define LTQ_ES_P0_CTL_REG_DSV8021X (0x1 << 1) |
| 355 | #define LTQ_ES_P0_CTL_REG_DSV8021X_VAL(val) (((val) & 0x1) << 1) |
| 356 | #define LTQ_ES_P0_CTL_REG_DSV8021X_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_DSV8021X) >> 1) & 0x1) |
| 357 | #define LTQ_ES_P0_CTL_REG_DSV8021X_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_DSV8021X) | (((val) & 0x1) << 1)) |
| 358 | /* ByPass Mode for Output (0) */ |
| 359 | #define LTQ_ES_P0_CTL_REG_BYPASS (0x1) |
| 360 | #define LTQ_ES_P0_CTL_REG_BYPASS_VAL(val) (((val) & 0x1) << 0) |
| 361 | #define LTQ_ES_P0_CTL_REG_BYPASS_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_BYPASS) >> 0) & 0x1) |
| 362 | #define LTQ_ES_P0_CTL_REG_BYPASS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_BYPASS) | (((val) & 0x1) << 0)) |
| 363 | |
| 364 | /******************************************************************************* |
| 365 | * Port 0 VLAN Control Register |
| 366 | ******************************************************************************/ |
| 367 | |
| 368 | /* Default FID (31:30) */ |
| 369 | #define LTQ_ES_P0_VLAN_REG_DFID (0x3 << 30) |
| 370 | #define LTQ_ES_P0_VLAN_REG_DFID_VAL(val) (((val) & 0x3) << 30) |
| 371 | #define LTQ_ES_P0_VLAN_REG_DFID_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_DFID) >> 30) & 0x3) |
| 372 | #define LTQ_ES_P0_VLAN_REG_DFID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_DFID) | (((val) & 0x3) << 30)) |
| 373 | /* Tagged Base VLAN Enable (29) */ |
| 374 | #define LTQ_ES_P0_VLAN_REG_TBVE (0x1 << 29) |
| 375 | #define LTQ_ES_P0_VLAN_REG_TBVE_VAL(val) (((val) & 0x1) << 29) |
| 376 | #define LTQ_ES_P0_VLAN_REG_TBVE_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_TBVE) >> 29) & 0x1) |
| 377 | #define LTQ_ES_P0_VLAN_REG_TBVE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_TBVE) | (((val) & 0x1) << 29)) |
| 378 | /* Input Force No TAG Enable (28) */ |
| 379 | #define LTQ_ES_P0_VLAN_REG_IFNTE (0x1 << 28) |
| 380 | #define LTQ_ES_P0_VLAN_REG_IFNTE_VAL(val) (((val) & 0x1) << 28) |
| 381 | #define LTQ_ES_P0_VLAN_REG_IFNTE_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_IFNTE) >> 28) & 0x1) |
| 382 | #define LTQ_ES_P0_VLAN_REG_IFNTE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_IFNTE) | (((val) & 0x1) << 28)) |
| 383 | /* VID Check with the VID table (27) */ |
| 384 | #define LTQ_ES_P0_VLAN_REG_VC (0x1 << 27) |
| 385 | #define LTQ_ES_P0_VLAN_REG_VC_VAL(val) (((val) & 0x1) << 27) |
| 386 | #define LTQ_ES_P0_VLAN_REG_VC_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_VC) >> 27) & 0x1) |
| 387 | #define LTQ_ES_P0_VLAN_REG_VC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_VC) | (((val) & 0x1) << 27)) |
| 388 | /* VLAN Security Disable (26) */ |
| 389 | #define LTQ_ES_P0_VLAN_REG_VSD (0x1 << 26) |
| 390 | #define LTQ_ES_P0_VLAN_REG_VSD_VAL(val) (((val) & 0x1) << 26) |
| 391 | #define LTQ_ES_P0_VLAN_REG_VSD_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_VSD) >> 26) & 0x1) |
| 392 | #define LTQ_ES_P0_VLAN_REG_VSD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_VSD) | (((val) & 0x1) << 26)) |
| 393 | /* Admit Only VLAN_Tagged Packet (25) */ |
| 394 | #define LTQ_ES_P0_VLAN_REG_AOVTP (0x1 << 25) |
| 395 | #define LTQ_ES_P0_VLAN_REG_AOVTP_VAL(val) (((val) & 0x1) << 25) |
| 396 | #define LTQ_ES_P0_VLAN_REG_AOVTP_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_AOVTP) >> 25) & 0x1) |
| 397 | #define LTQ_ES_P0_VLAN_REG_AOVTP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_AOVTP) | (((val) & 0x1) << 25)) |
| 398 | /* VLAN Member Check Enable (24) */ |
| 399 | #define LTQ_ES_P0_VLAN_REG_VMCE (0x1 << 24) |
| 400 | #define LTQ_ES_P0_VLAN_REG_VMCE_VAL(val) (((val) & 0x1) << 24) |
| 401 | #define LTQ_ES_P0_VLAN_REG_VMCE_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_VMCE) >> 24) & 0x1) |
| 402 | #define LTQ_ES_P0_VLAN_REG_VMCE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_VMCE) | (((val) & 0x1) << 24)) |
| 403 | /* Reserved (23:19) */ |
| 404 | #define LTQ_ES_P0_VLAN_REG_RES (0x1f << 19) |
| 405 | #define LTQ_ES_P0_VLAN_REG_RES_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_RES) >> 19) & 0x1f) |
| 406 | /* Default VLAN Port Map (18:16) */ |
| 407 | #define LTQ_ES_P0_VLAN_REG_DVPM (0x7 << 16) |
| 408 | #define LTQ_ES_P0_VLAN_REG_DVPM_VAL(val) (((val) & 0x7) << 16) |
| 409 | #define LTQ_ES_P0_VLAN_REG_DVPM_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_DVPM) >> 16) & 0x7) |
| 410 | #define LTQ_ES_P0_VLAN_REG_DVPM_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_DVPM) | (((val) & 0x7) << 16)) |
| 411 | /* Port Priority (15:14) */ |
| 412 | #define LTQ_ES_P0_VLAN_REG_PP (0x3 << 14) |
| 413 | #define LTQ_ES_P0_VLAN_REG_PP_VAL(val) (((val) & 0x3) << 14) |
| 414 | #define LTQ_ES_P0_VLAN_REG_PP_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_PP) >> 14) & 0x3) |
| 415 | #define LTQ_ES_P0_VLAN_REG_PP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_PP) | (((val) & 0x3) << 14)) |
| 416 | /* Port Priority Enable (13) */ |
| 417 | #define LTQ_ES_P0_VLAN_REG_PPE (0x1 << 13) |
| 418 | #define LTQ_ES_P0_VLAN_REG_PPE_VAL(val) (((val) & 0x1) << 13) |
| 419 | #define LTQ_ES_P0_VLAN_REG_PPE_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_PPE) >> 13) & 0x1) |
| 420 | #define LTQ_ES_P0_VLAN_REG_PPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_PPE) | (((val) & 0x1) << 13)) |
| 421 | /* Portbase VLAN tag member for Port 0 (12) */ |
| 422 | #define LTQ_ES_P0_VLAN_REG_PVTAGMP (0x1 << 12) |
| 423 | #define LTQ_ES_P0_VLAN_REG_PVTAGMP_VAL(val) (((val) & 0x1) << 12) |
| 424 | #define LTQ_ES_P0_VLAN_REG_PVTAGMP_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_PVTAGMP) >> 12) & 0x1) |
| 425 | #define LTQ_ES_P0_VLAN_REG_PVTAGMP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_PVTAGMP) | (((val) & 0x1) << 12)) |
| 426 | /* PVID (11:0) */ |
| 427 | #define LTQ_ES_P0_VLAN_REG_PVID (0xfff) |
| 428 | #define LTQ_ES_P0_VLAN_REG_PVID_VAL(val) (((val) & 0xfff) << 0) |
| 429 | #define LTQ_ES_P0_VLAN_REG_PVID_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_PVID) >> 0) & 0xfff) |
| 430 | #define LTQ_ES_P0_VLAN_REG_PVID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_PVID) | (((val) & 0xfff) << 0)) |
| 431 | |
| 432 | /******************************************************************************* |
| 433 | * Port 0 Ingress Control Register |
| 434 | ******************************************************************************/ |
| 435 | |
| 436 | /* Reserved (31:13) */ |
| 437 | #define LTQ_ES_P0_INCTL_REG_RES (0x7ffff << 13) |
| 438 | #define LTQ_ES_P0_INCTL_REG_RES_GET(val) ((((val) & LTQ_ES_P0_INCTL_REG_RES) >> 13) & 0x7ffff) |
| 439 | /* Port 0 Ingress/Egress Timer Tick T selection (12:11) */ |
| 440 | #define LTQ_ES_P0_INCTL_REG_P0ITT (0x3 << 11) |
| 441 | #define LTQ_ES_P0_INCTL_REG_P0ITT_VAL(val) (((val) & 0x3) << 11) |
| 442 | #define LTQ_ES_P0_INCTL_REG_P0ITT_GET(val) ((((val) & LTQ_ES_P0_INCTL_REG_P0ITT) >> 11) & 0x3) |
| 443 | #define LTQ_ES_P0_INCTL_REG_P0ITT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_INCTL_REG_P0ITT) | (((val) & 0x3) << 11)) |
| 444 | /* Port 0 Igress Token R (10:0) */ |
| 445 | #define LTQ_ES_P0_INCTL_REG_P0ITR (0x7ff) |
| 446 | #define LTQ_ES_P0_INCTL_REG_P0ITR_VAL(val) (((val) & 0x7ff) << 0) |
| 447 | #define LTQ_ES_P0_INCTL_REG_P0ITR_GET(val) ((((val) & LTQ_ES_P0_INCTL_REG_P0ITR) >> 0) & 0x7ff) |
| 448 | #define LTQ_ES_P0_INCTL_REG_P0ITR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_INCTL_REG_P0ITR) | (((val) & 0x7ff) << 0)) |
| 449 | |
| 450 | /******************************************************************************* |
| 451 | * Port 0 Egress Control for Strict Q32 Register |
| 452 | ******************************************************************************/ |
| 453 | |
| 454 | /* Port 0 Egress Token R for Strict Priority Q3 (26:16) */ |
| 455 | #define LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR (0x7ff << 16) |
| 456 | #define LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR_VAL(val) (((val) & 0x7ff) << 16) |
| 457 | #define LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR_GET(val) ((((val) & LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR) >> 16) & 0x7ff) |
| 458 | #define LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR) | (((val) & 0x7ff) << 16)) |
| 459 | /* Port 0 Egress Token R for Strict Priority Q2 (10:0) */ |
| 460 | #define LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR (0x7ff) |
| 461 | #define LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR_VAL(val) (((val) & 0x7ff) << 0) |
| 462 | #define LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR_GET(val) ((((val) & LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR) >> 0) & 0x7ff) |
| 463 | #define LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR) | (((val) & 0x7ff) << 0)) |
| 464 | |
| 465 | /******************************************************************************* |
| 466 | * Port 0 Egress Control for Strict Q10 Register |
| 467 | ******************************************************************************/ |
| 468 | |
| 469 | /* Reserved (31:27) */ |
| 470 | #define LTQ_ES_P0_ECS_Q10_REG_RES (0x1f << 27) |
| 471 | #define LTQ_ES_P0_ECS_Q10_REG_RES_GET(val) ((((val) & LTQ_ES_P0_ECS_Q10_REG_RES) >> 27) & 0x1f) |
| 472 | /* Port 0 Egress Token R for Strict Priority Q1 (26:16) */ |
| 473 | #define LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR (0x7ff << 16) |
| 474 | #define LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR_VAL(val) (((val) & 0x7ff) << 16) |
| 475 | #define LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR_GET(val) ((((val) & LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR) >> 16) & 0x7ff) |
| 476 | #define LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR) | (((val) & 0x7ff) << 16)) |
| 477 | /* Port 0 Egress Token R for Strict Priority Q0 (10:0) */ |
| 478 | #define LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR (0x7ff) |
| 479 | #define LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR_VAL(val) (((val) & 0x7ff) << 0) |
| 480 | #define LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR_GET(val) ((((val) & LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR) >> 0) & 0x7ff) |
| 481 | #define LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR) | (((val) & 0x7ff) << 0)) |
| 482 | |
| 483 | /******************************************************************************* |
| 484 | * Port 0 Egress Control for WFQ Q32 Register |
| 485 | ******************************************************************************/ |
| 486 | |
| 487 | /* Reserved (31:27) */ |
| 488 | #define LTQ_ES_P0_ECW_Q32_REG_RES (0x1f << 27) |
| 489 | #define LTQ_ES_P0_ECW_Q32_REG_RES_GET(val) ((((val) & LTQ_ES_P0_ECW_Q32_REG_RES) >> 27) & 0x1f) |
| 490 | /* Port 0 Egress Token R for WFQ Q3 (26:16) */ |
| 491 | #define LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR (0x7ff << 16) |
| 492 | #define LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR_VAL(val) (((val) & 0x7ff) << 16) |
| 493 | #define LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR_GET(val) ((((val) & LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR) >> 16) & 0x7ff) |
| 494 | #define LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR) | (((val) & 0x7ff) << 16)) |
| 495 | /* Port 0 Egress Token R for WFQ Q2 (10:0) */ |
| 496 | #define LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR (0x7ff) |
| 497 | #define LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR_VAL(val) (((val) & 0x7ff) << 0) |
| 498 | #define LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR_GET(val) ((((val) & LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR) >> 0) & 0x7ff) |
| 499 | #define LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR) | (((val) & 0x7ff) << 0)) |
| 500 | |
| 501 | /******************************************************************************* |
| 502 | * Port 0 Egress Control for WFQ Q10 Register |
| 503 | ******************************************************************************/ |
| 504 | |
| 505 | /* Reserved (31:27) */ |
| 506 | #define LTQ_ES_P0_ECW_Q10_REG_RES (0x1f << 27) |
| 507 | #define LTQ_ES_P0_ECW_Q10_REG_RES_GET(val) ((((val) & LTQ_ES_P0_ECW_Q10_REG_RES) >> 27) & 0x1f) |
| 508 | /* Port 0 Egress Token R for WFQ Q1 (26:16) */ |
| 509 | #define LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR (0x7ff << 16) |
| 510 | #define LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR_VAL(val) (((val) & 0x7ff) << 16) |
| 511 | #define LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR_GET(val) ((((val) & LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR) >> 16) & 0x7ff) |
| 512 | #define LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR) | (((val) & 0x7ff) << 16)) |
| 513 | /* Port 0 Egress Token R for WFQ Q0 (10:0) */ |
| 514 | #define LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR (0x7ff) |
| 515 | #define LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR_VAL(val) (((val) & 0x7ff) << 0) |
| 516 | #define LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR_GET(val) ((((val) & LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR) >> 0) & 0x7ff) |
| 517 | #define LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR) | (((val) & 0x7ff) << 0)) |
| 518 | |
| 519 | /******************************************************************************* |
| 520 | * Interrupt Enable Register |
| 521 | ******************************************************************************/ |
| 522 | |
| 523 | /* Reserved (31:8) */ |
| 524 | #define LTQ_ES_INT_ENA_REG_RES (0xffffff << 8) |
| 525 | #define LTQ_ES_INT_ENA_REG_RES_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_RES) >> 8) & 0xffffff) |
| 526 | /* Data Buffer is Full Interrupt Enable (7) */ |
| 527 | #define LTQ_ES_INT_ENA_REG_DBFIE (0x1 << 7) |
| 528 | #define LTQ_ES_INT_ENA_REG_DBFIE_VAL(val) (((val) & 0x1) << 7) |
| 529 | #define LTQ_ES_INT_ENA_REG_DBFIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_DBFIE) >> 7) & 0x1) |
| 530 | #define LTQ_ES_INT_ENA_REG_DBFIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_DBFIE) | (((val) & 0x1) << 7)) |
| 531 | /* Data Buffer is nearly Full Interrupt Enable (6) */ |
| 532 | #define LTQ_ES_INT_ENA_REG_DBNFIE (0x1 << 6) |
| 533 | #define LTQ_ES_INT_ENA_REG_DBNFIE_VAL(val) (((val) & 0x1) << 6) |
| 534 | #define LTQ_ES_INT_ENA_REG_DBNFIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_DBNFIE) >> 6) & 0x1) |
| 535 | #define LTQ_ES_INT_ENA_REG_DBNFIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_DBNFIE) | (((val) & 0x1) << 6)) |
| 536 | /* Learning Table Full Interrupt Enable (5) */ |
| 537 | #define LTQ_ES_INT_ENA_REG_LTFIE (0x1 << 5) |
| 538 | #define LTQ_ES_INT_ENA_REG_LTFIE_VAL(val) (((val) & 0x1) << 5) |
| 539 | #define LTQ_ES_INT_ENA_REG_LTFIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_LTFIE) >> 5) & 0x1) |
| 540 | #define LTQ_ES_INT_ENA_REG_LTFIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_LTFIE) | (((val) & 0x1) << 5)) |
| 541 | /* Leaning Table Access Done Interrupt Enable (4) */ |
| 542 | #define LTQ_ES_INT_ENA_REG_LTADIE (0x1 << 4) |
| 543 | #define LTQ_ES_INT_ENA_REG_LTADIE_VAL(val) (((val) & 0x1) << 4) |
| 544 | #define LTQ_ES_INT_ENA_REG_LTADIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_LTADIE) >> 4) & 0x1) |
| 545 | #define LTQ_ES_INT_ENA_REG_LTADIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_LTADIE) | (((val) & 0x1) << 4)) |
| 546 | /* Port Security Violation Interrupt Enable (3:1) */ |
| 547 | #define LTQ_ES_INT_ENA_REG_PSVIE (0x7 << 1) |
| 548 | #define LTQ_ES_INT_ENA_REG_PSVIE_VAL(val) (((val) & 0x7) << 1) |
| 549 | #define LTQ_ES_INT_ENA_REG_PSVIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_PSVIE) >> 1) & 0x7) |
| 550 | #define LTQ_ES_INT_ENA_REG_PSVIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_PSVIE) | (((val) & 0x7) << 1)) |
| 551 | /* Port Status Change Interrupt Enable (0) */ |
| 552 | #define LTQ_ES_INT_ENA_REG_PSCIE (0x1) |
| 553 | #define LTQ_ES_INT_ENA_REG_PSCIE_VAL(val) (((val) & 0x1) << 0) |
| 554 | #define LTQ_ES_INT_ENA_REG_PSCIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_PSCIE) >> 0) & 0x1) |
| 555 | #define LTQ_ES_INT_ENA_REG_PSCIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_PSCIE) | (((val) & 0x1) << 0)) |
| 556 | |
| 557 | /******************************************************************************* |
| 558 | * Interrupt Status Register |
| 559 | ******************************************************************************/ |
| 560 | |
| 561 | /* Reserved (31:8) */ |
| 562 | #define LTQ_ES_INT_ST_REG_RES (0xffffff << 8) |
| 563 | #define LTQ_ES_INT_ST_REG_RES_GET(val) ((((val) & LTQ_ES_INT_ST_REG_RES) >> 8) & 0xffffff) |
| 564 | /* Data Buffer is Full (7) */ |
| 565 | #define LTQ_ES_INT_ST_REG_DBF (0x1 << 7) |
| 566 | #define LTQ_ES_INT_ST_REG_DBF_GET(val) ((((val) & LTQ_ES_INT_ST_REG_DBF) >> 7) & 0x1) |
| 567 | /* Data Buffer is nearly Full (6) */ |
| 568 | #define LTQ_ES_INT_ST_REG_DBNF (0x1 << 6) |
| 569 | #define LTQ_ES_INT_ST_REG_DBNF_GET(val) ((((val) & LTQ_ES_INT_ST_REG_DBNF) >> 6) & 0x1) |
| 570 | /* Learning Table Full (5) */ |
| 571 | #define LTQ_ES_INT_ST_REG_LTF (0x1 << 5) |
| 572 | #define LTQ_ES_INT_ST_REG_LTF_GET(val) ((((val) & LTQ_ES_INT_ST_REG_LTF) >> 5) & 0x1) |
| 573 | /* Leaning Table Access Done (4) */ |
| 574 | #define LTQ_ES_INT_ST_REG_LTAD (0x1 << 4) |
| 575 | #define LTQ_ES_INT_ST_REG_LTAD_GET(val) ((((val) & LTQ_ES_INT_ST_REG_LTAD) >> 4) & 0x1) |
| 576 | /* Port Security Violation (3:1) */ |
| 577 | #define LTQ_ES_INT_ST_REG_PSV (0x7 << 1) |
| 578 | #define LTQ_ES_INT_ST_REG_PSV_GET(val) ((((val) & LTQ_ES_INT_ST_REG_PSV) >> 1) & 0x7) |
| 579 | /* Port Status Change (0) */ |
| 580 | #define LTQ_ES_INT_ST_REG_PSC (0x1) |
| 581 | #define LTQ_ES_INT_ST_REG_PSC_GET(val) ((((val) & LTQ_ES_INT_ST_REG_PSC) >> 0) & 0x1) |
| 582 | |
| 583 | /******************************************************************************* |
| 584 | * Switch Global Control Register 0 |
| 585 | ******************************************************************************/ |
| 586 | |
| 587 | /* Switch Enable (31) */ |
| 588 | #define LTQ_ES_SW_GCTL0_REG_SE (0x1 << 31) |
| 589 | #define LTQ_ES_SW_GCTL0_REG_SE_VAL(val) (((val) & 0x1) << 31) |
| 590 | #define LTQ_ES_SW_GCTL0_REG_SE_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_SE) >> 31) & 0x1) |
| 591 | #define LTQ_ES_SW_GCTL0_REG_SE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_SE) | (((val) & 0x1) << 31)) |
| 592 | /* CRC Check Disable (30) */ |
| 593 | #define LTQ_ES_SW_GCTL0_REG_ICRCCD (0x1 << 30) |
| 594 | #define LTQ_ES_SW_GCTL0_REG_ICRCCD_VAL(val) (((val) & 0x1) << 30) |
| 595 | #define LTQ_ES_SW_GCTL0_REG_ICRCCD_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_ICRCCD) >> 30) & 0x1) |
| 596 | #define LTQ_ES_SW_GCTL0_REG_ICRCCD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_ICRCCD) | (((val) & 0x1) << 30)) |
| 597 | /* Replace VID0 (28) */ |
| 598 | #define LTQ_ES_SW_GCTL0_REG_RVID0 (0x1 << 28) |
| 599 | #define LTQ_ES_SW_GCTL0_REG_RVID0_VAL(val) (((val) & 0x1) << 28) |
| 600 | #define LTQ_ES_SW_GCTL0_REG_RVID0_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_RVID0) >> 28) & 0x1) |
| 601 | #define LTQ_ES_SW_GCTL0_REG_RVID0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_RVID0) | (((val) & 0x1) << 28)) |
| 602 | /* Replace VID1 (27) */ |
| 603 | #define LTQ_ES_SW_GCTL0_REG_RVID1 (0x1 << 27) |
| 604 | #define LTQ_ES_SW_GCTL0_REG_RVID1_VAL(val) (((val) & 0x1) << 27) |
| 605 | #define LTQ_ES_SW_GCTL0_REG_RVID1_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_RVID1) >> 27) & 0x1) |
| 606 | #define LTQ_ES_SW_GCTL0_REG_RVID1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_RVID1) | (((val) & 0x1) << 27)) |
| 607 | /* Replace VIDFFF (26) */ |
| 608 | #define LTQ_ES_SW_GCTL0_REG_RVIDFFF (0x1 << 26) |
| 609 | #define LTQ_ES_SW_GCTL0_REG_RVIDFFF_VAL(val) (((val) & 0x1) << 26) |
| 610 | #define LTQ_ES_SW_GCTL0_REG_RVIDFFF_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_RVIDFFF) >> 26) & 0x1) |
| 611 | #define LTQ_ES_SW_GCTL0_REG_RVIDFFF_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_RVIDFFF) | (((val) & 0x1) << 26)) |
| 612 | /* Priority Change Rule (25) */ |
| 613 | #define LTQ_ES_SW_GCTL0_REG_PCR (0x1 << 25) |
| 614 | #define LTQ_ES_SW_GCTL0_REG_PCR_VAL(val) (((val) & 0x1) << 25) |
| 615 | #define LTQ_ES_SW_GCTL0_REG_PCR_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_PCR) >> 25) & 0x1) |
| 616 | #define LTQ_ES_SW_GCTL0_REG_PCR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_PCR) | (((val) & 0x1) << 25)) |
| 617 | /* Priority Change Enable (24) */ |
| 618 | #define LTQ_ES_SW_GCTL0_REG_PCE (0x1 << 24) |
| 619 | #define LTQ_ES_SW_GCTL0_REG_PCE_VAL(val) (((val) & 0x1) << 24) |
| 620 | #define LTQ_ES_SW_GCTL0_REG_PCE_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_PCE) >> 24) & 0x1) |
| 621 | #define LTQ_ES_SW_GCTL0_REG_PCE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_PCE) | (((val) & 0x1) << 24)) |
| 622 | /* Transmit Short IPG Enable (23) */ |
| 623 | #define LTQ_ES_SW_GCTL0_REG_TSIPGE (0x1 << 23) |
| 624 | #define LTQ_ES_SW_GCTL0_REG_TSIPGE_VAL(val) (((val) & 0x1) << 23) |
| 625 | #define LTQ_ES_SW_GCTL0_REG_TSIPGE_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_TSIPGE) >> 23) & 0x1) |
| 626 | #define LTQ_ES_SW_GCTL0_REG_TSIPGE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_TSIPGE) | (((val) & 0x1) << 23)) |
| 627 | /* PHY Base Address (22) */ |
| 628 | #define LTQ_ES_SW_GCTL0_REG_PHYBA (0x1 << 22) |
| 629 | #define LTQ_ES_SW_GCTL0_REG_PHYBA_VAL(val) (((val) & 0x1) << 22) |
| 630 | #define LTQ_ES_SW_GCTL0_REG_PHYBA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_PHYBA) >> 22) & 0x1) |
| 631 | #define LTQ_ES_SW_GCTL0_REG_PHYBA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_PHYBA) | (((val) & 0x1) << 22)) |
| 632 | /* Drop Packet When Excessive Collision Happen (21) */ |
| 633 | #define LTQ_ES_SW_GCTL0_REG_DPWECH (0x1 << 21) |
| 634 | #define LTQ_ES_SW_GCTL0_REG_DPWECH_VAL(val) (((val) & 0x1) << 21) |
| 635 | #define LTQ_ES_SW_GCTL0_REG_DPWECH_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DPWECH) >> 21) & 0x1) |
| 636 | #define LTQ_ES_SW_GCTL0_REG_DPWECH_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DPWECH) | (((val) & 0x1) << 21)) |
| 637 | /* Aging Timer Select (20:18) */ |
| 638 | #define LTQ_ES_SW_GCTL0_REG_ATS (0x7 << 18) |
| 639 | #define LTQ_ES_SW_GCTL0_REG_ATS_VAL(val) (((val) & 0x7) << 18) |
| 640 | #define LTQ_ES_SW_GCTL0_REG_ATS_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_ATS) >> 18) & 0x7) |
| 641 | #define LTQ_ES_SW_GCTL0_REG_ATS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_ATS) | (((val) & 0x7) << 18)) |
| 642 | /* Mirror CRC Also (17) */ |
| 643 | #define LTQ_ES_SW_GCTL0_REG_MCA (0x1 << 17) |
| 644 | #define LTQ_ES_SW_GCTL0_REG_MCA_VAL(val) (((val) & 0x1) << 17) |
| 645 | #define LTQ_ES_SW_GCTL0_REG_MCA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MCA) >> 17) & 0x1) |
| 646 | #define LTQ_ES_SW_GCTL0_REG_MCA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MCA) | (((val) & 0x1) << 17)) |
| 647 | /* Mirror RXER Also (16) */ |
| 648 | #define LTQ_ES_SW_GCTL0_REG_MRA (0x1 << 16) |
| 649 | #define LTQ_ES_SW_GCTL0_REG_MRA_VAL(val) (((val) & 0x1) << 16) |
| 650 | #define LTQ_ES_SW_GCTL0_REG_MRA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MRA) >> 16) & 0x1) |
| 651 | #define LTQ_ES_SW_GCTL0_REG_MRA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MRA) | (((val) & 0x1) << 16)) |
| 652 | /* Mirror PAUSE Also (15) */ |
| 653 | #define LTQ_ES_SW_GCTL0_REG_MPA (0x1 << 15) |
| 654 | #define LTQ_ES_SW_GCTL0_REG_MPA_VAL(val) (((val) & 0x1) << 15) |
| 655 | #define LTQ_ES_SW_GCTL0_REG_MPA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MPA) >> 15) & 0x1) |
| 656 | #define LTQ_ES_SW_GCTL0_REG_MPA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MPA) | (((val) & 0x1) << 15)) |
| 657 | /* Mirror Long Also (14) */ |
| 658 | #define LTQ_ES_SW_GCTL0_REG_MLA (0x1 << 14) |
| 659 | #define LTQ_ES_SW_GCTL0_REG_MLA_VAL(val) (((val) & 0x1) << 14) |
| 660 | #define LTQ_ES_SW_GCTL0_REG_MLA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MLA) >> 14) & 0x1) |
| 661 | #define LTQ_ES_SW_GCTL0_REG_MLA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MLA) | (((val) & 0x1) << 14)) |
| 662 | /* Mirror Short Also (13) */ |
| 663 | #define LTQ_ES_SW_GCTL0_REG_MSA (0x1 << 13) |
| 664 | #define LTQ_ES_SW_GCTL0_REG_MSA_VAL(val) (((val) & 0x1) << 13) |
| 665 | #define LTQ_ES_SW_GCTL0_REG_MSA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MSA) >> 13) & 0x1) |
| 666 | #define LTQ_ES_SW_GCTL0_REG_MSA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MSA) | (((val) & 0x1) << 13)) |
| 667 | /* Sniffer port number (12:11) */ |
| 668 | #define LTQ_ES_SW_GCTL0_REG_SNIFFPN (0x3 << 11) |
| 669 | #define LTQ_ES_SW_GCTL0_REG_SNIFFPN_VAL(val) (((val) & 0x3) << 11) |
| 670 | #define LTQ_ES_SW_GCTL0_REG_SNIFFPN_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_SNIFFPN) >> 11) & 0x3) |
| 671 | #define LTQ_ES_SW_GCTL0_REG_SNIFFPN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_SNIFFPN) | (((val) & 0x3) << 11)) |
| 672 | /* Max Packet Length (MAXPKTLEN) (9:8) */ |
| 673 | #define LTQ_ES_SW_GCTL0_REG_MPL (0x3 << 8) |
| 674 | #define LTQ_ES_SW_GCTL0_REG_MPL_VAL(val) (((val) & 0x3) << 8) |
| 675 | #define LTQ_ES_SW_GCTL0_REG_MPL_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MPL) >> 8) & 0x3) |
| 676 | #define LTQ_ES_SW_GCTL0_REG_MPL_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MPL) | (((val) & 0x3) << 8)) |
| 677 | /* Discard Mode (Drop scheme for Packets Classified as Q3) (7:6) */ |
| 678 | #define LTQ_ES_SW_GCTL0_REG_DMQ3 (0x3 << 6) |
| 679 | #define LTQ_ES_SW_GCTL0_REG_DMQ3_VAL(val) (((val) & 0x3) << 6) |
| 680 | #define LTQ_ES_SW_GCTL0_REG_DMQ3_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DMQ3) >> 6) & 0x3) |
| 681 | #define LTQ_ES_SW_GCTL0_REG_DMQ3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DMQ3) | (((val) & 0x3) << 6)) |
| 682 | /* Discard Mode (Drop scheme for Packets Classified as Q2) (5:4) */ |
| 683 | #define LTQ_ES_SW_GCTL0_REG_DMQ2 (0x3 << 4) |
| 684 | #define LTQ_ES_SW_GCTL0_REG_DMQ2_VAL(val) (((val) & 0x3) << 4) |
| 685 | #define LTQ_ES_SW_GCTL0_REG_DMQ2_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DMQ2) >> 4) & 0x3) |
| 686 | #define LTQ_ES_SW_GCTL0_REG_DMQ2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DMQ2) | (((val) & 0x3) << 4)) |
| 687 | /* Discard Mode (Drop scheme for Packets Classified as Q1) (3:2) */ |
| 688 | #define LTQ_ES_SW_GCTL0_REG_DMQ1 (0x3 << 2) |
| 689 | #define LTQ_ES_SW_GCTL0_REG_DMQ1_VAL(val) (((val) & 0x3) << 2) |
| 690 | #define LTQ_ES_SW_GCTL0_REG_DMQ1_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DMQ1) >> 2) & 0x3) |
| 691 | #define LTQ_ES_SW_GCTL0_REG_DMQ1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DMQ1) | (((val) & 0x3) << 2)) |
| 692 | /* Discard Mode (Drop scheme for Packets Classified as Q0) (1:0) */ |
| 693 | #define LTQ_ES_SW_GCTL0_REG_DMQ0 (0x3) |
| 694 | #define LTQ_ES_SW_GCTL0_REG_DMQ0_VAL(val) (((val) & 0x3) << 0) |
| 695 | #define LTQ_ES_SW_GCTL0_REG_DMQ0_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DMQ0) >> 0) & 0x3) |
| 696 | #define LTQ_ES_SW_GCTL0_REG_DMQ0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DMQ0) | (((val) & 0x3) << 0)) |
| 697 | |
| 698 | /******************************************************************************* |
| 699 | * Switch Global Control Register 1 |
| 700 | ******************************************************************************/ |
| 701 | |
| 702 | /* BIST Done (27) */ |
| 703 | #define LTQ_ES_SW_GCTL1_REG_BISTDN (0x1 << 27) |
| 704 | #define LTQ_ES_SW_GCTL1_REG_BISTDN_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_BISTDN) >> 27) & 0x1) |
| 705 | /* Enable drop scheme of TX and RX (26) */ |
| 706 | #define LTQ_ES_SW_GCTL1_REG_EDSTX (0x1 << 26) |
| 707 | #define LTQ_ES_SW_GCTL1_REG_EDSTX_VAL(val) (((val) & 0x1) << 26) |
| 708 | #define LTQ_ES_SW_GCTL1_REG_EDSTX_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_EDSTX) >> 26) & 0x1) |
| 709 | #define LTQ_ES_SW_GCTL1_REG_EDSTX_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_EDSTX) | (((val) & 0x1) << 26)) |
| 710 | /* Congestion threshold for TX queue (25:24) */ |
| 711 | #define LTQ_ES_SW_GCTL1_REG_CTTX (0x3 << 24) |
| 712 | #define LTQ_ES_SW_GCTL1_REG_CTTX_VAL(val) (((val) & 0x3) << 24) |
| 713 | #define LTQ_ES_SW_GCTL1_REG_CTTX_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_CTTX) >> 24) & 0x3) |
| 714 | #define LTQ_ES_SW_GCTL1_REG_CTTX_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_CTTX) | (((val) & 0x3) << 24)) |
| 715 | /* Input Jam Threshold (23:21) */ |
| 716 | #define LTQ_ES_SW_GCTL1_REG_IJT (0x7 << 21) |
| 717 | #define LTQ_ES_SW_GCTL1_REG_IJT_VAL(val) (((val) & 0x7) << 21) |
| 718 | #define LTQ_ES_SW_GCTL1_REG_IJT_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_IJT) >> 21) & 0x7) |
| 719 | #define LTQ_ES_SW_GCTL1_REG_IJT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_IJT) | (((val) & 0x7) << 21)) |
| 720 | /* Do not Identify VLAN after SNAP (20) */ |
| 721 | #define LTQ_ES_SW_GCTL1_REG_DIVS (0x1 << 20) |
| 722 | #define LTQ_ES_SW_GCTL1_REG_DIVS_VAL(val) (((val) & 0x1) << 20) |
| 723 | #define LTQ_ES_SW_GCTL1_REG_DIVS_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIVS) >> 20) & 0x1) |
| 724 | #define LTQ_ES_SW_GCTL1_REG_DIVS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIVS) | (((val) & 0x1) << 20)) |
| 725 | /* Do not Identify IPV6 in PPPOE (19) */ |
| 726 | #define LTQ_ES_SW_GCTL1_REG_DII6P (0x1 << 19) |
| 727 | #define LTQ_ES_SW_GCTL1_REG_DII6P_VAL(val) (((val) & 0x1) << 19) |
| 728 | #define LTQ_ES_SW_GCTL1_REG_DII6P_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DII6P) >> 19) & 0x1) |
| 729 | #define LTQ_ES_SW_GCTL1_REG_DII6P_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DII6P) | (((val) & 0x1) << 19)) |
| 730 | /* Do not Identify IP in PPPOE after SNAP (18) */ |
| 731 | #define LTQ_ES_SW_GCTL1_REG_DIIPS (0x1 << 18) |
| 732 | #define LTQ_ES_SW_GCTL1_REG_DIIPS_VAL(val) (((val) & 0x1) << 18) |
| 733 | #define LTQ_ES_SW_GCTL1_REG_DIIPS_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIIPS) >> 18) & 0x1) |
| 734 | #define LTQ_ES_SW_GCTL1_REG_DIIPS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIIPS) | (((val) & 0x1) << 18)) |
| 735 | /* Do not Identify Ether-Type = 0x0800, IP VER = 6 as IPV6 packets (17) */ |
| 736 | #define LTQ_ES_SW_GCTL1_REG_DIE (0x1 << 17) |
| 737 | #define LTQ_ES_SW_GCTL1_REG_DIE_VAL(val) (((val) & 0x1) << 17) |
| 738 | #define LTQ_ES_SW_GCTL1_REG_DIE_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIE) >> 17) & 0x1) |
| 739 | #define LTQ_ES_SW_GCTL1_REG_DIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIE) | (((val) & 0x1) << 17)) |
| 740 | /* Do not Identify IP in PPPOE (16) */ |
| 741 | #define LTQ_ES_SW_GCTL1_REG_DIIP (0x1 << 16) |
| 742 | #define LTQ_ES_SW_GCTL1_REG_DIIP_VAL(val) (((val) & 0x1) << 16) |
| 743 | #define LTQ_ES_SW_GCTL1_REG_DIIP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIIP) >> 16) & 0x1) |
| 744 | #define LTQ_ES_SW_GCTL1_REG_DIIP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIIP) | (((val) & 0x1) << 16)) |
| 745 | /* Do not Identify SNAP (15) */ |
| 746 | #define LTQ_ES_SW_GCTL1_REG_DIS (0x1 << 15) |
| 747 | #define LTQ_ES_SW_GCTL1_REG_DIS_VAL(val) (((val) & 0x1) << 15) |
| 748 | #define LTQ_ES_SW_GCTL1_REG_DIS_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIS) >> 15) & 0x1) |
| 749 | #define LTQ_ES_SW_GCTL1_REG_DIS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIS) | (((val) & 0x1) << 15)) |
| 750 | /* Unicast Portmap (14:12) */ |
| 751 | #define LTQ_ES_SW_GCTL1_REG_UP (0x7 << 12) |
| 752 | #define LTQ_ES_SW_GCTL1_REG_UP_VAL(val) (((val) & 0x7) << 12) |
| 753 | #define LTQ_ES_SW_GCTL1_REG_UP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_UP) >> 12) & 0x7) |
| 754 | #define LTQ_ES_SW_GCTL1_REG_UP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_UP) | (((val) & 0x7) << 12)) |
| 755 | /* Broadcast Portmap (10:8) */ |
| 756 | #define LTQ_ES_SW_GCTL1_REG_BP (0x7 << 8) |
| 757 | #define LTQ_ES_SW_GCTL1_REG_BP_VAL(val) (((val) & 0x7) << 8) |
| 758 | #define LTQ_ES_SW_GCTL1_REG_BP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_BP) >> 8) & 0x7) |
| 759 | #define LTQ_ES_SW_GCTL1_REG_BP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_BP) | (((val) & 0x7) << 8)) |
| 760 | /* Multicast Portmap (6:4) */ |
| 761 | #define LTQ_ES_SW_GCTL1_REG_MP (0x7 << 4) |
| 762 | #define LTQ_ES_SW_GCTL1_REG_MP_VAL(val) (((val) & 0x7) << 4) |
| 763 | #define LTQ_ES_SW_GCTL1_REG_MP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_MP) >> 4) & 0x7) |
| 764 | #define LTQ_ES_SW_GCTL1_REG_MP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_MP) | (((val) & 0x7) << 4)) |
| 765 | /* Reserve Portmap (2:0) */ |
| 766 | #define LTQ_ES_SW_GCTL1_REG_RP (0x7) |
| 767 | #define LTQ_ES_SW_GCTL1_REG_RP_VAL(val) (((val) & 0x7) << 0) |
| 768 | #define LTQ_ES_SW_GCTL1_REG_RP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_RP) >> 0) & 0x7) |
| 769 | #define LTQ_ES_SW_GCTL1_REG_RP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_RP) | (((val) & 0x7) << 0)) |
| 770 | |
| 771 | /******************************************************************************* |
| 772 | * ARP/RARP Register |
| 773 | ******************************************************************************/ |
| 774 | |
| 775 | /* MAC Control Action (15:14) */ |
| 776 | #define LTQ_ES_ARP_REG_MACA (0x3 << 14) |
| 777 | #define LTQ_ES_ARP_REG_MACA_VAL(val) (((val) & 0x3) << 14) |
| 778 | #define LTQ_ES_ARP_REG_MACA_GET(val) ((((val) & LTQ_ES_ARP_REG_MACA) >> 14) & 0x3) |
| 779 | #define LTQ_ES_ARP_REG_MACA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_MACA) | (((val) & 0x3) << 14)) |
| 780 | /* Unicast packet Treated as Cross_VLAN packet (13) */ |
| 781 | #define LTQ_ES_ARP_REG_UPT (0x1 << 13) |
| 782 | #define LTQ_ES_ARP_REG_UPT_VAL(val) (((val) & 0x1) << 13) |
| 783 | #define LTQ_ES_ARP_REG_UPT_GET(val) ((((val) & LTQ_ES_ARP_REG_UPT) >> 13) & 0x1) |
| 784 | #define LTQ_ES_ARP_REG_UPT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_UPT) | (((val) & 0x1) << 13)) |
| 785 | /* RARP Packet Treated as Cross_VLAN Packet (12) */ |
| 786 | #define LTQ_ES_ARP_REG_RPT (0x1 << 12) |
| 787 | #define LTQ_ES_ARP_REG_RPT_VAL(val) (((val) & 0x1) << 12) |
| 788 | #define LTQ_ES_ARP_REG_RPT_GET(val) ((((val) & LTQ_ES_ARP_REG_RPT) >> 12) & 0x1) |
| 789 | #define LTQ_ES_ARP_REG_RPT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RPT) | (((val) & 0x1) << 12)) |
| 790 | /* RARP/ARP Packet Action (11:10) */ |
| 791 | #define LTQ_ES_ARP_REG_RAPA (0x3 << 10) |
| 792 | #define LTQ_ES_ARP_REG_RAPA_VAL(val) (((val) & 0x3) << 10) |
| 793 | #define LTQ_ES_ARP_REG_RAPA_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPA) >> 10) & 0x3) |
| 794 | #define LTQ_ES_ARP_REG_RAPA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPA) | (((val) & 0x3) << 10)) |
| 795 | /* RARP/ARP Packet Priority Enable (9) */ |
| 796 | #define LTQ_ES_ARP_REG_RAPPE (0x1 << 9) |
| 797 | #define LTQ_ES_ARP_REG_RAPPE_VAL(val) (((val) & 0x1) << 9) |
| 798 | #define LTQ_ES_ARP_REG_RAPPE_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPPE) >> 9) & 0x1) |
| 799 | #define LTQ_ES_ARP_REG_RAPPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPPE) | (((val) & 0x1) << 9)) |
| 800 | /* RARP/ARP Packet Priority (8:7) */ |
| 801 | #define LTQ_ES_ARP_REG_RAPP (0x3 << 7) |
| 802 | #define LTQ_ES_ARP_REG_RAPP_VAL(val) (((val) & 0x3) << 7) |
| 803 | #define LTQ_ES_ARP_REG_RAPP_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPP) >> 7) & 0x3) |
| 804 | #define LTQ_ES_ARP_REG_RAPP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPP) | (((val) & 0x3) << 7)) |
| 805 | /* RARP/ARP Packet Output Tag Handle (6:5) */ |
| 806 | #define LTQ_ES_ARP_REG_RAPOTH (0x3 << 5) |
| 807 | #define LTQ_ES_ARP_REG_RAPOTH_VAL(val) (((val) & 0x3) << 5) |
| 808 | #define LTQ_ES_ARP_REG_RAPOTH_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPOTH) >> 5) & 0x3) |
| 809 | #define LTQ_ES_ARP_REG_RAPOTH_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPOTH) | (((val) & 0x3) << 5)) |
| 810 | /* ARP Packet Treated as Cross _ VLAN Packet (4) */ |
| 811 | #define LTQ_ES_ARP_REG_APT (0x1 << 4) |
| 812 | #define LTQ_ES_ARP_REG_APT_VAL(val) (((val) & 0x1) << 4) |
| 813 | #define LTQ_ES_ARP_REG_APT_GET(val) ((((val) & LTQ_ES_ARP_REG_APT) >> 4) & 0x1) |
| 814 | #define LTQ_ES_ARP_REG_APT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_APT) | (((val) & 0x1) << 4)) |
| 815 | /* RARP/ARP Packet Treated as Management Packet (3) */ |
| 816 | #define LTQ_ES_ARP_REG_RAPTM (0x1 << 3) |
| 817 | #define LTQ_ES_ARP_REG_RAPTM_VAL(val) (((val) & 0x1) << 3) |
| 818 | #define LTQ_ES_ARP_REG_RAPTM_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPTM) >> 3) & 0x1) |
| 819 | #define LTQ_ES_ARP_REG_RAPTM_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPTM) | (((val) & 0x1) << 3)) |
| 820 | /* RARP/ARP Packet Treated as Span Packet (2) */ |
| 821 | #define LTQ_ES_ARP_REG_TAPTS (0x1 << 2) |
| 822 | #define LTQ_ES_ARP_REG_TAPTS_VAL(val) (((val) & 0x1) << 2) |
| 823 | #define LTQ_ES_ARP_REG_TAPTS_GET(val) ((((val) & LTQ_ES_ARP_REG_TAPTS) >> 2) & 0x1) |
| 824 | #define LTQ_ES_ARP_REG_TAPTS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_TAPTS) | (((val) & 0x1) << 2)) |
| 825 | /* Trap ARP Packet (1) */ |
| 826 | #define LTQ_ES_ARP_REG_TAP (0x1 << 1) |
| 827 | #define LTQ_ES_ARP_REG_TAP_VAL(val) (((val) & 0x1) << 1) |
| 828 | #define LTQ_ES_ARP_REG_TAP_GET(val) ((((val) & LTQ_ES_ARP_REG_TAP) >> 1) & 0x1) |
| 829 | #define LTQ_ES_ARP_REG_TAP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_TAP) | (((val) & 0x1) << 1)) |
| 830 | /* Trap RARP Packet (0) */ |
| 831 | #define LTQ_ES_ARP_REG_TRP (0x1) |
| 832 | #define LTQ_ES_ARP_REG_TRP_VAL(val) (((val) & 0x1) << 0) |
| 833 | #define LTQ_ES_ARP_REG_TRP_GET(val) ((((val) & LTQ_ES_ARP_REG_TRP) >> 0) & 0x1) |
| 834 | #define LTQ_ES_ARP_REG_TRP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_TRP) | (((val) & 0x1) << 0)) |
| 835 | |
| 836 | /******************************************************************************* |
| 837 | * Storm control Register |
| 838 | ******************************************************************************/ |
| 839 | |
| 840 | /* Reserved (31:29) */ |
| 841 | #define LTQ_ES_STRM_CTL_REG_RES (0x7 << 29) |
| 842 | #define LTQ_ES_STRM_CTL_REG_RES_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_RES) >> 29) & 0x7) |
| 843 | /* 10M Threshold (28:16) */ |
| 844 | #define LTQ_ES_STRM_CTL_REG_STORM_10_TH (0x1fff << 16) |
| 845 | #define LTQ_ES_STRM_CTL_REG_STORM_10_TH_VAL(val) (((val) & 0x1fff) << 16) |
| 846 | #define LTQ_ES_STRM_CTL_REG_STORM_10_TH_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_10_TH) >> 16) & 0x1fff) |
| 847 | #define LTQ_ES_STRM_CTL_REG_STORM_10_TH_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_10_TH) | (((val) & 0x1fff) << 16)) |
| 848 | /* Storm Enable for Broadcast Packets (15) */ |
| 849 | #define LTQ_ES_STRM_CTL_REG_STORM_B (0x1 << 15) |
| 850 | #define LTQ_ES_STRM_CTL_REG_STORM_B_VAL(val) (((val) & 0x1) << 15) |
| 851 | #define LTQ_ES_STRM_CTL_REG_STORM_B_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_B) >> 15) & 0x1) |
| 852 | #define LTQ_ES_STRM_CTL_REG_STORM_B_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_B) | (((val) & 0x1) << 15)) |
| 853 | /* Storm Enable for Multicast Packets (14) */ |
| 854 | #define LTQ_ES_STRM_CTL_REG_STORM_M (0x1 << 14) |
| 855 | #define LTQ_ES_STRM_CTL_REG_STORM_M_VAL(val) (((val) & 0x1) << 14) |
| 856 | #define LTQ_ES_STRM_CTL_REG_STORM_M_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_M) >> 14) & 0x1) |
| 857 | #define LTQ_ES_STRM_CTL_REG_STORM_M_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_M) | (((val) & 0x1) << 14)) |
| 858 | /* Storm Enable for Un-learned Unicast Packets (13) */ |
| 859 | #define LTQ_ES_STRM_CTL_REG_STORM_U (0x1 << 13) |
| 860 | #define LTQ_ES_STRM_CTL_REG_STORM_U_VAL(val) (((val) & 0x1) << 13) |
| 861 | #define LTQ_ES_STRM_CTL_REG_STORM_U_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_U) >> 13) & 0x1) |
| 862 | #define LTQ_ES_STRM_CTL_REG_STORM_U_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_U) | (((val) & 0x1) << 13)) |
| 863 | /* 100M Threshold (12:0) */ |
| 864 | #define LTQ_ES_STRM_CTL_REG_STORM_100_TH (0x1fff) |
| 865 | #define LTQ_ES_STRM_CTL_REG_STORM_100_TH_VAL(val) (((val) & 0x1fff) << 0) |
| 866 | #define LTQ_ES_STRM_CTL_REG_STORM_100_TH_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_100_TH) >> 0) & 0x1fff) |
| 867 | #define LTQ_ES_STRM_CTL_REG_STORM_100_TH_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_100_TH) | (((val) & 0x1fff) << 0)) |
| 868 | |
| 869 | /******************************************************************************* |
| 870 | * RGMII/GMII Port Control Register |
| 871 | ******************************************************************************/ |
| 872 | |
| 873 | /* Management Clock Select (31:24) */ |
| 874 | #define LTQ_ES_RGMII_CTL_REG_MCS (0xff << 24) |
| 875 | #define LTQ_ES_RGMII_CTL_REG_MCS_VAL(val) (((val) & 0xff) << 24) |
| 876 | #define LTQ_ES_RGMII_CTL_REG_MCS_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_MCS) >> 24) & 0xff) |
| 877 | #define LTQ_ES_RGMII_CTL_REG_MCS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_MCS) | (((val) & 0xff) << 24)) |
| 878 | /* Interface Selection (19:18) */ |
| 879 | #define LTQ_ES_RGMII_CTL_REG_IS (0x3 << 18) |
| 880 | #define LTQ_ES_RGMII_CTL_REG_IS_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_IS) >> 18) & 0x3) |
| 881 | /* Port 1 RGMII Rx Clock Delay (17:16) */ |
| 882 | #define LTQ_ES_RGMII_CTL_REG_P1RDLY (0x3 << 16) |
| 883 | #define LTQ_ES_RGMII_CTL_REG_P1RDLY_VAL(val) (((val) & 0x3) << 16) |
| 884 | #define LTQ_ES_RGMII_CTL_REG_P1RDLY_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1RDLY) >> 16) & 0x3) |
| 885 | #define LTQ_ES_RGMII_CTL_REG_P1RDLY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1RDLY) | (((val) & 0x3) << 16)) |
| 886 | /* Port 1 RGMII Tx Clock Delay (15:14) */ |
| 887 | #define LTQ_ES_RGMII_CTL_REG_P1TDLY (0x3 << 14) |
| 888 | #define LTQ_ES_RGMII_CTL_REG_P1TDLY_VAL(val) (((val) & 0x3) << 14) |
| 889 | #define LTQ_ES_RGMII_CTL_REG_P1TDLY_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1TDLY) >> 14) & 0x3) |
| 890 | #define LTQ_ES_RGMII_CTL_REG_P1TDLY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1TDLY) | (((val) & 0x3) << 14)) |
| 891 | /* Port 1 Speed (13:12) */ |
| 892 | #define LTQ_ES_RGMII_CTL_REG_P1SPD (0x3 << 12) |
| 893 | #define LTQ_ES_RGMII_CTL_REG_P1SPD_VAL(val) (((val) & 0x3) << 12) |
| 894 | #define LTQ_ES_RGMII_CTL_REG_P1SPD_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1SPD) >> 12) & 0x3) |
| 895 | #define LTQ_ES_RGMII_CTL_REG_P1SPD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1SPD) | (((val) & 0x3) << 12)) |
| 896 | /* Port 1 Duplex mode (11) */ |
| 897 | #define LTQ_ES_RGMII_CTL_REG_P1DUP (0x1 << 11) |
| 898 | #define LTQ_ES_RGMII_CTL_REG_P1DUP_VAL(val) (((val) & 0x1) << 11) |
| 899 | #define LTQ_ES_RGMII_CTL_REG_P1DUP_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1DUP) >> 11) & 0x1) |
| 900 | #define LTQ_ES_RGMII_CTL_REG_P1DUP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1DUP) | (((val) & 0x1) << 11)) |
| 901 | /* Port 1 Flow Control Enable (10) */ |
| 902 | #define LTQ_ES_RGMII_CTL_REG_P1FCE (0x1 << 10) |
| 903 | #define LTQ_ES_RGMII_CTL_REG_P1FCE_VAL(val) (((val) & 0x1) << 10) |
| 904 | #define LTQ_ES_RGMII_CTL_REG_P1FCE_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1FCE) >> 10) & 0x1) |
| 905 | #define LTQ_ES_RGMII_CTL_REG_P1FCE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1FCE) | (((val) & 0x1) << 10)) |
| 906 | /* Port 0 RGMII Rx Clock Delay (7:6) */ |
| 907 | #define LTQ_ES_RGMII_CTL_REG_P0RDLY (0x3 << 6) |
| 908 | #define LTQ_ES_RGMII_CTL_REG_P0RDLY_VAL(val) (((val) & 0x3) << 6) |
| 909 | #define LTQ_ES_RGMII_CTL_REG_P0RDLY_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0RDLY) >> 6) & 0x3) |
| 910 | #define LTQ_ES_RGMII_CTL_REG_P0RDLY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0RDLY) | (((val) & 0x3) << 6)) |
| 911 | /* Port 0 RGMII Tx Clock Delay (5:4) */ |
| 912 | #define LTQ_ES_RGMII_CTL_REG_P0TDLY (0x3 << 4) |
| 913 | #define LTQ_ES_RGMII_CTL_REG_P0TDLY_VAL(val) (((val) & 0x3) << 4) |
| 914 | #define LTQ_ES_RGMII_CTL_REG_P0TDLY_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0TDLY) >> 4) & 0x3) |
| 915 | #define LTQ_ES_RGMII_CTL_REG_P0TDLY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0TDLY) | (((val) & 0x3) << 4)) |
| 916 | /* Port 0 Speed (3:2) */ |
| 917 | #define LTQ_ES_RGMII_CTL_REG_P0SPD (0x3 << 2) |
| 918 | #define LTQ_ES_RGMII_CTL_REG_P0SPD_VAL(val) (((val) & 0x3) << 2) |
| 919 | #define LTQ_ES_RGMII_CTL_REG_P0SPD_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0SPD) >> 2) & 0x3) |
| 920 | #define LTQ_ES_RGMII_CTL_REG_P0SPD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0SPD) | (((val) & 0x3) << 2)) |
| 921 | /* Port 0 Duplex mode (1) */ |
| 922 | #define LTQ_ES_RGMII_CTL_REG_P0DUP (0x1 << 1) |
| 923 | #define LTQ_ES_RGMII_CTL_REG_P0DUP_VAL(val) (((val) & 0x1) << 1) |
| 924 | #define LTQ_ES_RGMII_CTL_REG_P0DUP_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0DUP) >> 1) & 0x1) |
| 925 | #define LTQ_ES_RGMII_CTL_REG_P0DUP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0DUP) | (((val) & 0x1) << 1)) |
| 926 | /* Port 0 Flow Control Enable (0) */ |
| 927 | #define LTQ_ES_RGMII_CTL_REG_P0FCE (0x1) |
| 928 | #define LTQ_ES_RGMII_CTL_REG_P0FCE_VAL(val) (((val) & 0x1) << 0) |
| 929 | #define LTQ_ES_RGMII_CTL_REG_P0FCE_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0FCE) >> 0) & 0x1) |
| 930 | #define LTQ_ES_RGMII_CTL_REG_P0FCE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0FCE) | (((val) & 0x1) << 0)) |
| 931 | |
| 932 | /******************************************************************************* |
| 933 | * 802.1p Priority Map Register |
| 934 | ******************************************************************************/ |
| 935 | |
| 936 | /* Priority Queue 7 (15:14) */ |
| 937 | #define LTQ_ES_PRT_1P_REG_1PPQ7 (0x3 << 14) |
| 938 | #define LTQ_ES_PRT_1P_REG_1PPQ7_VAL(val) (((val) & 0x3) << 14) |
| 939 | #define LTQ_ES_PRT_1P_REG_1PPQ7_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ7) >> 14) & 0x3) |
| 940 | #define LTQ_ES_PRT_1P_REG_1PPQ7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ7) | (((val) & 0x3) << 14)) |
| 941 | /* Priority Queue 6 (13:12) */ |
| 942 | #define LTQ_ES_PRT_1P_REG_1PPQ6 (0x3 << 12) |
| 943 | #define LTQ_ES_PRT_1P_REG_1PPQ6_VAL(val) (((val) & 0x3) << 12) |
| 944 | #define LTQ_ES_PRT_1P_REG_1PPQ6_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ6) >> 12) & 0x3) |
| 945 | #define LTQ_ES_PRT_1P_REG_1PPQ6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ6) | (((val) & 0x3) << 12)) |
| 946 | /* Priority Queue 5 (11:10) */ |
| 947 | #define LTQ_ES_PRT_1P_REG_1PPQ5 (0x3 << 10) |
| 948 | #define LTQ_ES_PRT_1P_REG_1PPQ5_VAL(val) (((val) & 0x3) << 10) |
| 949 | #define LTQ_ES_PRT_1P_REG_1PPQ5_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ5) >> 10) & 0x3) |
| 950 | #define LTQ_ES_PRT_1P_REG_1PPQ5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ5) | (((val) & 0x3) << 10)) |
| 951 | /* Priority Queue 4 (9:8) */ |
| 952 | #define LTQ_ES_PRT_1P_REG_1PPQ4 (0x3 << 8) |
| 953 | #define LTQ_ES_PRT_1P_REG_1PPQ4_VAL(val) (((val) & 0x3) << 8) |
| 954 | #define LTQ_ES_PRT_1P_REG_1PPQ4_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ4) >> 8) & 0x3) |
| 955 | #define LTQ_ES_PRT_1P_REG_1PPQ4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ4) | (((val) & 0x3) << 8)) |
| 956 | /* Priority Queue 3 (7:6) */ |
| 957 | #define LTQ_ES_PRT_1P_REG_1PPQ3 (0x3 << 6) |
| 958 | #define LTQ_ES_PRT_1P_REG_1PPQ3_VAL(val) (((val) & 0x3) << 6) |
| 959 | #define LTQ_ES_PRT_1P_REG_1PPQ3_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ3) >> 6) & 0x3) |
| 960 | #define LTQ_ES_PRT_1P_REG_1PPQ3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ3) | (((val) & 0x3) << 6)) |
| 961 | /* Priority Queue 2 (5:4) */ |
| 962 | #define LTQ_ES_PRT_1P_REG_1PPQ2 (0x3 << 4) |
| 963 | #define LTQ_ES_PRT_1P_REG_1PPQ2_VAL(val) (((val) & 0x3) << 4) |
| 964 | #define LTQ_ES_PRT_1P_REG_1PPQ2_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ2) >> 4) & 0x3) |
| 965 | #define LTQ_ES_PRT_1P_REG_1PPQ2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ2) | (((val) & 0x3) << 4)) |
| 966 | /* Priority Queue 1 (3:2) */ |
| 967 | #define LTQ_ES_PRT_1P_REG_1PPQ1 (0x3 << 2) |
| 968 | #define LTQ_ES_PRT_1P_REG_1PPQ1_VAL(val) (((val) & 0x3) << 2) |
| 969 | #define LTQ_ES_PRT_1P_REG_1PPQ1_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ1) >> 2) & 0x3) |
| 970 | #define LTQ_ES_PRT_1P_REG_1PPQ1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ1) | (((val) & 0x3) << 2)) |
| 971 | /* Priority Queue 0 (1:0) */ |
| 972 | #define LTQ_ES_PRT_1P_REG_1PPQ0 (0x3) |
| 973 | #define LTQ_ES_PRT_1P_REG_1PPQ0_VAL(val) (((val) & 0x3) << 0) |
| 974 | #define LTQ_ES_PRT_1P_REG_1PPQ0_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ0) >> 0) & 0x3) |
| 975 | #define LTQ_ES_PRT_1P_REG_1PPQ0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ0) | (((val) & 0x3) << 0)) |
| 976 | |
| 977 | /******************************************************************************* |
| 978 | * Global Bucket Size Base counter |
| 979 | ******************************************************************************/ |
| 980 | |
| 981 | /* Reserved (31:18) */ |
| 982 | #define LTQ_ES_GBKT_SZBS_REG_REV (0x3fff << 18) |
| 983 | #define LTQ_ES_GBKT_SZBS_REG_REV_GET(val) ((((val) & LTQ_ES_GBKT_SZBS_REG_REV) >> 18) & 0x3fff) |
| 984 | /* Base[17:0] (17:0) */ |
| 985 | #define LTQ_ES_GBKT_SZBS_REG_BASE17_0 (0x3ffff) |
| 986 | #define LTQ_ES_GBKT_SZBS_REG_BASE17_0_VAL(val) (((val) & 0x3ffff) << 0) |
| 987 | #define LTQ_ES_GBKT_SZBS_REG_BASE17_0_GET(val) ((((val) & LTQ_ES_GBKT_SZBS_REG_BASE17_0) >> 0) & 0x3ffff) |
| 988 | #define LTQ_ES_GBKT_SZBS_REG_BASE17_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_GBKT_SZBS_REG_BASE17_0) | (((val) & 0x3ffff) << 0)) |
| 989 | |
| 990 | /******************************************************************************* |
| 991 | * Global Bucket Size Extend Base Counter |
| 992 | ******************************************************************************/ |
| 993 | |
| 994 | /* Reserved (31:18) */ |
| 995 | #define LTQ_ES_GBKT_SZEBS_REG_REV (0x3fff << 18) |
| 996 | #define LTQ_ES_GBKT_SZEBS_REG_REV_GET(val) ((((val) & LTQ_ES_GBKT_SZEBS_REG_REV) >> 18) & 0x3fff) |
| 997 | /* Extend Base[17:0] (17:0) */ |
| 998 | #define LTQ_ES_GBKT_SZEBS_REG_EBASE17_0 (0x3ffff) |
| 999 | #define LTQ_ES_GBKT_SZEBS_REG_EBASE17_0_VAL(val) (((val) & 0x3ffff) << 0) |
| 1000 | #define LTQ_ES_GBKT_SZEBS_REG_EBASE17_0_GET(val) ((((val) & LTQ_ES_GBKT_SZEBS_REG_EBASE17_0) >> 0) & 0x3ffff) |
| 1001 | #define LTQ_ES_GBKT_SZEBS_REG_EBASE17_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_GBKT_SZEBS_REG_EBASE17_0) | (((val) & 0x3ffff) << 0)) |
| 1002 | |
| 1003 | /******************************************************************************* |
| 1004 | * Buffer Threshold Register |
| 1005 | ******************************************************************************/ |
| 1006 | |
| 1007 | /* Port Unfull Offset 3 (31:30) */ |
| 1008 | #define LTQ_ES_BF_TH_REG_PUO3 (0x3 << 30) |
| 1009 | #define LTQ_ES_BF_TH_REG_PUO3_VAL(val) (((val) & 0x3) << 30) |
| 1010 | #define LTQ_ES_BF_TH_REG_PUO3_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUO3) >> 30) & 0x3) |
| 1011 | #define LTQ_ES_BF_TH_REG_PUO3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUO3) | (((val) & 0x3) << 30)) |
| 1012 | /* Port Unfull Offset 2 (29:28) */ |
| 1013 | #define LTQ_ES_BF_TH_REG_PUO2 (0x3 << 28) |
| 1014 | #define LTQ_ES_BF_TH_REG_PUO2_VAL(val) (((val) & 0x3) << 28) |
| 1015 | #define LTQ_ES_BF_TH_REG_PUO2_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUO2) >> 28) & 0x3) |
| 1016 | #define LTQ_ES_BF_TH_REG_PUO2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUO2) | (((val) & 0x3) << 28)) |
| 1017 | /* Port Unfull Offset 1 (27:26) */ |
| 1018 | #define LTQ_ES_BF_TH_REG_PUO1 (0x3 << 26) |
| 1019 | #define LTQ_ES_BF_TH_REG_PUO1_VAL(val) (((val) & 0x3) << 26) |
| 1020 | #define LTQ_ES_BF_TH_REG_PUO1_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUO1) >> 26) & 0x3) |
| 1021 | #define LTQ_ES_BF_TH_REG_PUO1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUO1) | (((val) & 0x3) << 26)) |
| 1022 | /* Port Unfull Offset 0 (25:24) */ |
| 1023 | #define LTQ_ES_BF_TH_REG_PUO0 (0x3 << 24) |
| 1024 | #define LTQ_ES_BF_TH_REG_PUO0_VAL(val) (((val) & 0x3) << 24) |
| 1025 | #define LTQ_ES_BF_TH_REG_PUO0_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUO0) >> 24) & 0x3) |
| 1026 | #define LTQ_ES_BF_TH_REG_PUO0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUO0) | (((val) & 0x3) << 24)) |
| 1027 | /* Port Full Offset 3 (23:22) */ |
| 1028 | #define LTQ_ES_BF_TH_REG_PFO3 (0x3 << 22) |
| 1029 | #define LTQ_ES_BF_TH_REG_PFO3_VAL(val) (((val) & 0x3) << 22) |
| 1030 | #define LTQ_ES_BF_TH_REG_PFO3_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFO3) >> 22) & 0x3) |
| 1031 | #define LTQ_ES_BF_TH_REG_PFO3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFO3) | (((val) & 0x3) << 22)) |
| 1032 | /* Port Full Offset 2 (21:20) */ |
| 1033 | #define LTQ_ES_BF_TH_REG_PFO2 (0x3 << 20) |
| 1034 | #define LTQ_ES_BF_TH_REG_PFO2_VAL(val) (((val) & 0x3) << 20) |
| 1035 | #define LTQ_ES_BF_TH_REG_PFO2_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFO2) >> 20) & 0x3) |
| 1036 | #define LTQ_ES_BF_TH_REG_PFO2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFO2) | (((val) & 0x3) << 20)) |
| 1037 | /* Port Full Offset 1 (19:18) */ |
| 1038 | #define LTQ_ES_BF_TH_REG_PFO1 (0x3 << 18) |
| 1039 | #define LTQ_ES_BF_TH_REG_PFO1_VAL(val) (((val) & 0x3) << 18) |
| 1040 | #define LTQ_ES_BF_TH_REG_PFO1_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFO1) >> 18) & 0x3) |
| 1041 | #define LTQ_ES_BF_TH_REG_PFO1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFO1) | (((val) & 0x3) << 18)) |
| 1042 | /* Port Full Offset 0 (17:16) */ |
| 1043 | #define LTQ_ES_BF_TH_REG_PFO0 (0x3 << 16) |
| 1044 | #define LTQ_ES_BF_TH_REG_PFO0_VAL(val) (((val) & 0x3) << 16) |
| 1045 | #define LTQ_ES_BF_TH_REG_PFO0_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFO0) >> 16) & 0x3) |
| 1046 | #define LTQ_ES_BF_TH_REG_PFO0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFO0) | (((val) & 0x3) << 16)) |
| 1047 | /* Reserved (15:14) */ |
| 1048 | #define LTQ_ES_BF_TH_REG_RES (0x3 << 14) |
| 1049 | #define LTQ_ES_BF_TH_REG_RES_GET(val) ((((val) & LTQ_ES_BF_TH_REG_RES) >> 14) & 0x3) |
| 1050 | /* Total Low Add (13) */ |
| 1051 | #define LTQ_ES_BF_TH_REG_TLA (0x1 << 13) |
| 1052 | #define LTQ_ES_BF_TH_REG_TLA_VAL(val) (((val) & 0x1) << 13) |
| 1053 | #define LTQ_ES_BF_TH_REG_TLA_GET(val) ((((val) & LTQ_ES_BF_TH_REG_TLA) >> 13) & 0x1) |
| 1054 | #define LTQ_ES_BF_TH_REG_TLA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_TLA) | (((val) & 0x1) << 13)) |
| 1055 | /* Total High Add (12) */ |
| 1056 | #define LTQ_ES_BF_TH_REG_THA (0x1 << 12) |
| 1057 | #define LTQ_ES_BF_TH_REG_THA_VAL(val) (((val) & 0x1) << 12) |
| 1058 | #define LTQ_ES_BF_TH_REG_THA_GET(val) ((((val) & LTQ_ES_BF_TH_REG_THA) >> 12) & 0x1) |
| 1059 | #define LTQ_ES_BF_TH_REG_THA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_THA) | (((val) & 0x1) << 12)) |
| 1060 | /* Total Low Offset (11:10) */ |
| 1061 | #define LTQ_ES_BF_TH_REG_TLO (0x3 << 10) |
| 1062 | #define LTQ_ES_BF_TH_REG_TLO_VAL(val) (((val) & 0x3) << 10) |
| 1063 | #define LTQ_ES_BF_TH_REG_TLO_GET(val) ((((val) & LTQ_ES_BF_TH_REG_TLO) >> 10) & 0x3) |
| 1064 | #define LTQ_ES_BF_TH_REG_TLO_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_TLO) | (((val) & 0x3) << 10)) |
| 1065 | /* Total High Offset (9:8) */ |
| 1066 | #define LTQ_ES_BF_TH_REG_THO (0x3 << 8) |
| 1067 | #define LTQ_ES_BF_TH_REG_THO_VAL(val) (((val) & 0x3) << 8) |
| 1068 | #define LTQ_ES_BF_TH_REG_THO_GET(val) ((((val) & LTQ_ES_BF_TH_REG_THO) >> 8) & 0x3) |
| 1069 | #define LTQ_ES_BF_TH_REG_THO_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_THO) | (((val) & 0x3) << 8)) |
| 1070 | /* Port Unfull Add (7:4) */ |
| 1071 | #define LTQ_ES_BF_TH_REG_PUA (0xf << 4) |
| 1072 | #define LTQ_ES_BF_TH_REG_PUA_VAL(val) (((val) & 0xf) << 4) |
| 1073 | #define LTQ_ES_BF_TH_REG_PUA_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUA) >> 4) & 0xf) |
| 1074 | #define LTQ_ES_BF_TH_REG_PUA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUA) | (((val) & 0xf) << 4)) |
| 1075 | /* Port Full Add (3:0) */ |
| 1076 | #define LTQ_ES_BF_TH_REG_PFA (0xf) |
| 1077 | #define LTQ_ES_BF_TH_REG_PFA_VAL(val) (((val) & 0xf) << 0) |
| 1078 | #define LTQ_ES_BF_TH_REG_PFA_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFA) >> 0) & 0xf) |
| 1079 | #define LTQ_ES_BF_TH_REG_PFA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFA) | (((val) & 0xf) << 0)) |
| 1080 | |
| 1081 | /******************************************************************************* |
| 1082 | * PMAC Header Control Register |
| 1083 | ******************************************************************************/ |
| 1084 | |
| 1085 | /* Reserved (31:22) */ |
| 1086 | #define LTQ_ES_PMAC_HD_CTL_RES (0x3ff << 22) |
| 1087 | #define LTQ_ES_PMAC_HD_CTL_RES_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_RES) >> 22) & 0x3ff) |
| 1088 | /* Remove Layer-2 Header from Packets Going from PMAC to DMA (21) */ |
| 1089 | #define LTQ_ES_PMAC_HD_CTL_RL2 (0x1 << 21) |
| 1090 | #define LTQ_ES_PMAC_HD_CTL_RL2_VAL(val) (((val) & 0x1) << 21) |
| 1091 | #define LTQ_ES_PMAC_HD_CTL_RL2_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_RL2) >> 21) & 0x1) |
| 1092 | #define LTQ_ES_PMAC_HD_CTL_RL2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_RL2) | (((val) & 0x1) << 21)) |
| 1093 | /* Remove CRC from Packets Going from PMAC to DMA (20) */ |
| 1094 | #define LTQ_ES_PMAC_HD_CTL_RC (0x1 << 20) |
| 1095 | #define LTQ_ES_PMAC_HD_CTL_RC_VAL(val) (((val) & 0x1) << 20) |
| 1096 | #define LTQ_ES_PMAC_HD_CTL_RC_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_RC) >> 20) & 0x1) |
| 1097 | #define LTQ_ES_PMAC_HD_CTL_RC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_RC) | (((val) & 0x1) << 20)) |
| 1098 | /* Status Header for Packets from PMAC to DMA (19) */ |
| 1099 | #define LTQ_ES_PMAC_HD_CTL_AS (0x1 << 19) |
| 1100 | #define LTQ_ES_PMAC_HD_CTL_AS_VAL(val) (((val) & 0x1) << 19) |
| 1101 | #define LTQ_ES_PMAC_HD_CTL_AS_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_AS) >> 19) & 0x1) |
| 1102 | #define LTQ_ES_PMAC_HD_CTL_AS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_AS) | (((val) & 0x1) << 19)) |
| 1103 | /* Add CRC for packets from DMA to PMAC (18) */ |
| 1104 | #define LTQ_ES_PMAC_HD_CTL_AC (0x1 << 18) |
| 1105 | #define LTQ_ES_PMAC_HD_CTL_AC_VAL(val) (((val) & 0x1) << 18) |
| 1106 | #define LTQ_ES_PMAC_HD_CTL_AC_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_AC) >> 18) & 0x1) |
| 1107 | #define LTQ_ES_PMAC_HD_CTL_AC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_AC) | (((val) & 0x1) << 18)) |
| 1108 | /* Contains the length/type value to the added to packets from DMA to PMAC (17:2) */ |
| 1109 | #define LTQ_ES_PMAC_HD_CTL_TYPE_LEN (0xffff << 2) |
| 1110 | #define LTQ_ES_PMAC_HD_CTL_TYPE_LEN_VAL(val) (((val) & 0xffff) << 2) |
| 1111 | #define LTQ_ES_PMAC_HD_CTL_TYPE_LEN_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_TYPE_LEN) >> 2) & 0xffff) |
| 1112 | #define LTQ_ES_PMAC_HD_CTL_TYPE_LEN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_TYPE_LEN) | (((val) & 0xffff) << 2)) |
| 1113 | /* Add TAG to Packets from DMA to PMAC (1) */ |
| 1114 | #define LTQ_ES_PMAC_HD_CTL_TAG (0x1 << 1) |
| 1115 | #define LTQ_ES_PMAC_HD_CTL_TAG_VAL(val) (((val) & 0x1) << 1) |
| 1116 | #define LTQ_ES_PMAC_HD_CTL_TAG_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_TAG) >> 1) & 0x1) |
| 1117 | #define LTQ_ES_PMAC_HD_CTL_TAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_TAG) | (((val) & 0x1) << 1)) |
| 1118 | /* ADD Header to Packets from DMA to PMAC (0) */ |
| 1119 | #define LTQ_ES_PMAC_HD_CTL_ADD (0x1) |
| 1120 | #define LTQ_ES_PMAC_HD_CTL_ADD_VAL(val) (((val) & 0x1) << 0) |
| 1121 | #define LTQ_ES_PMAC_HD_CTL_ADD_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_ADD) >> 0) & 0x1) |
| 1122 | #define LTQ_ES_PMAC_HD_CTL_ADD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_ADD) | (((val) & 0x1) << 0)) |
| 1123 | |
| 1124 | /******************************************************************************* |
| 1125 | * PMAC Source Address Register 1 |
| 1126 | ******************************************************************************/ |
| 1127 | |
| 1128 | /* Source Address to be inserted as a part of the Ethernet header. (15:0) */ |
| 1129 | #define LTQ_ES_PMAC_SA1_SA_47_32 (0xffff) |
| 1130 | #define LTQ_ES_PMAC_SA1_SA_47_32_VAL(val) (((val) & 0xffff) << 0) |
| 1131 | #define LTQ_ES_PMAC_SA1_SA_47_32_GET(val) ((((val) & LTQ_ES_PMAC_SA1_SA_47_32) >> 0) & 0xffff) |
| 1132 | #define LTQ_ES_PMAC_SA1_SA_47_32_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_SA1_SA_47_32) | (((val) & 0xffff) << 0)) |
| 1133 | |
| 1134 | /******************************************************************************* |
| 1135 | * PMAC Source Address Register 2 |
| 1136 | ******************************************************************************/ |
| 1137 | |
| 1138 | /* Source Address (31:0) */ |
| 1139 | #define LTQ_ES_PMAC_SA2_SA_31_0 (0xFFFFFFFFL) |
| 1140 | #define LTQ_ES_PMAC_SA2_SA_31_0_VAL(val) (((val) & 0xFFFFFFFFL) << 0) |
| 1141 | #define LTQ_ES_PMAC_SA2_SA_31_0_GET(val) ((((val) & LTQ_ES_PMAC_SA2_SA_31_0) >> 0) & 0xFFFFFFFFL) |
| 1142 | #define LTQ_ES_PMAC_SA2_SA_31_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_SA2_SA_31_0) | (((val) & 0xFFFFFFFFL) << 0)) |
| 1143 | |
| 1144 | /******************************************************************************* |
| 1145 | * PMAC Destination Address Register 1 |
| 1146 | ******************************************************************************/ |
| 1147 | |
| 1148 | /* Destination Address (15:0) */ |
| 1149 | #define LTQ_ES_PMAC_DA1_DA_47_32 (0xffff) |
| 1150 | #define LTQ_ES_PMAC_DA1_DA_47_32_VAL(val) (((val) & 0xffff) << 0) |
| 1151 | #define LTQ_ES_PMAC_DA1_DA_47_32_GET(val) ((((val) & LTQ_ES_PMAC_DA1_DA_47_32) >> 0) & 0xffff) |
| 1152 | #define LTQ_ES_PMAC_DA1_DA_47_32_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_DA1_DA_47_32) | (((val) & 0xffff) << 0)) |
| 1153 | |
| 1154 | /******************************************************************************* |
| 1155 | * PMAC Destination Address Register 2 |
| 1156 | ******************************************************************************/ |
| 1157 | |
| 1158 | /* Destination Address to be inserted as a part of the Ethernet header. (31:0) */ |
| 1159 | #define LTQ_ES_PMAC_DA2_DA_31_0 (0xFFFFFFFFL) |
| 1160 | #define LTQ_ES_PMAC_DA2_DA_31_0_VAL(val) (((val) & 0xFFFFFFFFL) << 0) |
| 1161 | #define LTQ_ES_PMAC_DA2_DA_31_0_GET(val) ((((val) & LTQ_ES_PMAC_DA2_DA_31_0) >> 0) & 0xFFFFFFFFL) |
| 1162 | #define LTQ_ES_PMAC_DA2_DA_31_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_DA2_DA_31_0) | (((val) & 0xFFFFFFFFL) << 0)) |
| 1163 | |
| 1164 | /******************************************************************************* |
| 1165 | * PMAC VLAN Register |
| 1166 | ******************************************************************************/ |
| 1167 | |
| 1168 | /* Priority to be inserted as a part of VLAN tag (15:13) */ |
| 1169 | #define LTQ_ES_PMAC_VLAN_PRI (0x7 << 13) |
| 1170 | #define LTQ_ES_PMAC_VLAN_PRI_VAL(val) (((val) & 0x7) << 13) |
| 1171 | #define LTQ_ES_PMAC_VLAN_PRI_GET(val) ((((val) & LTQ_ES_PMAC_VLAN_PRI) >> 13) & 0x7) |
| 1172 | #define LTQ_ES_PMAC_VLAN_PRI_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_VLAN_PRI) | (((val) & 0x7) << 13)) |
| 1173 | /* CFI bit to be inserted as a part of VLAN tag (12) */ |
| 1174 | #define LTQ_ES_PMAC_VLAN_CFI (0x1 << 12) |
| 1175 | #define LTQ_ES_PMAC_VLAN_CFI_VAL(val) (((val) & 0x1) << 12) |
| 1176 | #define LTQ_ES_PMAC_VLAN_CFI_GET(val) ((((val) & LTQ_ES_PMAC_VLAN_CFI) >> 12) & 0x1) |
| 1177 | #define LTQ_ES_PMAC_VLAN_CFI_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_VLAN_CFI) | (((val) & 0x1) << 12)) |
| 1178 | /* VLAN ID to be inserted as a part of VLAN tag (11:0) */ |
| 1179 | #define LTQ_ES_PMAC_VLAN_VLAN_ID (0xfff) |
| 1180 | #define LTQ_ES_PMAC_VLAN_VLAN_ID_VAL(val) (((val) & 0xfff) << 0) |
| 1181 | #define LTQ_ES_PMAC_VLAN_VLAN_ID_GET(val) ((((val) & LTQ_ES_PMAC_VLAN_VLAN_ID) >> 0) & 0xfff) |
| 1182 | #define LTQ_ES_PMAC_VLAN_VLAN_ID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_VLAN_VLAN ID) | (((val) & 0xfff) << 0)) |
| 1183 | |
| 1184 | /******************************************************************************* |
| 1185 | * PMAC TX IPG Counter Register |
| 1186 | ******************************************************************************/ |
| 1187 | |
| 1188 | /* IPG Counter (7:0) */ |
| 1189 | #define LTQ_ES_PMAC_TX_IPG_IPG_CNT (0xff) |
| 1190 | #define LTQ_ES_PMAC_TX_IPG_IPG_CNT_VAL(val) (((val) & 0xff) << 0) |
| 1191 | #define LTQ_ES_PMAC_TX_IPG_IPG_CNT_GET(val) ((((val) & LTQ_ES_PMAC_TX_IPG_IPG_CNT) >> 0) & 0xff) |
| 1192 | #define LTQ_ES_PMAC_TX_IPG_IPG_CNT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_TX_IPG_IPG_CNT) | (((val) & 0xff) << 0)) |
| 1193 | |
| 1194 | /******************************************************************************* |
| 1195 | * PMAC RX IPG Counter Register |
| 1196 | ******************************************************************************/ |
| 1197 | |
| 1198 | /* IPG Counter (7:0) */ |
| 1199 | #define LTQ_ES_PMAC_RX_IPG_IPG_CNT (0xff) |
| 1200 | #define LTQ_ES_PMAC_RX_IPG_IPG_CNT_VAL(val) (((val) & 0xff) << 0) |
| 1201 | #define LTQ_ES_PMAC_RX_IPG_IPG_CNT_GET(val) ((((val) & LTQ_ES_PMAC_RX_IPG_IPG_CNT) >> 0) & 0xff) |
| 1202 | #define LTQ_ES_PMAC_RX_IPG_IPG_CNT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_RX_IPG_IPG_CNT) | (((val) & 0xff) << 0)) |
| 1203 | |
| 1204 | /******************************************************************************* |
| 1205 | * Address Table Control 0 Register |
| 1206 | ******************************************************************************/ |
| 1207 | |
| 1208 | /* Address [31:0] (31:0) */ |
| 1209 | #define LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0 (0xFFFFFFFFL) |
| 1210 | #define LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0_VAL(val) (((val) & 0xFFFFFFFFL) << 0) |
| 1211 | #define LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0) >> 0) & 0xFFFFFFFFL) |
| 1212 | #define LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0) | (((val) & 0xFFFFFFFFL) << 0)) |
| 1213 | |
| 1214 | /******************************************************************************* |
| 1215 | * Address Table Control 1 Register |
| 1216 | ******************************************************************************/ |
| 1217 | |
| 1218 | /* Port Map (22:20) */ |
| 1219 | #define LTQ_ES_ADR_TB_CTL1_REG_PMAP (0x7 << 20) |
| 1220 | #define LTQ_ES_ADR_TB_CTL1_REG_PMAP_VAL(val) (((val) & 0x7) << 20) |
| 1221 | #define LTQ_ES_ADR_TB_CTL1_REG_PMAP_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL1_REG_PMAP) >> 20) & 0x7) |
| 1222 | #define LTQ_ES_ADR_TB_CTL1_REG_PMAP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL1_REG_PMAP) | (((val) & 0x7) << 20)) |
| 1223 | /* FID group (17:16) */ |
| 1224 | #define LTQ_ES_ADR_TB_CTL1_REG_FID (0x3 << 16) |
| 1225 | #define LTQ_ES_ADR_TB_CTL1_REG_FID_VAL(val) (((val) & 0x3) << 16) |
| 1226 | #define LTQ_ES_ADR_TB_CTL1_REG_FID_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL1_REG_FID) >> 16) & 0x3) |
| 1227 | #define LTQ_ES_ADR_TB_CTL1_REG_FID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL1_REG_FID) | (((val) & 0x3) << 16)) |
| 1228 | /* Address [47:32] (15:0) */ |
| 1229 | #define LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32 (0xffff) |
| 1230 | #define LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32_VAL(val) (((val) & 0xffff) << 0) |
| 1231 | #define LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32) >> 0) & 0xffff) |
| 1232 | #define LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32) | (((val) & 0xffff) << 0)) |
| 1233 | |
| 1234 | /******************************************************************************* |
| 1235 | * Address Table Control 2 Register |
| 1236 | ******************************************************************************/ |
| 1237 | |
| 1238 | /* Command (22:20) */ |
| 1239 | #define LTQ_ES_ADR_TB_CTL2_REG_CMD (0x7 << 20) |
| 1240 | #define LTQ_ES_ADR_TB_CTL2_REG_CMD_VAL(val) (((val) & 0x7) << 20) |
| 1241 | #define LTQ_ES_ADR_TB_CTL2_REG_CMD_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL2_REG_CMD) >> 20) & 0x7) |
| 1242 | #define LTQ_ES_ADR_TB_CTL2_REG_CMD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL2_REG_CMD) | (((val) & 0x7) << 20)) |
| 1243 | /* Access Control (19:16) */ |
| 1244 | #define LTQ_ES_ADR_TB_CTL2_REG_AC (0xf << 16) |
| 1245 | #define LTQ_ES_ADR_TB_CTL2_REG_AC_VAL(val) (((val) & 0xf) << 16) |
| 1246 | #define LTQ_ES_ADR_TB_CTL2_REG_AC_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL2_REG_AC) >> 16) & 0xf) |
| 1247 | #define LTQ_ES_ADR_TB_CTL2_REG_AC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL2_REG_AC) | (((val) & 0xf) << 16)) |
| 1248 | /* Info Type: Static address (12) */ |
| 1249 | #define LTQ_ES_ADR_TB_CTL2_REG_INFOT (0x1 << 12) |
| 1250 | #define LTQ_ES_ADR_TB_CTL2_REG_INFOT_VAL(val) (((val) & 0x1) << 12) |
| 1251 | #define LTQ_ES_ADR_TB_CTL2_REG_INFOT_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL2_REG_INFOT) >> 12) & 0x1) |
| 1252 | #define LTQ_ES_ADR_TB_CTL2_REG_INFOT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL2_REG_INFOT) | (((val) & 0x1) << 12)) |
| 1253 | /* Info_Ctrl/Age Timer (10:0) */ |
| 1254 | #define LTQ_ES_ADR_TB_CTL2_REG_ITAT (0x7ff) |
| 1255 | #define LTQ_ES_ADR_TB_CTL2_REG_ITAT_VAL(val) (((val) & 0x7ff) << 0) |
| 1256 | #define LTQ_ES_ADR_TB_CTL2_REG_ITAT_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL2_REG_ITAT) >> 0) & 0x7ff) |
| 1257 | #define LTQ_ES_ADR_TB_CTL2_REG_ITAT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL2_REG_ITAT) | (((val) & 0x7ff) << 0)) |
| 1258 | |
| 1259 | /******************************************************************************* |
| 1260 | * Address Table Status 0 Register |
| 1261 | ******************************************************************************/ |
| 1262 | |
| 1263 | /* Address [31:0] (31:0) */ |
| 1264 | #define LTQ_ES_ADR_TB_ST0_REG_ADDRS31_0 (0xFFFFFFFFL) |
| 1265 | #define LTQ_ES_ADR_TB_ST0_REG_ADDRS31_0_GET(val) ((((val) & LTQ_ES_ADR_TB_ST0_REG_ADDRS31_0) >> 0) & 0xFFFFFFFFL) |
| 1266 | |
| 1267 | /******************************************************************************* |
| 1268 | * Address Table Status 1 Register |
| 1269 | ******************************************************************************/ |
| 1270 | |
| 1271 | /* Port Map (22:20) */ |
| 1272 | #define LTQ_ES_ADR_TB_ST1_REG_PMAPS (0x7 << 20) |
| 1273 | #define LTQ_ES_ADR_TB_ST1_REG_PMAPS_GET(val) ((((val) & LTQ_ES_ADR_TB_ST1_REG_PMAPS) >> 20) & 0x7) |
| 1274 | /* FID group (17:16) */ |
| 1275 | #define LTQ_ES_ADR_TB_ST1_REG_FIDS (0x3 << 16) |
| 1276 | #define LTQ_ES_ADR_TB_ST1_REG_FIDS_GET(val) ((((val) & LTQ_ES_ADR_TB_ST1_REG_FIDS) >> 16) & 0x3) |
| 1277 | /* Address [47:32] (15:0) */ |
| 1278 | #define LTQ_ES_ADR_TB_ST1_REG_ADDRS47_32 (0xffff) |
| 1279 | #define LTQ_ES_ADR_TB_ST1_REG_ADDRS47_32_GET(val) ((((val) & LTQ_ES_ADR_TB_ST1_REG_ADDRS47_32) >> 0) & 0xffff) |
| 1280 | |
| 1281 | /******************************************************************************* |
| 1282 | * Address Table Status 2 Register |
| 1283 | ******************************************************************************/ |
| 1284 | |
| 1285 | /* Busy (31) */ |
| 1286 | #define LTQ_ES_ADR_TB_ST2_REG_BUSY (0x1 << 31) |
| 1287 | #define LTQ_ES_ADR_TB_ST2_REG_BUSY_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_BUSY) >> 31) & 0x1) |
| 1288 | /* Result (30:28) */ |
| 1289 | #define LTQ_ES_ADR_TB_ST2_REG_RSLT (0x7 << 28) |
| 1290 | #define LTQ_ES_ADR_TB_ST2_REG_RSLT_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_RSLT) >> 28) & 0x7) |
| 1291 | /* Command (22:20) */ |
| 1292 | #define LTQ_ES_ADR_TB_ST2_REG_CMD (0x7 << 20) |
| 1293 | #define LTQ_ES_ADR_TB_ST2_REG_CMD_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_CMD) >> 20) & 0x7) |
| 1294 | /* Access Control (19:16) */ |
| 1295 | #define LTQ_ES_ADR_TB_ST2_REG_AC (0xf << 16) |
| 1296 | #define LTQ_ES_ADR_TB_ST2_REG_AC_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_AC) >> 16) & 0xf) |
| 1297 | /* Bad Status (14) */ |
| 1298 | #define LTQ_ES_ADR_TB_ST2_REG_BAD (0x1 << 14) |
| 1299 | #define LTQ_ES_ADR_TB_ST2_REG_BAD_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_BAD) >> 14) & 0x1) |
| 1300 | /* Occupy (13) */ |
| 1301 | #define LTQ_ES_ADR_TB_ST2_REG_OCP (0x1 << 13) |
| 1302 | #define LTQ_ES_ADR_TB_ST2_REG_OCP_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_OCP) >> 13) & 0x1) |
| 1303 | /* Info Type: Static address (12) */ |
| 1304 | #define LTQ_ES_ADR_TB_ST2_REG_INFOTS (0x1 << 12) |
| 1305 | #define LTQ_ES_ADR_TB_ST2_REG_INFOTS_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_INFOTS) >> 12) & 0x1) |
| 1306 | /* Info_Ctrl/Age Timer Status (10:0) */ |
| 1307 | #define LTQ_ES_ADR_TB_ST2_REG_ITATS (0x7ff) |
| 1308 | #define LTQ_ES_ADR_TB_ST2_REG_ITATS_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_ITATS) >> 0) & 0x7ff) |
| 1309 | |
| 1310 | /******************************************************************************* |
| 1311 | * RMON Counter Control Register |
| 1312 | ******************************************************************************/ |
| 1313 | |
| 1314 | /* Reserved (31:12) */ |
| 1315 | #define LTQ_ES_RMON_CTL_REG_RES (0xfffff << 12) |
| 1316 | #define LTQ_ES_RMON_CTL_REG_RES_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_RES) >> 12) & 0xfffff) |
| 1317 | /* Busy/Access Start (11) */ |
| 1318 | #define LTQ_ES_RMON_CTL_REG_BAS (0x1 << 11) |
| 1319 | #define LTQ_ES_RMON_CTL_REG_BAS_VAL(val) (((val) & 0x1) << 11) |
| 1320 | #define LTQ_ES_RMON_CTL_REG_BAS_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_BAS) >> 11) & 0x1) |
| 1321 | #define LTQ_ES_RMON_CTL_REG_BAS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RMON_CTL_REG_BAS) | (((val) & 0x1) << 11)) |
| 1322 | /* Command for access counter (10:9) */ |
| 1323 | #define LTQ_ES_RMON_CTL_REG_CAC (0x3 << 9) |
| 1324 | #define LTQ_ES_RMON_CTL_REG_CAC_VAL(val) (((val) & 0x3) << 9) |
| 1325 | #define LTQ_ES_RMON_CTL_REG_CAC_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_CAC) >> 9) & 0x3) |
| 1326 | #define LTQ_ES_RMON_CTL_REG_CAC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RMON_CTL_REG_CAC) | (((val) & 0x3) << 9)) |
| 1327 | /* Port (8:6) */ |
| 1328 | #define LTQ_ES_RMON_CTL_REG_PORTC (0x7 << 6) |
| 1329 | #define LTQ_ES_RMON_CTL_REG_PORTC_VAL(val) (((val) & 0x7) << 6) |
| 1330 | #define LTQ_ES_RMON_CTL_REG_PORTC_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_PORTC) >> 6) & 0x7) |
| 1331 | #define LTQ_ES_RMON_CTL_REG_PORTC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RMON_CTL_REG_PORTC) | (((val) & 0x7) << 6)) |
| 1332 | /* Counter Offset (5:0) */ |
| 1333 | #define LTQ_ES_RMON_CTL_REG_OFFSET (0x3f) |
| 1334 | #define LTQ_ES_RMON_CTL_REG_OFFSET_VAL(val) (((val) & 0x3f) << 0) |
| 1335 | #define LTQ_ES_RMON_CTL_REG_OFFSET_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_OFFSET) >> 0) & 0x3f) |
| 1336 | #define LTQ_ES_RMON_CTL_REG_OFFSET_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RMON_CTL_REG_OFFSET) | (((val) & 0x3f) << 0)) |
| 1337 | |
| 1338 | /******************************************************************************* |
| 1339 | * RMON Counter Status Register |
| 1340 | ******************************************************************************/ |
| 1341 | |
| 1342 | /* Counter [31:0] or Counter[63:32] for byte count (31:0) */ |
| 1343 | #define LTQ_ES_RMON_ST_REG_COUNTER (0xFFFFFFFFL) |
| 1344 | #define LTQ_ES_RMON_ST_REG_COUNTER_GET(val) ((((val) & LTQ_ES_RMON_ST_REG_COUNTER) >> 0) & 0xFFFFFFFFL) |
| 1345 | |
| 1346 | /******************************************************************************* |
| 1347 | * MDIO Indirect Access Control |
| 1348 | ******************************************************************************/ |
| 1349 | |
| 1350 | /* The Write Data to the MDIO register (31:16) */ |
| 1351 | #define LTQ_ES_MDIO_CTL_REG_WD (0xffff << 16) |
| 1352 | #define LTQ_ES_MDIO_CTL_REG_WD_VAL(val) (((val) & 0xffff) << 16) |
| 1353 | #define LTQ_ES_MDIO_CTL_REG_WD_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_WD) >> 16) & 0xffff) |
| 1354 | #define LTQ_ES_MDIO_CTL_REG_WD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_WD) | (((val) & 0xffff) << 16)) |
| 1355 | /* Busy state (15) */ |
| 1356 | #define LTQ_ES_MDIO_CTL_REG_MBUSY (0x1 << 15) |
| 1357 | #define LTQ_ES_MDIO_CTL_REG_MBUSY_VAL(val) (((val) & 0x1) << 15) |
| 1358 | #define LTQ_ES_MDIO_CTL_REG_MBUSY_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_MBUSY) >> 15) & 0x1) |
| 1359 | #define LTQ_ES_MDIO_CTL_REG_MBUSY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_MBUSY) | (((val) & 0x1) << 15)) |
| 1360 | /* Reserved (14:12) */ |
| 1361 | #define LTQ_ES_MDIO_CTL_REG_RES (0x7 << 12) |
| 1362 | #define LTQ_ES_MDIO_CTL_REG_RES_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_RES) >> 12) & 0x7) |
| 1363 | /* Operation Code (11:10) */ |
| 1364 | #define LTQ_ES_MDIO_CTL_REG_OP (0x3 << 10) |
| 1365 | #define LTQ_ES_MDIO_CTL_REG_OP_VAL(val) (((val) & 0x3) << 10) |
| 1366 | #define LTQ_ES_MDIO_CTL_REG_OP_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_OP) >> 10) & 0x3) |
| 1367 | #define LTQ_ES_MDIO_CTL_REG_OP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_OP) | (((val) & 0x3) << 10)) |
| 1368 | /* PHY Address (9:5) */ |
| 1369 | #define LTQ_ES_MDIO_CTL_REG_PHYAD (0x1f << 5) |
| 1370 | #define LTQ_ES_MDIO_CTL_REG_PHYAD_VAL(val) (((val) & 0x1f) << 5) |
| 1371 | #define LTQ_ES_MDIO_CTL_REG_PHYAD_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_PHYAD) >> 5) & 0x1f) |
| 1372 | #define LTQ_ES_MDIO_CTL_REG_PHYAD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_PHYAD) | (((val) & 0x1f) << 5)) |
| 1373 | /* Register Address (4:0) */ |
| 1374 | #define LTQ_ES_MDIO_CTL_REG_REGAD (0x1f) |
| 1375 | #define LTQ_ES_MDIO_CTL_REG_REGAD_VAL(val) (((val) & 0x1f) << 0) |
| 1376 | #define LTQ_ES_MDIO_CTL_REG_REGAD_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_REGAD) >> 0) & 0x1f) |
| 1377 | #define LTQ_ES_MDIO_CTL_REG_REGAD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_REGAD) | (((val) & 0x1f) << 0)) |
| 1378 | |
| 1379 | /******************************************************************************* |
| 1380 | * MDIO Indirect Read Data |
| 1381 | ******************************************************************************/ |
| 1382 | |
| 1383 | /* Reserved (31:16) */ |
| 1384 | #define LTQ_ES_MDIO_DATA_REG_RES (0xffff << 16) |
| 1385 | #define LTQ_ES_MDIO_DATA_REG_RES_GET(val) ((((val) & LTQ_ES_MDIO_DATA_REG_RES) >> 16) & 0xffff) |
| 1386 | /* The Read Data (15:0) */ |
| 1387 | #define LTQ_ES_MDIO_DATA_REG_RD (0xffff) |
| 1388 | #define LTQ_ES_MDIO_DATA_REG_RD_GET(val) ((((val) & LTQ_ES_MDIO_DATA_REG_RD) >> 0) & 0xffff) |
| 1389 | |
| 1390 | /******************************************************************************* |
| 1391 | * Type Filter Action |
| 1392 | ******************************************************************************/ |
| 1393 | |
| 1394 | /* Destination Queue for Type Filter 7 (31:30) */ |
| 1395 | #define LTQ_ES_TP_FLT_ACT_REG_QATF7 (0x3 << 30) |
| 1396 | #define LTQ_ES_TP_FLT_ACT_REG_QATF7_VAL(val) (((val) & 0x3) << 30) |
| 1397 | #define LTQ_ES_TP_FLT_ACT_REG_QATF7_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QATF7) >> 30) & 0x3) |
| 1398 | #define LTQ_ES_TP_FLT_ACT_REG_QATF7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QATF7) | (((val) & 0x3) << 30)) |
| 1399 | /* Destination Queue for Type Filter 6 (29:28) */ |
| 1400 | #define LTQ_ES_TP_FLT_ACT_REG_QATF6 (0x3 << 28) |
| 1401 | #define LTQ_ES_TP_FLT_ACT_REG_QATF6_VAL(val) (((val) & 0x3) << 28) |
| 1402 | #define LTQ_ES_TP_FLT_ACT_REG_QATF6_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QATF6) >> 28) & 0x3) |
| 1403 | #define LTQ_ES_TP_FLT_ACT_REG_QATF6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QATF6) | (((val) & 0x3) << 28)) |
| 1404 | /* Destination Queue for Type Filter 5 (27:26) */ |
| 1405 | #define LTQ_ES_TP_FLT_ACT_REG_QTF5 (0x3 << 26) |
| 1406 | #define LTQ_ES_TP_FLT_ACT_REG_QTF5_VAL(val) (((val) & 0x3) << 26) |
| 1407 | #define LTQ_ES_TP_FLT_ACT_REG_QTF5_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF5) >> 26) & 0x3) |
| 1408 | #define LTQ_ES_TP_FLT_ACT_REG_QTF5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF5) | (((val) & 0x3) << 26)) |
| 1409 | /* Destination Queue for Type Filter 4 (25:24) */ |
| 1410 | #define LTQ_ES_TP_FLT_ACT_REG_QTF4 (0x3 << 24) |
| 1411 | #define LTQ_ES_TP_FLT_ACT_REG_QTF4_VAL(val) (((val) & 0x3) << 24) |
| 1412 | #define LTQ_ES_TP_FLT_ACT_REG_QTF4_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF4) >> 24) & 0x3) |
| 1413 | #define LTQ_ES_TP_FLT_ACT_REG_QTF4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF4) | (((val) & 0x3) << 24)) |
| 1414 | /* Destination Queue for Type Filter 3 (23:22) */ |
| 1415 | #define LTQ_ES_TP_FLT_ACT_REG_QTF3 (0x3 << 22) |
| 1416 | #define LTQ_ES_TP_FLT_ACT_REG_QTF3_VAL(val) (((val) & 0x3) << 22) |
| 1417 | #define LTQ_ES_TP_FLT_ACT_REG_QTF3_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF3) >> 22) & 0x3) |
| 1418 | #define LTQ_ES_TP_FLT_ACT_REG_QTF3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF3) | (((val) & 0x3) << 22)) |
| 1419 | /* Destination Queue for Type Filter 2 (21:20) */ |
| 1420 | #define LTQ_ES_TP_FLT_ACT_REG_QTF2 (0x3 << 20) |
| 1421 | #define LTQ_ES_TP_FLT_ACT_REG_QTF2_VAL(val) (((val) & 0x3) << 20) |
| 1422 | #define LTQ_ES_TP_FLT_ACT_REG_QTF2_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF2) >> 20) & 0x3) |
| 1423 | #define LTQ_ES_TP_FLT_ACT_REG_QTF2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF2) | (((val) & 0x3) << 20)) |
| 1424 | /* Destination Queue for Type Filter 1 (19:18) */ |
| 1425 | #define LTQ_ES_TP_FLT_ACT_REG_QTF1 (0x3 << 18) |
| 1426 | #define LTQ_ES_TP_FLT_ACT_REG_QTF1_VAL(val) (((val) & 0x3) << 18) |
| 1427 | #define LTQ_ES_TP_FLT_ACT_REG_QTF1_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF1) >> 18) & 0x3) |
| 1428 | #define LTQ_ES_TP_FLT_ACT_REG_QTF1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF1) | (((val) & 0x3) << 18)) |
| 1429 | /* Destination Queue for Type Filter 0 (17:16) */ |
| 1430 | #define LTQ_ES_TP_FLT_ACT_REG_QTF0 (0x3 << 16) |
| 1431 | #define LTQ_ES_TP_FLT_ACT_REG_QTF0_VAL(val) (((val) & 0x3) << 16) |
| 1432 | #define LTQ_ES_TP_FLT_ACT_REG_QTF0_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF0) >> 16) & 0x3) |
| 1433 | #define LTQ_ES_TP_FLT_ACT_REG_QTF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF0) | (((val) & 0x3) << 16)) |
| 1434 | /* Action for Type Filter 7 (15:14) */ |
| 1435 | #define LTQ_ES_TP_FLT_ACT_REG_ATF7 (0x3 << 14) |
| 1436 | #define LTQ_ES_TP_FLT_ACT_REG_ATF7_VAL(val) (((val) & 0x3) << 14) |
| 1437 | #define LTQ_ES_TP_FLT_ACT_REG_ATF7_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF7) >> 14) & 0x3) |
| 1438 | #define LTQ_ES_TP_FLT_ACT_REG_ATF7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF7) | (((val) & 0x3) << 14)) |
| 1439 | /* Action for Type Filter 6 (13:12) */ |
| 1440 | #define LTQ_ES_TP_FLT_ACT_REG_ATF6 (0x3 << 12) |
| 1441 | #define LTQ_ES_TP_FLT_ACT_REG_ATF6_VAL(val) (((val) & 0x3) << 12) |
| 1442 | #define LTQ_ES_TP_FLT_ACT_REG_ATF6_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF6) >> 12) & 0x3) |
| 1443 | #define LTQ_ES_TP_FLT_ACT_REG_ATF6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF6) | (((val) & 0x3) << 12)) |
| 1444 | /* Action for Type Filter 5 (11:10) */ |
| 1445 | #define LTQ_ES_TP_FLT_ACT_REG_ATF5 (0x3 << 10) |
| 1446 | #define LTQ_ES_TP_FLT_ACT_REG_ATF5_VAL(val) (((val) & 0x3) << 10) |
| 1447 | #define LTQ_ES_TP_FLT_ACT_REG_ATF5_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF5) >> 10) & 0x3) |
| 1448 | #define LTQ_ES_TP_FLT_ACT_REG_ATF5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF5) | (((val) & 0x3) << 10)) |
| 1449 | /* Action for Type Filter 4 (9:8) */ |
| 1450 | #define LTQ_ES_TP_FLT_ACT_REG_ATF4 (0x3 << 8) |
| 1451 | #define LTQ_ES_TP_FLT_ACT_REG_ATF4_VAL(val) (((val) & 0x3) << 8) |
| 1452 | #define LTQ_ES_TP_FLT_ACT_REG_ATF4_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF4) >> 8) & 0x3) |
| 1453 | #define LTQ_ES_TP_FLT_ACT_REG_ATF4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF4) | (((val) & 0x3) << 8)) |
| 1454 | /* Action for Type Filter 3 (7:6) */ |
| 1455 | #define LTQ_ES_TP_FLT_ACT_REG_ATF3 (0x3 << 6) |
| 1456 | #define LTQ_ES_TP_FLT_ACT_REG_ATF3_VAL(val) (((val) & 0x3) << 6) |
| 1457 | #define LTQ_ES_TP_FLT_ACT_REG_ATF3_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF3) >> 6) & 0x3) |
| 1458 | #define LTQ_ES_TP_FLT_ACT_REG_ATF3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF3) | (((val) & 0x3) << 6)) |
| 1459 | /* Action for Type Filter 2 (5:4) */ |
| 1460 | #define LTQ_ES_TP_FLT_ACT_REG_ATF2 (0x3 << 4) |
| 1461 | #define LTQ_ES_TP_FLT_ACT_REG_ATF2_VAL(val) (((val) & 0x3) << 4) |
| 1462 | #define LTQ_ES_TP_FLT_ACT_REG_ATF2_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF2) >> 4) & 0x3) |
| 1463 | #define LTQ_ES_TP_FLT_ACT_REG_ATF2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF2) | (((val) & 0x3) << 4)) |
| 1464 | /* Action for Type Filter 1 (3:2) */ |
| 1465 | #define LTQ_ES_TP_FLT_ACT_REG_ATF1 (0x3 << 2) |
| 1466 | #define LTQ_ES_TP_FLT_ACT_REG_ATF1_VAL(val) (((val) & 0x3) << 2) |
| 1467 | #define LTQ_ES_TP_FLT_ACT_REG_ATF1_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF1) >> 2) & 0x3) |
| 1468 | #define LTQ_ES_TP_FLT_ACT_REG_ATF1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF1) | (((val) & 0x3) << 2)) |
| 1469 | /* Action for Type Filter 0 (1:0) */ |
| 1470 | #define LTQ_ES_TP_FLT_ACT_REG_ATF0 (0x3) |
| 1471 | #define LTQ_ES_TP_FLT_ACT_REG_ATF0_VAL(val) (((val) & 0x3) << 0) |
| 1472 | #define LTQ_ES_TP_FLT_ACT_REG_ATF0_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF0) >> 0) & 0x3) |
| 1473 | #define LTQ_ES_TP_FLT_ACT_REG_ATF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF0) | (((val) & 0x3) << 0)) |
| 1474 | |
| 1475 | /******************************************************************************* |
| 1476 | * Protocol Filter Action |
| 1477 | ******************************************************************************/ |
| 1478 | |
| 1479 | /* Action for Protocol Filter 7 (15:14) */ |
| 1480 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF7 (0x3 << 14) |
| 1481 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF7_VAL(val) (((val) & 0x3) << 14) |
| 1482 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF7_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF7) >> 14) & 0x3) |
| 1483 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF7) | (((val) & 0x3) << 14)) |
| 1484 | /* Action for Protocol Filter 6 (13:12) */ |
| 1485 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF6 (0x3 << 12) |
| 1486 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF6_VAL(val) (((val) & 0x3) << 12) |
| 1487 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF6_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF6) >> 12) & 0x3) |
| 1488 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF6) | (((val) & 0x3) << 12)) |
| 1489 | /* Action for Protocol Filter 5 (11:10) */ |
| 1490 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF5 (0x3 << 10) |
| 1491 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF5_VAL(val) (((val) & 0x3) << 10) |
| 1492 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF5_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF5) >> 10) & 0x3) |
| 1493 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF5) | (((val) & 0x3) << 10)) |
| 1494 | /* Action for Protocol Filter 4 (9:8) */ |
| 1495 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF4 (0x3 << 8) |
| 1496 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF4_VAL(val) (((val) & 0x3) << 8) |
| 1497 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF4_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF4) >> 8) & 0x3) |
| 1498 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF4) | (((val) & 0x3) << 8)) |
| 1499 | /* Action for Protocol Filter 3 (7:6) */ |
| 1500 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF3 (0x3 << 6) |
| 1501 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF3_VAL(val) (((val) & 0x3) << 6) |
| 1502 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF3_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF3) >> 6) & 0x3) |
| 1503 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF3) | (((val) & 0x3) << 6)) |
| 1504 | /* Action for Protocol Filter 2 (5:4) */ |
| 1505 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF2 (0x3 << 4) |
| 1506 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF2_VAL(val) (((val) & 0x3) << 4) |
| 1507 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF2_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF2) >> 4) & 0x3) |
| 1508 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF2) | (((val) & 0x3) << 4)) |
| 1509 | /* Action for Protocol Filter 1 (3:2) */ |
| 1510 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF1 (0x3 << 2) |
| 1511 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF1_VAL(val) (((val) & 0x3) << 2) |
| 1512 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF1_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF1) >> 2) & 0x3) |
| 1513 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF1) | (((val) & 0x3) << 2)) |
| 1514 | /* Action for Protocol Filter 0 (1:0) */ |
| 1515 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF0 (0x3) |
| 1516 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF0_VAL(val) (((val) & 0x3) << 0) |
| 1517 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF0_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF0) >> 0) & 0x3) |
| 1518 | #define LTQ_ES_PRTCL_FLT_ACT_REG_APF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF0) | (((val) & 0x3) << 0)) |
| 1519 | |
| 1520 | /******************************************************************************* |
| 1521 | * VLAN Filter 0 |
| 1522 | ******************************************************************************/ |
| 1523 | |
| 1524 | /* Res (31:24) */ |
| 1525 | #define LTQ_ES_VLAN_FLT0_REG_RES (0xff << 24) |
| 1526 | #define LTQ_ES_VLAN_FLT0_REG_RES_VAL(val) (((val) & 0xff) << 24) |
| 1527 | #define LTQ_ES_VLAN_FLT0_REG_RES_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_RES) >> 24) & 0xff) |
| 1528 | #define LTQ_ES_VLAN_FLT0_REG_RES_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_RES) | (((val) & 0xff) << 24)) |
| 1529 | /* FID (23:22) */ |
| 1530 | #define LTQ_ES_VLAN_FLT0_REG_FID (0x3 << 22) |
| 1531 | #define LTQ_ES_VLAN_FLT0_REG_FID_VAL(val) (((val) & 0x3) << 22) |
| 1532 | #define LTQ_ES_VLAN_FLT0_REG_FID_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_FID) >> 22) & 0x3) |
| 1533 | #define LTQ_ES_VLAN_FLT0_REG_FID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_FID) | (((val) & 0x3) << 22)) |
| 1534 | /* Tagged Member (21:19) */ |
| 1535 | #define LTQ_ES_VLAN_FLT0_REG_TM (0x7 << 19) |
| 1536 | #define LTQ_ES_VLAN_FLT0_REG_TM_VAL(val) (((val) & 0x7) << 19) |
| 1537 | #define LTQ_ES_VLAN_FLT0_REG_TM_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_TM) >> 19) & 0x7) |
| 1538 | #define LTQ_ES_VLAN_FLT0_REG_TM_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_TM) | (((val) & 0x7) << 19)) |
| 1539 | /* Member (18:16) */ |
| 1540 | #define LTQ_ES_VLAN_FLT0_REG_M (0x7 << 16) |
| 1541 | #define LTQ_ES_VLAN_FLT0_REG_M_VAL(val) (((val) & 0x7) << 16) |
| 1542 | #define LTQ_ES_VLAN_FLT0_REG_M_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_M) >> 16) & 0x7) |
| 1543 | #define LTQ_ES_VLAN_FLT0_REG_M_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_M) | (((val) & 0x7) << 16)) |
| 1544 | /* VLAN_Valid (15) */ |
| 1545 | #define LTQ_ES_VLAN_FLT0_REG_VV (0x1 << 15) |
| 1546 | #define LTQ_ES_VLAN_FLT0_REG_VV_VAL(val) (((val) & 0x1) << 15) |
| 1547 | #define LTQ_ES_VLAN_FLT0_REG_VV_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_VV) >> 15) & 0x1) |
| 1548 | #define LTQ_ES_VLAN_FLT0_REG_VV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_VV) | (((val) & 0x1) << 15)) |
| 1549 | /* VLAN PRI (14:12) */ |
| 1550 | #define LTQ_ES_VLAN_FLT0_REG_VP (0x7 << 12) |
| 1551 | #define LTQ_ES_VLAN_FLT0_REG_VP_VAL(val) (((val) & 0x7) << 12) |
| 1552 | #define LTQ_ES_VLAN_FLT0_REG_VP_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_VP) >> 12) & 0x7) |
| 1553 | #define LTQ_ES_VLAN_FLT0_REG_VP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_VP) | (((val) & 0x7) << 12)) |
| 1554 | /* VID (11:0) */ |
| 1555 | #define LTQ_ES_VLAN_FLT0_REG_VID (0xfff) |
| 1556 | #define LTQ_ES_VLAN_FLT0_REG_VID_VAL(val) (((val) & 0xfff) << 0) |
| 1557 | #define LTQ_ES_VLAN_FLT0_REG_VID_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_VID) >> 0) & 0xfff) |
| 1558 | #define LTQ_ES_VLAN_FLT0_REG_VID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_VID) | (((val) & 0xfff) << 0)) |
| 1559 | |
| 1560 | /******************************************************************************* |
| 1561 | * Type Filter 10 |
| 1562 | ******************************************************************************/ |
| 1563 | |
| 1564 | /* Value 1 Compared with Ether-Type (31:16) */ |
| 1565 | #define LTQ_ES_TP_FLT10_REG_VCET1 (0xffff << 16) |
| 1566 | #define LTQ_ES_TP_FLT10_REG_VCET1_VAL(val) (((val) & 0xffff) << 16) |
| 1567 | #define LTQ_ES_TP_FLT10_REG_VCET1_GET(val) ((((val) & LTQ_ES_TP_FLT10_REG_VCET1) >> 16) & 0xffff) |
| 1568 | #define LTQ_ES_TP_FLT10_REG_VCET1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT10_REG_VCET1) | (((val) & 0xffff) << 16)) |
| 1569 | /* Value 0 Compared with Ether-Type (15:0) */ |
| 1570 | #define LTQ_ES_TP_FLT10_REG_VCET0 (0xffff) |
| 1571 | #define LTQ_ES_TP_FLT10_REG_VCET0_VAL(val) (((val) & 0xffff) << 0) |
| 1572 | #define LTQ_ES_TP_FLT10_REG_VCET0_GET(val) ((((val) & LTQ_ES_TP_FLT10_REG_VCET0) >> 0) & 0xffff) |
| 1573 | #define LTQ_ES_TP_FLT10_REG_VCET0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT10_REG_VCET0) | (((val) & 0xffff) << 0)) |
| 1574 | |
| 1575 | /******************************************************************************* |
| 1576 | * DiffServMapping 0 |
| 1577 | ******************************************************************************/ |
| 1578 | |
| 1579 | /* Priority Queue F (31:30) */ |
| 1580 | #define LTQ_ES_DFSRV_MAP0_REG_PQF (0x3 << 30) |
| 1581 | #define LTQ_ES_DFSRV_MAP0_REG_PQF_VAL(val) (((val) & 0x3) << 30) |
| 1582 | #define LTQ_ES_DFSRV_MAP0_REG_PQF_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQF) >> 30) & 0x3) |
| 1583 | #define LTQ_ES_DFSRV_MAP0_REG_PQF_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQF) | (((val) & 0x3) << 30)) |
| 1584 | /* Priority Queue E (29:28) */ |
| 1585 | #define LTQ_ES_DFSRV_MAP0_REG_PQE (0x3 << 28) |
| 1586 | #define LTQ_ES_DFSRV_MAP0_REG_PQE_VAL(val) (((val) & 0x3) << 28) |
| 1587 | #define LTQ_ES_DFSRV_MAP0_REG_PQE_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQE) >> 28) & 0x3) |
| 1588 | #define LTQ_ES_DFSRV_MAP0_REG_PQE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQE) | (((val) & 0x3) << 28)) |
| 1589 | /* Priority Queue D (27:26) */ |
| 1590 | #define LTQ_ES_DFSRV_MAP0_REG_PQD (0x3 << 26) |
| 1591 | #define LTQ_ES_DFSRV_MAP0_REG_PQD_VAL(val) (((val) & 0x3) << 26) |
| 1592 | #define LTQ_ES_DFSRV_MAP0_REG_PQD_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQD) >> 26) & 0x3) |
| 1593 | #define LTQ_ES_DFSRV_MAP0_REG_PQD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQD) | (((val) & 0x3) << 26)) |
| 1594 | /* Priority Queue C (25:24) */ |
| 1595 | #define LTQ_ES_DFSRV_MAP0_REG_PQC (0x3 << 24) |
| 1596 | #define LTQ_ES_DFSRV_MAP0_REG_PQC_VAL(val) (((val) & 0x3) << 24) |
| 1597 | #define LTQ_ES_DFSRV_MAP0_REG_PQC_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQC) >> 24) & 0x3) |
| 1598 | #define LTQ_ES_DFSRV_MAP0_REG_PQC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQC) | (((val) & 0x3) << 24)) |
| 1599 | /* Priority Queue B (23:22) */ |
| 1600 | #define LTQ_ES_DFSRV_MAP0_REG_PQB (0x3 << 22) |
| 1601 | #define LTQ_ES_DFSRV_MAP0_REG_PQB_VAL(val) (((val) & 0x3) << 22) |
| 1602 | #define LTQ_ES_DFSRV_MAP0_REG_PQB_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQB) >> 22) & 0x3) |
| 1603 | #define LTQ_ES_DFSRV_MAP0_REG_PQB_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQB) | (((val) & 0x3) << 22)) |
| 1604 | /* Priority Queue A (21:20) */ |
| 1605 | #define LTQ_ES_DFSRV_MAP0_REG_PQA (0x3 << 20) |
| 1606 | #define LTQ_ES_DFSRV_MAP0_REG_PQA_VAL(val) (((val) & 0x3) << 20) |
| 1607 | #define LTQ_ES_DFSRV_MAP0_REG_PQA_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQA) >> 20) & 0x3) |
| 1608 | #define LTQ_ES_DFSRV_MAP0_REG_PQA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQA) | (((val) & 0x3) << 20)) |
| 1609 | /* Priority Queue 9 (19:18) */ |
| 1610 | #define LTQ_ES_DFSRV_MAP0_REG_PQ9 (0x3 << 18) |
| 1611 | #define LTQ_ES_DFSRV_MAP0_REG_PQ9_VAL(val) (((val) & 0x3) << 18) |
| 1612 | #define LTQ_ES_DFSRV_MAP0_REG_PQ9_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ9) >> 18) & 0x3) |
| 1613 | #define LTQ_ES_DFSRV_MAP0_REG_PQ9_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ9) | (((val) & 0x3) << 18)) |
| 1614 | /* Priority Queue 8 (17:16) */ |
| 1615 | #define LTQ_ES_DFSRV_MAP0_REG_PQ8 (0x3 << 16) |
| 1616 | #define LTQ_ES_DFSRV_MAP0_REG_PQ8_VAL(val) (((val) & 0x3) << 16) |
| 1617 | #define LTQ_ES_DFSRV_MAP0_REG_PQ8_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ8) >> 16) & 0x3) |
| 1618 | #define LTQ_ES_DFSRV_MAP0_REG_PQ8_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ8) | (((val) & 0x3) << 16)) |
| 1619 | /* Priority Queue 7 (15:14) */ |
| 1620 | #define LTQ_ES_DFSRV_MAP0_REG_PQ7 (0x3 << 14) |
| 1621 | #define LTQ_ES_DFSRV_MAP0_REG_PQ7_VAL(val) (((val) & 0x3) << 14) |
| 1622 | #define LTQ_ES_DFSRV_MAP0_REG_PQ7_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ7) >> 14) & 0x3) |
| 1623 | #define LTQ_ES_DFSRV_MAP0_REG_PQ7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ7) | (((val) & 0x3) << 14)) |
| 1624 | /* Priority Queue 6 (13:12) */ |
| 1625 | #define LTQ_ES_DFSRV_MAP0_REG_PQ6 (0x3 << 12) |
| 1626 | #define LTQ_ES_DFSRV_MAP0_REG_PQ6_VAL(val) (((val) & 0x3) << 12) |
| 1627 | #define LTQ_ES_DFSRV_MAP0_REG_PQ6_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ6) >> 12) & 0x3) |
| 1628 | #define LTQ_ES_DFSRV_MAP0_REG_PQ6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ6) | (((val) & 0x3) << 12)) |
| 1629 | /* Priority Queue 5 (11:10) */ |
| 1630 | #define LTQ_ES_DFSRV_MAP0_REG_PQ5 (0x3 << 10) |
| 1631 | #define LTQ_ES_DFSRV_MAP0_REG_PQ5_VAL(val) (((val) & 0x3) << 10) |
| 1632 | #define LTQ_ES_DFSRV_MAP0_REG_PQ5_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ5) >> 10) & 0x3) |
| 1633 | #define LTQ_ES_DFSRV_MAP0_REG_PQ5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ5) | (((val) & 0x3) << 10)) |
| 1634 | /* Priority Queue 4 (9:8) */ |
| 1635 | #define LTQ_ES_DFSRV_MAP0_REG_PQ4 (0x3 << 8) |
| 1636 | #define LTQ_ES_DFSRV_MAP0_REG_PQ4_VAL(val) (((val) & 0x3) << 8) |
| 1637 | #define LTQ_ES_DFSRV_MAP0_REG_PQ4_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ4) >> 8) & 0x3) |
| 1638 | #define LTQ_ES_DFSRV_MAP0_REG_PQ4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ4) | (((val) & 0x3) << 8)) |
| 1639 | /* Priority Queue 3 (7:6) */ |
| 1640 | #define LTQ_ES_DFSRV_MAP0_REG_PQ3 (0x3 << 6) |
| 1641 | #define LTQ_ES_DFSRV_MAP0_REG_PQ3_VAL(val) (((val) & 0x3) << 6) |
| 1642 | #define LTQ_ES_DFSRV_MAP0_REG_PQ3_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ3) >> 6) & 0x3) |
| 1643 | #define LTQ_ES_DFSRV_MAP0_REG_PQ3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ3) | (((val) & 0x3) << 6)) |
| 1644 | /* Priority Queue 2 (5:4) */ |
| 1645 | #define LTQ_ES_DFSRV_MAP0_REG_PQ2 (0x3 << 4) |
| 1646 | #define LTQ_ES_DFSRV_MAP0_REG_PQ2_VAL(val) (((val) & 0x3) << 4) |
| 1647 | #define LTQ_ES_DFSRV_MAP0_REG_PQ2_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ2) >> 4) & 0x3) |
| 1648 | #define LTQ_ES_DFSRV_MAP0_REG_PQ2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ2) | (((val) & 0x3) << 4)) |
| 1649 | /* Priority Queue 1 (3:2) */ |
| 1650 | #define LTQ_ES_DFSRV_MAP0_REG_PQ1 (0x3 << 2) |
| 1651 | #define LTQ_ES_DFSRV_MAP0_REG_PQ1_VAL(val) (((val) & 0x3) << 2) |
| 1652 | #define LTQ_ES_DFSRV_MAP0_REG_PQ1_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ1) >> 2) & 0x3) |
| 1653 | #define LTQ_ES_DFSRV_MAP0_REG_PQ1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ1) | (((val) & 0x3) << 2)) |
| 1654 | /* Priority Queue 0 (1:0) */ |
| 1655 | #define LTQ_ES_DFSRV_MAP0_REG_PQ0 (0x3) |
| 1656 | #define LTQ_ES_DFSRV_MAP0_REG_PQ0_VAL(val) (((val) & 0x3) << 0) |
| 1657 | #define LTQ_ES_DFSRV_MAP0_REG_PQ0_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ0) >> 0) & 0x3) |
| 1658 | #define LTQ_ES_DFSRV_MAP0_REG_PQ0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ0) | (((val) & 0x3) << 0)) |
| 1659 | |
| 1660 | /******************************************************************************* |
| 1661 | * DiffServMapping 1 |
| 1662 | ******************************************************************************/ |
| 1663 | |
| 1664 | /* Priority Queue 1F (31:30) */ |
| 1665 | #define LTQ_ES_DFSRV_MAP1_REG_PQ1F (0x3 << 30) |
| 1666 | #define LTQ_ES_DFSRV_MAP1_REG_PQ1F_VAL(val) (((val) & 0x3) << 30) |
| 1667 | #define LTQ_ES_DFSRV_MAP1_REG_PQ1F_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1F) >> 30) & 0x3) |
| 1668 | #define LTQ_ES_DFSRV_MAP1_REG_PQ1F_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1F) | (((val) & 0x3) << 30)) |
| 1669 | /* Priority Queue 1E (29:28) */ |
| 1670 | #define LTQ_ES_DFSRV_MAP1_REG_PQ1E (0x3 << 28) |
| 1671 | #define LTQ_ES_DFSRV_MAP1_REG_PQ1E_VAL(val) (((val) & 0x3) << 28) |
| 1672 | #define LTQ_ES_DFSRV_MAP1_REG_PQ1E_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1E) >> 28) & 0x3) |
| 1673 | #define LTQ_ES_DFSRV_MAP1_REG_PQ1E_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1E) | (((val) & 0x3) << 28)) |
| 1674 | /* Priority Queue 1D (27:26) */ |
| 1675 | #define LTQ_ES_DFSRV_MAP1_REG_PQ1D (0x3 << 26) |
| 1676 | #define LTQ_ES_DFSRV_MAP1_REG_PQ1D_VAL(val) (((val) & 0x3) << 26) |
| 1677 | #define LTQ_ES_DFSRV_MAP1_REG_PQ1D_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1D) >> 26) & 0x3) |
| 1678 | #define LTQ_ES_DFSRV_MAP1_REG_PQ1D_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1D) | (((val) & 0x3) << 26)) |
| 1679 | /* Priority Queue 1C (25:24) */ |
| 1680 | #define LTQ_ES_DFSRV_MAP1_REG_PQ1C (0x3 << 24) |
| 1681 | #define LTQ_ES_DFSRV_MAP1_REG_PQ1C_VAL(val) (((val) & 0x3) << 24) |
| 1682 | #define LTQ_ES_DFSRV_MAP1_REG_PQ1C_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1C) >> 24) & 0x3) |
| 1683 | #define LTQ_ES_DFSRV_MAP1_REG_PQ1C_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1C) | (((val) & 0x3) << 24)) |
| 1684 | /* Priority Queue 1B (23:22) */ |
| 1685 | #define LTQ_ES_DFSRV_MAP1_REG_PQ1B (0x3 << 22) |
| 1686 | #define LTQ_ES_DFSRV_MAP1_REG_PQ1B_VAL(val) (((val) & 0x3) << 22) |
| 1687 | #define LTQ_ES_DFSRV_MAP1_REG_PQ1B_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1B) >> 22) & 0x3) |
| 1688 | #define LTQ_ES_DFSRV_MAP1_REG_PQ1B_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1B) | (((val) & 0x3) << 22)) |
| 1689 | /* Priority Queue 1A (21:20) */ |
| 1690 | #define LTQ_ES_DFSRV_MAP1_REG_PQ1A (0x3 << 20) |
| 1691 | #define LTQ_ES_DFSRV_MAP1_REG_PQ1A_VAL(val) (((val) & 0x3) << 20) |
| 1692 | #define LTQ_ES_DFSRV_MAP1_REG_PQ1A_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1A) >> 20) & 0x3) |
| 1693 | #define LTQ_ES_DFSRV_MAP1_REG_PQ1A_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1A) | (((val) & 0x3) << 20)) |
| 1694 | /* Priority Queue 19 (19:18) */ |
| 1695 | #define LTQ_ES_DFSRV_MAP1_REG_PQ19 (0x3 << 18) |
| 1696 | #define LTQ_ES_DFSRV_MAP1_REG_PQ19_VAL(val) (((val) & 0x3) << 18) |
| 1697 | #define LTQ_ES_DFSRV_MAP1_REG_PQ19_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ19) >> 18) & 0x3) |
| 1698 | #define LTQ_ES_DFSRV_MAP1_REG_PQ19_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ19) | (((val) & 0x3) << 18)) |
| 1699 | /* Priority Queue 18 (17:16) */ |
| 1700 | #define LTQ_ES_DFSRV_MAP1_REG_PQ18 (0x3 << 16) |
| 1701 | #define LTQ_ES_DFSRV_MAP1_REG_PQ18_VAL(val) (((val) & 0x3) << 16) |
| 1702 | #define LTQ_ES_DFSRV_MAP1_REG_PQ18_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ18) >> 16) & 0x3) |
| 1703 | #define LTQ_ES_DFSRV_MAP1_REG_PQ18_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ18) | (((val) & 0x3) << 16)) |
| 1704 | /* Priority Queue 17 (15:14) */ |
| 1705 | #define LTQ_ES_DFSRV_MAP1_REG_PQ17 (0x3 << 14) |
| 1706 | #define LTQ_ES_DFSRV_MAP1_REG_PQ17_VAL(val) (((val) & 0x3) << 14) |
| 1707 | #define LTQ_ES_DFSRV_MAP1_REG_PQ17_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ17) >> 14) & 0x3) |
| 1708 | #define LTQ_ES_DFSRV_MAP1_REG_PQ17_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ17) | (((val) & 0x3) << 14)) |
| 1709 | /* Priority Queue 16 (13:12) */ |
| 1710 | #define LTQ_ES_DFSRV_MAP1_REG_PQ16 (0x3 << 12) |
| 1711 | #define LTQ_ES_DFSRV_MAP1_REG_PQ16_VAL(val) (((val) & 0x3) << 12) |
| 1712 | #define LTQ_ES_DFSRV_MAP1_REG_PQ16_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ16) >> 12) & 0x3) |
| 1713 | #define LTQ_ES_DFSRV_MAP1_REG_PQ16_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ16) | (((val) & 0x3) << 12)) |
| 1714 | /* Priority Queue 15 (11:10) */ |
| 1715 | #define LTQ_ES_DFSRV_MAP1_REG_PQ15 (0x3 << 10) |
| 1716 | #define LTQ_ES_DFSRV_MAP1_REG_PQ15_VAL(val) (((val) & 0x3) << 10) |
| 1717 | #define LTQ_ES_DFSRV_MAP1_REG_PQ15_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ15) >> 10) & 0x3) |
| 1718 | #define LTQ_ES_DFSRV_MAP1_REG_PQ15_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ15) | (((val) & 0x3) << 10)) |
| 1719 | /* Priority Queue 14 (9:8) */ |
| 1720 | #define LTQ_ES_DFSRV_MAP1_REG_PQ14 (0x3 << 8) |
| 1721 | #define LTQ_ES_DFSRV_MAP1_REG_PQ14_VAL(val) (((val) & 0x3) << 8) |
| 1722 | #define LTQ_ES_DFSRV_MAP1_REG_PQ14_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ14) >> 8) & 0x3) |
| 1723 | #define LTQ_ES_DFSRV_MAP1_REG_PQ14_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ14) | (((val) & 0x3) << 8)) |
| 1724 | /* Priority Queue 13 (7:6) */ |
| 1725 | #define LTQ_ES_DFSRV_MAP1_REG_PQ13 (0x3 << 6) |
| 1726 | #define LTQ_ES_DFSRV_MAP1_REG_PQ13_VAL(val) (((val) & 0x3) << 6) |
| 1727 | #define LTQ_ES_DFSRV_MAP1_REG_PQ13_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ13) >> 6) & 0x3) |
| 1728 | #define LTQ_ES_DFSRV_MAP1_REG_PQ13_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ13) | (((val) & 0x3) << 6)) |
| 1729 | /* Priority Queue 12 (5:4) */ |
| 1730 | #define LTQ_ES_DFSRV_MAP1_REG_PQ12 (0x3 << 4) |
| 1731 | #define LTQ_ES_DFSRV_MAP1_REG_PQ12_VAL(val) (((val) & 0x3) << 4) |
| 1732 | #define LTQ_ES_DFSRV_MAP1_REG_PQ12_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ12) >> 4) & 0x3) |
| 1733 | #define LTQ_ES_DFSRV_MAP1_REG_PQ12_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ12) | (((val) & 0x3) << 4)) |
| 1734 | /* Priority Queue 11 (3:2) */ |
| 1735 | #define LTQ_ES_DFSRV_MAP1_REG_PQ11 (0x3 << 2) |
| 1736 | #define LTQ_ES_DFSRV_MAP1_REG_PQ11_VAL(val) (((val) & 0x3) << 2) |
| 1737 | #define LTQ_ES_DFSRV_MAP1_REG_PQ11_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ11) >> 2) & 0x3) |
| 1738 | #define LTQ_ES_DFSRV_MAP1_REG_PQ11_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ11) | (((val) & 0x3) << 2)) |
| 1739 | /* Priority Queue 10 (1:0) */ |
| 1740 | #define LTQ_ES_DFSRV_MAP1_REG_PQ10 (0x3) |
| 1741 | #define LTQ_ES_DFSRV_MAP1_REG_PQ10_VAL(val) (((val) & 0x3) << 0) |
| 1742 | #define LTQ_ES_DFSRV_MAP1_REG_PQ10_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ10) >> 0) & 0x3) |
| 1743 | #define LTQ_ES_DFSRV_MAP1_REG_PQ10_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ10) | (((val) & 0x3) << 0)) |
| 1744 | |
| 1745 | /******************************************************************************* |
| 1746 | * DiffServMapping 2 |
| 1747 | ******************************************************************************/ |
| 1748 | |
| 1749 | /* Priority Queue 2F (31:30) */ |
| 1750 | #define LTQ_ES_DFSRV_MAP2_REG_PQ2F (0x3 << 30) |
| 1751 | #define LTQ_ES_DFSRV_MAP2_REG_PQ2F_VAL(val) (((val) & 0x3) << 30) |
| 1752 | #define LTQ_ES_DFSRV_MAP2_REG_PQ2F_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2F) >> 30) & 0x3) |
| 1753 | #define LTQ_ES_DFSRV_MAP2_REG_PQ2F_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2F) | (((val) & 0x3) << 30)) |
| 1754 | /* Priority Queue 2E (29:28) */ |
| 1755 | #define LTQ_ES_DFSRV_MAP2_REG_PQ2E (0x3 << 28) |
| 1756 | #define LTQ_ES_DFSRV_MAP2_REG_PQ2E_VAL(val) (((val) & 0x3) << 28) |
| 1757 | #define LTQ_ES_DFSRV_MAP2_REG_PQ2E_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2E) >> 28) & 0x3) |
| 1758 | #define LTQ_ES_DFSRV_MAP2_REG_PQ2E_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2E) | (((val) & 0x3) << 28)) |
| 1759 | /* Priority Queue 2D (27:26) */ |
| 1760 | #define LTQ_ES_DFSRV_MAP2_REG_PQ2D (0x3 << 26) |
| 1761 | #define LTQ_ES_DFSRV_MAP2_REG_PQ2D_VAL(val) (((val) & 0x3) << 26) |
| 1762 | #define LTQ_ES_DFSRV_MAP2_REG_PQ2D_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2D) >> 26) & 0x3) |
| 1763 | #define LTQ_ES_DFSRV_MAP2_REG_PQ2D_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2D) | (((val) & 0x3) << 26)) |
| 1764 | /* Priority Queue 2C (25:24) */ |
| 1765 | #define LTQ_ES_DFSRV_MAP2_REG_PQ2C (0x3 << 24) |
| 1766 | #define LTQ_ES_DFSRV_MAP2_REG_PQ2C_VAL(val) (((val) & 0x3) << 24) |
| 1767 | #define LTQ_ES_DFSRV_MAP2_REG_PQ2C_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2C) >> 24) & 0x3) |
| 1768 | #define LTQ_ES_DFSRV_MAP2_REG_PQ2C_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2C) | (((val) & 0x3) << 24)) |
| 1769 | /* Priority Queue 2B (23:22) */ |
| 1770 | #define LTQ_ES_DFSRV_MAP2_REG_PQ2B (0x3 << 22) |
| 1771 | #define LTQ_ES_DFSRV_MAP2_REG_PQ2B_VAL(val) (((val) & 0x3) << 22) |
| 1772 | #define LTQ_ES_DFSRV_MAP2_REG_PQ2B_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2B) >> 22) & 0x3) |
| 1773 | #define LTQ_ES_DFSRV_MAP2_REG_PQ2B_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2B) | (((val) & 0x3) << 22)) |
| 1774 | /* Priority Queue 2A (21:20) */ |
| 1775 | #define LTQ_ES_DFSRV_MAP2_REG_PQ2A (0x3 << 20) |
| 1776 | #define LTQ_ES_DFSRV_MAP2_REG_PQ2A_VAL(val) (((val) & 0x3) << 20) |
| 1777 | #define LTQ_ES_DFSRV_MAP2_REG_PQ2A_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2A) >> 20) & 0x3) |
| 1778 | #define LTQ_ES_DFSRV_MAP2_REG_PQ2A_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2A) | (((val) & 0x3) << 20)) |
| 1779 | /* Priority Queue 29 (19:18) */ |
| 1780 | #define LTQ_ES_DFSRV_MAP2_REG_PQ29 (0x3 << 18) |
| 1781 | #define LTQ_ES_DFSRV_MAP2_REG_PQ29_VAL(val) (((val) & 0x3) << 18) |
| 1782 | #define LTQ_ES_DFSRV_MAP2_REG_PQ29_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ29) >> 18) & 0x3) |
| 1783 | #define LTQ_ES_DFSRV_MAP2_REG_PQ29_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ29) | (((val) & 0x3) << 18)) |
| 1784 | /* Priority Queue 28 (17:16) */ |
| 1785 | #define LTQ_ES_DFSRV_MAP2_REG_PQ28 (0x3 << 16) |
| 1786 | #define LTQ_ES_DFSRV_MAP2_REG_PQ28_VAL(val) (((val) & 0x3) << 16) |
| 1787 | #define LTQ_ES_DFSRV_MAP2_REG_PQ28_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ28) >> 16) & 0x3) |
| 1788 | #define LTQ_ES_DFSRV_MAP2_REG_PQ28_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ28) | (((val) & 0x3) << 16)) |
| 1789 | /* Priority Queue 27 (15:14) */ |
| 1790 | #define LTQ_ES_DFSRV_MAP2_REG_PQ27 (0x3 << 14) |
| 1791 | #define LTQ_ES_DFSRV_MAP2_REG_PQ27_VAL(val) (((val) & 0x3) << 14) |
| 1792 | #define LTQ_ES_DFSRV_MAP2_REG_PQ27_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ27) >> 14) & 0x3) |
| 1793 | #define LTQ_ES_DFSRV_MAP2_REG_PQ27_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ27) | (((val) & 0x3) << 14)) |
| 1794 | /* Priority Queue 26 (13:12) */ |
| 1795 | #define LTQ_ES_DFSRV_MAP2_REG_PQ26 (0x3 << 12) |
| 1796 | #define LTQ_ES_DFSRV_MAP2_REG_PQ26_VAL(val) (((val) & 0x3) << 12) |
| 1797 | #define LTQ_ES_DFSRV_MAP2_REG_PQ26_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ26) >> 12) & 0x3) |
| 1798 | #define LTQ_ES_DFSRV_MAP2_REG_PQ26_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ26) | (((val) & 0x3) << 12)) |
| 1799 | /* Priority Queue 25 (11:10) */ |
| 1800 | #define LTQ_ES_DFSRV_MAP2_REG_PQ25 (0x3 << 10) |
| 1801 | #define LTQ_ES_DFSRV_MAP2_REG_PQ25_VAL(val) (((val) & 0x3) << 10) |
| 1802 | #define LTQ_ES_DFSRV_MAP2_REG_PQ25_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ25) >> 10) & 0x3) |
| 1803 | #define LTQ_ES_DFSRV_MAP2_REG_PQ25_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ25) | (((val) & 0x3) << 10)) |
| 1804 | /* Priority Queue 24 (9:8) */ |
| 1805 | #define LTQ_ES_DFSRV_MAP2_REG_PQ24 (0x3 << 8) |
| 1806 | #define LTQ_ES_DFSRV_MAP2_REG_PQ24_VAL(val) (((val) & 0x3) << 8) |
| 1807 | #define LTQ_ES_DFSRV_MAP2_REG_PQ24_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ24) >> 8) & 0x3) |
| 1808 | #define LTQ_ES_DFSRV_MAP2_REG_PQ24_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ24) | (((val) & 0x3) << 8)) |
| 1809 | /* Priority Queue 23 (7:6) */ |
| 1810 | #define LTQ_ES_DFSRV_MAP2_REG_PQ23 (0x3 << 6) |
| 1811 | #define LTQ_ES_DFSRV_MAP2_REG_PQ23_VAL(val) (((val) & 0x3) << 6) |
| 1812 | #define LTQ_ES_DFSRV_MAP2_REG_PQ23_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ23) >> 6) & 0x3) |
| 1813 | #define LTQ_ES_DFSRV_MAP2_REG_PQ23_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ23) | (((val) & 0x3) << 6)) |
| 1814 | /* Priority Queue 22 (5:4) */ |
| 1815 | #define LTQ_ES_DFSRV_MAP2_REG_PQ22 (0x3 << 4) |
| 1816 | #define LTQ_ES_DFSRV_MAP2_REG_PQ22_VAL(val) (((val) & 0x3) << 4) |
| 1817 | #define LTQ_ES_DFSRV_MAP2_REG_PQ22_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ22) >> 4) & 0x3) |
| 1818 | #define LTQ_ES_DFSRV_MAP2_REG_PQ22_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ22) | (((val) & 0x3) << 4)) |
| 1819 | /* Priority Queue 21 (3:2) */ |
| 1820 | #define LTQ_ES_DFSRV_MAP2_REG_PQ21 (0x3 << 2) |
| 1821 | #define LTQ_ES_DFSRV_MAP2_REG_PQ21_VAL(val) (((val) & 0x3) << 2) |
| 1822 | #define LTQ_ES_DFSRV_MAP2_REG_PQ21_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ21) >> 2) & 0x3) |
| 1823 | #define LTQ_ES_DFSRV_MAP2_REG_PQ21_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ21) | (((val) & 0x3) << 2)) |
| 1824 | /* Priority Queue 20 (1:0) */ |
| 1825 | #define LTQ_ES_DFSRV_MAP2_REG_PQ20 (0x3) |
| 1826 | #define LTQ_ES_DFSRV_MAP2_REG_PQ20_VAL(val) (((val) & 0x3) << 0) |
| 1827 | #define LTQ_ES_DFSRV_MAP2_REG_PQ20_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ20) >> 0) & 0x3) |
| 1828 | #define LTQ_ES_DFSRV_MAP2_REG_PQ20_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ20) | (((val) & 0x3) << 0)) |
| 1829 | |
| 1830 | /******************************************************************************* |
| 1831 | * DiffServMapping 3 |
| 1832 | ******************************************************************************/ |
| 1833 | |
| 1834 | /* Priority Queue 3F (31:30) */ |
| 1835 | #define LTQ_ES_DFSRV_MAP3_REG_PQ3F (0x3 << 30) |
| 1836 | #define LTQ_ES_DFSRV_MAP3_REG_PQ3F_VAL(val) (((val) & 0x3) << 30) |
| 1837 | #define LTQ_ES_DFSRV_MAP3_REG_PQ3F_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3F) >> 30) & 0x3) |
| 1838 | #define LTQ_ES_DFSRV_MAP3_REG_PQ3F_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3F) | (((val) & 0x3) << 30)) |
| 1839 | /* Priority Queue 3E (29:28) */ |
| 1840 | #define LTQ_ES_DFSRV_MAP3_REG_PQ3E (0x3 << 28) |
| 1841 | #define LTQ_ES_DFSRV_MAP3_REG_PQ3E_VAL(val) (((val) & 0x3) << 28) |
| 1842 | #define LTQ_ES_DFSRV_MAP3_REG_PQ3E_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3E) >> 28) & 0x3) |
| 1843 | #define LTQ_ES_DFSRV_MAP3_REG_PQ3E_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3E) | (((val) & 0x3) << 28)) |
| 1844 | /* Priority Queue 3D (27:26) */ |
| 1845 | #define LTQ_ES_DFSRV_MAP3_REG_PQ3D (0x3 << 26) |
| 1846 | #define LTQ_ES_DFSRV_MAP3_REG_PQ3D_VAL(val) (((val) & 0x3) << 26) |
| 1847 | #define LTQ_ES_DFSRV_MAP3_REG_PQ3D_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3D) >> 26) & 0x3) |
| 1848 | #define LTQ_ES_DFSRV_MAP3_REG_PQ3D_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3D) | (((val) & 0x3) << 26)) |
| 1849 | /* Priority Queue 3C (25:24) */ |
| 1850 | #define LTQ_ES_DFSRV_MAP3_REG_PQ3C (0x3 << 24) |
| 1851 | #define LTQ_ES_DFSRV_MAP3_REG_PQ3C_VAL(val) (((val) & 0x3) << 24) |
| 1852 | #define LTQ_ES_DFSRV_MAP3_REG_PQ3C_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3C) >> 24) & 0x3) |
| 1853 | #define LTQ_ES_DFSRV_MAP3_REG_PQ3C_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3C) | (((val) & 0x3) << 24)) |
| 1854 | /* Priority Queue 3B (23:22) */ |
| 1855 | #define LTQ_ES_DFSRV_MAP3_REG_PQ3B (0x3 << 22) |
| 1856 | #define LTQ_ES_DFSRV_MAP3_REG_PQ3B_VAL(val) (((val) & 0x3) << 22) |
| 1857 | #define LTQ_ES_DFSRV_MAP3_REG_PQ3B_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3B) >> 22) & 0x3) |
| 1858 | #define LTQ_ES_DFSRV_MAP3_REG_PQ3B_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3B) | (((val) & 0x3) << 22)) |
| 1859 | /* Priority Queue 3A (21:20) */ |
| 1860 | #define LTQ_ES_DFSRV_MAP3_REG_PQ3A (0x3 << 20) |
| 1861 | #define LTQ_ES_DFSRV_MAP3_REG_PQ3A_VAL(val) (((val) & 0x3) << 20) |
| 1862 | #define LTQ_ES_DFSRV_MAP3_REG_PQ3A_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3A) >> 20) & 0x3) |
| 1863 | #define LTQ_ES_DFSRV_MAP3_REG_PQ3A_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3A) | (((val) & 0x3) << 20)) |
| 1864 | /* Priority Queue 39 (19:18) */ |
| 1865 | #define LTQ_ES_DFSRV_MAP3_REG_PQ39 (0x3 << 18) |
| 1866 | #define LTQ_ES_DFSRV_MAP3_REG_PQ39_VAL(val) (((val) & 0x3) << 18) |
| 1867 | #define LTQ_ES_DFSRV_MAP3_REG_PQ39_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ39) >> 18) & 0x3) |
| 1868 | #define LTQ_ES_DFSRV_MAP3_REG_PQ39_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ39) | (((val) & 0x3) << 18)) |
| 1869 | /* Priority Queue 38 (17:16) */ |
| 1870 | #define LTQ_ES_DFSRV_MAP3_REG_PQ38 (0x3 << 16) |
| 1871 | #define LTQ_ES_DFSRV_MAP3_REG_PQ38_VAL(val) (((val) & 0x3) << 16) |
| 1872 | #define LTQ_ES_DFSRV_MAP3_REG_PQ38_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ38) >> 16) & 0x3) |
| 1873 | #define LTQ_ES_DFSRV_MAP3_REG_PQ38_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ38) | (((val) & 0x3) << 16)) |
| 1874 | /* Priority Queue 37 (15:14) */ |
| 1875 | #define LTQ_ES_DFSRV_MAP3_REG_PQ37 (0x3 << 14) |
| 1876 | #define LTQ_ES_DFSRV_MAP3_REG_PQ37_VAL(val) (((val) & 0x3) << 14) |
| 1877 | #define LTQ_ES_DFSRV_MAP3_REG_PQ37_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ37) >> 14) & 0x3) |
| 1878 | #define LTQ_ES_DFSRV_MAP3_REG_PQ37_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ37) | (((val) & 0x3) << 14)) |
| 1879 | /* Priority Queue 36 (13:12) */ |
| 1880 | #define LTQ_ES_DFSRV_MAP3_REG_PQ36 (0x3 << 12) |
| 1881 | #define LTQ_ES_DFSRV_MAP3_REG_PQ36_VAL(val) (((val) & 0x3) << 12) |
| 1882 | #define LTQ_ES_DFSRV_MAP3_REG_PQ36_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ36) >> 12) & 0x3) |
| 1883 | #define LTQ_ES_DFSRV_MAP3_REG_PQ36_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ36) | (((val) & 0x3) << 12)) |
| 1884 | /* Priority Queue 35 (11:10) */ |
| 1885 | #define LTQ_ES_DFSRV_MAP3_REG_PQ35 (0x3 << 10) |
| 1886 | #define LTQ_ES_DFSRV_MAP3_REG_PQ35_VAL(val) (((val) & 0x3) << 10) |
| 1887 | #define LTQ_ES_DFSRV_MAP3_REG_PQ35_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ35) >> 10) & 0x3) |
| 1888 | #define LTQ_ES_DFSRV_MAP3_REG_PQ35_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ35) | (((val) & 0x3) << 10)) |
| 1889 | /* Priority Queue 34 (9:8) */ |
| 1890 | #define LTQ_ES_DFSRV_MAP3_REG_PQ34 (0x3 << 8) |
| 1891 | #define LTQ_ES_DFSRV_MAP3_REG_PQ34_VAL(val) (((val) & 0x3) << 8) |
| 1892 | #define LTQ_ES_DFSRV_MAP3_REG_PQ34_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ34) >> 8) & 0x3) |
| 1893 | #define LTQ_ES_DFSRV_MAP3_REG_PQ34_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ34) | (((val) & 0x3) << 8)) |
| 1894 | /* Priority Queue 33 (7:6) */ |
| 1895 | #define LTQ_ES_DFSRV_MAP3_REG_PQ33 (0x3 << 6) |
| 1896 | #define LTQ_ES_DFSRV_MAP3_REG_PQ33_VAL(val) (((val) & 0x3) << 6) |
| 1897 | #define LTQ_ES_DFSRV_MAP3_REG_PQ33_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ33) >> 6) & 0x3) |
| 1898 | #define LTQ_ES_DFSRV_MAP3_REG_PQ33_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ33) | (((val) & 0x3) << 6)) |
| 1899 | /* Priority Queue 32 (5:4) */ |
| 1900 | #define LTQ_ES_DFSRV_MAP3_REG_PQ32 (0x3 << 4) |
| 1901 | #define LTQ_ES_DFSRV_MAP3_REG_PQ32_VAL(val) (((val) & 0x3) << 4) |
| 1902 | #define LTQ_ES_DFSRV_MAP3_REG_PQ32_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ32) >> 4) & 0x3) |
| 1903 | #define LTQ_ES_DFSRV_MAP3_REG_PQ32_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ32) | (((val) & 0x3) << 4)) |
| 1904 | /* Priority Queue 31 (3:2) */ |
| 1905 | #define LTQ_ES_DFSRV_MAP3_REG_PQ31 (0x3 << 2) |
| 1906 | #define LTQ_ES_DFSRV_MAP3_REG_PQ31_VAL(val) (((val) & 0x3) << 2) |
| 1907 | #define LTQ_ES_DFSRV_MAP3_REG_PQ31_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ31) >> 2) & 0x3) |
| 1908 | #define LTQ_ES_DFSRV_MAP3_REG_PQ31_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ31) | (((val) & 0x3) << 2)) |
| 1909 | /* Priority Queue 30 (1:0) */ |
| 1910 | #define LTQ_ES_DFSRV_MAP3_REG_PQ30 (0x3) |
| 1911 | #define LTQ_ES_DFSRV_MAP3_REG_PQ30_VAL(val) (((val) & 0x3) << 0) |
| 1912 | #define LTQ_ES_DFSRV_MAP3_REG_PQ30_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ30) >> 0) & 0x3) |
| 1913 | #define LTQ_ES_DFSRV_MAP3_REG_PQ30_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ30) | (((val) & 0x3) << 0)) |
| 1914 | |
| 1915 | /******************************************************************************* |
| 1916 | * TCP/UDP Port Filter 0 |
| 1917 | ******************************************************************************/ |
| 1918 | |
| 1919 | /* Reserved (31:30) */ |
| 1920 | #define LTQ_ES_TCP_PF0_REG_RES (0x3 << 30) |
| 1921 | #define LTQ_ES_TCP_PF0_REG_RES_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_RES) >> 30) & 0x3) |
| 1922 | /* Action for TCP/UDP Port Filter 0 (29:28) */ |
| 1923 | #define LTQ_ES_TCP_PF0_REG_ATUF0 (0x3 << 28) |
| 1924 | #define LTQ_ES_TCP_PF0_REG_ATUF0_VAL(val) (((val) & 0x3) << 28) |
| 1925 | #define LTQ_ES_TCP_PF0_REG_ATUF0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_ATUF0) >> 28) & 0x3) |
| 1926 | #define LTQ_ES_TCP_PF0_REG_ATUF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_ATUF0) | (((val) & 0x3) << 28)) |
| 1927 | /* TCP/UDP PRI for TCP/UDP Port Filter 0 (27:26) */ |
| 1928 | #define LTQ_ES_TCP_PF0_REG_TUPF0 (0x3 << 26) |
| 1929 | #define LTQ_ES_TCP_PF0_REG_TUPF0_VAL(val) (((val) & 0x3) << 26) |
| 1930 | #define LTQ_ES_TCP_PF0_REG_TUPF0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_TUPF0) >> 26) & 0x3) |
| 1931 | #define LTQ_ES_TCP_PF0_REG_TUPF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_TUPF0) | (((val) & 0x3) << 26)) |
| 1932 | /* Compare TCP/UDP Source Port or Destination Port (25:24) */ |
| 1933 | #define LTQ_ES_TCP_PF0_REG_COMP0 (0x3 << 24) |
| 1934 | #define LTQ_ES_TCP_PF0_REG_COMP0_VAL(val) (((val) & 0x3) << 24) |
| 1935 | #define LTQ_ES_TCP_PF0_REG_COMP0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_COMP0) >> 24) & 0x3) |
| 1936 | #define LTQ_ES_TCP_PF0_REG_COMP0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_COMP0) | (((val) & 0x3) << 24)) |
| 1937 | /* Port Range in TCP/UDP (23:16) */ |
| 1938 | #define LTQ_ES_TCP_PF0_REG_PRANGE0 (0xff << 16) |
| 1939 | #define LTQ_ES_TCP_PF0_REG_PRANGE0_VAL(val) (((val) & 0xff) << 16) |
| 1940 | #define LTQ_ES_TCP_PF0_REG_PRANGE0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_PRANGE0) >> 16) & 0xff) |
| 1941 | #define LTQ_ES_TCP_PF0_REG_PRANGE0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_PRANGE0) | (((val) & 0xff) << 16)) |
| 1942 | /* Base Port number 0 (15:0) */ |
| 1943 | #define LTQ_ES_TCP_PF0_REG_BASEPT0 (0xffff) |
| 1944 | #define LTQ_ES_TCP_PF0_REG_BASEPT0_VAL(val) (((val) & 0xffff) << 0) |
| 1945 | #define LTQ_ES_TCP_PF0_REG_BASEPT0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_BASEPT0) >> 0) & 0xffff) |
| 1946 | #define LTQ_ES_TCP_PF0_REG_BASEPT0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_BASEPT0) | (((val) & 0xffff) << 0)) |
| 1947 | |
| 1948 | /******************************************************************************* |
| 1949 | * Reserved DA(0180C2000003~0180C2000000) control register |
| 1950 | ******************************************************************************/ |
| 1951 | |
| 1952 | /* Valid bit for 0180C2000003 (31) */ |
| 1953 | #define LTQ_ES_RA_03_00_REG_RA03_VALID (0x1 << 31) |
| 1954 | #define LTQ_ES_RA_03_00_REG_RA03_VALID_VAL(val) (((val) & 0x1) << 31) |
| 1955 | #define LTQ_ES_RA_03_00_REG_RA03_VALID_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_VALID) >> 31) & 0x1) |
| 1956 | #define LTQ_ES_RA_03_00_REG_RA03_VALID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_VALID) | (((val) & 0x1) << 31)) |
| 1957 | /* Span bit for 0180C2000003 (30) */ |
| 1958 | #define LTQ_ES_RA_03_00_REG_RA03_SPAN (0x1 << 30) |
| 1959 | #define LTQ_ES_RA_03_00_REG_RA03_SPAN_VAL(val) (((val) & 0x1) << 30) |
| 1960 | #define LTQ_ES_RA_03_00_REG_RA03_SPAN_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_SPAN) >> 30) & 0x1) |
| 1961 | #define LTQ_ES_RA_03_00_REG_RA03_SPAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_SPAN) | (((val) & 0x1) << 30)) |
| 1962 | /* Management bit for 0180C2000003 (29) */ |
| 1963 | #define LTQ_ES_RA_03_00_REG_RA03_MG (0x1 << 29) |
| 1964 | #define LTQ_ES_RA_03_00_REG_RA03_MG_VAL(val) (((val) & 0x1) << 29) |
| 1965 | #define LTQ_ES_RA_03_00_REG_RA03_MG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_MG) >> 29) & 0x1) |
| 1966 | #define LTQ_ES_RA_03_00_REG_RA03_MG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_MG) | (((val) & 0x1) << 29)) |
| 1967 | /* Cross_VLAN bit for 0180C2000003 (28) */ |
| 1968 | #define LTQ_ES_RA_03_00_REG_RA03_CV (0x1 << 28) |
| 1969 | #define LTQ_ES_RA_03_00_REG_RA03_CV_VAL(val) (((val) & 0x1) << 28) |
| 1970 | #define LTQ_ES_RA_03_00_REG_RA03_CV_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_CV) >> 28) & 0x1) |
| 1971 | #define LTQ_ES_RA_03_00_REG_RA03_CV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_CV) | (((val) & 0x1) << 28)) |
| 1972 | /* TXTAG bit for 0180C2000003 (27:26) */ |
| 1973 | #define LTQ_ES_RA_03_00_REG_RA03_TXTAG (0x3 << 26) |
| 1974 | #define LTQ_ES_RA_03_00_REG_RA03_TXTAG_VAL(val) (((val) & 0x3) << 26) |
| 1975 | #define LTQ_ES_RA_03_00_REG_RA03_TXTAG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_TXTAG) >> 26) & 0x3) |
| 1976 | #define LTQ_ES_RA_03_00_REG_RA03_TXTAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_TXTAG) | (((val) & 0x3) << 26)) |
| 1977 | /* Action bit for 0180C2000003 (25:24) */ |
| 1978 | #define LTQ_ES_RA_03_00_REG_RA03_ACT (0x3 << 24) |
| 1979 | #define LTQ_ES_RA_03_00_REG_RA03_ACT_VAL(val) (((val) & 0x3) << 24) |
| 1980 | #define LTQ_ES_RA_03_00_REG_RA03_ACT_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_ACT) >> 24) & 0x3) |
| 1981 | #define LTQ_ES_RA_03_00_REG_RA03_ACT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_ACT) | (((val) & 0x3) << 24)) |
| 1982 | /* Valid bit for 0180C2000002 (23) */ |
| 1983 | #define LTQ_ES_RA_03_00_REG_RA02_VALID (0x1 << 23) |
| 1984 | #define LTQ_ES_RA_03_00_REG_RA02_VALID_VAL(val) (((val) & 0x1) << 23) |
| 1985 | #define LTQ_ES_RA_03_00_REG_RA02_VALID_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_VALID) >> 23) & 0x1) |
| 1986 | #define LTQ_ES_RA_03_00_REG_RA02_VALID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_VALID) | (((val) & 0x1) << 23)) |
| 1987 | /* Span bit for 0180C2000002 (22) */ |
| 1988 | #define LTQ_ES_RA_03_00_REG_RA02_SPAN (0x1 << 22) |
| 1989 | #define LTQ_ES_RA_03_00_REG_RA02_SPAN_VAL(val) (((val) & 0x1) << 22) |
| 1990 | #define LTQ_ES_RA_03_00_REG_RA02_SPAN_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_SPAN) >> 22) & 0x1) |
| 1991 | #define LTQ_ES_RA_03_00_REG_RA02_SPAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_SPAN) | (((val) & 0x1) << 22)) |
| 1992 | /* Management bit for 0180C2000002 (21) */ |
| 1993 | #define LTQ_ES_RA_03_00_REG_RA02_MG (0x1 << 21) |
| 1994 | #define LTQ_ES_RA_03_00_REG_RA02_MG_VAL(val) (((val) & 0x1) << 21) |
| 1995 | #define LTQ_ES_RA_03_00_REG_RA02_MG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_MG) >> 21) & 0x1) |
| 1996 | #define LTQ_ES_RA_03_00_REG_RA02_MG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_MG) | (((val) & 0x1) << 21)) |
| 1997 | /* Cross_VLAN bit for 0180C2000002 (20) */ |
| 1998 | #define LTQ_ES_RA_03_00_REG_RA02_CV (0x1 << 20) |
| 1999 | #define LTQ_ES_RA_03_00_REG_RA02_CV_VAL(val) (((val) & 0x1) << 20) |
| 2000 | #define LTQ_ES_RA_03_00_REG_RA02_CV_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_CV) >> 20) & 0x1) |
| 2001 | #define LTQ_ES_RA_03_00_REG_RA02_CV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_CV) | (((val) & 0x1) << 20)) |
| 2002 | /* TXTAG bit for 0180C2000002 (19:18) */ |
| 2003 | #define LTQ_ES_RA_03_00_REG_RA02_TXTAG (0x3 << 18) |
| 2004 | #define LTQ_ES_RA_03_00_REG_RA02_TXTAG_VAL(val) (((val) & 0x3) << 18) |
| 2005 | #define LTQ_ES_RA_03_00_REG_RA02_TXTAG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_TXTAG) >> 18) & 0x3) |
| 2006 | #define LTQ_ES_RA_03_00_REG_RA02_TXTAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_TXTAG) | (((val) & 0x3) << 18)) |
| 2007 | /* Action bit for 0180C2000002 (17:16) */ |
| 2008 | #define LTQ_ES_RA_03_00_REG_RA02_ACT (0x3 << 16) |
| 2009 | #define LTQ_ES_RA_03_00_REG_RA02_ACT_VAL(val) (((val) & 0x3) << 16) |
| 2010 | #define LTQ_ES_RA_03_00_REG_RA02_ACT_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_ACT) >> 16) & 0x3) |
| 2011 | #define LTQ_ES_RA_03_00_REG_RA02_ACT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_ACT) | (((val) & 0x3) << 16)) |
| 2012 | /* Valid bit for 0180C2000001 (15) */ |
| 2013 | #define LTQ_ES_RA_03_00_REG_RA01_VALID (0x1 << 15) |
| 2014 | #define LTQ_ES_RA_03_00_REG_RA01_VALID_VAL(val) (((val) & 0x1) << 15) |
| 2015 | #define LTQ_ES_RA_03_00_REG_RA01_VALID_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_VALID) >> 15) & 0x1) |
| 2016 | #define LTQ_ES_RA_03_00_REG_RA01_VALID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_VALID) | (((val) & 0x1) << 15)) |
| 2017 | /* Span bit for 0180C2000001 (14) */ |
| 2018 | #define LTQ_ES_RA_03_00_REG_RA01_SPAN (0x1 << 14) |
| 2019 | #define LTQ_ES_RA_03_00_REG_RA01_SPAN_VAL(val) (((val) & 0x1) << 14) |
| 2020 | #define LTQ_ES_RA_03_00_REG_RA01_SPAN_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_SPAN) >> 14) & 0x1) |
| 2021 | #define LTQ_ES_RA_03_00_REG_RA01_SPAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_SPAN) | (((val) & 0x1) << 14)) |
| 2022 | /* Management bit for 0180C2000001 (13) */ |
| 2023 | #define LTQ_ES_RA_03_00_REG_RA01_MG (0x1 << 13) |
| 2024 | #define LTQ_ES_RA_03_00_REG_RA01_MG_VAL(val) (((val) & 0x1) << 13) |
| 2025 | #define LTQ_ES_RA_03_00_REG_RA01_MG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_MG) >> 13) & 0x1) |
| 2026 | #define LTQ_ES_RA_03_00_REG_RA01_MG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_MG) | (((val) & 0x1) << 13)) |
| 2027 | /* Cross_VLAN bit for 0180C2000001 (12) */ |
| 2028 | #define LTQ_ES_RA_03_00_REG_RA01_CV (0x1 << 12) |
| 2029 | #define LTQ_ES_RA_03_00_REG_RA01_CV_VAL(val) (((val) & 0x1) << 12) |
| 2030 | #define LTQ_ES_RA_03_00_REG_RA01_CV_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_CV) >> 12) & 0x1) |
| 2031 | #define LTQ_ES_RA_03_00_REG_RA01_CV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_CV) | (((val) & 0x1) << 12)) |
| 2032 | /* TXTAG bit for 0180C2000001 (11:10) */ |
| 2033 | #define LTQ_ES_RA_03_00_REG_RA01_TXTAG (0x3 << 10) |
| 2034 | #define LTQ_ES_RA_03_00_REG_RA01_TXTAG_VAL(val) (((val) & 0x3) << 10) |
| 2035 | #define LTQ_ES_RA_03_00_REG_RA01_TXTAG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_TXTAG) >> 10) & 0x3) |
| 2036 | #define LTQ_ES_RA_03_00_REG_RA01_TXTAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_TXTAG) | (((val) & 0x3) << 10)) |
| 2037 | /* Action bit for 0180C2000001 (9:8) */ |
| 2038 | #define LTQ_ES_RA_03_00_REG_RA01_ACT (0x3 << 8) |
| 2039 | #define LTQ_ES_RA_03_00_REG_RA01_ACT_VAL(val) (((val) & 0x3) << 8) |
| 2040 | #define LTQ_ES_RA_03_00_REG_RA01_ACT_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_ACT) >> 8) & 0x3) |
| 2041 | #define LTQ_ES_RA_03_00_REG_RA01_ACT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_ACT) | (((val) & 0x3) << 8)) |
| 2042 | /* Valid bit for 0180C2000000 (7) */ |
| 2043 | #define LTQ_ES_RA_03_00_REG_RA00_VALID (0x1 << 7) |
| 2044 | #define LTQ_ES_RA_03_00_REG_RA00_VALID_VAL(val) (((val) & 0x1) << 7) |
| 2045 | #define LTQ_ES_RA_03_00_REG_RA00_VALID_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_VALID) >> 7) & 0x1) |
| 2046 | #define LTQ_ES_RA_03_00_REG_RA00_VALID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_VALID) | (((val) & 0x1) << 7)) |
| 2047 | /* Span bit for 0180C2000000 (6) */ |
| 2048 | #define LTQ_ES_RA_03_00_REG_RA00_SPAN (0x1 << 6) |
| 2049 | #define LTQ_ES_RA_03_00_REG_RA00_SPAN_VAL(val) (((val) & 0x1) << 6) |
| 2050 | #define LTQ_ES_RA_03_00_REG_RA00_SPAN_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_SPAN) >> 6) & 0x1) |
| 2051 | #define LTQ_ES_RA_03_00_REG_RA00_SPAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_SPAN) | (((val) & 0x1) << 6)) |
| 2052 | /* Management bit for 0180C2000000 (5) */ |
| 2053 | #define LTQ_ES_RA_03_00_REG_RA00_MG (0x1 << 5) |
| 2054 | #define LTQ_ES_RA_03_00_REG_RA00_MG_VAL(val) (((val) & 0x1) << 5) |
| 2055 | #define LTQ_ES_RA_03_00_REG_RA00_MG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_MG) >> 5) & 0x1) |
| 2056 | #define LTQ_ES_RA_03_00_REG_RA00_MG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_MG) | (((val) & 0x1) << 5)) |
| 2057 | /* Cross_VLAN bit for 0180C2000000 (4) */ |
| 2058 | #define LTQ_ES_RA_03_00_REG_RA00_CV (0x1 << 4) |
| 2059 | #define LTQ_ES_RA_03_00_REG_RA00_CV_VAL(val) (((val) & 0x1) << 4) |
| 2060 | #define LTQ_ES_RA_03_00_REG_RA00_CV_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_CV) >> 4) & 0x1) |
| 2061 | #define LTQ_ES_RA_03_00_REG_RA00_CV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_CV) | (((val) & 0x1) << 4)) |
| 2062 | /* TXTAG bit for 0180C2000000 (3:2) */ |
| 2063 | #define LTQ_ES_RA_03_00_REG_RA00_TXTAG (0x3 << 2) |
| 2064 | #define LTQ_ES_RA_03_00_REG_RA00_TXTAG_VAL(val) (((val) & 0x3) << 2) |
| 2065 | #define LTQ_ES_RA_03_00_REG_RA00_TXTAG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_TXTAG) >> 2) & 0x3) |
| 2066 | #define LTQ_ES_RA_03_00_REG_RA00_TXTAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_TXTAG) | (((val) & 0x3) << 2)) |
| 2067 | /* Action bit for 0180C2000000 (1:0) */ |
| 2068 | #define LTQ_ES_RA_03_00_REG_RA00_ACT (0x3) |
| 2069 | #define LTQ_ES_RA_03_00_REG_RA00_ACT_VAL(val) (((val) & 0x3) << 0) |
| 2070 | #define LTQ_ES_RA_03_00_REG_RA00_ACT_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_ACT) >> 0) & 0x3) |
| 2071 | #define LTQ_ES_RA_03_00_REG_RA00_ACT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_ACT) | (((val) & 0x3) << 0)) |
| 2072 | |
| 2073 | /******************************************************************************* |
| 2074 | * Protocol Filter 0 |
| 2075 | ******************************************************************************/ |
| 2076 | |
| 2077 | /* Value Compared with Protocol in IP Header (31:24) */ |
| 2078 | #define LTQ_ES_PRTCL_F0_REG_PFR3 (0xff << 24) |
| 2079 | #define LTQ_ES_PRTCL_F0_REG_PFR3_VAL(val) (((val) & 0xff) << 24) |
| 2080 | #define LTQ_ES_PRTCL_F0_REG_PFR3_GET(val) ((((val) & LTQ_ES_PRTCL_F0_REG_PFR3) >> 24) & 0xff) |
| 2081 | #define LTQ_ES_PRTCL_F0_REG_PFR3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_F0_REG_PFR3) | (((val) & 0xff) << 24)) |
| 2082 | /* Value Compared with Protocol in IP Header (23:16) */ |
| 2083 | #define LTQ_ES_PRTCL_F0_REG_PFR2 (0xff << 16) |
| 2084 | #define LTQ_ES_PRTCL_F0_REG_PFR2_VAL(val) (((val) & 0xff) << 16) |
| 2085 | #define LTQ_ES_PRTCL_F0_REG_PFR2_GET(val) ((((val) & LTQ_ES_PRTCL_F0_REG_PFR2) >> 16) & 0xff) |
| 2086 | #define LTQ_ES_PRTCL_F0_REG_PFR2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_F0_REG_PFR2) | (((val) & 0xff) << 16)) |
| 2087 | /* Value Compared with Protocol in IP Header (15:8) */ |
| 2088 | #define LTQ_ES_PRTCL_F0_REG_PFR1 (0xff << 8) |
| 2089 | #define LTQ_ES_PRTCL_F0_REG_PFR1_VAL(val) (((val) & 0xff) << 8) |
| 2090 | #define LTQ_ES_PRTCL_F0_REG_PFR1_GET(val) ((((val) & LTQ_ES_PRTCL_F0_REG_PFR1) >> 8) & 0xff) |
| 2091 | #define LTQ_ES_PRTCL_F0_REG_PFR1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_F0_REG_PFR1) | (((val) & 0xff) << 8)) |
| 2092 | /* Value Compared with Protocol in IP Header (7:0) */ |
| 2093 | #define LTQ_ES_PRTCL_F0_REG_PFR0 (0xff) |
| 2094 | #define LTQ_ES_PRTCL_F0_REG_PFR0_VAL(val) (((val) & 0xff) << 0) |
| 2095 | #define LTQ_ES_PRTCL_F0_REG_PFR0_GET(val) ((((val) & LTQ_ES_PRTCL_F0_REG_PFR0) >> 0) & 0xff) |
| 2096 | #define LTQ_ES_PRTCL_F0_REG_PFR0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_F0_REG_PFR0) | (((val) & 0xff) << 0)) |
| 2097 | |
| 2098 | #endif |
| 2099 | |
