| 1 | /****************************************************************************** |
| 2 | |
| 3 | Copyright (c) 2007 |
| 4 | Infineon Technologies AG |
| 5 | St. Martin Strasse 53; 81669 Munich, Germany |
| 6 | |
| 7 | Any use of this Software is subject to the conclusion of a respective |
| 8 | License Agreement. Without such a License Agreement no rights to the |
| 9 | Software are granted. |
| 10 | |
| 11 | ******************************************************************************/ |
| 12 | |
| 13 | #ifndef __MPS_REG_H |
| 14 | #define __MPS_REG_H |
| 15 | |
| 16 | #define mbs_r32(reg) ltq_r32(&mbs->reg) |
| 17 | #define mbs_w32(val, reg) ltq_w32(val, &mbs->reg) |
| 18 | #define mbs_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &mbs->reg) |
| 19 | |
| 20 | /** MBS register structure */ |
| 21 | struct svip_reg_mbs { |
| 22 | unsigned long reserved0[4]; |
| 23 | unsigned long mbsr0; /* 0x0010 */ |
| 24 | unsigned long mbsr1; /* 0x0014 */ |
| 25 | unsigned long mbsr2; /* 0x0018 */ |
| 26 | unsigned long mbsr3; /* 0x001c */ |
| 27 | unsigned long mbsr4; /* 0x0020 */ |
| 28 | unsigned long mbsr5; /* 0x0024 */ |
| 29 | unsigned long mbsr6; /* 0x0028 */ |
| 30 | unsigned long mbsr7; /* 0x002c */ |
| 31 | unsigned long mbsr8; /* 0x0030 */ |
| 32 | unsigned long mbsr9; /* 0x0034 */ |
| 33 | unsigned long mbsr10; /* 0x0038 */ |
| 34 | unsigned long mbsr11; /* 0x003c */ |
| 35 | unsigned long mbsr12; /* 0x0040 */ |
| 36 | unsigned long mbsr13; /* 0x0044 */ |
| 37 | unsigned long mbsr14; /* 0x0048 */ |
| 38 | unsigned long mbsr15; /* 0x004c */ |
| 39 | unsigned long mbsr16; /* 0x0050 */ |
| 40 | unsigned long mbsr17; /* 0x0054 */ |
| 41 | unsigned long mbsr18; /* 0x0058 */ |
| 42 | unsigned long mbsr19; /* 0x005c */ |
| 43 | unsigned long mbsr20; /* 0x0060 */ |
| 44 | unsigned long mbsr21; /* 0x0064 */ |
| 45 | unsigned long mbsr22; /* 0x0068 */ |
| 46 | unsigned long mbsr23; /* 0x006c */ |
| 47 | unsigned long mbsr24; /* 0x0070 */ |
| 48 | unsigned long mbsr25; /* 0x0074 */ |
| 49 | unsigned long mbsr26; /* 0x0078 */ |
| 50 | unsigned long mbsr27; /* 0x007c */ |
| 51 | unsigned long mbsr28; /* 0x0080 */ |
| 52 | }; |
| 53 | |
| 54 | /** MPS register structure */ |
| 55 | struct svip_reg_mps { |
| 56 | volatile unsigned long mps_swirn0set; /* 0x0000 */ |
| 57 | volatile unsigned long mps_swirn0en; /* 0x0004 */ |
| 58 | volatile unsigned long mps_swirn0cr; /* 0x0008 */ |
| 59 | volatile unsigned long mps_swirn0icr; /* 0x000C */ |
| 60 | volatile unsigned long mps_swirn1set; /* 0x0010 */ |
| 61 | volatile unsigned long mps_swirn1en; /* 0x0014 */ |
| 62 | volatile unsigned long mps_swirn1cr; /* 0x0018 */ |
| 63 | volatile unsigned long mps_swirn1icr; /* 0x001C */ |
| 64 | volatile unsigned long mps_swirn2set; /* 0x0020 */ |
| 65 | volatile unsigned long mps_swirn2en; /* 0x0024 */ |
| 66 | volatile unsigned long mps_swirn2cr; /* 0x0028 */ |
| 67 | volatile unsigned long mps_swirn2icr; /* 0x002C */ |
| 68 | volatile unsigned long mps_swirn3set; /* 0x0030 */ |
| 69 | volatile unsigned long mps_swirn3en; /* 0x0034 */ |
| 70 | volatile unsigned long mps_swirn3cr; /* 0x0038 */ |
| 71 | volatile unsigned long mps_swirn3icr; /* 0x003C */ |
| 72 | volatile unsigned long mps_swirn4set; /* 0x0040 */ |
| 73 | volatile unsigned long mps_swirn4en; /* 0x0044 */ |
| 74 | volatile unsigned long mps_swirn4cr; /* 0x0048 */ |
| 75 | volatile unsigned long mps_swirn4icr; /* 0x004C */ |
| 76 | volatile unsigned long mps_swirn5set; /* 0x0050 */ |
| 77 | volatile unsigned long mps_swirn5en; /* 0x0054 */ |
| 78 | volatile unsigned long mps_swirn5cr; /* 0x0058 */ |
| 79 | volatile unsigned long mps_swirn5icr; /* 0x005C */ |
| 80 | volatile unsigned long mps_swirn6set; /* 0x0060 */ |
| 81 | volatile unsigned long mps_swirn6en; /* 0x0064 */ |
| 82 | volatile unsigned long mps_swirn6cr; /* 0x0068 */ |
| 83 | volatile unsigned long mps_swirn6icr; /* 0x006C */ |
| 84 | volatile unsigned long mps_swirn7set; /* 0x0070 */ |
| 85 | volatile unsigned long mps_swirn7en; /* 0x0074 */ |
| 86 | volatile unsigned long mps_swirn7cr; /* 0x0078 */ |
| 87 | volatile unsigned long mps_swirn7icr; /* 0x007C */ |
| 88 | volatile unsigned long mps_swirn8set; /* 0x0080 */ |
| 89 | volatile unsigned long mps_swirn8en; /* 0x0084 */ |
| 90 | volatile unsigned long mps_swirn8cr; /* 0x0088 */ |
| 91 | volatile unsigned long mps_swirn8icr; /* 0x008C */ |
| 92 | }; |
| 93 | |
| 94 | /* Software Interrupt */ |
| 95 | #define IFX_MPS_SWIRN0SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0000)) |
| 96 | #define IFX_MPS_SWIRN0EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0004)) |
| 97 | #define IFX_MPS_SWIRN0CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0008)) |
| 98 | #define IFX_MPS_SWIRN0ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x000C)) |
| 99 | #define IFX_MPS_SWIRN1SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0010)) |
| 100 | #define IFX_MPS_SWIRN1EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0014)) |
| 101 | #define IFX_MPS_SWIRN1CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0018)) |
| 102 | #define IFX_MPS_SWIRN1ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x001C)) |
| 103 | #define IFX_MPS_SWIRN2SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0020)) |
| 104 | #define IFX_MPS_SWIRN2EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0024)) |
| 105 | #define IFX_MPS_SWIRN2CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0028)) |
| 106 | #define IFX_MPS_SWIRN2ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x002C)) |
| 107 | #define IFX_MPS_SWIRN3SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0030)) |
| 108 | #define IFX_MPS_SWIRN3EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0034)) |
| 109 | #define IFX_MPS_SWIRN3CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0038)) |
| 110 | #define IFX_MPS_SWIRN3ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x003C)) |
| 111 | #define IFX_MPS_SWIRN4SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0040)) |
| 112 | #define IFX_MPS_SWIRN4EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0044)) |
| 113 | #define IFX_MPS_SWIRN4CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0048)) |
| 114 | #define IFX_MPS_SWIRN4ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x004C)) |
| 115 | #define IFX_MPS_SWIRN5SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0050)) |
| 116 | #define IFX_MPS_SWIRN5EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0054)) |
| 117 | #define IFX_MPS_SWIRN5CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0058)) |
| 118 | #define IFX_MPS_SWIRN5ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x005C)) |
| 119 | #define IFX_MPS_SWIRN6SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0060)) |
| 120 | #define IFX_MPS_SWIRN6EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0064)) |
| 121 | #define IFX_MPS_SWIRN6CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0068)) |
| 122 | #define IFX_MPS_SWIRN6ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x006C)) |
| 123 | #define IFX_MPS_SWIRN7SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0070)) |
| 124 | #define IFX_MPS_SWIRN7EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0074)) |
| 125 | #define IFX_MPS_SWIRN7CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0078)) |
| 126 | #define IFX_MPS_SWIRN7ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x007C)) |
| 127 | #define IFX_MPS_SWIRN8SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0080)) |
| 128 | #define IFX_MPS_SWIRN8EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0084)) |
| 129 | #define IFX_MPS_SWIRN8ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x008C)) |
| 130 | #define IFX_MPS_SWIRN8CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0088)) |
| 131 | |
| 132 | /******************************************************************************* |
| 133 | * MPS_SWIRNSET Register |
| 134 | ******************************************************************************/ |
| 135 | |
| 136 | /* Software Interrupt Request IR5 (5) */ |
| 137 | #define IFX_MPS_SWIRNSET_IR5 (0x1 << 5) |
| 138 | #define IFX_MPS_SWIRNSET_IR5_VAL(val) (((val) & 0x1) << 5) |
| 139 | #define IFX_MPS_SWIRNSET_IR5_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR5) | (val) & 1) << 5) |
| 140 | /* Software Interrupt Request IR4 (4) */ |
| 141 | #define IFX_MPS_SWIRNSET_IR4 (0x1 << 4) |
| 142 | #define IFX_MPS_SWIRNSET_IR4_VAL(val) (((val) & 0x1) << 4) |
| 143 | #define IFX_MPS_SWIRNSET_IR4_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR4) | (val) & 1) << 4) |
| 144 | /* Software Interrupt Request IR3 (3) */ |
| 145 | #define IFX_MPS_SWIRNSET_IR3 (0x1 << 3) |
| 146 | #define IFX_MPS_SWIRNSET_IR3_VAL(val) (((val) & 0x1) << 3) |
| 147 | #define IFX_MPS_SWIRNSET_IR3_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR3) | (val) & 1) << 3) |
| 148 | /* Software Interrupt Request IR2 (2) */ |
| 149 | #define IFX_MPS_SWIRNSET_IR2 (0x1 << 2) |
| 150 | #define IFX_MPS_SWIRNSET_IR2_VAL(val) (((val) & 0x1) << 2) |
| 151 | #define IFX_MPS_SWIRNSET_IR2_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR2) | (val) & 1) << 2) |
| 152 | /* Software Interrupt Request IR1 (1) */ |
| 153 | #define IFX_MPS_SWIRNSET_IR1 (0x1 << 1) |
| 154 | #define IFX_MPS_SWIRNSET_IR1_VAL(val) (((val) & 0x1) << 1) |
| 155 | #define IFX_MPS_SWIRNSET_IR1_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR1) | (val) & 1) << 1) |
| 156 | /* Software Interrupt Request IR0 (0) */ |
| 157 | #define IFX_MPS_SWIRNSET_IR0 (0x1) |
| 158 | #define IFX_MPS_SWIRNSET_IR0_VAL(val) (((val) & 0x1) << 0) |
| 159 | #define IFX_MPS_SWIRNSET_IR0_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR0) | (val) & 1) << 0) |
| 160 | |
| 161 | /******************************************************************************* |
| 162 | * MPS_SWIRNEN Register |
| 163 | ******************************************************************************/ |
| 164 | |
| 165 | /* Software Interrupt Request IR5 (5) */ |
| 166 | #define IFX_MPS_SWIRNEN_IR5 (0x1 << 5) |
| 167 | #define IFX_MPS_SWIRNEN_IR5_VAL(val) (((val) & 0x1) << 5) |
| 168 | #define IFX_MPS_SWIRNEN_IR5_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR5) >> 5) & 0x1) |
| 169 | #define IFX_MPS_SWIRNEN_IR5_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR5) | (((val) & 0x1) << 5)) |
| 170 | /* Software Interrupt Request IR4 (4) */ |
| 171 | #define IFX_MPS_SWIRNEN_IR4 (0x1 << 4) |
| 172 | #define IFX_MPS_SWIRNEN_IR4_VAL(val) (((val) & 0x1) << 4) |
| 173 | #define IFX_MPS_SWIRNEN_IR4_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR4) >> 4) & 0x1) |
| 174 | #define IFX_MPS_SWIRNEN_IR4_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR4) | (((val) & 0x1) << 4)) |
| 175 | /* Software Interrupt Request IR3 (3) */ |
| 176 | #define IFX_MPS_SWIRNEN_IR3 (0x1 << 3) |
| 177 | #define IFX_MPS_SWIRNEN_IR3_VAL(val) (((val) & 0x1) << 3) |
| 178 | #define IFX_MPS_SWIRNEN_IR3_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR3) >> 3) & 0x1) |
| 179 | #define IFX_MPS_SWIRNEN_IR3_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR3) | (((val) & 0x1) << 3)) |
| 180 | /* Software Interrupt Request IR2 (2) */ |
| 181 | #define IFX_MPS_SWIRNEN_IR2 (0x1 << 2) |
| 182 | #define IFX_MPS_SWIRNEN_IR2_VAL(val) (((val) & 0x1) << 2) |
| 183 | #define IFX_MPS_SWIRNEN_IR2_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR2) >> 2) & 0x1) |
| 184 | #define IFX_MPS_SWIRNEN_IR2_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR2) | (((val) & 0x1) << 2)) |
| 185 | /* Software Interrupt Request IR1 (1) */ |
| 186 | #define IFX_MPS_SWIRNEN_IR1 (0x1 << 1) |
| 187 | #define IFX_MPS_SWIRNEN_IR1_VAL(val) (((val) & 0x1) << 1) |
| 188 | #define IFX_MPS_SWIRNEN_IR1_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR1) >> 1) & 0x1) |
| 189 | #define IFX_MPS_SWIRNEN_IR1_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR1) | (((val) & 0x1) << 1)) |
| 190 | /* Software Interrupt Request IR0 (0) */ |
| 191 | #define IFX_MPS_SWIRNEN_IR0 (0x1) |
| 192 | #define IFX_MPS_SWIRNEN_IR0_VAL(val) (((val) & 0x1) << 0) |
| 193 | #define IFX_MPS_SWIRNEN_IR0_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR0) >> 0) & 0x1) |
| 194 | #define IFX_MPS_SWIRNEN_IR0_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR0) | (((val) & 0x1) << 0)) |
| 195 | |
| 196 | /******************************************************************************* |
| 197 | * MPS_SWIRNICR Register |
| 198 | ******************************************************************************/ |
| 199 | |
| 200 | /* Software Interrupt Request IR5 (5) */ |
| 201 | #define IFX_MPS_SWIRNICR_IR5 (0x1 << 5) |
| 202 | #define IFX_MPS_SWIRNICR_IR5_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR5) >> 5) & 0x1) |
| 203 | /* Software Interrupt Request IR4 (4) */ |
| 204 | #define IFX_MPS_SWIRNICR_IR4 (0x1 << 4) |
| 205 | #define IFX_MPS_SWIRNICR_IR4_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR4) >> 4) & 0x1) |
| 206 | /* Software Interrupt Request IR3 (3) */ |
| 207 | #define IFX_MPS_SWIRNICR_IR3 (0x1 << 3) |
| 208 | #define IFX_MPS_SWIRNICR_IR3_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR3) >> 3) & 0x1) |
| 209 | /* Software Interrupt Request IR2 (2) */ |
| 210 | #define IFX_MPS_SWIRNICR_IR2 (0x1 << 2) |
| 211 | #define IFX_MPS_SWIRNICR_IR2_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR2) >> 2) & 0x1) |
| 212 | /* Software Interrupt Request IR1 (1) */ |
| 213 | #define IFX_MPS_SWIRNICR_IR1 (0x1 << 1) |
| 214 | #define IFX_MPS_SWIRNICR_IR1_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR1) >> 1) & 0x1) |
| 215 | /* Software Interrupt Request IR0 (0) */ |
| 216 | #define IFX_MPS_SWIRNICR_IR0 (0x1) |
| 217 | #define IFX_MPS_SWIRNICR_IR0_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR0) >> 0) & 0x1) |
| 218 | |
| 219 | /******************************************************************************* |
| 220 | * MPS_SWIRNCR Register |
| 221 | ******************************************************************************/ |
| 222 | |
| 223 | /* Software Interrupt Request IR5 (5) */ |
| 224 | #define IFX_MPS_SWIRNCR_IR5 (0x1 << 5) |
| 225 | #define IFX_MPS_SWIRNCR_IR5_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR5) >> 5) & 0x1) |
| 226 | /* Software Interrupt Request IR4 (4) */ |
| 227 | #define IFX_MPS_SWIRNCR_IR4 (0x1 << 4) |
| 228 | #define IFX_MPS_SWIRNCR_IR4_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR4) >> 4) & 0x1) |
| 229 | /* Software Interrupt Request IR3 (3) */ |
| 230 | #define IFX_MPS_SWIRNCR_IR3 (0x1 << 3) |
| 231 | #define IFX_MPS_SWIRNCR_IR3_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR3) >> 3) & 0x1) |
| 232 | /* Software Interrupt Request IR2 (2) */ |
| 233 | #define IFX_MPS_SWIRNCR_IR2 (0x1 << 2) |
| 234 | #define IFX_MPS_SWIRNCR_IR2_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR2) >> 2) & 0x1) |
| 235 | /* Software Interrupt Request IR1 (1) */ |
| 236 | #define IFX_MPS_SWIRNCR_IR1 (0x1 << 1) |
| 237 | #define IFX_MPS_SWIRNCR_IR1_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR1) >> 1) & 0x1) |
| 238 | /* Software Interrupt Request IR0 (0) */ |
| 239 | #define IFX_MPS_SWIRNCR_IR0 (0x1) |
| 240 | #define IFX_MPS_SWIRNCR_IR0_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR0) >> 0) & 0x1) |
| 241 | |
| 242 | #endif |
| 243 | |
