| 1 | /****************************************************************************** |
| 2 | |
| 3 | Copyright (c) 2007 |
| 4 | Infineon Technologies AG |
| 5 | St. Martin Strasse 53; 81669 Munich, Germany |
| 6 | |
| 7 | Any use of this Software is subject to the conclusion of a respective |
| 8 | License Agreement. Without such a License Agreement no rights to the |
| 9 | Software are granted. |
| 10 | |
| 11 | ******************************************************************************/ |
| 12 | |
| 13 | #ifndef __PORT_REG_H |
| 14 | #define __PORT_REG_H |
| 15 | |
| 16 | #define port_r32(reg) __raw_readl(®) |
| 17 | #define port_w32(val, reg) __raw_writel(val, ®) |
| 18 | |
| 19 | /** PORT register structure */ |
| 20 | struct svip_reg_port { |
| 21 | volatile u32 out; /* 0x0000 */ |
| 22 | volatile u32 in; /* 0x0004 */ |
| 23 | volatile u32 dir; /* 0x0008 */ |
| 24 | volatile u32 altsel0; /* 0x000C */ |
| 25 | volatile u32 altsel1; /* 0x0010 */ |
| 26 | volatile u32 puen; /* 0x0014 */ |
| 27 | volatile u32 exintcr0; /* 0x0018 */ |
| 28 | volatile u32 exintcr1; /* 0x001C */ |
| 29 | volatile u32 irncr; /* 0x0020 */ |
| 30 | volatile u32 irnicr; /* 0x0024 */ |
| 31 | volatile u32 irnen; /* 0x0028 */ |
| 32 | volatile u32 irncfg; /* 0x002C */ |
| 33 | volatile u32 irnenset; /* 0x0030 */ |
| 34 | volatile u32 irnenclr; /* 0x0034 */ |
| 35 | }; |
| 36 | |
| 37 | /******************************************************************************* |
| 38 | * Port 0 Data Output Register |
| 39 | ******************************************************************************/ |
| 40 | |
| 41 | /* Port 0 Pin # Output Value (19) */ |
| 42 | #define PORT_P0_OUT_P19 (0x1 << 19) |
| 43 | #define PORT_P0_OUT_P19_VAL(val) (((val) & 0x1) << 19) |
| 44 | #define PORT_P0_OUT_P19_GET(val) ((((val) & PORT_P0_OUT_P19) >> 19) & 0x1) |
| 45 | #define PORT_P0_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P19) | (((val) & 0x1) << 19)) |
| 46 | /* Port 0 Pin # Output Value (18) */ |
| 47 | #define PORT_P0_OUT_P18 (0x1 << 18) |
| 48 | #define PORT_P0_OUT_P18_VAL(val) (((val) & 0x1) << 18) |
| 49 | #define PORT_P0_OUT_P18_GET(val) ((((val) & PORT_P0_OUT_P18) >> 18) & 0x1) |
| 50 | #define PORT_P0_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P18) | (((val) & 0x1) << 18)) |
| 51 | /* Port 0 Pin # Output Value (17) */ |
| 52 | #define PORT_P0_OUT_P17 (0x1 << 17) |
| 53 | #define PORT_P0_OUT_P17_VAL(val) (((val) & 0x1) << 17) |
| 54 | #define PORT_P0_OUT_P17_GET(val) ((((val) & PORT_P0_OUT_P17) >> 17) & 0x1) |
| 55 | #define PORT_P0_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P17) | (((val) & 0x1) << 17)) |
| 56 | /* Port 0 Pin # Output Value (16) */ |
| 57 | #define PORT_P0_OUT_P16 (0x1 << 16) |
| 58 | #define PORT_P0_OUT_P16_VAL(val) (((val) & 0x1) << 16) |
| 59 | #define PORT_P0_OUT_P16_GET(val) ((((val) & PORT_P0_OUT_P16) >> 16) & 0x1) |
| 60 | #define PORT_P0_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P16) | (((val) & 0x1) << 16)) |
| 61 | /* Port 0 Pin # Output Value (15) */ |
| 62 | #define PORT_P0_OUT_P15 (0x1 << 15) |
| 63 | #define PORT_P0_OUT_P15_VAL(val) (((val) & 0x1) << 15) |
| 64 | #define PORT_P0_OUT_P15_GET(val) ((((val) & PORT_P0_OUT_P15) >> 15) & 0x1) |
| 65 | #define PORT_P0_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P15) | (((val) & 0x1) << 15)) |
| 66 | /* Port 0 Pin # Output Value (14) */ |
| 67 | #define PORT_P0_OUT_P14 (0x1 << 14) |
| 68 | #define PORT_P0_OUT_P14_VAL(val) (((val) & 0x1) << 14) |
| 69 | #define PORT_P0_OUT_P14_GET(val) ((((val) & PORT_P0_OUT_P14) >> 14) & 0x1) |
| 70 | #define PORT_P0_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P14) | (((val) & 0x1) << 14)) |
| 71 | /* Port 0 Pin # Output Value (13) */ |
| 72 | #define PORT_P0_OUT_P13 (0x1 << 13) |
| 73 | #define PORT_P0_OUT_P13_VAL(val) (((val) & 0x1) << 13) |
| 74 | #define PORT_P0_OUT_P13_GET(val) ((((val) & PORT_P0_OUT_P13) >> 13) & 0x1) |
| 75 | #define PORT_P0_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P13) | (((val) & 0x1) << 13)) |
| 76 | /* Port 0 Pin # Output Value (12) */ |
| 77 | #define PORT_P0_OUT_P12 (0x1 << 12) |
| 78 | #define PORT_P0_OUT_P12_VAL(val) (((val) & 0x1) << 12) |
| 79 | #define PORT_P0_OUT_P12_GET(val) ((((val) & PORT_P0_OUT_P12) >> 12) & 0x1) |
| 80 | #define PORT_P0_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P12) | (((val) & 0x1) << 12)) |
| 81 | /* Port 0 Pin # Output Value (11) */ |
| 82 | #define PORT_P0_OUT_P11 (0x1 << 11) |
| 83 | #define PORT_P0_OUT_P11_VAL(val) (((val) & 0x1) << 11) |
| 84 | #define PORT_P0_OUT_P11_GET(val) ((((val) & PORT_P0_OUT_P11) >> 11) & 0x1) |
| 85 | #define PORT_P0_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P11) | (((val) & 0x1) << 11)) |
| 86 | /* Port 0 Pin # Output Value (10) */ |
| 87 | #define PORT_P0_OUT_P10 (0x1 << 10) |
| 88 | #define PORT_P0_OUT_P10_VAL(val) (((val) & 0x1) << 10) |
| 89 | #define PORT_P0_OUT_P10_GET(val) ((((val) & PORT_P0_OUT_P10) >> 10) & 0x1) |
| 90 | #define PORT_P0_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P10) | (((val) & 0x1) << 10)) |
| 91 | /* Port 0 Pin # Output Value (9) */ |
| 92 | #define PORT_P0_OUT_P9 (0x1 << 9) |
| 93 | #define PORT_P0_OUT_P9_VAL(val) (((val) & 0x1) << 9) |
| 94 | #define PORT_P0_OUT_P9_GET(val) ((((val) & PORT_P0_OUT_P9) >> 9) & 0x1) |
| 95 | #define PORT_P0_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P9) | (((val) & 0x1) << 9)) |
| 96 | /* Port 0 Pin # Output Value (8) */ |
| 97 | #define PORT_P0_OUT_P8 (0x1 << 8) |
| 98 | #define PORT_P0_OUT_P8_VAL(val) (((val) & 0x1) << 8) |
| 99 | #define PORT_P0_OUT_P8_GET(val) ((((val) & PORT_P0_OUT_P8) >> 8) & 0x1) |
| 100 | #define PORT_P0_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P8) | (((val) & 0x1) << 8)) |
| 101 | /* Port 0 Pin # Output Value (7) */ |
| 102 | #define PORT_P0_OUT_P7 (0x1 << 7) |
| 103 | #define PORT_P0_OUT_P7_VAL(val) (((val) & 0x1) << 7) |
| 104 | #define PORT_P0_OUT_P7_GET(val) ((((val) & PORT_P0_OUT_P7) >> 7) & 0x1) |
| 105 | #define PORT_P0_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P7) | (((val) & 0x1) << 7)) |
| 106 | /* Port 0 Pin # Output Value (6) */ |
| 107 | #define PORT_P0_OUT_P6 (0x1 << 6) |
| 108 | #define PORT_P0_OUT_P6_VAL(val) (((val) & 0x1) << 6) |
| 109 | #define PORT_P0_OUT_P6_GET(val) ((((val) & PORT_P0_OUT_P6) >> 6) & 0x1) |
| 110 | #define PORT_P0_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P6) | (((val) & 0x1) << 6)) |
| 111 | /* Port 0 Pin # Output Value (5) */ |
| 112 | #define PORT_P0_OUT_P5 (0x1 << 5) |
| 113 | #define PORT_P0_OUT_P5_VAL(val) (((val) & 0x1) << 5) |
| 114 | #define PORT_P0_OUT_P5_GET(val) ((((val) & PORT_P0_OUT_P5) >> 5) & 0x1) |
| 115 | #define PORT_P0_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P5) | (((val) & 0x1) << 5)) |
| 116 | /* Port 0 Pin # Output Value (4) */ |
| 117 | #define PORT_P0_OUT_P4 (0x1 << 4) |
| 118 | #define PORT_P0_OUT_P4_VAL(val) (((val) & 0x1) << 4) |
| 119 | #define PORT_P0_OUT_P4_GET(val) ((((val) & PORT_P0_OUT_P4) >> 4) & 0x1) |
| 120 | #define PORT_P0_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P4) | (((val) & 0x1) << 4)) |
| 121 | /* Port 0 Pin # Output Value (3) */ |
| 122 | #define PORT_P0_OUT_P3 (0x1 << 3) |
| 123 | #define PORT_P0_OUT_P3_VAL(val) (((val) & 0x1) << 3) |
| 124 | #define PORT_P0_OUT_P3_GET(val) ((((val) & PORT_P0_OUT_P3) >> 3) & 0x1) |
| 125 | #define PORT_P0_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P3) | (((val) & 0x1) << 3)) |
| 126 | /* Port 0 Pin # Output Value (2) */ |
| 127 | #define PORT_P0_OUT_P2 (0x1 << 2) |
| 128 | #define PORT_P0_OUT_P2_VAL(val) (((val) & 0x1) << 2) |
| 129 | #define PORT_P0_OUT_P2_GET(val) ((((val) & PORT_P0_OUT_P2) >> 2) & 0x1) |
| 130 | #define PORT_P0_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P2) | (((val) & 0x1) << 2)) |
| 131 | /* Port 0 Pin # Output Value (1) */ |
| 132 | #define PORT_P0_OUT_P1 (0x1 << 1) |
| 133 | #define PORT_P0_OUT_P1_VAL(val) (((val) & 0x1) << 1) |
| 134 | #define PORT_P0_OUT_P1_GET(val) ((((val) & PORT_P0_OUT_P1) >> 1) & 0x1) |
| 135 | #define PORT_P0_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P1) | (((val) & 0x1) << 1)) |
| 136 | /* Port 0 Pin # Output Value (0) */ |
| 137 | #define PORT_P0_OUT_P0 (0x1) |
| 138 | #define PORT_P0_OUT_P0_VAL(val) (((val) & 0x1) << 0) |
| 139 | #define PORT_P0_OUT_P0_GET(val) ((((val) & PORT_P0_OUT_P0) >> 0) & 0x1) |
| 140 | #define PORT_P0_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P0) | (((val) & 0x1) << 0)) |
| 141 | |
| 142 | /******************************************************************************* |
| 143 | * Port 0 Data Input Register |
| 144 | ******************************************************************************/ |
| 145 | |
| 146 | /* Port 0 Pin # Latched Input Value (19) */ |
| 147 | #define PORT_P0_IN_P19 (0x1 << 19) |
| 148 | #define PORT_P0_IN_P19_GET(val) ((((val) & PORT_P0_IN_P19) >> 19) & 0x1) |
| 149 | /* Port 0 Pin # Latched Input Value (18) */ |
| 150 | #define PORT_P0_IN_P18 (0x1 << 18) |
| 151 | #define PORT_P0_IN_P18_GET(val) ((((val) & PORT_P0_IN_P18) >> 18) & 0x1) |
| 152 | /* Port 0 Pin # Latched Input Value (17) */ |
| 153 | #define PORT_P0_IN_P17 (0x1 << 17) |
| 154 | #define PORT_P0_IN_P17_GET(val) ((((val) & PORT_P0_IN_P17) >> 17) & 0x1) |
| 155 | /* Port 0 Pin # Latched Input Value (16) */ |
| 156 | #define PORT_P0_IN_P16 (0x1 << 16) |
| 157 | #define PORT_P0_IN_P16_GET(val) ((((val) & PORT_P0_IN_P16) >> 16) & 0x1) |
| 158 | /* Port 0 Pin # Latched Input Value (15) */ |
| 159 | #define PORT_P0_IN_P15 (0x1 << 15) |
| 160 | #define PORT_P0_IN_P15_GET(val) ((((val) & PORT_P0_IN_P15) >> 15) & 0x1) |
| 161 | /* Port 0 Pin # Latched Input Value (14) */ |
| 162 | #define PORT_P0_IN_P14 (0x1 << 14) |
| 163 | #define PORT_P0_IN_P14_GET(val) ((((val) & PORT_P0_IN_P14) >> 14) & 0x1) |
| 164 | /* Port 0 Pin # Latched Input Value (13) */ |
| 165 | #define PORT_P0_IN_P13 (0x1 << 13) |
| 166 | #define PORT_P0_IN_P13_GET(val) ((((val) & PORT_P0_IN_P13) >> 13) & 0x1) |
| 167 | /* Port 0 Pin # Latched Input Value (12) */ |
| 168 | #define PORT_P0_IN_P12 (0x1 << 12) |
| 169 | #define PORT_P0_IN_P12_GET(val) ((((val) & PORT_P0_IN_P12) >> 12) & 0x1) |
| 170 | /* Port 0 Pin # Latched Input Value (11) */ |
| 171 | #define PORT_P0_IN_P11 (0x1 << 11) |
| 172 | #define PORT_P0_IN_P11_GET(val) ((((val) & PORT_P0_IN_P11) >> 11) & 0x1) |
| 173 | /* Port 0 Pin # Latched Input Value (10) */ |
| 174 | #define PORT_P0_IN_P10 (0x1 << 10) |
| 175 | #define PORT_P0_IN_P10_GET(val) ((((val) & PORT_P0_IN_P10) >> 10) & 0x1) |
| 176 | /* Port 0 Pin # Latched Input Value (9) */ |
| 177 | #define PORT_P0_IN_P9 (0x1 << 9) |
| 178 | #define PORT_P0_IN_P9_GET(val) ((((val) & PORT_P0_IN_P9) >> 9) & 0x1) |
| 179 | /* Port 0 Pin # Latched Input Value (8) */ |
| 180 | #define PORT_P0_IN_P8 (0x1 << 8) |
| 181 | #define PORT_P0_IN_P8_GET(val) ((((val) & PORT_P0_IN_P8) >> 8) & 0x1) |
| 182 | /* Port 0 Pin # Latched Input Value (7) */ |
| 183 | #define PORT_P0_IN_P7 (0x1 << 7) |
| 184 | #define PORT_P0_IN_P7_GET(val) ((((val) & PORT_P0_IN_P7) >> 7) & 0x1) |
| 185 | /* Port 0 Pin # Latched Input Value (6) */ |
| 186 | #define PORT_P0_IN_P6 (0x1 << 6) |
| 187 | #define PORT_P0_IN_P6_GET(val) ((((val) & PORT_P0_IN_P6) >> 6) & 0x1) |
| 188 | /* Port 0 Pin # Latched Input Value (5) */ |
| 189 | #define PORT_P0_IN_P5 (0x1 << 5) |
| 190 | #define PORT_P0_IN_P5_GET(val) ((((val) & PORT_P0_IN_P5) >> 5) & 0x1) |
| 191 | /* Port 0 Pin # Latched Input Value (4) */ |
| 192 | #define PORT_P0_IN_P4 (0x1 << 4) |
| 193 | #define PORT_P0_IN_P4_GET(val) ((((val) & PORT_P0_IN_P4) >> 4) & 0x1) |
| 194 | /* Port 0 Pin # Latched Input Value (3) */ |
| 195 | #define PORT_P0_IN_P3 (0x1 << 3) |
| 196 | #define PORT_P0_IN_P3_GET(val) ((((val) & PORT_P0_IN_P3) >> 3) & 0x1) |
| 197 | /* Port 0 Pin # Latched Input Value (2) */ |
| 198 | #define PORT_P0_IN_P2 (0x1 << 2) |
| 199 | #define PORT_P0_IN_P2_GET(val) ((((val) & PORT_P0_IN_P2) >> 2) & 0x1) |
| 200 | /* Port 0 Pin # Latched Input Value (1) */ |
| 201 | #define PORT_P0_IN_P1 (0x1 << 1) |
| 202 | #define PORT_P0_IN_P1_GET(val) ((((val) & PORT_P0_IN_P1) >> 1) & 0x1) |
| 203 | /* Port 0 Pin # Latched Input Value (0) */ |
| 204 | #define PORT_P0_IN_P0 (0x1) |
| 205 | #define PORT_P0_IN_P0_GET(val) ((((val) & PORT_P0_IN_P0) >> 0) & 0x1) |
| 206 | |
| 207 | /******************************************************************************* |
| 208 | * Port 0 Direction Register |
| 209 | ******************************************************************************/ |
| 210 | |
| 211 | /* Port 0 Pin #Direction Control (19) */ |
| 212 | #define PORT_P0_DIR_P19 (0x1 << 19) |
| 213 | #define PORT_P0_DIR_P19_VAL(val) (((val) & 0x1) << 19) |
| 214 | #define PORT_P0_DIR_P19_GET(val) ((((val) & PORT_P0_DIR_P19) >> 19) & 0x1) |
| 215 | #define PORT_P0_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P19) | (((val) & 0x1) << 19)) |
| 216 | /* Port 0 Pin #Direction Control (18) */ |
| 217 | #define PORT_P0_DIR_P18 (0x1 << 18) |
| 218 | #define PORT_P0_DIR_P18_VAL(val) (((val) & 0x1) << 18) |
| 219 | #define PORT_P0_DIR_P18_GET(val) ((((val) & PORT_P0_DIR_P18) >> 18) & 0x1) |
| 220 | #define PORT_P0_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P18) | (((val) & 0x1) << 18)) |
| 221 | /* Port 0 Pin #Direction Control (17) */ |
| 222 | #define PORT_P0_DIR_P17 (0x1 << 17) |
| 223 | #define PORT_P0_DIR_P17_VAL(val) (((val) & 0x1) << 17) |
| 224 | #define PORT_P0_DIR_P17_GET(val) ((((val) & PORT_P0_DIR_P17) >> 17) & 0x1) |
| 225 | #define PORT_P0_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P17) | (((val) & 0x1) << 17)) |
| 226 | /* Port 0 Pin #Direction Control (16) */ |
| 227 | #define PORT_P0_DIR_P16 (0x1 << 16) |
| 228 | #define PORT_P0_DIR_P16_VAL(val) (((val) & 0x1) << 16) |
| 229 | #define PORT_P0_DIR_P16_GET(val) ((((val) & PORT_P0_DIR_P16) >> 16) & 0x1) |
| 230 | #define PORT_P0_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P16) | (((val) & 0x1) << 16)) |
| 231 | /* Port 0 Pin #Direction Control (15) */ |
| 232 | #define PORT_P0_DIR_P15 (0x1 << 15) |
| 233 | #define PORT_P0_DIR_P15_VAL(val) (((val) & 0x1) << 15) |
| 234 | #define PORT_P0_DIR_P15_GET(val) ((((val) & PORT_P0_DIR_P15) >> 15) & 0x1) |
| 235 | #define PORT_P0_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P15) | (((val) & 0x1) << 15)) |
| 236 | /* Port 0 Pin #Direction Control (14) */ |
| 237 | #define PORT_P0_DIR_P14 (0x1 << 14) |
| 238 | #define PORT_P0_DIR_P14_VAL(val) (((val) & 0x1) << 14) |
| 239 | #define PORT_P0_DIR_P14_GET(val) ((((val) & PORT_P0_DIR_P14) >> 14) & 0x1) |
| 240 | #define PORT_P0_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P14) | (((val) & 0x1) << 14)) |
| 241 | /* Port 0 Pin #Direction Control (13) */ |
| 242 | #define PORT_P0_DIR_P13 (0x1 << 13) |
| 243 | #define PORT_P0_DIR_P13_VAL(val) (((val) & 0x1) << 13) |
| 244 | #define PORT_P0_DIR_P13_GET(val) ((((val) & PORT_P0_DIR_P13) >> 13) & 0x1) |
| 245 | #define PORT_P0_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P13) | (((val) & 0x1) << 13)) |
| 246 | /* Port 0 Pin #Direction Control (12) */ |
| 247 | #define PORT_P0_DIR_P12 (0x1 << 12) |
| 248 | #define PORT_P0_DIR_P12_VAL(val) (((val) & 0x1) << 12) |
| 249 | #define PORT_P0_DIR_P12_GET(val) ((((val) & PORT_P0_DIR_P12) >> 12) & 0x1) |
| 250 | #define PORT_P0_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P12) | (((val) & 0x1) << 12)) |
| 251 | /* Port 0 Pin #Direction Control (11) */ |
| 252 | #define PORT_P0_DIR_P11 (0x1 << 11) |
| 253 | #define PORT_P0_DIR_P11_VAL(val) (((val) & 0x1) << 11) |
| 254 | #define PORT_P0_DIR_P11_GET(val) ((((val) & PORT_P0_DIR_P11) >> 11) & 0x1) |
| 255 | #define PORT_P0_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P11) | (((val) & 0x1) << 11)) |
| 256 | /* Port 0 Pin #Direction Control (10) */ |
| 257 | #define PORT_P0_DIR_P10 (0x1 << 10) |
| 258 | #define PORT_P0_DIR_P10_VAL(val) (((val) & 0x1) << 10) |
| 259 | #define PORT_P0_DIR_P10_GET(val) ((((val) & PORT_P0_DIR_P10) >> 10) & 0x1) |
| 260 | #define PORT_P0_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P10) | (((val) & 0x1) << 10)) |
| 261 | /* Port 0 Pin #Direction Control (9) */ |
| 262 | #define PORT_P0_DIR_P9 (0x1 << 9) |
| 263 | #define PORT_P0_DIR_P9_VAL(val) (((val) & 0x1) << 9) |
| 264 | #define PORT_P0_DIR_P9_GET(val) ((((val) & PORT_P0_DIR_P9) >> 9) & 0x1) |
| 265 | #define PORT_P0_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P9) | (((val) & 0x1) << 9)) |
| 266 | /* Port 0 Pin #Direction Control (8) */ |
| 267 | #define PORT_P0_DIR_P8 (0x1 << 8) |
| 268 | #define PORT_P0_DIR_P8_VAL(val) (((val) & 0x1) << 8) |
| 269 | #define PORT_P0_DIR_P8_GET(val) ((((val) & PORT_P0_DIR_P8) >> 8) & 0x1) |
| 270 | #define PORT_P0_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P8) | (((val) & 0x1) << 8)) |
| 271 | /* Port 0 Pin #Direction Control (7) */ |
| 272 | #define PORT_P0_DIR_P7 (0x1 << 7) |
| 273 | #define PORT_P0_DIR_P7_VAL(val) (((val) & 0x1) << 7) |
| 274 | #define PORT_P0_DIR_P7_GET(val) ((((val) & PORT_P0_DIR_P7) >> 7) & 0x1) |
| 275 | #define PORT_P0_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P7) | (((val) & 0x1) << 7)) |
| 276 | /* Port 0 Pin #Direction Control (6) */ |
| 277 | #define PORT_P0_DIR_P6 (0x1 << 6) |
| 278 | #define PORT_P0_DIR_P6_VAL(val) (((val) & 0x1) << 6) |
| 279 | #define PORT_P0_DIR_P6_GET(val) ((((val) & PORT_P0_DIR_P6) >> 6) & 0x1) |
| 280 | #define PORT_P0_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P6) | (((val) & 0x1) << 6)) |
| 281 | /* Port 0 Pin #Direction Control (5) */ |
| 282 | #define PORT_P0_DIR_P5 (0x1 << 5) |
| 283 | #define PORT_P0_DIR_P5_VAL(val) (((val) & 0x1) << 5) |
| 284 | #define PORT_P0_DIR_P5_GET(val) ((((val) & PORT_P0_DIR_P5) >> 5) & 0x1) |
| 285 | #define PORT_P0_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P5) | (((val) & 0x1) << 5)) |
| 286 | /* Port 0 Pin #Direction Control (4) */ |
| 287 | #define PORT_P0_DIR_P4 (0x1 << 4) |
| 288 | #define PORT_P0_DIR_P4_VAL(val) (((val) & 0x1) << 4) |
| 289 | #define PORT_P0_DIR_P4_GET(val) ((((val) & PORT_P0_DIR_P4) >> 4) & 0x1) |
| 290 | #define PORT_P0_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P4) | (((val) & 0x1) << 4)) |
| 291 | /* Port 0 Pin #Direction Control (3) */ |
| 292 | #define PORT_P0_DIR_P3 (0x1 << 3) |
| 293 | #define PORT_P0_DIR_P3_VAL(val) (((val) & 0x1) << 3) |
| 294 | #define PORT_P0_DIR_P3_GET(val) ((((val) & PORT_P0_DIR_P3) >> 3) & 0x1) |
| 295 | #define PORT_P0_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P3) | (((val) & 0x1) << 3)) |
| 296 | /* Port 0 Pin #Direction Control (2) */ |
| 297 | #define PORT_P0_DIR_P2 (0x1 << 2) |
| 298 | #define PORT_P0_DIR_P2_VAL(val) (((val) & 0x1) << 2) |
| 299 | #define PORT_P0_DIR_P2_GET(val) ((((val) & PORT_P0_DIR_P2) >> 2) & 0x1) |
| 300 | #define PORT_P0_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P2) | (((val) & 0x1) << 2)) |
| 301 | /* Port 0 Pin #Direction Control (1) */ |
| 302 | #define PORT_P0_DIR_P1 (0x1 << 1) |
| 303 | #define PORT_P0_DIR_P1_VAL(val) (((val) & 0x1) << 1) |
| 304 | #define PORT_P0_DIR_P1_GET(val) ((((val) & PORT_P0_DIR_P1) >> 1) & 0x1) |
| 305 | #define PORT_P0_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P1) | (((val) & 0x1) << 1)) |
| 306 | /* Port 0 Pin #Direction Control (0) */ |
| 307 | #define PORT_P0_DIR_P0 (0x1) |
| 308 | #define PORT_P0_DIR_P0_VAL(val) (((val) & 0x1) << 0) |
| 309 | #define PORT_P0_DIR_P0_GET(val) ((((val) & PORT_P0_DIR_P0) >> 0) & 0x1) |
| 310 | #define PORT_P0_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P0) | (((val) & 0x1) << 0)) |
| 311 | |
| 312 | /******************************************************************************* |
| 313 | * Port 0 Alternate Function Select Register 0 |
| 314 | ******************************************************************************/ |
| 315 | |
| 316 | /* Alternate Function at Port 0 Bit # (19) */ |
| 317 | #define PORT_P0_ALTSEL0_P19 (0x1 << 19) |
| 318 | #define PORT_P0_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) |
| 319 | #define PORT_P0_ALTSEL0_P19_GET(val) ((((val) & PORT_P0_ALTSEL0_P19) >> 19) & 0x1) |
| 320 | #define PORT_P0_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P19) | (((val) & 0x1) << 19)) |
| 321 | /* Alternate Function at Port 0 Bit # (18) */ |
| 322 | #define PORT_P0_ALTSEL0_P18 (0x1 << 18) |
| 323 | #define PORT_P0_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) |
| 324 | #define PORT_P0_ALTSEL0_P18_GET(val) ((((val) & PORT_P0_ALTSEL0_P18) >> 18) & 0x1) |
| 325 | #define PORT_P0_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P18) | (((val) & 0x1) << 18)) |
| 326 | /* Alternate Function at Port 0 Bit # (17) */ |
| 327 | #define PORT_P0_ALTSEL0_P17 (0x1 << 17) |
| 328 | #define PORT_P0_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) |
| 329 | #define PORT_P0_ALTSEL0_P17_GET(val) ((((val) & PORT_P0_ALTSEL0_P17) >> 17) & 0x1) |
| 330 | #define PORT_P0_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P17) | (((val) & 0x1) << 17)) |
| 331 | /* Alternate Function at Port 0 Bit # (16) */ |
| 332 | #define PORT_P0_ALTSEL0_P16 (0x1 << 16) |
| 333 | #define PORT_P0_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) |
| 334 | #define PORT_P0_ALTSEL0_P16_GET(val) ((((val) & PORT_P0_ALTSEL0_P16) >> 16) & 0x1) |
| 335 | #define PORT_P0_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P16) | (((val) & 0x1) << 16)) |
| 336 | /* Alternate Function at Port 0 Bit # (15) */ |
| 337 | #define PORT_P0_ALTSEL0_P15 (0x1 << 15) |
| 338 | #define PORT_P0_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) |
| 339 | #define PORT_P0_ALTSEL0_P15_GET(val) ((((val) & PORT_P0_ALTSEL0_P15) >> 15) & 0x1) |
| 340 | #define PORT_P0_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P15) | (((val) & 0x1) << 15)) |
| 341 | /* Alternate Function at Port 0 Bit # (14) */ |
| 342 | #define PORT_P0_ALTSEL0_P14 (0x1 << 14) |
| 343 | #define PORT_P0_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) |
| 344 | #define PORT_P0_ALTSEL0_P14_GET(val) ((((val) & PORT_P0_ALTSEL0_P14) >> 14) & 0x1) |
| 345 | #define PORT_P0_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P14) | (((val) & 0x1) << 14)) |
| 346 | /* Alternate Function at Port 0 Bit # (13) */ |
| 347 | #define PORT_P0_ALTSEL0_P13 (0x1 << 13) |
| 348 | #define PORT_P0_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) |
| 349 | #define PORT_P0_ALTSEL0_P13_GET(val) ((((val) & PORT_P0_ALTSEL0_P13) >> 13) & 0x1) |
| 350 | #define PORT_P0_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P13) | (((val) & 0x1) << 13)) |
| 351 | /* Alternate Function at Port 0 Bit # (12) */ |
| 352 | #define PORT_P0_ALTSEL0_P12 (0x1 << 12) |
| 353 | #define PORT_P0_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) |
| 354 | #define PORT_P0_ALTSEL0_P12_GET(val) ((((val) & PORT_P0_ALTSEL0_P12) >> 12) & 0x1) |
| 355 | #define PORT_P0_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P12) | (((val) & 0x1) << 12)) |
| 356 | /* Alternate Function at Port 0 Bit # (11) */ |
| 357 | #define PORT_P0_ALTSEL0_P11 (0x1 << 11) |
| 358 | #define PORT_P0_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) |
| 359 | #define PORT_P0_ALTSEL0_P11_GET(val) ((((val) & PORT_P0_ALTSEL0_P11) >> 11) & 0x1) |
| 360 | #define PORT_P0_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P11) | (((val) & 0x1) << 11)) |
| 361 | /* Alternate Function at Port 0 Bit # (10) */ |
| 362 | #define PORT_P0_ALTSEL0_P10 (0x1 << 10) |
| 363 | #define PORT_P0_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) |
| 364 | #define PORT_P0_ALTSEL0_P10_GET(val) ((((val) & PORT_P0_ALTSEL0_P10) >> 10) & 0x1) |
| 365 | #define PORT_P0_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P10) | (((val) & 0x1) << 10)) |
| 366 | /* Alternate Function at Port 0 Bit # (9) */ |
| 367 | #define PORT_P0_ALTSEL0_P9 (0x1 << 9) |
| 368 | #define PORT_P0_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) |
| 369 | #define PORT_P0_ALTSEL0_P9_GET(val) ((((val) & PORT_P0_ALTSEL0_P9) >> 9) & 0x1) |
| 370 | #define PORT_P0_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P9) | (((val) & 0x1) << 9)) |
| 371 | /* Alternate Function at Port 0 Bit # (8) */ |
| 372 | #define PORT_P0_ALTSEL0_P8 (0x1 << 8) |
| 373 | #define PORT_P0_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) |
| 374 | #define PORT_P0_ALTSEL0_P8_GET(val) ((((val) & PORT_P0_ALTSEL0_P8) >> 8) & 0x1) |
| 375 | #define PORT_P0_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P8) | (((val) & 0x1) << 8)) |
| 376 | /* Alternate Function at Port 0 Bit # (7) */ |
| 377 | #define PORT_P0_ALTSEL0_P7 (0x1 << 7) |
| 378 | #define PORT_P0_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) |
| 379 | #define PORT_P0_ALTSEL0_P7_GET(val) ((((val) & PORT_P0_ALTSEL0_P7) >> 7) & 0x1) |
| 380 | #define PORT_P0_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P7) | (((val) & 0x1) << 7)) |
| 381 | /* Alternate Function at Port 0 Bit # (6) */ |
| 382 | #define PORT_P0_ALTSEL0_P6 (0x1 << 6) |
| 383 | #define PORT_P0_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) |
| 384 | #define PORT_P0_ALTSEL0_P6_GET(val) ((((val) & PORT_P0_ALTSEL0_P6) >> 6) & 0x1) |
| 385 | #define PORT_P0_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P6) | (((val) & 0x1) << 6)) |
| 386 | /* Alternate Function at Port 0 Bit # (5) */ |
| 387 | #define PORT_P0_ALTSEL0_P5 (0x1 << 5) |
| 388 | #define PORT_P0_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) |
| 389 | #define PORT_P0_ALTSEL0_P5_GET(val) ((((val) & PORT_P0_ALTSEL0_P5) >> 5) & 0x1) |
| 390 | #define PORT_P0_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P5) | (((val) & 0x1) << 5)) |
| 391 | /* Alternate Function at Port 0 Bit # (4) */ |
| 392 | #define PORT_P0_ALTSEL0_P4 (0x1 << 4) |
| 393 | #define PORT_P0_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) |
| 394 | #define PORT_P0_ALTSEL0_P4_GET(val) ((((val) & PORT_P0_ALTSEL0_P4) >> 4) & 0x1) |
| 395 | #define PORT_P0_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P4) | (((val) & 0x1) << 4)) |
| 396 | /* Alternate Function at Port 0 Bit # (3) */ |
| 397 | #define PORT_P0_ALTSEL0_P3 (0x1 << 3) |
| 398 | #define PORT_P0_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) |
| 399 | #define PORT_P0_ALTSEL0_P3_GET(val) ((((val) & PORT_P0_ALTSEL0_P3) >> 3) & 0x1) |
| 400 | #define PORT_P0_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P3) | (((val) & 0x1) << 3)) |
| 401 | /* Alternate Function at Port 0 Bit # (2) */ |
| 402 | #define PORT_P0_ALTSEL0_P2 (0x1 << 2) |
| 403 | #define PORT_P0_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) |
| 404 | #define PORT_P0_ALTSEL0_P2_GET(val) ((((val) & PORT_P0_ALTSEL0_P2) >> 2) & 0x1) |
| 405 | #define PORT_P0_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P2) | (((val) & 0x1) << 2)) |
| 406 | /* Alternate Function at Port 0 Bit # (1) */ |
| 407 | #define PORT_P0_ALTSEL0_P1 (0x1 << 1) |
| 408 | #define PORT_P0_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) |
| 409 | #define PORT_P0_ALTSEL0_P1_GET(val) ((((val) & PORT_P0_ALTSEL0_P1) >> 1) & 0x1) |
| 410 | #define PORT_P0_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P1) | (((val) & 0x1) << 1)) |
| 411 | /* Alternate Function at Port 0 Bit # (0) */ |
| 412 | #define PORT_P0_ALTSEL0_P0 (0x1) |
| 413 | #define PORT_P0_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) |
| 414 | #define PORT_P0_ALTSEL0_P0_GET(val) ((((val) & PORT_P0_ALTSEL0_P0) >> 0) & 0x1) |
| 415 | #define PORT_P0_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P0) | (((val) & 0x1) << 0)) |
| 416 | |
| 417 | /******************************************************************************* |
| 418 | * Port 0 Alternate Function Select Register 1 |
| 419 | ******************************************************************************/ |
| 420 | |
| 421 | /* Alternate Function at Port 0 Bit # (13) */ |
| 422 | #define PORT_P0_ALTSEL1_P13 (0x1 << 13) |
| 423 | #define PORT_P0_ALTSEL1_P13_VAL(val) (((val) & 0x1) << 13) |
| 424 | #define PORT_P0_ALTSEL1_P13_GET(val) ((((val) & PORT_P0_ALTSEL1_P13) >> 13) & 0x1) |
| 425 | #define PORT_P0_ALTSEL1_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P13) | (((val) & 0x1) << 13)) |
| 426 | /* Alternate Function at Port 0 Bit # (12) */ |
| 427 | #define PORT_P0_ALTSEL1_P12 (0x1 << 12) |
| 428 | #define PORT_P0_ALTSEL1_P12_VAL(val) (((val) & 0x1) << 12) |
| 429 | #define PORT_P0_ALTSEL1_P12_GET(val) ((((val) & PORT_P0_ALTSEL1_P12) >> 12) & 0x1) |
| 430 | #define PORT_P0_ALTSEL1_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P12) | (((val) & 0x1) << 12)) |
| 431 | /* Alternate Function at Port 0 Bit # (11) */ |
| 432 | #define PORT_P0_ALTSEL1_P11 (0x1 << 11) |
| 433 | #define PORT_P0_ALTSEL1_P11_VAL(val) (((val) & 0x1) << 11) |
| 434 | #define PORT_P0_ALTSEL1_P11_GET(val) ((((val) & PORT_P0_ALTSEL1_P11) >> 11) & 0x1) |
| 435 | #define PORT_P0_ALTSEL1_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P11) | (((val) & 0x1) << 11)) |
| 436 | /* Alternate Function at Port 0 Bit # (10) */ |
| 437 | #define PORT_P0_ALTSEL1_P10 (0x1 << 10) |
| 438 | #define PORT_P0_ALTSEL1_P10_VAL(val) (((val) & 0x1) << 10) |
| 439 | #define PORT_P0_ALTSEL1_P10_GET(val) ((((val) & PORT_P0_ALTSEL1_P10) >> 10) & 0x1) |
| 440 | #define PORT_P0_ALTSEL1_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P10) | (((val) & 0x1) << 10)) |
| 441 | /* Alternate Function at Port 0 Bit # (9) */ |
| 442 | #define PORT_P0_ALTSEL1_P9 (0x1 << 9) |
| 443 | #define PORT_P0_ALTSEL1_P9_VAL(val) (((val) & 0x1) << 9) |
| 444 | #define PORT_P0_ALTSEL1_P9_GET(val) ((((val) & PORT_P0_ALTSEL1_P9) >> 9) & 0x1) |
| 445 | #define PORT_P0_ALTSEL1_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P9) | (((val) & 0x1) << 9)) |
| 446 | /* Alternate Function at Port 0 Bit # (8) */ |
| 447 | #define PORT_P0_ALTSEL1_P8 (0x1 << 8) |
| 448 | #define PORT_P0_ALTSEL1_P8_VAL(val) (((val) & 0x1) << 8) |
| 449 | #define PORT_P0_ALTSEL1_P8_GET(val) ((((val) & PORT_P0_ALTSEL1_P8) >> 8) & 0x1) |
| 450 | #define PORT_P0_ALTSEL1_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P8) | (((val) & 0x1) << 8)) |
| 451 | /* Alternate Function at Port 0 Bit # (7) */ |
| 452 | #define PORT_P0_ALTSEL1_P7 (0x1 << 7) |
| 453 | #define PORT_P0_ALTSEL1_P7_VAL(val) (((val) & 0x1) << 7) |
| 454 | #define PORT_P0_ALTSEL1_P7_GET(val) ((((val) & PORT_P0_ALTSEL1_P7) >> 7) & 0x1) |
| 455 | #define PORT_P0_ALTSEL1_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P7) | (((val) & 0x1) << 7)) |
| 456 | /* Alternate Function at Port 0 Bit # (6) */ |
| 457 | #define PORT_P0_ALTSEL1_P6 (0x1 << 6) |
| 458 | #define PORT_P0_ALTSEL1_P6_VAL(val) (((val) & 0x1) << 6) |
| 459 | #define PORT_P0_ALTSEL1_P6_GET(val) ((((val) & PORT_P0_ALTSEL1_P6) >> 6) & 0x1) |
| 460 | #define PORT_P0_ALTSEL1_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P6) | (((val) & 0x1) << 6)) |
| 461 | /* Alternate Function at Port 0 Bit # (3) */ |
| 462 | #define PORT_P0_ALTSEL1_P3 (0x1 << 3) |
| 463 | #define PORT_P0_ALTSEL1_P3_VAL(val) (((val) & 0x1) << 3) |
| 464 | #define PORT_P0_ALTSEL1_P3_GET(val) ((((val) & PORT_P0_ALTSEL1_P3) >> 3) & 0x1) |
| 465 | #define PORT_P0_ALTSEL1_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P3) | (((val) & 0x1) << 3)) |
| 466 | |
| 467 | /******************************************************************************* |
| 468 | * Port 0 Pull Up Enable Register |
| 469 | ******************************************************************************/ |
| 470 | |
| 471 | /* Pull Up Device Enable at Port 0 Bit # (19) */ |
| 472 | #define PORT_P0_PUEN_P19 (0x1 << 19) |
| 473 | #define PORT_P0_PUEN_P19_VAL(val) (((val) & 0x1) << 19) |
| 474 | #define PORT_P0_PUEN_P19_GET(val) ((((val) & PORT_P0_PUEN_P19) >> 19) & 0x1) |
| 475 | #define PORT_P0_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P19) | (((val) & 0x1) << 19)) |
| 476 | /* Pull Up Device Enable at Port 0 Bit # (18) */ |
| 477 | #define PORT_P0_PUEN_P18 (0x1 << 18) |
| 478 | #define PORT_P0_PUEN_P18_VAL(val) (((val) & 0x1) << 18) |
| 479 | #define PORT_P0_PUEN_P18_GET(val) ((((val) & PORT_P0_PUEN_P18) >> 18) & 0x1) |
| 480 | #define PORT_P0_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P18) | (((val) & 0x1) << 18)) |
| 481 | /* Pull Up Device Enable at Port 0 Bit # (17) */ |
| 482 | #define PORT_P0_PUEN_P17 (0x1 << 17) |
| 483 | #define PORT_P0_PUEN_P17_VAL(val) (((val) & 0x1) << 17) |
| 484 | #define PORT_P0_PUEN_P17_GET(val) ((((val) & PORT_P0_PUEN_P17) >> 17) & 0x1) |
| 485 | #define PORT_P0_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P17) | (((val) & 0x1) << 17)) |
| 486 | /* Pull Up Device Enable at Port 0 Bit # (16) */ |
| 487 | #define PORT_P0_PUEN_P16 (0x1 << 16) |
| 488 | #define PORT_P0_PUEN_P16_VAL(val) (((val) & 0x1) << 16) |
| 489 | #define PORT_P0_PUEN_P16_GET(val) ((((val) & PORT_P0_PUEN_P16) >> 16) & 0x1) |
| 490 | #define PORT_P0_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P16) | (((val) & 0x1) << 16)) |
| 491 | /* Pull Up Device Enable at Port 0 Bit # (15) */ |
| 492 | #define PORT_P0_PUEN_P15 (0x1 << 15) |
| 493 | #define PORT_P0_PUEN_P15_VAL(val) (((val) & 0x1) << 15) |
| 494 | #define PORT_P0_PUEN_P15_GET(val) ((((val) & PORT_P0_PUEN_P15) >> 15) & 0x1) |
| 495 | #define PORT_P0_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P15) | (((val) & 0x1) << 15)) |
| 496 | /* Pull Up Device Enable at Port 0 Bit # (14) */ |
| 497 | #define PORT_P0_PUEN_P14 (0x1 << 14) |
| 498 | #define PORT_P0_PUEN_P14_VAL(val) (((val) & 0x1) << 14) |
| 499 | #define PORT_P0_PUEN_P14_GET(val) ((((val) & PORT_P0_PUEN_P14) >> 14) & 0x1) |
| 500 | #define PORT_P0_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P14) | (((val) & 0x1) << 14)) |
| 501 | /* Pull Up Device Enable at Port 0 Bit # (13) */ |
| 502 | #define PORT_P0_PUEN_P13 (0x1 << 13) |
| 503 | #define PORT_P0_PUEN_P13_VAL(val) (((val) & 0x1) << 13) |
| 504 | #define PORT_P0_PUEN_P13_GET(val) ((((val) & PORT_P0_PUEN_P13) >> 13) & 0x1) |
| 505 | #define PORT_P0_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P13) | (((val) & 0x1) << 13)) |
| 506 | /* Pull Up Device Enable at Port 0 Bit # (12) */ |
| 507 | #define PORT_P0_PUEN_P12 (0x1 << 12) |
| 508 | #define PORT_P0_PUEN_P12_VAL(val) (((val) & 0x1) << 12) |
| 509 | #define PORT_P0_PUEN_P12_GET(val) ((((val) & PORT_P0_PUEN_P12) >> 12) & 0x1) |
| 510 | #define PORT_P0_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P12) | (((val) & 0x1) << 12)) |
| 511 | /* Pull Up Device Enable at Port 0 Bit # (11) */ |
| 512 | #define PORT_P0_PUEN_P11 (0x1 << 11) |
| 513 | #define PORT_P0_PUEN_P11_VAL(val) (((val) & 0x1) << 11) |
| 514 | #define PORT_P0_PUEN_P11_GET(val) ((((val) & PORT_P0_PUEN_P11) >> 11) & 0x1) |
| 515 | #define PORT_P0_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P11) | (((val) & 0x1) << 11)) |
| 516 | /* Pull Up Device Enable at Port 0 Bit # (10) */ |
| 517 | #define PORT_P0_PUEN_P10 (0x1 << 10) |
| 518 | #define PORT_P0_PUEN_P10_VAL(val) (((val) & 0x1) << 10) |
| 519 | #define PORT_P0_PUEN_P10_GET(val) ((((val) & PORT_P0_PUEN_P10) >> 10) & 0x1) |
| 520 | #define PORT_P0_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P10) | (((val) & 0x1) << 10)) |
| 521 | /* Pull Up Device Enable at Port 0 Bit # (9) */ |
| 522 | #define PORT_P0_PUEN_P9 (0x1 << 9) |
| 523 | #define PORT_P0_PUEN_P9_VAL(val) (((val) & 0x1) << 9) |
| 524 | #define PORT_P0_PUEN_P9_GET(val) ((((val) & PORT_P0_PUEN_P9) >> 9) & 0x1) |
| 525 | #define PORT_P0_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P9) | (((val) & 0x1) << 9)) |
| 526 | /* Pull Up Device Enable at Port 0 Bit # (8) */ |
| 527 | #define PORT_P0_PUEN_P8 (0x1 << 8) |
| 528 | #define PORT_P0_PUEN_P8_VAL(val) (((val) & 0x1) << 8) |
| 529 | #define PORT_P0_PUEN_P8_GET(val) ((((val) & PORT_P0_PUEN_P8) >> 8) & 0x1) |
| 530 | #define PORT_P0_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P8) | (((val) & 0x1) << 8)) |
| 531 | /* Pull Up Device Enable at Port 0 Bit # (7) */ |
| 532 | #define PORT_P0_PUEN_P7 (0x1 << 7) |
| 533 | #define PORT_P0_PUEN_P7_VAL(val) (((val) & 0x1) << 7) |
| 534 | #define PORT_P0_PUEN_P7_GET(val) ((((val) & PORT_P0_PUEN_P7) >> 7) & 0x1) |
| 535 | #define PORT_P0_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P7) | (((val) & 0x1) << 7)) |
| 536 | /* Pull Up Device Enable at Port 0 Bit # (6) */ |
| 537 | #define PORT_P0_PUEN_P6 (0x1 << 6) |
| 538 | #define PORT_P0_PUEN_P6_VAL(val) (((val) & 0x1) << 6) |
| 539 | #define PORT_P0_PUEN_P6_GET(val) ((((val) & PORT_P0_PUEN_P6) >> 6) & 0x1) |
| 540 | #define PORT_P0_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P6) | (((val) & 0x1) << 6)) |
| 541 | /* Pull Up Device Enable at Port 0 Bit # (5) */ |
| 542 | #define PORT_P0_PUEN_P5 (0x1 << 5) |
| 543 | #define PORT_P0_PUEN_P5_VAL(val) (((val) & 0x1) << 5) |
| 544 | #define PORT_P0_PUEN_P5_GET(val) ((((val) & PORT_P0_PUEN_P5) >> 5) & 0x1) |
| 545 | #define PORT_P0_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P5) | (((val) & 0x1) << 5)) |
| 546 | /* Pull Up Device Enable at Port 0 Bit # (4) */ |
| 547 | #define PORT_P0_PUEN_P4 (0x1 << 4) |
| 548 | #define PORT_P0_PUEN_P4_VAL(val) (((val) & 0x1) << 4) |
| 549 | #define PORT_P0_PUEN_P4_GET(val) ((((val) & PORT_P0_PUEN_P4) >> 4) & 0x1) |
| 550 | #define PORT_P0_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P4) | (((val) & 0x1) << 4)) |
| 551 | /* Pull Up Device Enable at Port 0 Bit # (3) */ |
| 552 | #define PORT_P0_PUEN_P3 (0x1 << 3) |
| 553 | #define PORT_P0_PUEN_P3_VAL(val) (((val) & 0x1) << 3) |
| 554 | #define PORT_P0_PUEN_P3_GET(val) ((((val) & PORT_P0_PUEN_P3) >> 3) & 0x1) |
| 555 | #define PORT_P0_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P3) | (((val) & 0x1) << 3)) |
| 556 | /* Pull Up Device Enable at Port 0 Bit # (2) */ |
| 557 | #define PORT_P0_PUEN_P2 (0x1 << 2) |
| 558 | #define PORT_P0_PUEN_P2_VAL(val) (((val) & 0x1) << 2) |
| 559 | #define PORT_P0_PUEN_P2_GET(val) ((((val) & PORT_P0_PUEN_P2) >> 2) & 0x1) |
| 560 | #define PORT_P0_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P2) | (((val) & 0x1) << 2)) |
| 561 | /* Pull Up Device Enable at Port 0 Bit # (1) */ |
| 562 | #define PORT_P0_PUEN_P1 (0x1 << 1) |
| 563 | #define PORT_P0_PUEN_P1_VAL(val) (((val) & 0x1) << 1) |
| 564 | #define PORT_P0_PUEN_P1_GET(val) ((((val) & PORT_P0_PUEN_P1) >> 1) & 0x1) |
| 565 | #define PORT_P0_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P1) | (((val) & 0x1) << 1)) |
| 566 | /* Pull Up Device Enable at Port 0 Bit # (0) */ |
| 567 | #define PORT_P0_PUEN_P0 (0x1) |
| 568 | #define PORT_P0_PUEN_P0_VAL(val) (((val) & 0x1) << 0) |
| 569 | #define PORT_P0_PUEN_P0_GET(val) ((((val) & PORT_P0_PUEN_P0) >> 0) & 0x1) |
| 570 | #define PORT_P0_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P0) | (((val) & 0x1) << 0)) |
| 571 | |
| 572 | /******************************************************************************* |
| 573 | * External Interrupt Control Register 0 |
| 574 | ******************************************************************************/ |
| 575 | |
| 576 | /* Type of Level or Edge Detection of EXINT16 (19) */ |
| 577 | #define PORT_P0_EXINTCR0_EXINT16 (0x1 << 19) |
| 578 | #define PORT_P0_EXINTCR0_EXINT16_VAL(val) (((val) & 0x1) << 19) |
| 579 | #define PORT_P0_EXINTCR0_EXINT16_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT16) >> 19) & 0x1) |
| 580 | #define PORT_P0_EXINTCR0_EXINT16_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT16) | (((val) & 0x1) << 19)) |
| 581 | /* Type of Level or Edge Detection of EXINT10 (17) */ |
| 582 | #define PORT_P0_EXINTCR0_EXINT10 (0x1 << 17) |
| 583 | #define PORT_P0_EXINTCR0_EXINT10_VAL(val) (((val) & 0x1) << 17) |
| 584 | #define PORT_P0_EXINTCR0_EXINT10_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT10) >> 17) & 0x1) |
| 585 | #define PORT_P0_EXINTCR0_EXINT10_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT10) | (((val) & 0x1) << 17)) |
| 586 | /* Type of Level or Edge Detection of EXINT9 (16) */ |
| 587 | #define PORT_P0_EXINTCR0_EXINT9 (0x1 << 16) |
| 588 | #define PORT_P0_EXINTCR0_EXINT9_VAL(val) (((val) & 0x1) << 16) |
| 589 | #define PORT_P0_EXINTCR0_EXINT9_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT9) >> 16) & 0x1) |
| 590 | #define PORT_P0_EXINTCR0_EXINT9_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT9) | (((val) & 0x1) << 16)) |
| 591 | /* Type of Level or Edge Detection of EXINT8 (15) */ |
| 592 | #define PORT_P0_EXINTCR0_EXINT8 (0x1 << 15) |
| 593 | #define PORT_P0_EXINTCR0_EXINT8_VAL(val) (((val) & 0x1) << 15) |
| 594 | #define PORT_P0_EXINTCR0_EXINT8_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT8) >> 15) & 0x1) |
| 595 | #define PORT_P0_EXINTCR0_EXINT8_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT8) | (((val) & 0x1) << 15)) |
| 596 | /* Type of Level or Edge Detection of EXINT7 (14) */ |
| 597 | #define PORT_P0_EXINTCR0_EXINT7 (0x1 << 14) |
| 598 | #define PORT_P0_EXINTCR0_EXINT7_VAL(val) (((val) & 0x1) << 14) |
| 599 | #define PORT_P0_EXINTCR0_EXINT7_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT7) >> 14) & 0x1) |
| 600 | #define PORT_P0_EXINTCR0_EXINT7_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT7) | (((val) & 0x1) << 14)) |
| 601 | /* Type of Level or Edge Detection of EXINT6 (13) */ |
| 602 | #define PORT_P0_EXINTCR0_EXINT6 (0x1 << 13) |
| 603 | #define PORT_P0_EXINTCR0_EXINT6_VAL(val) (((val) & 0x1) << 13) |
| 604 | #define PORT_P0_EXINTCR0_EXINT6_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT6) >> 13) & 0x1) |
| 605 | #define PORT_P0_EXINTCR0_EXINT6_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT6) | (((val) & 0x1) << 13)) |
| 606 | /* Type of Level or Edge Detection of EXINT5 (12) */ |
| 607 | #define PORT_P0_EXINTCR0_EXINT5 (0x1 << 12) |
| 608 | #define PORT_P0_EXINTCR0_EXINT5_VAL(val) (((val) & 0x1) << 12) |
| 609 | #define PORT_P0_EXINTCR0_EXINT5_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT5) >> 12) & 0x1) |
| 610 | #define PORT_P0_EXINTCR0_EXINT5_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT5) | (((val) & 0x1) << 12)) |
| 611 | /* Type of Level or Edge Detection of EXINT4 (11) */ |
| 612 | #define PORT_P0_EXINTCR0_EXINT4 (0x1 << 11) |
| 613 | #define PORT_P0_EXINTCR0_EXINT4_VAL(val) (((val) & 0x1) << 11) |
| 614 | #define PORT_P0_EXINTCR0_EXINT4_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT4) >> 11) & 0x1) |
| 615 | #define PORT_P0_EXINTCR0_EXINT4_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT4) | (((val) & 0x1) << 11)) |
| 616 | /* Type of Level or Edge Detection of EXINT3 (10) */ |
| 617 | #define PORT_P0_EXINTCR0_EXINT3 (0x1 << 10) |
| 618 | #define PORT_P0_EXINTCR0_EXINT3_VAL(val) (((val) & 0x1) << 10) |
| 619 | #define PORT_P0_EXINTCR0_EXINT3_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT3) >> 10) & 0x1) |
| 620 | #define PORT_P0_EXINTCR0_EXINT3_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT3) | (((val) & 0x1) << 10)) |
| 621 | /* Type of Level or Edge Detection of EXINT2 (9) */ |
| 622 | #define PORT_P0_EXINTCR0_EXINT2 (0x1 << 9) |
| 623 | #define PORT_P0_EXINTCR0_EXINT2_VAL(val) (((val) & 0x1) << 9) |
| 624 | #define PORT_P0_EXINTCR0_EXINT2_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT2) >> 9) & 0x1) |
| 625 | #define PORT_P0_EXINTCR0_EXINT2_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT2) | (((val) & 0x1) << 9)) |
| 626 | /* Type of Level or Edge Detection of EXINT1 (8) */ |
| 627 | #define PORT_P0_EXINTCR0_EXINT1 (0x1 << 8) |
| 628 | #define PORT_P0_EXINTCR0_EXINT1_VAL(val) (((val) & 0x1) << 8) |
| 629 | #define PORT_P0_EXINTCR0_EXINT1_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT1) >> 8) & 0x1) |
| 630 | #define PORT_P0_EXINTCR0_EXINT1_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT1) | (((val) & 0x1) << 8)) |
| 631 | /* Type of Level or Edge Detection of EXINT0 (7) */ |
| 632 | #define PORT_P0_EXINTCR0_EXINT0 (0x1 << 7) |
| 633 | #define PORT_P0_EXINTCR0_EXINT0_VAL(val) (((val) & 0x1) << 7) |
| 634 | #define PORT_P0_EXINTCR0_EXINT0_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT0) >> 7) & 0x1) |
| 635 | #define PORT_P0_EXINTCR0_EXINT0_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT0) | (((val) & 0x1) << 7)) |
| 636 | |
| 637 | /******************************************************************************* |
| 638 | * External Interrupt Control Register 1 |
| 639 | ******************************************************************************/ |
| 640 | |
| 641 | /* Type of Level or Edge Detection of EXINT16 (19) */ |
| 642 | #define PORT_P0_EXINTCR1_EXINT16 (0x1 << 19) |
| 643 | #define PORT_P0_EXINTCR1_EXINT16_VAL(val) (((val) & 0x1) << 19) |
| 644 | #define PORT_P0_EXINTCR1_EXINT16_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT16) >> 19) & 0x1) |
| 645 | #define PORT_P0_EXINTCR1_EXINT16_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT16) | (((val) & 0x1) << 19)) |
| 646 | /* Type of Level or Edge Detection of EXINT10 (17) */ |
| 647 | #define PORT_P0_EXINTCR1_EXINT10 (0x1 << 17) |
| 648 | #define PORT_P0_EXINTCR1_EXINT10_VAL(val) (((val) & 0x1) << 17) |
| 649 | #define PORT_P0_EXINTCR1_EXINT10_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT10) >> 17) & 0x1) |
| 650 | #define PORT_P0_EXINTCR1_EXINT10_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT10) | (((val) & 0x1) << 17)) |
| 651 | /* Type of Level or Edge Detection of EXINT9 (16) */ |
| 652 | #define PORT_P0_EXINTCR1_EXINT9 (0x1 << 16) |
| 653 | #define PORT_P0_EXINTCR1_EXINT9_VAL(val) (((val) & 0x1) << 16) |
| 654 | #define PORT_P0_EXINTCR1_EXINT9_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT9) >> 16) & 0x1) |
| 655 | #define PORT_P0_EXINTCR1_EXINT9_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT9) | (((val) & 0x1) << 16)) |
| 656 | /* Type of Level or Edge Detection of EXINT8 (15) */ |
| 657 | #define PORT_P0_EXINTCR1_EXINT8 (0x1 << 15) |
| 658 | #define PORT_P0_EXINTCR1_EXINT8_VAL(val) (((val) & 0x1) << 15) |
| 659 | #define PORT_P0_EXINTCR1_EXINT8_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT8) >> 15) & 0x1) |
| 660 | #define PORT_P0_EXINTCR1_EXINT8_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT8) | (((val) & 0x1) << 15)) |
| 661 | /* Type of Level or Edge Detection of EXINT7 (14) */ |
| 662 | #define PORT_P0_EXINTCR1_EXINT7 (0x1 << 14) |
| 663 | #define PORT_P0_EXINTCR1_EXINT7_VAL(val) (((val) & 0x1) << 14) |
| 664 | #define PORT_P0_EXINTCR1_EXINT7_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT7) >> 14) & 0x1) |
| 665 | #define PORT_P0_EXINTCR1_EXINT7_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT7) | (((val) & 0x1) << 14)) |
| 666 | /* Type of Level or Edge Detection of EXINT6 (13) */ |
| 667 | #define PORT_P0_EXINTCR1_EXINT6 (0x1 << 13) |
| 668 | #define PORT_P0_EXINTCR1_EXINT6_VAL(val) (((val) & 0x1) << 13) |
| 669 | #define PORT_P0_EXINTCR1_EXINT6_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT6) >> 13) & 0x1) |
| 670 | #define PORT_P0_EXINTCR1_EXINT6_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT6) | (((val) & 0x1) << 13)) |
| 671 | /* Type of Level or Edge Detection of EXINT5 (12) */ |
| 672 | #define PORT_P0_EXINTCR1_EXINT5 (0x1 << 12) |
| 673 | #define PORT_P0_EXINTCR1_EXINT5_VAL(val) (((val) & 0x1) << 12) |
| 674 | #define PORT_P0_EXINTCR1_EXINT5_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT5) >> 12) & 0x1) |
| 675 | #define PORT_P0_EXINTCR1_EXINT5_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT5) | (((val) & 0x1) << 12)) |
| 676 | /* Type of Level or Edge Detection of EXINT4 (11) */ |
| 677 | #define PORT_P0_EXINTCR1_EXINT4 (0x1 << 11) |
| 678 | #define PORT_P0_EXINTCR1_EXINT4_VAL(val) (((val) & 0x1) << 11) |
| 679 | #define PORT_P0_EXINTCR1_EXINT4_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT4) >> 11) & 0x1) |
| 680 | #define PORT_P0_EXINTCR1_EXINT4_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT4) | (((val) & 0x1) << 11)) |
| 681 | /* Type of Level or Edge Detection of EXINT3 (10) */ |
| 682 | #define PORT_P0_EXINTCR1_EXINT3 (0x1 << 10) |
| 683 | #define PORT_P0_EXINTCR1_EXINT3_VAL(val) (((val) & 0x1) << 10) |
| 684 | #define PORT_P0_EXINTCR1_EXINT3_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT3) >> 10) & 0x1) |
| 685 | #define PORT_P0_EXINTCR1_EXINT3_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT3) | (((val) & 0x1) << 10)) |
| 686 | /* Type of Level or Edge Detection of EXINT2 (9) */ |
| 687 | #define PORT_P0_EXINTCR1_EXINT2 (0x1 << 9) |
| 688 | #define PORT_P0_EXINTCR1_EXINT2_VAL(val) (((val) & 0x1) << 9) |
| 689 | #define PORT_P0_EXINTCR1_EXINT2_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT2) >> 9) & 0x1) |
| 690 | #define PORT_P0_EXINTCR1_EXINT2_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT2) | (((val) & 0x1) << 9)) |
| 691 | /* Type of Level or Edge Detection of EXINT1 (8) */ |
| 692 | #define PORT_P0_EXINTCR1_EXINT1 (0x1 << 8) |
| 693 | #define PORT_P0_EXINTCR1_EXINT1_VAL(val) (((val) & 0x1) << 8) |
| 694 | #define PORT_P0_EXINTCR1_EXINT1_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT1) >> 8) & 0x1) |
| 695 | #define PORT_P0_EXINTCR1_EXINT1_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT1) | (((val) & 0x1) << 8)) |
| 696 | /* Type of Level or Edge Detection of EXINT0 (7) */ |
| 697 | #define PORT_P0_EXINTCR1_EXINT0 (0x1 << 7) |
| 698 | #define PORT_P0_EXINTCR1_EXINT0_VAL(val) (((val) & 0x1) << 7) |
| 699 | #define PORT_P0_EXINTCR1_EXINT0_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT0) >> 7) & 0x1) |
| 700 | #define PORT_P0_EXINTCR1_EXINT0_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT0) | (((val) & 0x1) << 7)) |
| 701 | |
| 702 | /******************************************************************************* |
| 703 | * P0_IRNEN Register |
| 704 | ******************************************************************************/ |
| 705 | |
| 706 | /* EXINT16 Interrupt Request Enable (19) */ |
| 707 | #define PORT_P0_IRNEN_EXINT16 (0x1 << 19) |
| 708 | #define PORT_P0_IRNEN_EXINT16_VAL(val) (((val) & 0x1) << 19) |
| 709 | #define PORT_P0_IRNEN_EXINT16_GET(val) ((((val) & PORT_P0_IRNEN_EXINT16) >> 19) & 0x1) |
| 710 | #define PORT_P0_IRNEN_EXINT16_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT16) | (((val) & 0x1) << 19)) |
| 711 | /* EXINT10 Interrupt Request Enable (17) */ |
| 712 | #define PORT_P0_IRNEN_EXINT10 (0x1 << 17) |
| 713 | #define PORT_P0_IRNEN_EXINT10_VAL(val) (((val) & 0x1) << 17) |
| 714 | #define PORT_P0_IRNEN_EXINT10_GET(val) ((((val) & PORT_P0_IRNEN_EXINT10) >> 17) & 0x1) |
| 715 | #define PORT_P0_IRNEN_EXINT10_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT10) | (((val) & 0x1) << 17)) |
| 716 | /* EXINT9 Interrupt Request Enable (16) */ |
| 717 | #define PORT_P0_IRNEN_EXINT9 (0x1 << 16) |
| 718 | #define PORT_P0_IRNEN_EXINT9_VAL(val) (((val) & 0x1) << 16) |
| 719 | #define PORT_P0_IRNEN_EXINT9_GET(val) ((((val) & PORT_P0_IRNEN_EXINT9) >> 16) & 0x1) |
| 720 | #define PORT_P0_IRNEN_EXINT9_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT9) | (((val) & 0x1) << 16)) |
| 721 | /* EXINT8 Interrupt Request Enable (15) */ |
| 722 | #define PORT_P0_IRNEN_EXINT8 (0x1 << 15) |
| 723 | #define PORT_P0_IRNEN_EXINT8_VAL(val) (((val) & 0x1) << 15) |
| 724 | #define PORT_P0_IRNEN_EXINT8_GET(val) ((((val) & PORT_P0_IRNEN_EXINT8) >> 15) & 0x1) |
| 725 | #define PORT_P0_IRNEN_EXINT8_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT8) | (((val) & 0x1) << 15)) |
| 726 | /* EXINT7 Interrupt Request Enable (14) */ |
| 727 | #define PORT_P0_IRNEN_EXINT7 (0x1 << 14) |
| 728 | #define PORT_P0_IRNEN_EXINT7_VAL(val) (((val) & 0x1) << 14) |
| 729 | #define PORT_P0_IRNEN_EXINT7_GET(val) ((((val) & PORT_P0_IRNEN_EXINT7) >> 14) & 0x1) |
| 730 | #define PORT_P0_IRNEN_EXINT7_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT7) | (((val) & 0x1) << 14)) |
| 731 | /* EXINT6 Interrupt Request Enable (13) */ |
| 732 | #define PORT_P0_IRNEN_EXINT6 (0x1 << 13) |
| 733 | #define PORT_P0_IRNEN_EXINT6_VAL(val) (((val) & 0x1) << 13) |
| 734 | #define PORT_P0_IRNEN_EXINT6_GET(val) ((((val) & PORT_P0_IRNEN_EXINT6) >> 13) & 0x1) |
| 735 | #define PORT_P0_IRNEN_EXINT6_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT6) | (((val) & 0x1) << 13)) |
| 736 | /* EXINT5 Interrupt Request Enable (12) */ |
| 737 | #define PORT_P0_IRNEN_EXINT5 (0x1 << 12) |
| 738 | #define PORT_P0_IRNEN_EXINT5_VAL(val) (((val) & 0x1) << 12) |
| 739 | #define PORT_P0_IRNEN_EXINT5_GET(val) ((((val) & PORT_P0_IRNEN_EXINT5) >> 12) & 0x1) |
| 740 | #define PORT_P0_IRNEN_EXINT5_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT5) | (((val) & 0x1) << 12)) |
| 741 | /* EXINT4 Interrupt Request Enable (11) */ |
| 742 | #define PORT_P0_IRNEN_EXINT4 (0x1 << 11) |
| 743 | #define PORT_P0_IRNEN_EXINT4_VAL(val) (((val) & 0x1) << 11) |
| 744 | #define PORT_P0_IRNEN_EXINT4_GET(val) ((((val) & PORT_P0_IRNEN_EXINT4) >> 11) & 0x1) |
| 745 | #define PORT_P0_IRNEN_EXINT4_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT4) | (((val) & 0x1) << 11)) |
| 746 | /* EXINT3 Interrupt Request Enable (10) */ |
| 747 | #define PORT_P0_IRNEN_EXINT3 (0x1 << 10) |
| 748 | #define PORT_P0_IRNEN_EXINT3_VAL(val) (((val) & 0x1) << 10) |
| 749 | #define PORT_P0_IRNEN_EXINT3_GET(val) ((((val) & PORT_P0_IRNEN_EXINT3) >> 10) & 0x1) |
| 750 | #define PORT_P0_IRNEN_EXINT3_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT3) | (((val) & 0x1) << 10)) |
| 751 | /* EXINT2 Interrupt Request Enable (9) */ |
| 752 | #define PORT_P0_IRNEN_EXINT2 (0x1 << 9) |
| 753 | #define PORT_P0_IRNEN_EXINT2_VAL(val) (((val) & 0x1) << 9) |
| 754 | #define PORT_P0_IRNEN_EXINT2_GET(val) ((((val) & PORT_P0_IRNEN_EXINT2) >> 9) & 0x1) |
| 755 | #define PORT_P0_IRNEN_EXINT2_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT2) | (((val) & 0x1) << 9)) |
| 756 | /* EXINT1 Interrupt Request Enable (8) */ |
| 757 | #define PORT_P0_IRNEN_EXINT1 (0x1 << 8) |
| 758 | #define PORT_P0_IRNEN_EXINT1_VAL(val) (((val) & 0x1) << 8) |
| 759 | #define PORT_P0_IRNEN_EXINT1_GET(val) ((((val) & PORT_P0_IRNEN_EXINT1) >> 8) & 0x1) |
| 760 | #define PORT_P0_IRNEN_EXINT1_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT1) | (((val) & 0x1) << 8)) |
| 761 | /* EXINT0 Interrupt Request Enable (7) */ |
| 762 | #define PORT_P0_IRNEN_EXINT0 (0x1 << 7) |
| 763 | #define PORT_P0_IRNEN_EXINT0_VAL(val) (((val) & 0x1) << 7) |
| 764 | #define PORT_P0_IRNEN_EXINT0_GET(val) ((((val) & PORT_P0_IRNEN_EXINT0) >> 7) & 0x1) |
| 765 | #define PORT_P0_IRNEN_EXINT0_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT0) | (((val) & 0x1) << 7)) |
| 766 | |
| 767 | /******************************************************************************* |
| 768 | * P0_IRNICR Register |
| 769 | ******************************************************************************/ |
| 770 | |
| 771 | /* EXINT16 Interrupt Request (19) */ |
| 772 | #define PORT_P0_IRNICR_EXINT16 (0x1 << 19) |
| 773 | #define PORT_P0_IRNICR_EXINT16_GET(val) ((((val) & PORT_P0_IRNICR_EXINT16) >> 19) & 0x1) |
| 774 | /* EXINT10 Interrupt Request (17) */ |
| 775 | #define PORT_P0_IRNICR_EXINT10 (0x1 << 17) |
| 776 | #define PORT_P0_IRNICR_EXINT10_GET(val) ((((val) & PORT_P0_IRNICR_EXINT10) >> 17) & 0x1) |
| 777 | /* EXINT9 Interrupt Request (16) */ |
| 778 | #define PORT_P0_IRNICR_EXINT9 (0x1 << 16) |
| 779 | #define PORT_P0_IRNICR_EXINT9_GET(val) ((((val) & PORT_P0_IRNICR_EXINT9) >> 16) & 0x1) |
| 780 | /* EXINT8 Interrupt Request (15) */ |
| 781 | #define PORT_P0_IRNICR_EXINT8 (0x1 << 15) |
| 782 | #define PORT_P0_IRNICR_EXINT8_GET(val) ((((val) & PORT_P0_IRNICR_EXINT8) >> 15) & 0x1) |
| 783 | /* EXINT7 Interrupt Request (14) */ |
| 784 | #define PORT_P0_IRNICR_EXINT7 (0x1 << 14) |
| 785 | #define PORT_P0_IRNICR_EXINT7_GET(val) ((((val) & PORT_P0_IRNICR_EXINT7) >> 14) & 0x1) |
| 786 | /* EXINT6 Interrupt Request (13) */ |
| 787 | #define PORT_P0_IRNICR_EXINT6 (0x1 << 13) |
| 788 | #define PORT_P0_IRNICR_EXINT6_GET(val) ((((val) & PORT_P0_IRNICR_EXINT6) >> 13) & 0x1) |
| 789 | /* EXINT5 Interrupt Request (12) */ |
| 790 | #define PORT_P0_IRNICR_EXINT5 (0x1 << 12) |
| 791 | #define PORT_P0_IRNICR_EXINT5_GET(val) ((((val) & PORT_P0_IRNICR_EXINT5) >> 12) & 0x1) |
| 792 | /* EXINT4 Interrupt Request (11) */ |
| 793 | #define PORT_P0_IRNICR_EXINT4 (0x1 << 11) |
| 794 | #define PORT_P0_IRNICR_EXINT4_GET(val) ((((val) & PORT_P0_IRNICR_EXINT4) >> 11) & 0x1) |
| 795 | /* EXINT3 Interrupt Request (10) */ |
| 796 | #define PORT_P0_IRNICR_EXINT3 (0x1 << 10) |
| 797 | #define PORT_P0_IRNICR_EXINT3_GET(val) ((((val) & PORT_P0_IRNICR_EXINT3) >> 10) & 0x1) |
| 798 | /* EXINT2 Interrupt Request (9) */ |
| 799 | #define PORT_P0_IRNICR_EXINT2 (0x1 << 9) |
| 800 | #define PORT_P0_IRNICR_EXINT2_GET(val) ((((val) & PORT_P0_IRNICR_EXINT2) >> 9) & 0x1) |
| 801 | /* EXINT1 Interrupt Request (8) */ |
| 802 | #define PORT_P0_IRNICR_EXINT1 (0x1 << 8) |
| 803 | #define PORT_P0_IRNICR_EXINT1_GET(val) ((((val) & PORT_P0_IRNICR_EXINT1) >> 8) & 0x1) |
| 804 | /* EXINT0 Interrupt Request (7) */ |
| 805 | #define PORT_P0_IRNICR_EXINT0 (0x1 << 7) |
| 806 | #define PORT_P0_IRNICR_EXINT0_GET(val) ((((val) & PORT_P0_IRNICR_EXINT0) >> 7) & 0x1) |
| 807 | |
| 808 | /******************************************************************************* |
| 809 | * P0_IRNCR Register |
| 810 | ******************************************************************************/ |
| 811 | |
| 812 | /* EXINT16 Interrupt Request (19) */ |
| 813 | #define PORT_P0_IRNCR_EXINT16 (0x1 << 19) |
| 814 | #define PORT_P0_IRNCR_EXINT16_GET(val) ((((val) & PORT_P0_IRNCR_EXINT16) >> 19) & 0x1) |
| 815 | /* EXINT10 Interrupt Request (17) */ |
| 816 | #define PORT_P0_IRNCR_EXINT10 (0x1 << 17) |
| 817 | #define PORT_P0_IRNCR_EXINT10_GET(val) ((((val) & PORT_P0_IRNCR_EXINT10) >> 17) & 0x1) |
| 818 | /* EXINT9 Interrupt Request (16) */ |
| 819 | #define PORT_P0_IRNCR_EXINT9 (0x1 << 16) |
| 820 | #define PORT_P0_IRNCR_EXINT9_GET(val) ((((val) & PORT_P0_IRNCR_EXINT9) >> 16) & 0x1) |
| 821 | /* EXINT8 Interrupt Request (15) */ |
| 822 | #define PORT_P0_IRNCR_EXINT8 (0x1 << 15) |
| 823 | #define PORT_P0_IRNCR_EXINT8_GET(val) ((((val) & PORT_P0_IRNCR_EXINT8) >> 15) & 0x1) |
| 824 | /* EXINT7 Interrupt Request (14) */ |
| 825 | #define PORT_P0_IRNCR_EXINT7 (0x1 << 14) |
| 826 | #define PORT_P0_IRNCR_EXINT7_GET(val) ((((val) & PORT_P0_IRNCR_EXINT7) >> 14) & 0x1) |
| 827 | /* EXINT6 Interrupt Request (13) */ |
| 828 | #define PORT_P0_IRNCR_EXINT6 (0x1 << 13) |
| 829 | #define PORT_P0_IRNCR_EXINT6_GET(val) ((((val) & PORT_P0_IRNCR_EXINT6) >> 13) & 0x1) |
| 830 | /* EXINT5 Interrupt Request (12) */ |
| 831 | #define PORT_P0_IRNCR_EXINT5 (0x1 << 12) |
| 832 | #define PORT_P0_IRNCR_EXINT5_GET(val) ((((val) & PORT_P0_IRNCR_EXINT5) >> 12) & 0x1) |
| 833 | /* EXINT4 Interrupt Request (11) */ |
| 834 | #define PORT_P0_IRNCR_EXINT4 (0x1 << 11) |
| 835 | #define PORT_P0_IRNCR_EXINT4_GET(val) ((((val) & PORT_P0_IRNCR_EXINT4) >> 11) & 0x1) |
| 836 | /* EXINT3 Interrupt Request (10) */ |
| 837 | #define PORT_P0_IRNCR_EXINT3 (0x1 << 10) |
| 838 | #define PORT_P0_IRNCR_EXINT3_GET(val) ((((val) & PORT_P0_IRNCR_EXINT3) >> 10) & 0x1) |
| 839 | /* EXINT2 Interrupt Request (9) */ |
| 840 | #define PORT_P0_IRNCR_EXINT2 (0x1 << 9) |
| 841 | #define PORT_P0_IRNCR_EXINT2_GET(val) ((((val) & PORT_P0_IRNCR_EXINT2) >> 9) & 0x1) |
| 842 | /* EXINT1 Interrupt Request (8) */ |
| 843 | #define PORT_P0_IRNCR_EXINT1 (0x1 << 8) |
| 844 | #define PORT_P0_IRNCR_EXINT1_GET(val) ((((val) & PORT_P0_IRNCR_EXINT1) >> 8) & 0x1) |
| 845 | /* EXINT0 Interrupt Request (7) */ |
| 846 | #define PORT_P0_IRNCR_EXINT0 (0x1 << 7) |
| 847 | #define PORT_P0_IRNCR_EXINT0_GET(val) ((((val) & PORT_P0_IRNCR_EXINT0) >> 7) & 0x1) |
| 848 | |
| 849 | /******************************************************************************* |
| 850 | * P0 External Event Detection Configuration Register |
| 851 | ******************************************************************************/ |
| 852 | |
| 853 | /* EXINT16 configured for Edge or Level Detection (19) */ |
| 854 | #define PORT_P0_IRNCFG_EXINT16 (0x1 << 19) |
| 855 | #define PORT_P0_IRNCFG_EXINT16_VAL(val) (((val) & 0x1) << 19) |
| 856 | #define PORT_P0_IRNCFG_EXINT16_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT16) >> 19) & 0x1) |
| 857 | #define PORT_P0_IRNCFG_EXINT16_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT16) | (((val) & 0x1) << 19)) |
| 858 | /* EXINT10 configured for Edge or Level Detection (17) */ |
| 859 | #define PORT_P0_IRNCFG_EXINT10 (0x1 << 17) |
| 860 | #define PORT_P0_IRNCFG_EXINT10_VAL(val) (((val) & 0x1) << 17) |
| 861 | #define PORT_P0_IRNCFG_EXINT10_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT10) >> 17) & 0x1) |
| 862 | #define PORT_P0_IRNCFG_EXINT10_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT10) | (((val) & 0x1) << 17)) |
| 863 | /* EXINT9 configured for Edge or Level Detection (16) */ |
| 864 | #define PORT_P0_IRNCFG_EXINT9 (0x1 << 16) |
| 865 | #define PORT_P0_IRNCFG_EXINT9_VAL(val) (((val) & 0x1) << 16) |
| 866 | #define PORT_P0_IRNCFG_EXINT9_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT9) >> 16) & 0x1) |
| 867 | #define PORT_P0_IRNCFG_EXINT9_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT9) | (((val) & 0x1) << 16)) |
| 868 | /* EXINT8 configured for Edge or Level Detection (15) */ |
| 869 | #define PORT_P0_IRNCFG_EXINT8 (0x1 << 15) |
| 870 | #define PORT_P0_IRNCFG_EXINT8_VAL(val) (((val) & 0x1) << 15) |
| 871 | #define PORT_P0_IRNCFG_EXINT8_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT8) >> 15) & 0x1) |
| 872 | #define PORT_P0_IRNCFG_EXINT8_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT8) | (((val) & 0x1) << 15)) |
| 873 | /* EXINT7 configured for Edge or Level Detection (14) */ |
| 874 | #define PORT_P0_IRNCFG_EXINT7 (0x1 << 14) |
| 875 | #define PORT_P0_IRNCFG_EXINT7_VAL(val) (((val) & 0x1) << 14) |
| 876 | #define PORT_P0_IRNCFG_EXINT7_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT7) >> 14) & 0x1) |
| 877 | #define PORT_P0_IRNCFG_EXINT7_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT7) | (((val) & 0x1) << 14)) |
| 878 | /* EXINT6 configured for Edge or Level Detection (13) */ |
| 879 | #define PORT_P0_IRNCFG_EXINT6 (0x1 << 13) |
| 880 | #define PORT_P0_IRNCFG_EXINT6_VAL(val) (((val) & 0x1) << 13) |
| 881 | #define PORT_P0_IRNCFG_EXINT6_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT6) >> 13) & 0x1) |
| 882 | #define PORT_P0_IRNCFG_EXINT6_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT6) | (((val) & 0x1) << 13)) |
| 883 | /* EXINT5 configured for Edge or Level Detection (12) */ |
| 884 | #define PORT_P0_IRNCFG_EXINT5 (0x1 << 12) |
| 885 | #define PORT_P0_IRNCFG_EXINT5_VAL(val) (((val) & 0x1) << 12) |
| 886 | #define PORT_P0_IRNCFG_EXINT5_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT5) >> 12) & 0x1) |
| 887 | #define PORT_P0_IRNCFG_EXINT5_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT5) | (((val) & 0x1) << 12)) |
| 888 | /* EXINT4 configured for Edge or Level Detection (11) */ |
| 889 | #define PORT_P0_IRNCFG_EXINT4 (0x1 << 11) |
| 890 | #define PORT_P0_IRNCFG_EXINT4_VAL(val) (((val) & 0x1) << 11) |
| 891 | #define PORT_P0_IRNCFG_EXINT4_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT4) >> 11) & 0x1) |
| 892 | #define PORT_P0_IRNCFG_EXINT4_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT4) | (((val) & 0x1) << 11)) |
| 893 | /* EXINT3 configured for Edge or Level Detection (10) */ |
| 894 | #define PORT_P0_IRNCFG_EXINT3 (0x1 << 10) |
| 895 | #define PORT_P0_IRNCFG_EXINT3_VAL(val) (((val) & 0x1) << 10) |
| 896 | #define PORT_P0_IRNCFG_EXINT3_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT3) >> 10) & 0x1) |
| 897 | #define PORT_P0_IRNCFG_EXINT3_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT3) | (((val) & 0x1) << 10)) |
| 898 | /* EXINT2 configured for Edge or Level Detection (9) */ |
| 899 | #define PORT_P0_IRNCFG_EXINT2 (0x1 << 9) |
| 900 | #define PORT_P0_IRNCFG_EXINT2_VAL(val) (((val) & 0x1) << 9) |
| 901 | #define PORT_P0_IRNCFG_EXINT2_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT2) >> 9) & 0x1) |
| 902 | #define PORT_P0_IRNCFG_EXINT2_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT2) | (((val) & 0x1) << 9)) |
| 903 | /* EXINT1 configured for Edge or Level Detection (8) */ |
| 904 | #define PORT_P0_IRNCFG_EXINT1 (0x1 << 8) |
| 905 | #define PORT_P0_IRNCFG_EXINT1_VAL(val) (((val) & 0x1) << 8) |
| 906 | #define PORT_P0_IRNCFG_EXINT1_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT1) >> 8) & 0x1) |
| 907 | #define PORT_P0_IRNCFG_EXINT1_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT1) | (((val) & 0x1) << 8)) |
| 908 | /* EXINT0 configured for Edge or Level Detection (7) */ |
| 909 | #define PORT_P0_IRNCFG_EXINT0 (0x1 << 7) |
| 910 | #define PORT_P0_IRNCFG_EXINT0_VAL(val) (((val) & 0x1) << 7) |
| 911 | #define PORT_P0_IRNCFG_EXINT0_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT0) >> 7) & 0x1) |
| 912 | #define PORT_P0_IRNCFG_EXINT0_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT0) | (((val) & 0x1) << 7)) |
| 913 | |
| 914 | /******************************************************************************* |
| 915 | * P0_IRNENSET Register |
| 916 | ******************************************************************************/ |
| 917 | |
| 918 | /* Set Interrupt Node Enable Flag EXINT16 (19) */ |
| 919 | #define PORT_P0_IRNENSET_EXINT16 (0x1 << 19) |
| 920 | #define PORT_P0_IRNENSET_EXINT16_VAL(val) (((val) & 0x1) << 19) |
| 921 | #define PORT_P0_IRNENSET_EXINT16_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT16) | (val) & 1) << 19) |
| 922 | /* Set Interrupt Node Enable Flag EXINT10 (17) */ |
| 923 | #define PORT_P0_IRNENSET_EXINT10 (0x1 << 17) |
| 924 | #define PORT_P0_IRNENSET_EXINT10_VAL(val) (((val) & 0x1) << 17) |
| 925 | #define PORT_P0_IRNENSET_EXINT10_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT10) | (val) & 1) << 17) |
| 926 | /* Set Interrupt Node Enable Flag EXINT9 (16) */ |
| 927 | #define PORT_P0_IRNENSET_EXINT9 (0x1 << 16) |
| 928 | #define PORT_P0_IRNENSET_EXINT9_VAL(val) (((val) & 0x1) << 16) |
| 929 | #define PORT_P0_IRNENSET_EXINT9_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT9) | (val) & 1) << 16) |
| 930 | /* Set Interrupt Node Enable Flag EXINT8 (15) */ |
| 931 | #define PORT_P0_IRNENSET_EXINT8 (0x1 << 15) |
| 932 | #define PORT_P0_IRNENSET_EXINT8_VAL(val) (((val) & 0x1) << 15) |
| 933 | #define PORT_P0_IRNENSET_EXINT8_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT8) | (val) & 1) << 15) |
| 934 | /* Set Interrupt Node Enable Flag EXINT7 (14) */ |
| 935 | #define PORT_P0_IRNENSET_EXINT7 (0x1 << 14) |
| 936 | #define PORT_P0_IRNENSET_EXINT7_VAL(val) (((val) & 0x1) << 14) |
| 937 | #define PORT_P0_IRNENSET_EXINT7_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT7) | (val) & 1) << 14) |
| 938 | /* Set Interrupt Node Enable Flag EXINT6 (13) */ |
| 939 | #define PORT_P0_IRNENSET_EXINT6 (0x1 << 13) |
| 940 | #define PORT_P0_IRNENSET_EXINT6_VAL(val) (((val) & 0x1) << 13) |
| 941 | #define PORT_P0_IRNENSET_EXINT6_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT6) | (val) & 1) << 13) |
| 942 | /* Set Interrupt Node Enable Flag EXINT5 (12) */ |
| 943 | #define PORT_P0_IRNENSET_EXINT5 (0x1 << 12) |
| 944 | #define PORT_P0_IRNENSET_EXINT5_VAL(val) (((val) & 0x1) << 12) |
| 945 | #define PORT_P0_IRNENSET_EXINT5_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT5) | (val) & 1) << 12) |
| 946 | /* Set Interrupt Node Enable Flag EXINT4 (11) */ |
| 947 | #define PORT_P0_IRNENSET_EXINT4 (0x1 << 11) |
| 948 | #define PORT_P0_IRNENSET_EXINT4_VAL(val) (((val) & 0x1) << 11) |
| 949 | #define PORT_P0_IRNENSET_EXINT4_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT4) | (val) & 1) << 11) |
| 950 | /* Set Interrupt Node Enable Flag EXINT3 (10) */ |
| 951 | #define PORT_P0_IRNENSET_EXINT3 (0x1 << 10) |
| 952 | #define PORT_P0_IRNENSET_EXINT3_VAL(val) (((val) & 0x1) << 10) |
| 953 | #define PORT_P0_IRNENSET_EXINT3_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT3) | (val) & 1) << 10) |
| 954 | /* Set Interrupt Node Enable Flag EXINT2 (9) */ |
| 955 | #define PORT_P0_IRNENSET_EXINT2 (0x1 << 9) |
| 956 | #define PORT_P0_IRNENSET_EXINT2_VAL(val) (((val) & 0x1) << 9) |
| 957 | #define PORT_P0_IRNENSET_EXINT2_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT2) | (val) & 1) << 9) |
| 958 | /* Set Interrupt Node Enable Flag EXINT1 (8) */ |
| 959 | #define PORT_P0_IRNENSET_EXINT1 (0x1 << 8) |
| 960 | #define PORT_P0_IRNENSET_EXINT1_VAL(val) (((val) & 0x1) << 8) |
| 961 | #define PORT_P0_IRNENSET_EXINT1_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT1) | (val) & 1) << 8) |
| 962 | /* Set Interrupt Node Enable Flag EXINT0 (7) */ |
| 963 | #define PORT_P0_IRNENSET_EXINT0 (0x1 << 7) |
| 964 | #define PORT_P0_IRNENSET_EXINT0_VAL(val) (((val) & 0x1) << 7) |
| 965 | #define PORT_P0_IRNENSET_EXINT0_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT0) | (val) & 1) << 7) |
| 966 | |
| 967 | /******************************************************************************* |
| 968 | * P0_IRNENCLR Register |
| 969 | ******************************************************************************/ |
| 970 | |
| 971 | /* Clear Interrupt Node Enable Flag EXINT16 (19) */ |
| 972 | #define PORT_P0_IRNENCLR_EXINT16 (0x1 << 19) |
| 973 | #define PORT_P0_IRNENCLR_EXINT16_VAL(val) (((val) & 0x1) << 19) |
| 974 | #define PORT_P0_IRNENCLR_EXINT16_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT16) | (val) & 1) << 19) |
| 975 | /* Clear Interrupt Node Enable Flag EXINT10 (17) */ |
| 976 | #define PORT_P0_IRNENCLR_EXINT10 (0x1 << 17) |
| 977 | #define PORT_P0_IRNENCLR_EXINT10_VAL(val) (((val) & 0x1) << 17) |
| 978 | #define PORT_P0_IRNENCLR_EXINT10_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT10) | (val) & 1) << 17) |
| 979 | /* Clear Interrupt Node Enable Flag EXINT9 (16) */ |
| 980 | #define PORT_P0_IRNENCLR_EXINT9 (0x1 << 16) |
| 981 | #define PORT_P0_IRNENCLR_EXINT9_VAL(val) (((val) & 0x1) << 16) |
| 982 | #define PORT_P0_IRNENCLR_EXINT9_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT9) | (val) & 1) << 16) |
| 983 | /* Clear Interrupt Node Enable Flag EXINT8 (15) */ |
| 984 | #define PORT_P0_IRNENCLR_EXINT8 (0x1 << 15) |
| 985 | #define PORT_P0_IRNENCLR_EXINT8_VAL(val) (((val) & 0x1) << 15) |
| 986 | #define PORT_P0_IRNENCLR_EXINT8_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT8) | (val) & 1) << 15) |
| 987 | /* Clear Interrupt Node Enable Flag EXINT7 (14) */ |
| 988 | #define PORT_P0_IRNENCLR_EXINT7 (0x1 << 14) |
| 989 | #define PORT_P0_IRNENCLR_EXINT7_VAL(val) (((val) & 0x1) << 14) |
| 990 | #define PORT_P0_IRNENCLR_EXINT7_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT7) | (val) & 1) << 14) |
| 991 | /* Clear Interrupt Node Enable Flag EXINT6 (13) */ |
| 992 | #define PORT_P0_IRNENCLR_EXINT6 (0x1 << 13) |
| 993 | #define PORT_P0_IRNENCLR_EXINT6_VAL(val) (((val) & 0x1) << 13) |
| 994 | #define PORT_P0_IRNENCLR_EXINT6_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT6) | (val) & 1) << 13) |
| 995 | /* Clear Interrupt Node Enable Flag EXINT5 (12) */ |
| 996 | #define PORT_P0_IRNENCLR_EXINT5 (0x1 << 12) |
| 997 | #define PORT_P0_IRNENCLR_EXINT5_VAL(val) (((val) & 0x1) << 12) |
| 998 | #define PORT_P0_IRNENCLR_EXINT5_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT5) | (val) & 1) << 12) |
| 999 | /* Clear Interrupt Node Enable Flag EXINT4 (11) */ |
| 1000 | #define PORT_P0_IRNENCLR_EXINT4 (0x1 << 11) |
| 1001 | #define PORT_P0_IRNENCLR_EXINT4_VAL(val) (((val) & 0x1) << 11) |
| 1002 | #define PORT_P0_IRNENCLR_EXINT4_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT4) | (val) & 1) << 11) |
| 1003 | /* Clear Interrupt Node Enable Flag EXINT3 (10) */ |
| 1004 | #define PORT_P0_IRNENCLR_EXINT3 (0x1 << 10) |
| 1005 | #define PORT_P0_IRNENCLR_EXINT3_VAL(val) (((val) & 0x1) << 10) |
| 1006 | #define PORT_P0_IRNENCLR_EXINT3_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT3) | (val) & 1) << 10) |
| 1007 | /* Clear Interrupt Node Enable Flag EXINT2 (9) */ |
| 1008 | #define PORT_P0_IRNENCLR_EXINT2 (0x1 << 9) |
| 1009 | #define PORT_P0_IRNENCLR_EXINT2_VAL(val) (((val) & 0x1) << 9) |
| 1010 | #define PORT_P0_IRNENCLR_EXINT2_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT2) | (val) & 1) << 9) |
| 1011 | /* Clear Interrupt Node Enable Flag EXINT1 (8) */ |
| 1012 | #define PORT_P0_IRNENCLR_EXINT1 (0x1 << 8) |
| 1013 | #define PORT_P0_IRNENCLR_EXINT1_VAL(val) (((val) & 0x1) << 8) |
| 1014 | #define PORT_P0_IRNENCLR_EXINT1_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT1) | (val) & 1) << 8) |
| 1015 | /* Clear Interrupt Node Enable Flag EXINT0 (7) */ |
| 1016 | #define PORT_P0_IRNENCLR_EXINT0 (0x1 << 7) |
| 1017 | #define PORT_P0_IRNENCLR_EXINT0_VAL(val) (((val) & 0x1) << 7) |
| 1018 | #define PORT_P0_IRNENCLR_EXINT0_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT0) | (val) & 1) << 7) |
| 1019 | |
| 1020 | /******************************************************************************* |
| 1021 | * Port 1 Data Output Register |
| 1022 | ******************************************************************************/ |
| 1023 | |
| 1024 | /* Port 1 Pin # Output Value (19) */ |
| 1025 | #define PORT_P1_OUT_P19 (0x1 << 19) |
| 1026 | #define PORT_P1_OUT_P19_VAL(val) (((val) & 0x1) << 19) |
| 1027 | #define PORT_P1_OUT_P19_GET(val) ((((val) & PORT_P1_OUT_P19) >> 19) & 0x1) |
| 1028 | #define PORT_P1_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P19) | (((val) & 0x1) << 19)) |
| 1029 | /* Port 1 Pin # Output Value (18) */ |
| 1030 | #define PORT_P1_OUT_P18 (0x1 << 18) |
| 1031 | #define PORT_P1_OUT_P18_VAL(val) (((val) & 0x1) << 18) |
| 1032 | #define PORT_P1_OUT_P18_GET(val) ((((val) & PORT_P1_OUT_P18) >> 18) & 0x1) |
| 1033 | #define PORT_P1_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P18) | (((val) & 0x1) << 18)) |
| 1034 | /* Port 1 Pin # Output Value (17) */ |
| 1035 | #define PORT_P1_OUT_P17 (0x1 << 17) |
| 1036 | #define PORT_P1_OUT_P17_VAL(val) (((val) & 0x1) << 17) |
| 1037 | #define PORT_P1_OUT_P17_GET(val) ((((val) & PORT_P1_OUT_P17) >> 17) & 0x1) |
| 1038 | #define PORT_P1_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P17) | (((val) & 0x1) << 17)) |
| 1039 | /* Port 1 Pin # Output Value (16) */ |
| 1040 | #define PORT_P1_OUT_P16 (0x1 << 16) |
| 1041 | #define PORT_P1_OUT_P16_VAL(val) (((val) & 0x1) << 16) |
| 1042 | #define PORT_P1_OUT_P16_GET(val) ((((val) & PORT_P1_OUT_P16) >> 16) & 0x1) |
| 1043 | #define PORT_P1_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P16) | (((val) & 0x1) << 16)) |
| 1044 | /* Port 1 Pin # Output Value (15) */ |
| 1045 | #define PORT_P1_OUT_P15 (0x1 << 15) |
| 1046 | #define PORT_P1_OUT_P15_VAL(val) (((val) & 0x1) << 15) |
| 1047 | #define PORT_P1_OUT_P15_GET(val) ((((val) & PORT_P1_OUT_P15) >> 15) & 0x1) |
| 1048 | #define PORT_P1_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P15) | (((val) & 0x1) << 15)) |
| 1049 | /* Port 1 Pin # Output Value (14) */ |
| 1050 | #define PORT_P1_OUT_P14 (0x1 << 14) |
| 1051 | #define PORT_P1_OUT_P14_VAL(val) (((val) & 0x1) << 14) |
| 1052 | #define PORT_P1_OUT_P14_GET(val) ((((val) & PORT_P1_OUT_P14) >> 14) & 0x1) |
| 1053 | #define PORT_P1_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P14) | (((val) & 0x1) << 14)) |
| 1054 | /* Port 1 Pin # Output Value (13) */ |
| 1055 | #define PORT_P1_OUT_P13 (0x1 << 13) |
| 1056 | #define PORT_P1_OUT_P13_VAL(val) (((val) & 0x1) << 13) |
| 1057 | #define PORT_P1_OUT_P13_GET(val) ((((val) & PORT_P1_OUT_P13) >> 13) & 0x1) |
| 1058 | #define PORT_P1_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P13) | (((val) & 0x1) << 13)) |
| 1059 | /* Port 1 Pin # Output Value (12) */ |
| 1060 | #define PORT_P1_OUT_P12 (0x1 << 12) |
| 1061 | #define PORT_P1_OUT_P12_VAL(val) (((val) & 0x1) << 12) |
| 1062 | #define PORT_P1_OUT_P12_GET(val) ((((val) & PORT_P1_OUT_P12) >> 12) & 0x1) |
| 1063 | #define PORT_P1_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P12) | (((val) & 0x1) << 12)) |
| 1064 | /* Port 1 Pin # Output Value (11) */ |
| 1065 | #define PORT_P1_OUT_P11 (0x1 << 11) |
| 1066 | #define PORT_P1_OUT_P11_VAL(val) (((val) & 0x1) << 11) |
| 1067 | #define PORT_P1_OUT_P11_GET(val) ((((val) & PORT_P1_OUT_P11) >> 11) & 0x1) |
| 1068 | #define PORT_P1_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P11) | (((val) & 0x1) << 11)) |
| 1069 | /* Port 1 Pin # Output Value (10) */ |
| 1070 | #define PORT_P1_OUT_P10 (0x1 << 10) |
| 1071 | #define PORT_P1_OUT_P10_VAL(val) (((val) & 0x1) << 10) |
| 1072 | #define PORT_P1_OUT_P10_GET(val) ((((val) & PORT_P1_OUT_P10) >> 10) & 0x1) |
| 1073 | #define PORT_P1_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P10) | (((val) & 0x1) << 10)) |
| 1074 | /* Port 1 Pin # Output Value (9) */ |
| 1075 | #define PORT_P1_OUT_P9 (0x1 << 9) |
| 1076 | #define PORT_P1_OUT_P9_VAL(val) (((val) & 0x1) << 9) |
| 1077 | #define PORT_P1_OUT_P9_GET(val) ((((val) & PORT_P1_OUT_P9) >> 9) & 0x1) |
| 1078 | #define PORT_P1_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P9) | (((val) & 0x1) << 9)) |
| 1079 | /* Port 1 Pin # Output Value (8) */ |
| 1080 | #define PORT_P1_OUT_P8 (0x1 << 8) |
| 1081 | #define PORT_P1_OUT_P8_VAL(val) (((val) & 0x1) << 8) |
| 1082 | #define PORT_P1_OUT_P8_GET(val) ((((val) & PORT_P1_OUT_P8) >> 8) & 0x1) |
| 1083 | #define PORT_P1_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P8) | (((val) & 0x1) << 8)) |
| 1084 | /* Port 1 Pin # Output Value (7) */ |
| 1085 | #define PORT_P1_OUT_P7 (0x1 << 7) |
| 1086 | #define PORT_P1_OUT_P7_VAL(val) (((val) & 0x1) << 7) |
| 1087 | #define PORT_P1_OUT_P7_GET(val) ((((val) & PORT_P1_OUT_P7) >> 7) & 0x1) |
| 1088 | #define PORT_P1_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P7) | (((val) & 0x1) << 7)) |
| 1089 | /* Port 1 Pin # Output Value (6) */ |
| 1090 | #define PORT_P1_OUT_P6 (0x1 << 6) |
| 1091 | #define PORT_P1_OUT_P6_VAL(val) (((val) & 0x1) << 6) |
| 1092 | #define PORT_P1_OUT_P6_GET(val) ((((val) & PORT_P1_OUT_P6) >> 6) & 0x1) |
| 1093 | #define PORT_P1_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P6) | (((val) & 0x1) << 6)) |
| 1094 | /* Port 1 Pin # Output Value (5) */ |
| 1095 | #define PORT_P1_OUT_P5 (0x1 << 5) |
| 1096 | #define PORT_P1_OUT_P5_VAL(val) (((val) & 0x1) << 5) |
| 1097 | #define PORT_P1_OUT_P5_GET(val) ((((val) & PORT_P1_OUT_P5) >> 5) & 0x1) |
| 1098 | #define PORT_P1_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P5) | (((val) & 0x1) << 5)) |
| 1099 | /* Port 1 Pin # Output Value (4) */ |
| 1100 | #define PORT_P1_OUT_P4 (0x1 << 4) |
| 1101 | #define PORT_P1_OUT_P4_VAL(val) (((val) & 0x1) << 4) |
| 1102 | #define PORT_P1_OUT_P4_GET(val) ((((val) & PORT_P1_OUT_P4) >> 4) & 0x1) |
| 1103 | #define PORT_P1_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P4) | (((val) & 0x1) << 4)) |
| 1104 | /* Port 1 Pin # Output Value (3) */ |
| 1105 | #define PORT_P1_OUT_P3 (0x1 << 3) |
| 1106 | #define PORT_P1_OUT_P3_VAL(val) (((val) & 0x1) << 3) |
| 1107 | #define PORT_P1_OUT_P3_GET(val) ((((val) & PORT_P1_OUT_P3) >> 3) & 0x1) |
| 1108 | #define PORT_P1_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P3) | (((val) & 0x1) << 3)) |
| 1109 | /* Port 1 Pin # Output Value (2) */ |
| 1110 | #define PORT_P1_OUT_P2 (0x1 << 2) |
| 1111 | #define PORT_P1_OUT_P2_VAL(val) (((val) & 0x1) << 2) |
| 1112 | #define PORT_P1_OUT_P2_GET(val) ((((val) & PORT_P1_OUT_P2) >> 2) & 0x1) |
| 1113 | #define PORT_P1_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P2) | (((val) & 0x1) << 2)) |
| 1114 | /* Port 1 Pin # Output Value (1) */ |
| 1115 | #define PORT_P1_OUT_P1 (0x1 << 1) |
| 1116 | #define PORT_P1_OUT_P1_VAL(val) (((val) & 0x1) << 1) |
| 1117 | #define PORT_P1_OUT_P1_GET(val) ((((val) & PORT_P1_OUT_P1) >> 1) & 0x1) |
| 1118 | #define PORT_P1_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P1) | (((val) & 0x1) << 1)) |
| 1119 | /* Port 1 Pin # Output Value (0) */ |
| 1120 | #define PORT_P1_OUT_P0 (0x1) |
| 1121 | #define PORT_P1_OUT_P0_VAL(val) (((val) & 0x1) << 0) |
| 1122 | #define PORT_P1_OUT_P0_GET(val) ((((val) & PORT_P1_OUT_P0) >> 0) & 0x1) |
| 1123 | #define PORT_P1_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P0) | (((val) & 0x1) << 0)) |
| 1124 | |
| 1125 | /******************************************************************************* |
| 1126 | * Port 1 Data Input Register |
| 1127 | ******************************************************************************/ |
| 1128 | |
| 1129 | /* Port 1 Pin # Latched Input Value (19) */ |
| 1130 | #define PORT_P1_IN_P19 (0x1 << 19) |
| 1131 | #define PORT_P1_IN_P19_GET(val) ((((val) & PORT_P1_IN_P19) >> 19) & 0x1) |
| 1132 | /* Port 1 Pin # Latched Input Value (18) */ |
| 1133 | #define PORT_P1_IN_P18 (0x1 << 18) |
| 1134 | #define PORT_P1_IN_P18_GET(val) ((((val) & PORT_P1_IN_P18) >> 18) & 0x1) |
| 1135 | /* Port 1 Pin # Latched Input Value (17) */ |
| 1136 | #define PORT_P1_IN_P17 (0x1 << 17) |
| 1137 | #define PORT_P1_IN_P17_GET(val) ((((val) & PORT_P1_IN_P17) >> 17) & 0x1) |
| 1138 | /* Port 1 Pin # Latched Input Value (16) */ |
| 1139 | #define PORT_P1_IN_P16 (0x1 << 16) |
| 1140 | #define PORT_P1_IN_P16_GET(val) ((((val) & PORT_P1_IN_P16) >> 16) & 0x1) |
| 1141 | /* Port 1 Pin # Latched Input Value (15) */ |
| 1142 | #define PORT_P1_IN_P15 (0x1 << 15) |
| 1143 | #define PORT_P1_IN_P15_GET(val) ((((val) & PORT_P1_IN_P15) >> 15) & 0x1) |
| 1144 | /* Port 1 Pin # Latched Input Value (14) */ |
| 1145 | #define PORT_P1_IN_P14 (0x1 << 14) |
| 1146 | #define PORT_P1_IN_P14_GET(val) ((((val) & PORT_P1_IN_P14) >> 14) & 0x1) |
| 1147 | /* Port 1 Pin # Latched Input Value (13) */ |
| 1148 | #define PORT_P1_IN_P13 (0x1 << 13) |
| 1149 | #define PORT_P1_IN_P13_GET(val) ((((val) & PORT_P1_IN_P13) >> 13) & 0x1) |
| 1150 | /* Port 1 Pin # Latched Input Value (12) */ |
| 1151 | #define PORT_P1_IN_P12 (0x1 << 12) |
| 1152 | #define PORT_P1_IN_P12_GET(val) ((((val) & PORT_P1_IN_P12) >> 12) & 0x1) |
| 1153 | /* Port 1 Pin # Latched Input Value (11) */ |
| 1154 | #define PORT_P1_IN_P11 (0x1 << 11) |
| 1155 | #define PORT_P1_IN_P11_GET(val) ((((val) & PORT_P1_IN_P11) >> 11) & 0x1) |
| 1156 | /* Port 1 Pin # Latched Input Value (10) */ |
| 1157 | #define PORT_P1_IN_P10 (0x1 << 10) |
| 1158 | #define PORT_P1_IN_P10_GET(val) ((((val) & PORT_P1_IN_P10) >> 10) & 0x1) |
| 1159 | /* Port 1 Pin # Latched Input Value (9) */ |
| 1160 | #define PORT_P1_IN_P9 (0x1 << 9) |
| 1161 | #define PORT_P1_IN_P9_GET(val) ((((val) & PORT_P1_IN_P9) >> 9) & 0x1) |
| 1162 | /* Port 1 Pin # Latched Input Value (8) */ |
| 1163 | #define PORT_P1_IN_P8 (0x1 << 8) |
| 1164 | #define PORT_P1_IN_P8_GET(val) ((((val) & PORT_P1_IN_P8) >> 8) & 0x1) |
| 1165 | /* Port 1 Pin # Latched Input Value (7) */ |
| 1166 | #define PORT_P1_IN_P7 (0x1 << 7) |
| 1167 | #define PORT_P1_IN_P7_GET(val) ((((val) & PORT_P1_IN_P7) >> 7) & 0x1) |
| 1168 | /* Port 1 Pin # Latched Input Value (6) */ |
| 1169 | #define PORT_P1_IN_P6 (0x1 << 6) |
| 1170 | #define PORT_P1_IN_P6_GET(val) ((((val) & PORT_P1_IN_P6) >> 6) & 0x1) |
| 1171 | /* Port 1 Pin # Latched Input Value (5) */ |
| 1172 | #define PORT_P1_IN_P5 (0x1 << 5) |
| 1173 | #define PORT_P1_IN_P5_GET(val) ((((val) & PORT_P1_IN_P5) >> 5) & 0x1) |
| 1174 | /* Port 1 Pin # Latched Input Value (4) */ |
| 1175 | #define PORT_P1_IN_P4 (0x1 << 4) |
| 1176 | #define PORT_P1_IN_P4_GET(val) ((((val) & PORT_P1_IN_P4) >> 4) & 0x1) |
| 1177 | /* Port 1 Pin # Latched Input Value (3) */ |
| 1178 | #define PORT_P1_IN_P3 (0x1 << 3) |
| 1179 | #define PORT_P1_IN_P3_GET(val) ((((val) & PORT_P1_IN_P3) >> 3) & 0x1) |
| 1180 | /* Port 1 Pin # Latched Input Value (2) */ |
| 1181 | #define PORT_P1_IN_P2 (0x1 << 2) |
| 1182 | #define PORT_P1_IN_P2_GET(val) ((((val) & PORT_P1_IN_P2) >> 2) & 0x1) |
| 1183 | /* Port 1 Pin # Latched Input Value (1) */ |
| 1184 | #define PORT_P1_IN_P1 (0x1 << 1) |
| 1185 | #define PORT_P1_IN_P1_GET(val) ((((val) & PORT_P1_IN_P1) >> 1) & 0x1) |
| 1186 | /* Port 1 Pin # Latched Input Value (0) */ |
| 1187 | #define PORT_P1_IN_P0 (0x1) |
| 1188 | #define PORT_P1_IN_P0_GET(val) ((((val) & PORT_P1_IN_P0) >> 0) & 0x1) |
| 1189 | |
| 1190 | /******************************************************************************* |
| 1191 | * Port 1 Direction Register |
| 1192 | ******************************************************************************/ |
| 1193 | |
| 1194 | /* Port 1 Pin #Direction Control (19) */ |
| 1195 | #define PORT_P1_DIR_P19 (0x1 << 19) |
| 1196 | #define PORT_P1_DIR_P19_VAL(val) (((val) & 0x1) << 19) |
| 1197 | #define PORT_P1_DIR_P19_GET(val) ((((val) & PORT_P1_DIR_P19) >> 19) & 0x1) |
| 1198 | #define PORT_P1_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P19) | (((val) & 0x1) << 19)) |
| 1199 | /* Port 1 Pin #Direction Control (18) */ |
| 1200 | #define PORT_P1_DIR_P18 (0x1 << 18) |
| 1201 | #define PORT_P1_DIR_P18_VAL(val) (((val) & 0x1) << 18) |
| 1202 | #define PORT_P1_DIR_P18_GET(val) ((((val) & PORT_P1_DIR_P18) >> 18) & 0x1) |
| 1203 | #define PORT_P1_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P18) | (((val) & 0x1) << 18)) |
| 1204 | /* Port 1 Pin #Direction Control (17) */ |
| 1205 | #define PORT_P1_DIR_P17 (0x1 << 17) |
| 1206 | #define PORT_P1_DIR_P17_VAL(val) (((val) & 0x1) << 17) |
| 1207 | #define PORT_P1_DIR_P17_GET(val) ((((val) & PORT_P1_DIR_P17) >> 17) & 0x1) |
| 1208 | #define PORT_P1_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P17) | (((val) & 0x1) << 17)) |
| 1209 | /* Port 1 Pin #Direction Control (16) */ |
| 1210 | #define PORT_P1_DIR_P16 (0x1 << 16) |
| 1211 | #define PORT_P1_DIR_P16_VAL(val) (((val) & 0x1) << 16) |
| 1212 | #define PORT_P1_DIR_P16_GET(val) ((((val) & PORT_P1_DIR_P16) >> 16) & 0x1) |
| 1213 | #define PORT_P1_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P16) | (((val) & 0x1) << 16)) |
| 1214 | /* Port 1 Pin #Direction Control (15) */ |
| 1215 | #define PORT_P1_DIR_P15 (0x1 << 15) |
| 1216 | #define PORT_P1_DIR_P15_VAL(val) (((val) & 0x1) << 15) |
| 1217 | #define PORT_P1_DIR_P15_GET(val) ((((val) & PORT_P1_DIR_P15) >> 15) & 0x1) |
| 1218 | #define PORT_P1_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P15) | (((val) & 0x1) << 15)) |
| 1219 | /* Port 1 Pin #Direction Control (14) */ |
| 1220 | #define PORT_P1_DIR_P14 (0x1 << 14) |
| 1221 | #define PORT_P1_DIR_P14_VAL(val) (((val) & 0x1) << 14) |
| 1222 | #define PORT_P1_DIR_P14_GET(val) ((((val) & PORT_P1_DIR_P14) >> 14) & 0x1) |
| 1223 | #define PORT_P1_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P14) | (((val) & 0x1) << 14)) |
| 1224 | /* Port 1 Pin #Direction Control (13) */ |
| 1225 | #define PORT_P1_DIR_P13 (0x1 << 13) |
| 1226 | #define PORT_P1_DIR_P13_VAL(val) (((val) & 0x1) << 13) |
| 1227 | #define PORT_P1_DIR_P13_GET(val) ((((val) & PORT_P1_DIR_P13) >> 13) & 0x1) |
| 1228 | #define PORT_P1_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P13) | (((val) & 0x1) << 13)) |
| 1229 | /* Port 1 Pin #Direction Control (12) */ |
| 1230 | #define PORT_P1_DIR_P12 (0x1 << 12) |
| 1231 | #define PORT_P1_DIR_P12_VAL(val) (((val) & 0x1) << 12) |
| 1232 | #define PORT_P1_DIR_P12_GET(val) ((((val) & PORT_P1_DIR_P12) >> 12) & 0x1) |
| 1233 | #define PORT_P1_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P12) | (((val) & 0x1) << 12)) |
| 1234 | /* Port 1 Pin #Direction Control (11) */ |
| 1235 | #define PORT_P1_DIR_P11 (0x1 << 11) |
| 1236 | #define PORT_P1_DIR_P11_VAL(val) (((val) & 0x1) << 11) |
| 1237 | #define PORT_P1_DIR_P11_GET(val) ((((val) & PORT_P1_DIR_P11) >> 11) & 0x1) |
| 1238 | #define PORT_P1_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P11) | (((val) & 0x1) << 11)) |
| 1239 | /* Port 1 Pin #Direction Control (10) */ |
| 1240 | #define PORT_P1_DIR_P10 (0x1 << 10) |
| 1241 | #define PORT_P1_DIR_P10_VAL(val) (((val) & 0x1) << 10) |
| 1242 | #define PORT_P1_DIR_P10_GET(val) ((((val) & PORT_P1_DIR_P10) >> 10) & 0x1) |
| 1243 | #define PORT_P1_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P10) | (((val) & 0x1) << 10)) |
| 1244 | /* Port 1 Pin #Direction Control (9) */ |
| 1245 | #define PORT_P1_DIR_P9 (0x1 << 9) |
| 1246 | #define PORT_P1_DIR_P9_VAL(val) (((val) & 0x1) << 9) |
| 1247 | #define PORT_P1_DIR_P9_GET(val) ((((val) & PORT_P1_DIR_P9) >> 9) & 0x1) |
| 1248 | #define PORT_P1_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P9) | (((val) & 0x1) << 9)) |
| 1249 | /* Port 1 Pin #Direction Control (8) */ |
| 1250 | #define PORT_P1_DIR_P8 (0x1 << 8) |
| 1251 | #define PORT_P1_DIR_P8_VAL(val) (((val) & 0x1) << 8) |
| 1252 | #define PORT_P1_DIR_P8_GET(val) ((((val) & PORT_P1_DIR_P8) >> 8) & 0x1) |
| 1253 | #define PORT_P1_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P8) | (((val) & 0x1) << 8)) |
| 1254 | /* Port 1 Pin #Direction Control (7) */ |
| 1255 | #define PORT_P1_DIR_P7 (0x1 << 7) |
| 1256 | #define PORT_P1_DIR_P7_VAL(val) (((val) & 0x1) << 7) |
| 1257 | #define PORT_P1_DIR_P7_GET(val) ((((val) & PORT_P1_DIR_P7) >> 7) & 0x1) |
| 1258 | #define PORT_P1_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P7) | (((val) & 0x1) << 7)) |
| 1259 | /* Port 1 Pin #Direction Control (6) */ |
| 1260 | #define PORT_P1_DIR_P6 (0x1 << 6) |
| 1261 | #define PORT_P1_DIR_P6_VAL(val) (((val) & 0x1) << 6) |
| 1262 | #define PORT_P1_DIR_P6_GET(val) ((((val) & PORT_P1_DIR_P6) >> 6) & 0x1) |
| 1263 | #define PORT_P1_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P6) | (((val) & 0x1) << 6)) |
| 1264 | /* Port 1 Pin #Direction Control (5) */ |
| 1265 | #define PORT_P1_DIR_P5 (0x1 << 5) |
| 1266 | #define PORT_P1_DIR_P5_VAL(val) (((val) & 0x1) << 5) |
| 1267 | #define PORT_P1_DIR_P5_GET(val) ((((val) & PORT_P1_DIR_P5) >> 5) & 0x1) |
| 1268 | #define PORT_P1_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P5) | (((val) & 0x1) << 5)) |
| 1269 | /* Port 1 Pin #Direction Control (4) */ |
| 1270 | #define PORT_P1_DIR_P4 (0x1 << 4) |
| 1271 | #define PORT_P1_DIR_P4_VAL(val) (((val) & 0x1) << 4) |
| 1272 | #define PORT_P1_DIR_P4_GET(val) ((((val) & PORT_P1_DIR_P4) >> 4) & 0x1) |
| 1273 | #define PORT_P1_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P4) | (((val) & 0x1) << 4)) |
| 1274 | /* Port 1 Pin #Direction Control (3) */ |
| 1275 | #define PORT_P1_DIR_P3 (0x1 << 3) |
| 1276 | #define PORT_P1_DIR_P3_VAL(val) (((val) & 0x1) << 3) |
| 1277 | #define PORT_P1_DIR_P3_GET(val) ((((val) & PORT_P1_DIR_P3) >> 3) & 0x1) |
| 1278 | #define PORT_P1_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P3) | (((val) & 0x1) << 3)) |
| 1279 | /* Port 1 Pin #Direction Control (2) */ |
| 1280 | #define PORT_P1_DIR_P2 (0x1 << 2) |
| 1281 | #define PORT_P1_DIR_P2_VAL(val) (((val) & 0x1) << 2) |
| 1282 | #define PORT_P1_DIR_P2_GET(val) ((((val) & PORT_P1_DIR_P2) >> 2) & 0x1) |
| 1283 | #define PORT_P1_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P2) | (((val) & 0x1) << 2)) |
| 1284 | /* Port 1 Pin #Direction Control (1) */ |
| 1285 | #define PORT_P1_DIR_P1 (0x1 << 1) |
| 1286 | #define PORT_P1_DIR_P1_VAL(val) (((val) & 0x1) << 1) |
| 1287 | #define PORT_P1_DIR_P1_GET(val) ((((val) & PORT_P1_DIR_P1) >> 1) & 0x1) |
| 1288 | #define PORT_P1_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P1) | (((val) & 0x1) << 1)) |
| 1289 | /* Port 1 Pin #Direction Control (0) */ |
| 1290 | #define PORT_P1_DIR_P0 (0x1) |
| 1291 | #define PORT_P1_DIR_P0_VAL(val) (((val) & 0x1) << 0) |
| 1292 | #define PORT_P1_DIR_P0_GET(val) ((((val) & PORT_P1_DIR_P0) >> 0) & 0x1) |
| 1293 | #define PORT_P1_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P0) | (((val) & 0x1) << 0)) |
| 1294 | |
| 1295 | /******************************************************************************* |
| 1296 | * Port 1 Alternate Function Select Register 0 |
| 1297 | ******************************************************************************/ |
| 1298 | |
| 1299 | /* Alternate Function at Port 1 Bit # (19) */ |
| 1300 | #define PORT_P1_ALTSEL0_P19 (0x1 << 19) |
| 1301 | #define PORT_P1_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) |
| 1302 | #define PORT_P1_ALTSEL0_P19_GET(val) ((((val) & PORT_P1_ALTSEL0_P19) >> 19) & 0x1) |
| 1303 | #define PORT_P1_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P19) | (((val) & 0x1) << 19)) |
| 1304 | /* Alternate Function at Port 1 Bit # (18) */ |
| 1305 | #define PORT_P1_ALTSEL0_P18 (0x1 << 18) |
| 1306 | #define PORT_P1_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) |
| 1307 | #define PORT_P1_ALTSEL0_P18_GET(val) ((((val) & PORT_P1_ALTSEL0_P18) >> 18) & 0x1) |
| 1308 | #define PORT_P1_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P18) | (((val) & 0x1) << 18)) |
| 1309 | /* Alternate Function at Port 1 Bit # (17) */ |
| 1310 | #define PORT_P1_ALTSEL0_P17 (0x1 << 17) |
| 1311 | #define PORT_P1_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) |
| 1312 | #define PORT_P1_ALTSEL0_P17_GET(val) ((((val) & PORT_P1_ALTSEL0_P17) >> 17) & 0x1) |
| 1313 | #define PORT_P1_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P17) | (((val) & 0x1) << 17)) |
| 1314 | /* Alternate Function at Port 1 Bit # (16) */ |
| 1315 | #define PORT_P1_ALTSEL0_P16 (0x1 << 16) |
| 1316 | #define PORT_P1_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) |
| 1317 | #define PORT_P1_ALTSEL0_P16_GET(val) ((((val) & PORT_P1_ALTSEL0_P16) >> 16) & 0x1) |
| 1318 | #define PORT_P1_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P16) | (((val) & 0x1) << 16)) |
| 1319 | /* Alternate Function at Port 1 Bit # (15) */ |
| 1320 | #define PORT_P1_ALTSEL0_P15 (0x1 << 15) |
| 1321 | #define PORT_P1_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) |
| 1322 | #define PORT_P1_ALTSEL0_P15_GET(val) ((((val) & PORT_P1_ALTSEL0_P15) >> 15) & 0x1) |
| 1323 | #define PORT_P1_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P15) | (((val) & 0x1) << 15)) |
| 1324 | /* Alternate Function at Port 1 Bit # (14) */ |
| 1325 | #define PORT_P1_ALTSEL0_P14 (0x1 << 14) |
| 1326 | #define PORT_P1_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) |
| 1327 | #define PORT_P1_ALTSEL0_P14_GET(val) ((((val) & PORT_P1_ALTSEL0_P14) >> 14) & 0x1) |
| 1328 | #define PORT_P1_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P14) | (((val) & 0x1) << 14)) |
| 1329 | /* Alternate Function at Port 1 Bit # (13) */ |
| 1330 | #define PORT_P1_ALTSEL0_P13 (0x1 << 13) |
| 1331 | #define PORT_P1_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) |
| 1332 | #define PORT_P1_ALTSEL0_P13_GET(val) ((((val) & PORT_P1_ALTSEL0_P13) >> 13) & 0x1) |
| 1333 | #define PORT_P1_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P13) | (((val) & 0x1) << 13)) |
| 1334 | /* Alternate Function at Port 1 Bit # (12) */ |
| 1335 | #define PORT_P1_ALTSEL0_P12 (0x1 << 12) |
| 1336 | #define PORT_P1_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) |
| 1337 | #define PORT_P1_ALTSEL0_P12_GET(val) ((((val) & PORT_P1_ALTSEL0_P12) >> 12) & 0x1) |
| 1338 | #define PORT_P1_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P12) | (((val) & 0x1) << 12)) |
| 1339 | /* Alternate Function at Port 1 Bit # (11) */ |
| 1340 | #define PORT_P1_ALTSEL0_P11 (0x1 << 11) |
| 1341 | #define PORT_P1_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) |
| 1342 | #define PORT_P1_ALTSEL0_P11_GET(val) ((((val) & PORT_P1_ALTSEL0_P11) >> 11) & 0x1) |
| 1343 | #define PORT_P1_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P11) | (((val) & 0x1) << 11)) |
| 1344 | /* Alternate Function at Port 1 Bit # (10) */ |
| 1345 | #define PORT_P1_ALTSEL0_P10 (0x1 << 10) |
| 1346 | #define PORT_P1_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) |
| 1347 | #define PORT_P1_ALTSEL0_P10_GET(val) ((((val) & PORT_P1_ALTSEL0_P10) >> 10) & 0x1) |
| 1348 | #define PORT_P1_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P10) | (((val) & 0x1) << 10)) |
| 1349 | /* Alternate Function at Port 1 Bit # (9) */ |
| 1350 | #define PORT_P1_ALTSEL0_P9 (0x1 << 9) |
| 1351 | #define PORT_P1_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) |
| 1352 | #define PORT_P1_ALTSEL0_P9_GET(val) ((((val) & PORT_P1_ALTSEL0_P9) >> 9) & 0x1) |
| 1353 | #define PORT_P1_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P9) | (((val) & 0x1) << 9)) |
| 1354 | /* Alternate Function at Port 1 Bit # (8) */ |
| 1355 | #define PORT_P1_ALTSEL0_P8 (0x1 << 8) |
| 1356 | #define PORT_P1_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) |
| 1357 | #define PORT_P1_ALTSEL0_P8_GET(val) ((((val) & PORT_P1_ALTSEL0_P8) >> 8) & 0x1) |
| 1358 | #define PORT_P1_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P8) | (((val) & 0x1) << 8)) |
| 1359 | /* Alternate Function at Port 1 Bit # (7) */ |
| 1360 | #define PORT_P1_ALTSEL0_P7 (0x1 << 7) |
| 1361 | #define PORT_P1_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) |
| 1362 | #define PORT_P1_ALTSEL0_P7_GET(val) ((((val) & PORT_P1_ALTSEL0_P7) >> 7) & 0x1) |
| 1363 | #define PORT_P1_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P7) | (((val) & 0x1) << 7)) |
| 1364 | /* Alternate Function at Port 1 Bit # (6) */ |
| 1365 | #define PORT_P1_ALTSEL0_P6 (0x1 << 6) |
| 1366 | #define PORT_P1_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) |
| 1367 | #define PORT_P1_ALTSEL0_P6_GET(val) ((((val) & PORT_P1_ALTSEL0_P6) >> 6) & 0x1) |
| 1368 | #define PORT_P1_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P6) | (((val) & 0x1) << 6)) |
| 1369 | /* Alternate Function at Port 1 Bit # (5) */ |
| 1370 | #define PORT_P1_ALTSEL0_P5 (0x1 << 5) |
| 1371 | #define PORT_P1_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) |
| 1372 | #define PORT_P1_ALTSEL0_P5_GET(val) ((((val) & PORT_P1_ALTSEL0_P5) >> 5) & 0x1) |
| 1373 | #define PORT_P1_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P5) | (((val) & 0x1) << 5)) |
| 1374 | /* Alternate Function at Port 1 Bit # (4) */ |
| 1375 | #define PORT_P1_ALTSEL0_P4 (0x1 << 4) |
| 1376 | #define PORT_P1_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) |
| 1377 | #define PORT_P1_ALTSEL0_P4_GET(val) ((((val) & PORT_P1_ALTSEL0_P4) >> 4) & 0x1) |
| 1378 | #define PORT_P1_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P4) | (((val) & 0x1) << 4)) |
| 1379 | /* Alternate Function at Port 1 Bit # (3) */ |
| 1380 | #define PORT_P1_ALTSEL0_P3 (0x1 << 3) |
| 1381 | #define PORT_P1_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) |
| 1382 | #define PORT_P1_ALTSEL0_P3_GET(val) ((((val) & PORT_P1_ALTSEL0_P3) >> 3) & 0x1) |
| 1383 | #define PORT_P1_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P3) | (((val) & 0x1) << 3)) |
| 1384 | /* Alternate Function at Port 1 Bit # (2) */ |
| 1385 | #define PORT_P1_ALTSEL0_P2 (0x1 << 2) |
| 1386 | #define PORT_P1_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) |
| 1387 | #define PORT_P1_ALTSEL0_P2_GET(val) ((((val) & PORT_P1_ALTSEL0_P2) >> 2) & 0x1) |
| 1388 | #define PORT_P1_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P2) | (((val) & 0x1) << 2)) |
| 1389 | /* Alternate Function at Port 1 Bit # (1) */ |
| 1390 | #define PORT_P1_ALTSEL0_P1 (0x1 << 1) |
| 1391 | #define PORT_P1_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) |
| 1392 | #define PORT_P1_ALTSEL0_P1_GET(val) ((((val) & PORT_P1_ALTSEL0_P1) >> 1) & 0x1) |
| 1393 | #define PORT_P1_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P1) | (((val) & 0x1) << 1)) |
| 1394 | /* Alternate Function at Port 1 Bit # (0) */ |
| 1395 | #define PORT_P1_ALTSEL0_P0 (0x1) |
| 1396 | #define PORT_P1_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) |
| 1397 | #define PORT_P1_ALTSEL0_P0_GET(val) ((((val) & PORT_P1_ALTSEL0_P0) >> 0) & 0x1) |
| 1398 | #define PORT_P1_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P0) | (((val) & 0x1) << 0)) |
| 1399 | |
| 1400 | /******************************************************************************* |
| 1401 | * Port 1 Pull Up Device Enable Register |
| 1402 | ******************************************************************************/ |
| 1403 | |
| 1404 | /* Pull Up Device Enable at Port 1 Bit # (19) */ |
| 1405 | #define PORT_P1_PUEN_P19 (0x1 << 19) |
| 1406 | #define PORT_P1_PUEN_P19_VAL(val) (((val) & 0x1) << 19) |
| 1407 | #define PORT_P1_PUEN_P19_GET(val) ((((val) & PORT_P1_PUEN_P19) >> 19) & 0x1) |
| 1408 | #define PORT_P1_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P19) | (((val) & 0x1) << 19)) |
| 1409 | /* Pull Up Device Enable at Port 1 Bit # (18) */ |
| 1410 | #define PORT_P1_PUEN_P18 (0x1 << 18) |
| 1411 | #define PORT_P1_PUEN_P18_VAL(val) (((val) & 0x1) << 18) |
| 1412 | #define PORT_P1_PUEN_P18_GET(val) ((((val) & PORT_P1_PUEN_P18) >> 18) & 0x1) |
| 1413 | #define PORT_P1_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P18) | (((val) & 0x1) << 18)) |
| 1414 | /* Pull Up Device Enable at Port 1 Bit # (17) */ |
| 1415 | #define PORT_P1_PUEN_P17 (0x1 << 17) |
| 1416 | #define PORT_P1_PUEN_P17_VAL(val) (((val) & 0x1) << 17) |
| 1417 | #define PORT_P1_PUEN_P17_GET(val) ((((val) & PORT_P1_PUEN_P17) >> 17) & 0x1) |
| 1418 | #define PORT_P1_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P17) | (((val) & 0x1) << 17)) |
| 1419 | /* Pull Up Device Enable at Port 1 Bit # (16) */ |
| 1420 | #define PORT_P1_PUEN_P16 (0x1 << 16) |
| 1421 | #define PORT_P1_PUEN_P16_VAL(val) (((val) & 0x1) << 16) |
| 1422 | #define PORT_P1_PUEN_P16_GET(val) ((((val) & PORT_P1_PUEN_P16) >> 16) & 0x1) |
| 1423 | #define PORT_P1_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P16) | (((val) & 0x1) << 16)) |
| 1424 | /* Pull Up Device Enable at Port 1 Bit # (15) */ |
| 1425 | #define PORT_P1_PUEN_P15 (0x1 << 15) |
| 1426 | #define PORT_P1_PUEN_P15_VAL(val) (((val) & 0x1) << 15) |
| 1427 | #define PORT_P1_PUEN_P15_GET(val) ((((val) & PORT_P1_PUEN_P15) >> 15) & 0x1) |
| 1428 | #define PORT_P1_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P15) | (((val) & 0x1) << 15)) |
| 1429 | /* Pull Up Device Enable at Port 1 Bit # (14) */ |
| 1430 | #define PORT_P1_PUEN_P14 (0x1 << 14) |
| 1431 | #define PORT_P1_PUEN_P14_VAL(val) (((val) & 0x1) << 14) |
| 1432 | #define PORT_P1_PUEN_P14_GET(val) ((((val) & PORT_P1_PUEN_P14) >> 14) & 0x1) |
| 1433 | #define PORT_P1_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P14) | (((val) & 0x1) << 14)) |
| 1434 | /* Pull Up Device Enable at Port 1 Bit # (13) */ |
| 1435 | #define PORT_P1_PUEN_P13 (0x1 << 13) |
| 1436 | #define PORT_P1_PUEN_P13_VAL(val) (((val) & 0x1) << 13) |
| 1437 | #define PORT_P1_PUEN_P13_GET(val) ((((val) & PORT_P1_PUEN_P13) >> 13) & 0x1) |
| 1438 | #define PORT_P1_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P13) | (((val) & 0x1) << 13)) |
| 1439 | /* Pull Up Device Enable at Port 1 Bit # (12) */ |
| 1440 | #define PORT_P1_PUEN_P12 (0x1 << 12) |
| 1441 | #define PORT_P1_PUEN_P12_VAL(val) (((val) & 0x1) << 12) |
| 1442 | #define PORT_P1_PUEN_P12_GET(val) ((((val) & PORT_P1_PUEN_P12) >> 12) & 0x1) |
| 1443 | #define PORT_P1_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P12) | (((val) & 0x1) << 12)) |
| 1444 | /* Pull Up Device Enable at Port 1 Bit # (11) */ |
| 1445 | #define PORT_P1_PUEN_P11 (0x1 << 11) |
| 1446 | #define PORT_P1_PUEN_P11_VAL(val) (((val) & 0x1) << 11) |
| 1447 | #define PORT_P1_PUEN_P11_GET(val) ((((val) & PORT_P1_PUEN_P11) >> 11) & 0x1) |
| 1448 | #define PORT_P1_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P11) | (((val) & 0x1) << 11)) |
| 1449 | /* Pull Up Device Enable at Port 1 Bit # (10) */ |
| 1450 | #define PORT_P1_PUEN_P10 (0x1 << 10) |
| 1451 | #define PORT_P1_PUEN_P10_VAL(val) (((val) & 0x1) << 10) |
| 1452 | #define PORT_P1_PUEN_P10_GET(val) ((((val) & PORT_P1_PUEN_P10) >> 10) & 0x1) |
| 1453 | #define PORT_P1_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P10) | (((val) & 0x1) << 10)) |
| 1454 | /* Pull Up Device Enable at Port 1 Bit # (9) */ |
| 1455 | #define PORT_P1_PUEN_P9 (0x1 << 9) |
| 1456 | #define PORT_P1_PUEN_P9_VAL(val) (((val) & 0x1) << 9) |
| 1457 | #define PORT_P1_PUEN_P9_GET(val) ((((val) & PORT_P1_PUEN_P9) >> 9) & 0x1) |
| 1458 | #define PORT_P1_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P9) | (((val) & 0x1) << 9)) |
| 1459 | /* Pull Up Device Enable at Port 1 Bit # (8) */ |
| 1460 | #define PORT_P1_PUEN_P8 (0x1 << 8) |
| 1461 | #define PORT_P1_PUEN_P8_VAL(val) (((val) & 0x1) << 8) |
| 1462 | #define PORT_P1_PUEN_P8_GET(val) ((((val) & PORT_P1_PUEN_P8) >> 8) & 0x1) |
| 1463 | #define PORT_P1_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P8) | (((val) & 0x1) << 8)) |
| 1464 | /* Pull Up Device Enable at Port 1 Bit # (7) */ |
| 1465 | #define PORT_P1_PUEN_P7 (0x1 << 7) |
| 1466 | #define PORT_P1_PUEN_P7_VAL(val) (((val) & 0x1) << 7) |
| 1467 | #define PORT_P1_PUEN_P7_GET(val) ((((val) & PORT_P1_PUEN_P7) >> 7) & 0x1) |
| 1468 | #define PORT_P1_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P7) | (((val) & 0x1) << 7)) |
| 1469 | /* Pull Up Device Enable at Port 1 Bit # (6) */ |
| 1470 | #define PORT_P1_PUEN_P6 (0x1 << 6) |
| 1471 | #define PORT_P1_PUEN_P6_VAL(val) (((val) & 0x1) << 6) |
| 1472 | #define PORT_P1_PUEN_P6_GET(val) ((((val) & PORT_P1_PUEN_P6) >> 6) & 0x1) |
| 1473 | #define PORT_P1_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P6) | (((val) & 0x1) << 6)) |
| 1474 | /* Pull Up Device Enable at Port 1 Bit # (5) */ |
| 1475 | #define PORT_P1_PUEN_P5 (0x1 << 5) |
| 1476 | #define PORT_P1_PUEN_P5_VAL(val) (((val) & 0x1) << 5) |
| 1477 | #define PORT_P1_PUEN_P5_GET(val) ((((val) & PORT_P1_PUEN_P5) >> 5) & 0x1) |
| 1478 | #define PORT_P1_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P5) | (((val) & 0x1) << 5)) |
| 1479 | /* Pull Up Device Enable at Port 1 Bit # (4) */ |
| 1480 | #define PORT_P1_PUEN_P4 (0x1 << 4) |
| 1481 | #define PORT_P1_PUEN_P4_VAL(val) (((val) & 0x1) << 4) |
| 1482 | #define PORT_P1_PUEN_P4_GET(val) ((((val) & PORT_P1_PUEN_P4) >> 4) & 0x1) |
| 1483 | #define PORT_P1_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P4) | (((val) & 0x1) << 4)) |
| 1484 | /* Pull Up Device Enable at Port 1 Bit # (3) */ |
| 1485 | #define PORT_P1_PUEN_P3 (0x1 << 3) |
| 1486 | #define PORT_P1_PUEN_P3_VAL(val) (((val) & 0x1) << 3) |
| 1487 | #define PORT_P1_PUEN_P3_GET(val) ((((val) & PORT_P1_PUEN_P3) >> 3) & 0x1) |
| 1488 | #define PORT_P1_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P3) | (((val) & 0x1) << 3)) |
| 1489 | /* Pull Up Device Enable at Port 1 Bit # (2) */ |
| 1490 | #define PORT_P1_PUEN_P2 (0x1 << 2) |
| 1491 | #define PORT_P1_PUEN_P2_VAL(val) (((val) & 0x1) << 2) |
| 1492 | #define PORT_P1_PUEN_P2_GET(val) ((((val) & PORT_P1_PUEN_P2) >> 2) & 0x1) |
| 1493 | #define PORT_P1_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P2) | (((val) & 0x1) << 2)) |
| 1494 | /* Pull Up Device Enable at Port 1 Bit # (1) */ |
| 1495 | #define PORT_P1_PUEN_P1 (0x1 << 1) |
| 1496 | #define PORT_P1_PUEN_P1_VAL(val) (((val) & 0x1) << 1) |
| 1497 | #define PORT_P1_PUEN_P1_GET(val) ((((val) & PORT_P1_PUEN_P1) >> 1) & 0x1) |
| 1498 | #define PORT_P1_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P1) | (((val) & 0x1) << 1)) |
| 1499 | /* Pull Up Device Enable at Port 1 Bit # (0) */ |
| 1500 | #define PORT_P1_PUEN_P0 (0x1) |
| 1501 | #define PORT_P1_PUEN_P0_VAL(val) (((val) & 0x1) << 0) |
| 1502 | #define PORT_P1_PUEN_P0_GET(val) ((((val) & PORT_P1_PUEN_P0) >> 0) & 0x1) |
| 1503 | #define PORT_P1_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P0) | (((val) & 0x1) << 0)) |
| 1504 | |
| 1505 | /******************************************************************************* |
| 1506 | * External Interrupt Control Register 0 |
| 1507 | ******************************************************************************/ |
| 1508 | |
| 1509 | /* Type of Level or Edge Detection of EXINT15 (19) */ |
| 1510 | #define PORT_P1_EXINTCR0_EXINT15 (0x1 << 19) |
| 1511 | #define PORT_P1_EXINTCR0_EXINT15_VAL(val) (((val) & 0x1) << 19) |
| 1512 | #define PORT_P1_EXINTCR0_EXINT15_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT15) >> 19) & 0x1) |
| 1513 | #define PORT_P1_EXINTCR0_EXINT15_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT15) | (((val) & 0x1) << 19)) |
| 1514 | /* Type of Level or Edge Detection of EXINT11 (18) */ |
| 1515 | #define PORT_P1_EXINTCR0_EXINT11 (0x1 << 18) |
| 1516 | #define PORT_P1_EXINTCR0_EXINT11_VAL(val) (((val) & 0x1) << 18) |
| 1517 | #define PORT_P1_EXINTCR0_EXINT11_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT11) >> 18) & 0x1) |
| 1518 | #define PORT_P1_EXINTCR0_EXINT11_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT11) | (((val) & 0x1) << 18)) |
| 1519 | /* Type of Level or Edge Detection of EXINT12 (17) */ |
| 1520 | #define PORT_P1_EXINTCR0_EXINT12 (0x1 << 17) |
| 1521 | #define PORT_P1_EXINTCR0_EXINT12_VAL(val) (((val) & 0x1) << 17) |
| 1522 | #define PORT_P1_EXINTCR0_EXINT12_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT12) >> 17) & 0x1) |
| 1523 | #define PORT_P1_EXINTCR0_EXINT12_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT12) | (((val) & 0x1) << 17)) |
| 1524 | /* Type of Level or Edge Detection of EXINT13 (16) */ |
| 1525 | #define PORT_P1_EXINTCR0_EXINT13 (0x1 << 16) |
| 1526 | #define PORT_P1_EXINTCR0_EXINT13_VAL(val) (((val) & 0x1) << 16) |
| 1527 | #define PORT_P1_EXINTCR0_EXINT13_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT13) >> 16) & 0x1) |
| 1528 | #define PORT_P1_EXINTCR0_EXINT13_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT13) | (((val) & 0x1) << 16)) |
| 1529 | /* Type of Level or Edge Detection of EXINT14 (15) */ |
| 1530 | #define PORT_P1_EXINTCR0_EXINT14 (0x1 << 15) |
| 1531 | #define PORT_P1_EXINTCR0_EXINT14_VAL(val) (((val) & 0x1) << 15) |
| 1532 | #define PORT_P1_EXINTCR0_EXINT14_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT14) >> 15) & 0x1) |
| 1533 | #define PORT_P1_EXINTCR0_EXINT14_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT14) | (((val) & 0x1) << 15)) |
| 1534 | |
| 1535 | /******************************************************************************* |
| 1536 | * External Interrupt Control Register 1 |
| 1537 | ******************************************************************************/ |
| 1538 | |
| 1539 | /* Type of Level or Edge Detection of EXINT15 (19) */ |
| 1540 | #define PORT_P1_EXINTCR1_EXINT15 (0x1 << 19) |
| 1541 | #define PORT_P1_EXINTCR1_EXINT15_VAL(val) (((val) & 0x1) << 19) |
| 1542 | #define PORT_P1_EXINTCR1_EXINT15_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT15) >> 19) & 0x1) |
| 1543 | #define PORT_P1_EXINTCR1_EXINT15_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT15) | (((val) & 0x1) << 19)) |
| 1544 | /* Type of Level or Edge Detection of EXINT11 (18) */ |
| 1545 | #define PORT_P1_EXINTCR1_EXINT11 (0x1 << 18) |
| 1546 | #define PORT_P1_EXINTCR1_EXINT11_VAL(val) (((val) & 0x1) << 18) |
| 1547 | #define PORT_P1_EXINTCR1_EXINT11_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT11) >> 18) & 0x1) |
| 1548 | #define PORT_P1_EXINTCR1_EXINT11_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT11) | (((val) & 0x1) << 18)) |
| 1549 | /* Type of Level or Edge Detection of EXINT12 (17) */ |
| 1550 | #define PORT_P1_EXINTCR1_EXINT12 (0x1 << 17) |
| 1551 | #define PORT_P1_EXINTCR1_EXINT12_VAL(val) (((val) & 0x1) << 17) |
| 1552 | #define PORT_P1_EXINTCR1_EXINT12_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT12) >> 17) & 0x1) |
| 1553 | #define PORT_P1_EXINTCR1_EXINT12_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT12) | (((val) & 0x1) << 17)) |
| 1554 | /* Type of Level or Edge Detection of EXINT13 (16) */ |
| 1555 | #define PORT_P1_EXINTCR1_EXINT13 (0x1 << 16) |
| 1556 | #define PORT_P1_EXINTCR1_EXINT13_VAL(val) (((val) & 0x1) << 16) |
| 1557 | #define PORT_P1_EXINTCR1_EXINT13_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT13) >> 16) & 0x1) |
| 1558 | #define PORT_P1_EXINTCR1_EXINT13_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT13) | (((val) & 0x1) << 16)) |
| 1559 | /* Type of Level or Edge Detection of EXINT14 (15) */ |
| 1560 | #define PORT_P1_EXINTCR1_EXINT14 (0x1 << 15) |
| 1561 | #define PORT_P1_EXINTCR1_EXINT14_VAL(val) (((val) & 0x1) << 15) |
| 1562 | #define PORT_P1_EXINTCR1_EXINT14_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT14) >> 15) & 0x1) |
| 1563 | #define PORT_P1_EXINTCR1_EXINT14_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT14) | (((val) & 0x1) << 15)) |
| 1564 | |
| 1565 | /******************************************************************************* |
| 1566 | * P1_IRNEN Register |
| 1567 | ******************************************************************************/ |
| 1568 | |
| 1569 | /* EXINT15 Interrupt Request Enable (19) */ |
| 1570 | #define PORT_P1_IRNEN_EXINT15 (0x1 << 19) |
| 1571 | #define PORT_P1_IRNEN_EXINT15_VAL(val) (((val) & 0x1) << 19) |
| 1572 | #define PORT_P1_IRNEN_EXINT15_GET(val) ((((val) & PORT_P1_IRNEN_EXINT15) >> 19) & 0x1) |
| 1573 | #define PORT_P1_IRNEN_EXINT15_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT15) | (((val) & 0x1) << 19)) |
| 1574 | /* EXINT11 Interrupt Request Enable (18) */ |
| 1575 | #define PORT_P1_IRNEN_EXINT11 (0x1 << 18) |
| 1576 | #define PORT_P1_IRNEN_EXINT11_VAL(val) (((val) & 0x1) << 18) |
| 1577 | #define PORT_P1_IRNEN_EXINT11_GET(val) ((((val) & PORT_P1_IRNEN_EXINT11) >> 18) & 0x1) |
| 1578 | #define PORT_P1_IRNEN_EXINT11_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT11) | (((val) & 0x1) << 18)) |
| 1579 | /* EXINT12 Interrupt Request Enable (17) */ |
| 1580 | #define PORT_P1_IRNEN_EXINT12 (0x1 << 17) |
| 1581 | #define PORT_P1_IRNEN_EXINT12_VAL(val) (((val) & 0x1) << 17) |
| 1582 | #define PORT_P1_IRNEN_EXINT12_GET(val) ((((val) & PORT_P1_IRNEN_EXINT12) >> 17) & 0x1) |
| 1583 | #define PORT_P1_IRNEN_EXINT12_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT12) | (((val) & 0x1) << 17)) |
| 1584 | /* EXINT13 Interrupt Request Enable (16) */ |
| 1585 | #define PORT_P1_IRNEN_EXINT13 (0x1 << 16) |
| 1586 | #define PORT_P1_IRNEN_EXINT13_VAL(val) (((val) & 0x1) << 16) |
| 1587 | #define PORT_P1_IRNEN_EXINT13_GET(val) ((((val) & PORT_P1_IRNEN_EXINT13) >> 16) & 0x1) |
| 1588 | #define PORT_P1_IRNEN_EXINT13_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT13) | (((val) & 0x1) << 16)) |
| 1589 | /* EXINT14 Interrupt Request Enable (15) */ |
| 1590 | #define PORT_P1_IRNEN_EXINT14 (0x1 << 15) |
| 1591 | #define PORT_P1_IRNEN_EXINT14_VAL(val) (((val) & 0x1) << 15) |
| 1592 | #define PORT_P1_IRNEN_EXINT14_GET(val) ((((val) & PORT_P1_IRNEN_EXINT14) >> 15) & 0x1) |
| 1593 | #define PORT_P1_IRNEN_EXINT14_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT14) | (((val) & 0x1) << 15)) |
| 1594 | |
| 1595 | /******************************************************************************* |
| 1596 | * P1_IRNICR Register |
| 1597 | ******************************************************************************/ |
| 1598 | |
| 1599 | /* EXINT15 Interrupt Request (19) */ |
| 1600 | #define PORT_P1_IRNICR_EXINT15 (0x1 << 19) |
| 1601 | #define PORT_P1_IRNICR_EXINT15_GET(val) ((((val) & PORT_P1_IRNICR_EXINT15) >> 19) & 0x1) |
| 1602 | /* EXINT11 Interrupt Request (18) */ |
| 1603 | #define PORT_P1_IRNICR_EXINT11 (0x1 << 18) |
| 1604 | #define PORT_P1_IRNICR_EXINT11_GET(val) ((((val) & PORT_P1_IRNICR_EXINT11) >> 18) & 0x1) |
| 1605 | /* EXINT12 Interrupt Request (17) */ |
| 1606 | #define PORT_P1_IRNICR_EXINT12 (0x1 << 17) |
| 1607 | #define PORT_P1_IRNICR_EXINT12_GET(val) ((((val) & PORT_P1_IRNICR_EXINT12) >> 17) & 0x1) |
| 1608 | /* EXINT13 Interrupt Request (16) */ |
| 1609 | #define PORT_P1_IRNICR_EXINT13 (0x1 << 16) |
| 1610 | #define PORT_P1_IRNICR_EXINT13_GET(val) ((((val) & PORT_P1_IRNICR_EXINT13) >> 16) & 0x1) |
| 1611 | /* EXINT14 Interrupt Request (15) */ |
| 1612 | #define PORT_P1_IRNICR_EXINT14 (0x1 << 15) |
| 1613 | #define PORT_P1_IRNICR_EXINT14_GET(val) ((((val) & PORT_P1_IRNICR_EXINT14) >> 15) & 0x1) |
| 1614 | |
| 1615 | /******************************************************************************* |
| 1616 | * P1_IRNCR Register |
| 1617 | ******************************************************************************/ |
| 1618 | |
| 1619 | /* EXINT15 Interrupt Request (19) */ |
| 1620 | #define PORT_P1_IRNCR_EXINT15 (0x1 << 19) |
| 1621 | #define PORT_P1_IRNCR_EXINT15_GET(val) ((((val) & PORT_P1_IRNCR_EXINT15) >> 19) & 0x1) |
| 1622 | /* EXINT11 Interrupt Request (18) */ |
| 1623 | #define PORT_P1_IRNCR_EXINT11 (0x1 << 18) |
| 1624 | #define PORT_P1_IRNCR_EXINT11_GET(val) ((((val) & PORT_P1_IRNCR_EXINT11) >> 18) & 0x1) |
| 1625 | /* EXINT12 Interrupt Request (17) */ |
| 1626 | #define PORT_P1_IRNCR_EXINT12 (0x1 << 17) |
| 1627 | #define PORT_P1_IRNCR_EXINT12_GET(val) ((((val) & PORT_P1_IRNCR_EXINT12) >> 17) & 0x1) |
| 1628 | /* EXINT13 Interrupt Request (16) */ |
| 1629 | #define PORT_P1_IRNCR_EXINT13 (0x1 << 16) |
| 1630 | #define PORT_P1_IRNCR_EXINT13_GET(val) ((((val) & PORT_P1_IRNCR_EXINT13) >> 16) & 0x1) |
| 1631 | /* EXINT14 Interrupt Request (15) */ |
| 1632 | #define PORT_P1_IRNCR_EXINT14 (0x1 << 15) |
| 1633 | #define PORT_P1_IRNCR_EXINT14_GET(val) ((((val) & PORT_P1_IRNCR_EXINT14) >> 15) & 0x1) |
| 1634 | |
| 1635 | /******************************************************************************* |
| 1636 | * P1 External Event Detection Configuration Register |
| 1637 | ******************************************************************************/ |
| 1638 | |
| 1639 | /* EXINT15 configured for Edge or Level Detection (19) */ |
| 1640 | #define PORT_P1_IRNCFG_EXINT15 (0x1 << 19) |
| 1641 | #define PORT_P1_IRNCFG_EXINT15_VAL(val) (((val) & 0x1) << 19) |
| 1642 | #define PORT_P1_IRNCFG_EXINT15_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT15) >> 19) & 0x1) |
| 1643 | #define PORT_P1_IRNCFG_EXINT15_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT15) | (((val) & 0x1) << 19)) |
| 1644 | /* EXINT11 configured for Edge or Level Detection (18) */ |
| 1645 | #define PORT_P1_IRNCFG_EXINT11 (0x1 << 18) |
| 1646 | #define PORT_P1_IRNCFG_EXINT11_VAL(val) (((val) & 0x1) << 18) |
| 1647 | #define PORT_P1_IRNCFG_EXINT11_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT11) >> 18) & 0x1) |
| 1648 | #define PORT_P1_IRNCFG_EXINT11_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT11) | (((val) & 0x1) << 18)) |
| 1649 | /* EXINT12 configured for Edge or Level Detection (17) */ |
| 1650 | #define PORT_P1_IRNCFG_EXINT12 (0x1 << 17) |
| 1651 | #define PORT_P1_IRNCFG_EXINT12_VAL(val) (((val) & 0x1) << 17) |
| 1652 | #define PORT_P1_IRNCFG_EXINT12_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT12) >> 17) & 0x1) |
| 1653 | #define PORT_P1_IRNCFG_EXINT12_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT12) | (((val) & 0x1) << 17)) |
| 1654 | /* EXINT13 configured for Edge or Level Detection (16) */ |
| 1655 | #define PORT_P1_IRNCFG_EXINT13 (0x1 << 16) |
| 1656 | #define PORT_P1_IRNCFG_EXINT13_VAL(val) (((val) & 0x1) << 16) |
| 1657 | #define PORT_P1_IRNCFG_EXINT13_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT13) >> 16) & 0x1) |
| 1658 | #define PORT_P1_IRNCFG_EXINT13_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT13) | (((val) & 0x1) << 16)) |
| 1659 | /* EXINT14 configured for Edge or Level Detection (15) */ |
| 1660 | #define PORT_P1_IRNCFG_EXINT14 (0x1 << 15) |
| 1661 | #define PORT_P1_IRNCFG_EXINT14_VAL(val) (((val) & 0x1) << 15) |
| 1662 | #define PORT_P1_IRNCFG_EXINT14_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT14) >> 15) & 0x1) |
| 1663 | #define PORT_P1_IRNCFG_EXINT14_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT14) | (((val) & 0x1) << 15)) |
| 1664 | |
| 1665 | /******************************************************************************* |
| 1666 | * P1_IRNENSET Register |
| 1667 | ******************************************************************************/ |
| 1668 | |
| 1669 | /* Set Interrupt Node Enable Flag EXINT15 (19) */ |
| 1670 | #define PORT_P1_IRNENSET_EXINT15 (0x1 << 19) |
| 1671 | #define PORT_P1_IRNENSET_EXINT15_VAL(val) (((val) & 0x1) << 19) |
| 1672 | #define PORT_P1_IRNENSET_EXINT15_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT15) | (val) & 1) << 19) |
| 1673 | /* Set Interrupt Node Enable Flag EXINT11 (18) */ |
| 1674 | #define PORT_P1_IRNENSET_EXINT11 (0x1 << 18) |
| 1675 | #define PORT_P1_IRNENSET_EXINT11_VAL(val) (((val) & 0x1) << 18) |
| 1676 | #define PORT_P1_IRNENSET_EXINT11_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT11) | (val) & 1) << 18) |
| 1677 | /* Set Interrupt Node Enable Flag EXINT12 (17) */ |
| 1678 | #define PORT_P1_IRNENSET_EXINT12 (0x1 << 17) |
| 1679 | #define PORT_P1_IRNENSET_EXINT12_VAL(val) (((val) & 0x1) << 17) |
| 1680 | #define PORT_P1_IRNENSET_EXINT12_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT12) | (val) & 1) << 17) |
| 1681 | /* Set Interrupt Node Enable Flag EXINT13 (16) */ |
| 1682 | #define PORT_P1_IRNENSET_EXINT13 (0x1 << 16) |
| 1683 | #define PORT_P1_IRNENSET_EXINT13_VAL(val) (((val) & 0x1) << 16) |
| 1684 | #define PORT_P1_IRNENSET_EXINT13_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT13) | (val) & 1) << 16) |
| 1685 | /* Set Interrupt Node Enable Flag EXINT14 (15) */ |
| 1686 | #define PORT_P1_IRNENSET_EXINT14 (0x1 << 15) |
| 1687 | #define PORT_P1_IRNENSET_EXINT14_VAL(val) (((val) & 0x1) << 15) |
| 1688 | #define PORT_P1_IRNENSET_EXINT14_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT14) | (val) & 1) << 15) |
| 1689 | |
| 1690 | /******************************************************************************* |
| 1691 | * P1_IRNENCLR Register |
| 1692 | ******************************************************************************/ |
| 1693 | |
| 1694 | /* Clear Interrupt Node Enable Flag EXINT15 (19) */ |
| 1695 | #define PORT_P1_IRNENCLR_EXINT15 (0x1 << 19) |
| 1696 | #define PORT_P1_IRNENCLR_EXINT15_VAL(val) (((val) & 0x1) << 19) |
| 1697 | #define PORT_P1_IRNENCLR_EXINT15_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT15) | (val) & 1) << 19) |
| 1698 | /* Clear Interrupt Node Enable Flag EXINT11 (18) */ |
| 1699 | #define PORT_P1_IRNENCLR_EXINT11 (0x1 << 18) |
| 1700 | #define PORT_P1_IRNENCLR_EXINT11_VAL(val) (((val) & 0x1) << 18) |
| 1701 | #define PORT_P1_IRNENCLR_EXINT11_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT11) | (val) & 1) << 18) |
| 1702 | /* Clear Interrupt Node Enable Flag EXINT12 (17) */ |
| 1703 | #define PORT_P1_IRNENCLR_EXINT12 (0x1 << 17) |
| 1704 | #define PORT_P1_IRNENCLR_EXINT12_VAL(val) (((val) & 0x1) << 17) |
| 1705 | #define PORT_P1_IRNENCLR_EXINT12_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT12) | (val) & 1) << 17) |
| 1706 | /* Clear Interrupt Node Enable Flag EXINT13 (16) */ |
| 1707 | #define PORT_P1_IRNENCLR_EXINT13 (0x1 << 16) |
| 1708 | #define PORT_P1_IRNENCLR_EXINT13_VAL(val) (((val) & 0x1) << 16) |
| 1709 | #define PORT_P1_IRNENCLR_EXINT13_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT13) | (val) & 1) << 16) |
| 1710 | /* Clear Interrupt Node Enable Flag EXINT14 (15) */ |
| 1711 | #define PORT_P1_IRNENCLR_EXINT14 (0x1 << 15) |
| 1712 | #define PORT_P1_IRNENCLR_EXINT14_VAL(val) (((val) & 0x1) << 15) |
| 1713 | #define PORT_P1_IRNENCLR_EXINT14_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT14) | (val) & 1) << 15) |
| 1714 | |
| 1715 | /******************************************************************************* |
| 1716 | * Port 2 Data Output Register |
| 1717 | ******************************************************************************/ |
| 1718 | |
| 1719 | /* Port 2 Pin # Output Value (19) */ |
| 1720 | #define PORT_P2_OUT_P19 (0x1 << 19) |
| 1721 | #define PORT_P2_OUT_P19_VAL(val) (((val) & 0x1) << 19) |
| 1722 | #define PORT_P2_OUT_P19_GET(val) ((((val) & PORT_P2_OUT_P19) >> 19) & 0x1) |
| 1723 | #define PORT_P2_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P19) | (((val) & 0x1) << 19)) |
| 1724 | /* Port 2 Pin # Output Value (18) */ |
| 1725 | #define PORT_P2_OUT_P18 (0x1 << 18) |
| 1726 | #define PORT_P2_OUT_P18_VAL(val) (((val) & 0x1) << 18) |
| 1727 | #define PORT_P2_OUT_P18_GET(val) ((((val) & PORT_P2_OUT_P18) >> 18) & 0x1) |
| 1728 | #define PORT_P2_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P18) | (((val) & 0x1) << 18)) |
| 1729 | /* Port 2 Pin # Output Value (17) */ |
| 1730 | #define PORT_P2_OUT_P17 (0x1 << 17) |
| 1731 | #define PORT_P2_OUT_P17_VAL(val) (((val) & 0x1) << 17) |
| 1732 | #define PORT_P2_OUT_P17_GET(val) ((((val) & PORT_P2_OUT_P17) >> 17) & 0x1) |
| 1733 | #define PORT_P2_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P17) | (((val) & 0x1) << 17)) |
| 1734 | /* Port 2 Pin # Output Value (16) */ |
| 1735 | #define PORT_P2_OUT_P16 (0x1 << 16) |
| 1736 | #define PORT_P2_OUT_P16_VAL(val) (((val) & 0x1) << 16) |
| 1737 | #define PORT_P2_OUT_P16_GET(val) ((((val) & PORT_P2_OUT_P16) >> 16) & 0x1) |
| 1738 | #define PORT_P2_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P16) | (((val) & 0x1) << 16)) |
| 1739 | /* Port 2 Pin # Output Value (15) */ |
| 1740 | #define PORT_P2_OUT_P15 (0x1 << 15) |
| 1741 | #define PORT_P2_OUT_P15_VAL(val) (((val) & 0x1) << 15) |
| 1742 | #define PORT_P2_OUT_P15_GET(val) ((((val) & PORT_P2_OUT_P15) >> 15) & 0x1) |
| 1743 | #define PORT_P2_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P15) | (((val) & 0x1) << 15)) |
| 1744 | /* Port 2 Pin # Output Value (14) */ |
| 1745 | #define PORT_P2_OUT_P14 (0x1 << 14) |
| 1746 | #define PORT_P2_OUT_P14_VAL(val) (((val) & 0x1) << 14) |
| 1747 | #define PORT_P2_OUT_P14_GET(val) ((((val) & PORT_P2_OUT_P14) >> 14) & 0x1) |
| 1748 | #define PORT_P2_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P14) | (((val) & 0x1) << 14)) |
| 1749 | /* Port 2 Pin # Output Value (13) */ |
| 1750 | #define PORT_P2_OUT_P13 (0x1 << 13) |
| 1751 | #define PORT_P2_OUT_P13_VAL(val) (((val) & 0x1) << 13) |
| 1752 | #define PORT_P2_OUT_P13_GET(val) ((((val) & PORT_P2_OUT_P13) >> 13) & 0x1) |
| 1753 | #define PORT_P2_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P13) | (((val) & 0x1) << 13)) |
| 1754 | /* Port 2 Pin # Output Value (12) */ |
| 1755 | #define PORT_P2_OUT_P12 (0x1 << 12) |
| 1756 | #define PORT_P2_OUT_P12_VAL(val) (((val) & 0x1) << 12) |
| 1757 | #define PORT_P2_OUT_P12_GET(val) ((((val) & PORT_P2_OUT_P12) >> 12) & 0x1) |
| 1758 | #define PORT_P2_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P12) | (((val) & 0x1) << 12)) |
| 1759 | /* Port 2 Pin # Output Value (11) */ |
| 1760 | #define PORT_P2_OUT_P11 (0x1 << 11) |
| 1761 | #define PORT_P2_OUT_P11_VAL(val) (((val) & 0x1) << 11) |
| 1762 | #define PORT_P2_OUT_P11_GET(val) ((((val) & PORT_P2_OUT_P11) >> 11) & 0x1) |
| 1763 | #define PORT_P2_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P11) | (((val) & 0x1) << 11)) |
| 1764 | /* Port 2 Pin # Output Value (10) */ |
| 1765 | #define PORT_P2_OUT_P10 (0x1 << 10) |
| 1766 | #define PORT_P2_OUT_P10_VAL(val) (((val) & 0x1) << 10) |
| 1767 | #define PORT_P2_OUT_P10_GET(val) ((((val) & PORT_P2_OUT_P10) >> 10) & 0x1) |
| 1768 | #define PORT_P2_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P10) | (((val) & 0x1) << 10)) |
| 1769 | /* Port 2 Pin # Output Value (9) */ |
| 1770 | #define PORT_P2_OUT_P9 (0x1 << 9) |
| 1771 | #define PORT_P2_OUT_P9_VAL(val) (((val) & 0x1) << 9) |
| 1772 | #define PORT_P2_OUT_P9_GET(val) ((((val) & PORT_P2_OUT_P9) >> 9) & 0x1) |
| 1773 | #define PORT_P2_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P9) | (((val) & 0x1) << 9)) |
| 1774 | /* Port 2 Pin # Output Value (8) */ |
| 1775 | #define PORT_P2_OUT_P8 (0x1 << 8) |
| 1776 | #define PORT_P2_OUT_P8_VAL(val) (((val) & 0x1) << 8) |
| 1777 | #define PORT_P2_OUT_P8_GET(val) ((((val) & PORT_P2_OUT_P8) >> 8) & 0x1) |
| 1778 | #define PORT_P2_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P8) | (((val) & 0x1) << 8)) |
| 1779 | /* Port 2 Pin # Output Value (7) */ |
| 1780 | #define PORT_P2_OUT_P7 (0x1 << 7) |
| 1781 | #define PORT_P2_OUT_P7_VAL(val) (((val) & 0x1) << 7) |
| 1782 | #define PORT_P2_OUT_P7_GET(val) ((((val) & PORT_P2_OUT_P7) >> 7) & 0x1) |
| 1783 | #define PORT_P2_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P7) | (((val) & 0x1) << 7)) |
| 1784 | /* Port 2 Pin # Output Value (6) */ |
| 1785 | #define PORT_P2_OUT_P6 (0x1 << 6) |
| 1786 | #define PORT_P2_OUT_P6_VAL(val) (((val) & 0x1) << 6) |
| 1787 | #define PORT_P2_OUT_P6_GET(val) ((((val) & PORT_P2_OUT_P6) >> 6) & 0x1) |
| 1788 | #define PORT_P2_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P6) | (((val) & 0x1) << 6)) |
| 1789 | /* Port 2 Pin # Output Value (5) */ |
| 1790 | #define PORT_P2_OUT_P5 (0x1 << 5) |
| 1791 | #define PORT_P2_OUT_P5_VAL(val) (((val) & 0x1) << 5) |
| 1792 | #define PORT_P2_OUT_P5_GET(val) ((((val) & PORT_P2_OUT_P5) >> 5) & 0x1) |
| 1793 | #define PORT_P2_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P5) | (((val) & 0x1) << 5)) |
| 1794 | /* Port 2 Pin # Output Value (4) */ |
| 1795 | #define PORT_P2_OUT_P4 (0x1 << 4) |
| 1796 | #define PORT_P2_OUT_P4_VAL(val) (((val) & 0x1) << 4) |
| 1797 | #define PORT_P2_OUT_P4_GET(val) ((((val) & PORT_P2_OUT_P4) >> 4) & 0x1) |
| 1798 | #define PORT_P2_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P4) | (((val) & 0x1) << 4)) |
| 1799 | /* Port 2 Pin # Output Value (3) */ |
| 1800 | #define PORT_P2_OUT_P3 (0x1 << 3) |
| 1801 | #define PORT_P2_OUT_P3_VAL(val) (((val) & 0x1) << 3) |
| 1802 | #define PORT_P2_OUT_P3_GET(val) ((((val) & PORT_P2_OUT_P3) >> 3) & 0x1) |
| 1803 | #define PORT_P2_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P3) | (((val) & 0x1) << 3)) |
| 1804 | /* Port 2 Pin # Output Value (2) */ |
| 1805 | #define PORT_P2_OUT_P2 (0x1 << 2) |
| 1806 | #define PORT_P2_OUT_P2_VAL(val) (((val) & 0x1) << 2) |
| 1807 | #define PORT_P2_OUT_P2_GET(val) ((((val) & PORT_P2_OUT_P2) >> 2) & 0x1) |
| 1808 | #define PORT_P2_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P2) | (((val) & 0x1) << 2)) |
| 1809 | /* Port 2 Pin # Output Value (1) */ |
| 1810 | #define PORT_P2_OUT_P1 (0x1 << 1) |
| 1811 | #define PORT_P2_OUT_P1_VAL(val) (((val) & 0x1) << 1) |
| 1812 | #define PORT_P2_OUT_P1_GET(val) ((((val) & PORT_P2_OUT_P1) >> 1) & 0x1) |
| 1813 | #define PORT_P2_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P1) | (((val) & 0x1) << 1)) |
| 1814 | /* Port 2 Pin # Output Value (0) */ |
| 1815 | #define PORT_P2_OUT_P0 (0x1) |
| 1816 | #define PORT_P2_OUT_P0_VAL(val) (((val) & 0x1) << 0) |
| 1817 | #define PORT_P2_OUT_P0_GET(val) ((((val) & PORT_P2_OUT_P0) >> 0) & 0x1) |
| 1818 | #define PORT_P2_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P0) | (((val) & 0x1) << 0)) |
| 1819 | |
| 1820 | /******************************************************************************* |
| 1821 | * Port 2 Data Input Register |
| 1822 | ******************************************************************************/ |
| 1823 | |
| 1824 | /* Port 2 Pin # Latched Input Value (19) */ |
| 1825 | #define PORT_P2_IN_P19 (0x1 << 19) |
| 1826 | #define PORT_P2_IN_P19_GET(val) ((((val) & PORT_P2_IN_P19) >> 19) & 0x1) |
| 1827 | /* Port 2 Pin # Latched Input Value (18) */ |
| 1828 | #define PORT_P2_IN_P18 (0x1 << 18) |
| 1829 | #define PORT_P2_IN_P18_GET(val) ((((val) & PORT_P2_IN_P18) >> 18) & 0x1) |
| 1830 | /* Port 2 Pin # Latched Input Value (17) */ |
| 1831 | #define PORT_P2_IN_P17 (0x1 << 17) |
| 1832 | #define PORT_P2_IN_P17_GET(val) ((((val) & PORT_P2_IN_P17) >> 17) & 0x1) |
| 1833 | /* Port 2 Pin # Latched Input Value (16) */ |
| 1834 | #define PORT_P2_IN_P16 (0x1 << 16) |
| 1835 | #define PORT_P2_IN_P16_GET(val) ((((val) & PORT_P2_IN_P16) >> 16) & 0x1) |
| 1836 | /* Port 2 Pin # Latched Input Value (15) */ |
| 1837 | #define PORT_P2_IN_P15 (0x1 << 15) |
| 1838 | #define PORT_P2_IN_P15_GET(val) ((((val) & PORT_P2_IN_P15) >> 15) & 0x1) |
| 1839 | /* Port 2 Pin # Latched Input Value (14) */ |
| 1840 | #define PORT_P2_IN_P14 (0x1 << 14) |
| 1841 | #define PORT_P2_IN_P14_GET(val) ((((val) & PORT_P2_IN_P14) >> 14) & 0x1) |
| 1842 | /* Port 2 Pin # Latched Input Value (13) */ |
| 1843 | #define PORT_P2_IN_P13 (0x1 << 13) |
| 1844 | #define PORT_P2_IN_P13_GET(val) ((((val) & PORT_P2_IN_P13) >> 13) & 0x1) |
| 1845 | /* Port 2 Pin # Latched Input Value (12) */ |
| 1846 | #define PORT_P2_IN_P12 (0x1 << 12) |
| 1847 | #define PORT_P2_IN_P12_GET(val) ((((val) & PORT_P2_IN_P12) >> 12) & 0x1) |
| 1848 | /* Port 2 Pin # Latched Input Value (11) */ |
| 1849 | #define PORT_P2_IN_P11 (0x1 << 11) |
| 1850 | #define PORT_P2_IN_P11_GET(val) ((((val) & PORT_P2_IN_P11) >> 11) & 0x1) |
| 1851 | /* Port 2 Pin # Latched Input Value (10) */ |
| 1852 | #define PORT_P2_IN_P10 (0x1 << 10) |
| 1853 | #define PORT_P2_IN_P10_GET(val) ((((val) & PORT_P2_IN_P10) >> 10) & 0x1) |
| 1854 | /* Port 2 Pin # Latched Input Value (9) */ |
| 1855 | #define PORT_P2_IN_P9 (0x1 << 9) |
| 1856 | #define PORT_P2_IN_P9_GET(val) ((((val) & PORT_P2_IN_P9) >> 9) & 0x1) |
| 1857 | /* Port 2 Pin # Latched Input Value (8) */ |
| 1858 | #define PORT_P2_IN_P8 (0x1 << 8) |
| 1859 | #define PORT_P2_IN_P8_GET(val) ((((val) & PORT_P2_IN_P8) >> 8) & 0x1) |
| 1860 | /* Port 2 Pin # Latched Input Value (7) */ |
| 1861 | #define PORT_P2_IN_P7 (0x1 << 7) |
| 1862 | #define PORT_P2_IN_P7_GET(val) ((((val) & PORT_P2_IN_P7) >> 7) & 0x1) |
| 1863 | /* Port 2 Pin # Latched Input Value (6) */ |
| 1864 | #define PORT_P2_IN_P6 (0x1 << 6) |
| 1865 | #define PORT_P2_IN_P6_GET(val) ((((val) & PORT_P2_IN_P6) >> 6) & 0x1) |
| 1866 | /* Port 2 Pin # Latched Input Value (5) */ |
| 1867 | #define PORT_P2_IN_P5 (0x1 << 5) |
| 1868 | #define PORT_P2_IN_P5_GET(val) ((((val) & PORT_P2_IN_P5) >> 5) & 0x1) |
| 1869 | /* Port 2 Pin # Latched Input Value (4) */ |
| 1870 | #define PORT_P2_IN_P4 (0x1 << 4) |
| 1871 | #define PORT_P2_IN_P4_GET(val) ((((val) & PORT_P2_IN_P4) >> 4) & 0x1) |
| 1872 | /* Port 2 Pin # Latched Input Value (3) */ |
| 1873 | #define PORT_P2_IN_P3 (0x1 << 3) |
| 1874 | #define PORT_P2_IN_P3_GET(val) ((((val) & PORT_P2_IN_P3) >> 3) & 0x1) |
| 1875 | /* Port 2 Pin # Latched Input Value (2) */ |
| 1876 | #define PORT_P2_IN_P2 (0x1 << 2) |
| 1877 | #define PORT_P2_IN_P2_GET(val) ((((val) & PORT_P2_IN_P2) >> 2) & 0x1) |
| 1878 | /* Port 2 Pin # Latched Input Value (1) */ |
| 1879 | #define PORT_P2_IN_P1 (0x1 << 1) |
| 1880 | #define PORT_P2_IN_P1_GET(val) ((((val) & PORT_P2_IN_P1) >> 1) & 0x1) |
| 1881 | /* Port 2 Pin # Latched Input Value (0) */ |
| 1882 | #define PORT_P2_IN_P0 (0x1) |
| 1883 | #define PORT_P2_IN_P0_GET(val) ((((val) & PORT_P2_IN_P0) >> 0) & 0x1) |
| 1884 | |
| 1885 | /******************************************************************************* |
| 1886 | * Port 2 Direction Register |
| 1887 | ******************************************************************************/ |
| 1888 | |
| 1889 | /* Port 2 Pin #Direction Control (19) */ |
| 1890 | #define PORT_P2_DIR_P19 (0x1 << 19) |
| 1891 | #define PORT_P2_DIR_P19_VAL(val) (((val) & 0x1) << 19) |
| 1892 | #define PORT_P2_DIR_P19_GET(val) ((((val) & PORT_P2_DIR_P19) >> 19) & 0x1) |
| 1893 | #define PORT_P2_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P19) | (((val) & 0x1) << 19)) |
| 1894 | /* Port 2 Pin #Direction Control (18) */ |
| 1895 | #define PORT_P2_DIR_P18 (0x1 << 18) |
| 1896 | #define PORT_P2_DIR_P18_VAL(val) (((val) & 0x1) << 18) |
| 1897 | #define PORT_P2_DIR_P18_GET(val) ((((val) & PORT_P2_DIR_P18) >> 18) & 0x1) |
| 1898 | #define PORT_P2_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P18) | (((val) & 0x1) << 18)) |
| 1899 | /* Port 2 Pin #Direction Control (17) */ |
| 1900 | #define PORT_P2_DIR_P17 (0x1 << 17) |
| 1901 | #define PORT_P2_DIR_P17_VAL(val) (((val) & 0x1) << 17) |
| 1902 | #define PORT_P2_DIR_P17_GET(val) ((((val) & PORT_P2_DIR_P17) >> 17) & 0x1) |
| 1903 | #define PORT_P2_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P17) | (((val) & 0x1) << 17)) |
| 1904 | /* Port 2 Pin #Direction Control (16) */ |
| 1905 | #define PORT_P2_DIR_P16 (0x1 << 16) |
| 1906 | #define PORT_P2_DIR_P16_VAL(val) (((val) & 0x1) << 16) |
| 1907 | #define PORT_P2_DIR_P16_GET(val) ((((val) & PORT_P2_DIR_P16) >> 16) & 0x1) |
| 1908 | #define PORT_P2_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P16) | (((val) & 0x1) << 16)) |
| 1909 | /* Port 2 Pin #Direction Control (15) */ |
| 1910 | #define PORT_P2_DIR_P15 (0x1 << 15) |
| 1911 | #define PORT_P2_DIR_P15_VAL(val) (((val) & 0x1) << 15) |
| 1912 | #define PORT_P2_DIR_P15_GET(val) ((((val) & PORT_P2_DIR_P15) >> 15) & 0x1) |
| 1913 | #define PORT_P2_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P15) | (((val) & 0x1) << 15)) |
| 1914 | /* Port 2 Pin #Direction Control (14) */ |
| 1915 | #define PORT_P2_DIR_P14 (0x1 << 14) |
| 1916 | #define PORT_P2_DIR_P14_VAL(val) (((val) & 0x1) << 14) |
| 1917 | #define PORT_P2_DIR_P14_GET(val) ((((val) & PORT_P2_DIR_P14) >> 14) & 0x1) |
| 1918 | #define PORT_P2_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P14) | (((val) & 0x1) << 14)) |
| 1919 | /* Port 2 Pin #Direction Control (13) */ |
| 1920 | #define PORT_P2_DIR_P13 (0x1 << 13) |
| 1921 | #define PORT_P2_DIR_P13_VAL(val) (((val) & 0x1) << 13) |
| 1922 | #define PORT_P2_DIR_P13_GET(val) ((((val) & PORT_P2_DIR_P13) >> 13) & 0x1) |
| 1923 | #define PORT_P2_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P13) | (((val) & 0x1) << 13)) |
| 1924 | /* Port 2 Pin #Direction Control (12) */ |
| 1925 | #define PORT_P2_DIR_P12 (0x1 << 12) |
| 1926 | #define PORT_P2_DIR_P12_VAL(val) (((val) & 0x1) << 12) |
| 1927 | #define PORT_P2_DIR_P12_GET(val) ((((val) & PORT_P2_DIR_P12) >> 12) & 0x1) |
| 1928 | #define PORT_P2_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P12) | (((val) & 0x1) << 12)) |
| 1929 | /* Port 2 Pin #Direction Control (11) */ |
| 1930 | #define PORT_P2_DIR_P11 (0x1 << 11) |
| 1931 | #define PORT_P2_DIR_P11_VAL(val) (((val) & 0x1) << 11) |
| 1932 | #define PORT_P2_DIR_P11_GET(val) ((((val) & PORT_P2_DIR_P11) >> 11) & 0x1) |
| 1933 | #define PORT_P2_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P11) | (((val) & 0x1) << 11)) |
| 1934 | /* Port 2 Pin #Direction Control (10) */ |
| 1935 | #define PORT_P2_DIR_P10 (0x1 << 10) |
| 1936 | #define PORT_P2_DIR_P10_VAL(val) (((val) & 0x1) << 10) |
| 1937 | #define PORT_P2_DIR_P10_GET(val) ((((val) & PORT_P2_DIR_P10) >> 10) & 0x1) |
| 1938 | #define PORT_P2_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P10) | (((val) & 0x1) << 10)) |
| 1939 | /* Port 2 Pin #Direction Control (9) */ |
| 1940 | #define PORT_P2_DIR_P9 (0x1 << 9) |
| 1941 | #define PORT_P2_DIR_P9_VAL(val) (((val) & 0x1) << 9) |
| 1942 | #define PORT_P2_DIR_P9_GET(val) ((((val) & PORT_P2_DIR_P9) >> 9) & 0x1) |
| 1943 | #define PORT_P2_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P9) | (((val) & 0x1) << 9)) |
| 1944 | /* Port 2 Pin #Direction Control (8) */ |
| 1945 | #define PORT_P2_DIR_P8 (0x1 << 8) |
| 1946 | #define PORT_P2_DIR_P8_VAL(val) (((val) & 0x1) << 8) |
| 1947 | #define PORT_P2_DIR_P8_GET(val) ((((val) & PORT_P2_DIR_P8) >> 8) & 0x1) |
| 1948 | #define PORT_P2_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P8) | (((val) & 0x1) << 8)) |
| 1949 | /* Port 2 Pin #Direction Control (7) */ |
| 1950 | #define PORT_P2_DIR_P7 (0x1 << 7) |
| 1951 | #define PORT_P2_DIR_P7_VAL(val) (((val) & 0x1) << 7) |
| 1952 | #define PORT_P2_DIR_P7_GET(val) ((((val) & PORT_P2_DIR_P7) >> 7) & 0x1) |
| 1953 | #define PORT_P2_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P7) | (((val) & 0x1) << 7)) |
| 1954 | /* Port 2 Pin #Direction Control (6) */ |
| 1955 | #define PORT_P2_DIR_P6 (0x1 << 6) |
| 1956 | #define PORT_P2_DIR_P6_VAL(val) (((val) & 0x1) << 6) |
| 1957 | #define PORT_P2_DIR_P6_GET(val) ((((val) & PORT_P2_DIR_P6) >> 6) & 0x1) |
| 1958 | #define PORT_P2_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P6) | (((val) & 0x1) << 6)) |
| 1959 | /* Port 2 Pin #Direction Control (5) */ |
| 1960 | #define PORT_P2_DIR_P5 (0x1 << 5) |
| 1961 | #define PORT_P2_DIR_P5_VAL(val) (((val) & 0x1) << 5) |
| 1962 | #define PORT_P2_DIR_P5_GET(val) ((((val) & PORT_P2_DIR_P5) >> 5) & 0x1) |
| 1963 | #define PORT_P2_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P5) | (((val) & 0x1) << 5)) |
| 1964 | /* Port 2 Pin #Direction Control (4) */ |
| 1965 | #define PORT_P2_DIR_P4 (0x1 << 4) |
| 1966 | #define PORT_P2_DIR_P4_VAL(val) (((val) & 0x1) << 4) |
| 1967 | #define PORT_P2_DIR_P4_GET(val) ((((val) & PORT_P2_DIR_P4) >> 4) & 0x1) |
| 1968 | #define PORT_P2_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P4) | (((val) & 0x1) << 4)) |
| 1969 | /* Port 2 Pin #Direction Control (3) */ |
| 1970 | #define PORT_P2_DIR_P3 (0x1 << 3) |
| 1971 | #define PORT_P2_DIR_P3_VAL(val) (((val) & 0x1) << 3) |
| 1972 | #define PORT_P2_DIR_P3_GET(val) ((((val) & PORT_P2_DIR_P3) >> 3) & 0x1) |
| 1973 | #define PORT_P2_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P3) | (((val) & 0x1) << 3)) |
| 1974 | /* Port 2 Pin #Direction Control (2) */ |
| 1975 | #define PORT_P2_DIR_P2 (0x1 << 2) |
| 1976 | #define PORT_P2_DIR_P2_VAL(val) (((val) & 0x1) << 2) |
| 1977 | #define PORT_P2_DIR_P2_GET(val) ((((val) & PORT_P2_DIR_P2) >> 2) & 0x1) |
| 1978 | #define PORT_P2_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P2) | (((val) & 0x1) << 2)) |
| 1979 | /* Port 2 Pin #Direction Control (1) */ |
| 1980 | #define PORT_P2_DIR_P1 (0x1 << 1) |
| 1981 | #define PORT_P2_DIR_P1_VAL(val) (((val) & 0x1) << 1) |
| 1982 | #define PORT_P2_DIR_P1_GET(val) ((((val) & PORT_P2_DIR_P1) >> 1) & 0x1) |
| 1983 | #define PORT_P2_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P1) | (((val) & 0x1) << 1)) |
| 1984 | /* Port 2 Pin #Direction Control (0) */ |
| 1985 | #define PORT_P2_DIR_P0 (0x1) |
| 1986 | #define PORT_P2_DIR_P0_VAL(val) (((val) & 0x1) << 0) |
| 1987 | #define PORT_P2_DIR_P0_GET(val) ((((val) & PORT_P2_DIR_P0) >> 0) & 0x1) |
| 1988 | #define PORT_P2_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P0) | (((val) & 0x1) << 0)) |
| 1989 | |
| 1990 | /******************************************************************************* |
| 1991 | * Port 2 Alternate Function Select Register 0 |
| 1992 | ******************************************************************************/ |
| 1993 | |
| 1994 | /* Alternate Function at Port 2 Bit # (19) */ |
| 1995 | #define PORT_P2_ALTSEL0_P19 (0x1 << 19) |
| 1996 | #define PORT_P2_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) |
| 1997 | #define PORT_P2_ALTSEL0_P19_GET(val) ((((val) & PORT_P2_ALTSEL0_P19) >> 19) & 0x1) |
| 1998 | #define PORT_P2_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P19) | (((val) & 0x1) << 19)) |
| 1999 | /* Alternate Function at Port 2 Bit # (18) */ |
| 2000 | #define PORT_P2_ALTSEL0_P18 (0x1 << 18) |
| 2001 | #define PORT_P2_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) |
| 2002 | #define PORT_P2_ALTSEL0_P18_GET(val) ((((val) & PORT_P2_ALTSEL0_P18) >> 18) & 0x1) |
| 2003 | #define PORT_P2_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P18) | (((val) & 0x1) << 18)) |
| 2004 | /* Alternate Function at Port 2 Bit # (17) */ |
| 2005 | #define PORT_P2_ALTSEL0_P17 (0x1 << 17) |
| 2006 | #define PORT_P2_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) |
| 2007 | #define PORT_P2_ALTSEL0_P17_GET(val) ((((val) & PORT_P2_ALTSEL0_P17) >> 17) & 0x1) |
| 2008 | #define PORT_P2_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P17) | (((val) & 0x1) << 17)) |
| 2009 | /* Alternate Function at Port 2 Bit # (16) */ |
| 2010 | #define PORT_P2_ALTSEL0_P16 (0x1 << 16) |
| 2011 | #define PORT_P2_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) |
| 2012 | #define PORT_P2_ALTSEL0_P16_GET(val) ((((val) & PORT_P2_ALTSEL0_P16) >> 16) & 0x1) |
| 2013 | #define PORT_P2_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P16) | (((val) & 0x1) << 16)) |
| 2014 | /* Alternate Function at Port 2 Bit # (15) */ |
| 2015 | #define PORT_P2_ALTSEL0_P15 (0x1 << 15) |
| 2016 | #define PORT_P2_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) |
| 2017 | #define PORT_P2_ALTSEL0_P15_GET(val) ((((val) & PORT_P2_ALTSEL0_P15) >> 15) & 0x1) |
| 2018 | #define PORT_P2_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P15) | (((val) & 0x1) << 15)) |
| 2019 | /* Alternate Function at Port 2 Bit # (14) */ |
| 2020 | #define PORT_P2_ALTSEL0_P14 (0x1 << 14) |
| 2021 | #define PORT_P2_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) |
| 2022 | #define PORT_P2_ALTSEL0_P14_GET(val) ((((val) & PORT_P2_ALTSEL0_P14) >> 14) & 0x1) |
| 2023 | #define PORT_P2_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P14) | (((val) & 0x1) << 14)) |
| 2024 | /* Alternate Function at Port 2 Bit # (13) */ |
| 2025 | #define PORT_P2_ALTSEL0_P13 (0x1 << 13) |
| 2026 | #define PORT_P2_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) |
| 2027 | #define PORT_P2_ALTSEL0_P13_GET(val) ((((val) & PORT_P2_ALTSEL0_P13) >> 13) & 0x1) |
| 2028 | #define PORT_P2_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P13) | (((val) & 0x1) << 13)) |
| 2029 | /* Alternate Function at Port 2 Bit # (12) */ |
| 2030 | #define PORT_P2_ALTSEL0_P12 (0x1 << 12) |
| 2031 | #define PORT_P2_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) |
| 2032 | #define PORT_P2_ALTSEL0_P12_GET(val) ((((val) & PORT_P2_ALTSEL0_P12) >> 12) & 0x1) |
| 2033 | #define PORT_P2_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P12) | (((val) & 0x1) << 12)) |
| 2034 | /* Alternate Function at Port 2 Bit # (11) */ |
| 2035 | #define PORT_P2_ALTSEL0_P11 (0x1 << 11) |
| 2036 | #define PORT_P2_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) |
| 2037 | #define PORT_P2_ALTSEL0_P11_GET(val) ((((val) & PORT_P2_ALTSEL0_P11) >> 11) & 0x1) |
| 2038 | #define PORT_P2_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P11) | (((val) & 0x1) << 11)) |
| 2039 | /* Alternate Function at Port 2 Bit # (10) */ |
| 2040 | #define PORT_P2_ALTSEL0_P10 (0x1 << 10) |
| 2041 | #define PORT_P2_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) |
| 2042 | #define PORT_P2_ALTSEL0_P10_GET(val) ((((val) & PORT_P2_ALTSEL0_P10) >> 10) & 0x1) |
| 2043 | #define PORT_P2_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P10) | (((val) & 0x1) << 10)) |
| 2044 | /* Alternate Function at Port 2 Bit # (9) */ |
| 2045 | #define PORT_P2_ALTSEL0_P9 (0x1 << 9) |
| 2046 | #define PORT_P2_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) |
| 2047 | #define PORT_P2_ALTSEL0_P9_GET(val) ((((val) & PORT_P2_ALTSEL0_P9) >> 9) & 0x1) |
| 2048 | #define PORT_P2_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P9) | (((val) & 0x1) << 9)) |
| 2049 | /* Alternate Function at Port 2 Bit # (8) */ |
| 2050 | #define PORT_P2_ALTSEL0_P8 (0x1 << 8) |
| 2051 | #define PORT_P2_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) |
| 2052 | #define PORT_P2_ALTSEL0_P8_GET(val) ((((val) & PORT_P2_ALTSEL0_P8) >> 8) & 0x1) |
| 2053 | #define PORT_P2_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P8) | (((val) & 0x1) << 8)) |
| 2054 | /* Alternate Function at Port 2 Bit # (7) */ |
| 2055 | #define PORT_P2_ALTSEL0_P7 (0x1 << 7) |
| 2056 | #define PORT_P2_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) |
| 2057 | #define PORT_P2_ALTSEL0_P7_GET(val) ((((val) & PORT_P2_ALTSEL0_P7) >> 7) & 0x1) |
| 2058 | #define PORT_P2_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P7) | (((val) & 0x1) << 7)) |
| 2059 | /* Alternate Function at Port 2 Bit # (6) */ |
| 2060 | #define PORT_P2_ALTSEL0_P6 (0x1 << 6) |
| 2061 | #define PORT_P2_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) |
| 2062 | #define PORT_P2_ALTSEL0_P6_GET(val) ((((val) & PORT_P2_ALTSEL0_P6) >> 6) & 0x1) |
| 2063 | #define PORT_P2_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P6) | (((val) & 0x1) << 6)) |
| 2064 | /* Alternate Function at Port 2 Bit # (5) */ |
| 2065 | #define PORT_P2_ALTSEL0_P5 (0x1 << 5) |
| 2066 | #define PORT_P2_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) |
| 2067 | #define PORT_P2_ALTSEL0_P5_GET(val) ((((val) & PORT_P2_ALTSEL0_P5) >> 5) & 0x1) |
| 2068 | #define PORT_P2_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P5) | (((val) & 0x1) << 5)) |
| 2069 | /* Alternate Function at Port 2 Bit # (4) */ |
| 2070 | #define PORT_P2_ALTSEL0_P4 (0x1 << 4) |
| 2071 | #define PORT_P2_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) |
| 2072 | #define PORT_P2_ALTSEL0_P4_GET(val) ((((val) & PORT_P2_ALTSEL0_P4) >> 4) & 0x1) |
| 2073 | #define PORT_P2_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P4) | (((val) & 0x1) << 4)) |
| 2074 | /* Alternate Function at Port 2 Bit # (3) */ |
| 2075 | #define PORT_P2_ALTSEL0_P3 (0x1 << 3) |
| 2076 | #define PORT_P2_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) |
| 2077 | #define PORT_P2_ALTSEL0_P3_GET(val) ((((val) & PORT_P2_ALTSEL0_P3) >> 3) & 0x1) |
| 2078 | #define PORT_P2_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P3) | (((val) & 0x1) << 3)) |
| 2079 | /* Alternate Function at Port 2 Bit # (2) */ |
| 2080 | #define PORT_P2_ALTSEL0_P2 (0x1 << 2) |
| 2081 | #define PORT_P2_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) |
| 2082 | #define PORT_P2_ALTSEL0_P2_GET(val) ((((val) & PORT_P2_ALTSEL0_P2) >> 2) & 0x1) |
| 2083 | #define PORT_P2_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P2) | (((val) & 0x1) << 2)) |
| 2084 | /* Alternate Function at Port 2 Bit # (1) */ |
| 2085 | #define PORT_P2_ALTSEL0_P1 (0x1 << 1) |
| 2086 | #define PORT_P2_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) |
| 2087 | #define PORT_P2_ALTSEL0_P1_GET(val) ((((val) & PORT_P2_ALTSEL0_P1) >> 1) & 0x1) |
| 2088 | #define PORT_P2_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P1) | (((val) & 0x1) << 1)) |
| 2089 | /* Alternate Function at Port 2 Bit # (0) */ |
| 2090 | #define PORT_P2_ALTSEL0_P0 (0x1) |
| 2091 | #define PORT_P2_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) |
| 2092 | #define PORT_P2_ALTSEL0_P0_GET(val) ((((val) & PORT_P2_ALTSEL0_P0) >> 0) & 0x1) |
| 2093 | #define PORT_P2_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P0) | (((val) & 0x1) << 0)) |
| 2094 | |
| 2095 | /******************************************************************************* |
| 2096 | * Port 2 Pull Up Device Enable Register |
| 2097 | ******************************************************************************/ |
| 2098 | |
| 2099 | /* Pull Up Device Enable at Port 2 Bit # (19) */ |
| 2100 | #define PORT_P2_PUEN_P19 (0x1 << 19) |
| 2101 | #define PORT_P2_PUEN_P19_VAL(val) (((val) & 0x1) << 19) |
| 2102 | #define PORT_P2_PUEN_P19_GET(val) ((((val) & PORT_P2_PUEN_P19) >> 19) & 0x1) |
| 2103 | #define PORT_P2_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P19) | (((val) & 0x1) << 19)) |
| 2104 | /* Pull Up Device Enable at Port 2 Bit # (18) */ |
| 2105 | #define PORT_P2_PUEN_P18 (0x1 << 18) |
| 2106 | #define PORT_P2_PUEN_P18_VAL(val) (((val) & 0x1) << 18) |
| 2107 | #define PORT_P2_PUEN_P18_GET(val) ((((val) & PORT_P2_PUEN_P18) >> 18) & 0x1) |
| 2108 | #define PORT_P2_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P18) | (((val) & 0x1) << 18)) |
| 2109 | /* Pull Up Device Enable at Port 2 Bit # (17) */ |
| 2110 | #define PORT_P2_PUEN_P17 (0x1 << 17) |
| 2111 | #define PORT_P2_PUEN_P17_VAL(val) (((val) & 0x1) << 17) |
| 2112 | #define PORT_P2_PUEN_P17_GET(val) ((((val) & PORT_P2_PUEN_P17) >> 17) & 0x1) |
| 2113 | #define PORT_P2_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P17) | (((val) & 0x1) << 17)) |
| 2114 | /* Pull Up Device Enable at Port 2 Bit # (16) */ |
| 2115 | #define PORT_P2_PUEN_P16 (0x1 << 16) |
| 2116 | #define PORT_P2_PUEN_P16_VAL(val) (((val) & 0x1) << 16) |
| 2117 | #define PORT_P2_PUEN_P16_GET(val) ((((val) & PORT_P2_PUEN_P16) >> 16) & 0x1) |
| 2118 | #define PORT_P2_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P16) | (((val) & 0x1) << 16)) |
| 2119 | /* Pull Up Device Enable at Port 2 Bit # (15) */ |
| 2120 | #define PORT_P2_PUEN_P15 (0x1 << 15) |
| 2121 | #define PORT_P2_PUEN_P15_VAL(val) (((val) & 0x1) << 15) |
| 2122 | #define PORT_P2_PUEN_P15_GET(val) ((((val) & PORT_P2_PUEN_P15) >> 15) & 0x1) |
| 2123 | #define PORT_P2_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P15) | (((val) & 0x1) << 15)) |
| 2124 | /* Pull Up Device Enable at Port 2 Bit # (14) */ |
| 2125 | #define PORT_P2_PUEN_P14 (0x1 << 14) |
| 2126 | #define PORT_P2_PUEN_P14_VAL(val) (((val) & 0x1) << 14) |
| 2127 | #define PORT_P2_PUEN_P14_GET(val) ((((val) & PORT_P2_PUEN_P14) >> 14) & 0x1) |
| 2128 | #define PORT_P2_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P14) | (((val) & 0x1) << 14)) |
| 2129 | /* Pull Up Device Enable at Port 2 Bit # (13) */ |
| 2130 | #define PORT_P2_PUEN_P13 (0x1 << 13) |
| 2131 | #define PORT_P2_PUEN_P13_VAL(val) (((val) & 0x1) << 13) |
| 2132 | #define PORT_P2_PUEN_P13_GET(val) ((((val) & PORT_P2_PUEN_P13) >> 13) & 0x1) |
| 2133 | #define PORT_P2_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P13) | (((val) & 0x1) << 13)) |
| 2134 | /* Pull Up Device Enable at Port 2 Bit # (12) */ |
| 2135 | #define PORT_P2_PUEN_P12 (0x1 << 12) |
| 2136 | #define PORT_P2_PUEN_P12_VAL(val) (((val) & 0x1) << 12) |
| 2137 | #define PORT_P2_PUEN_P12_GET(val) ((((val) & PORT_P2_PUEN_P12) >> 12) & 0x1) |
| 2138 | #define PORT_P2_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P12) | (((val) & 0x1) << 12)) |
| 2139 | /* Pull Up Device Enable at Port 2 Bit # (11) */ |
| 2140 | #define PORT_P2_PUEN_P11 (0x1 << 11) |
| 2141 | #define PORT_P2_PUEN_P11_VAL(val) (((val) & 0x1) << 11) |
| 2142 | #define PORT_P2_PUEN_P11_GET(val) ((((val) & PORT_P2_PUEN_P11) >> 11) & 0x1) |
| 2143 | #define PORT_P2_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P11) | (((val) & 0x1) << 11)) |
| 2144 | /* Pull Up Device Enable at Port 2 Bit # (10) */ |
| 2145 | #define PORT_P2_PUEN_P10 (0x1 << 10) |
| 2146 | #define PORT_P2_PUEN_P10_VAL(val) (((val) & 0x1) << 10) |
| 2147 | #define PORT_P2_PUEN_P10_GET(val) ((((val) & PORT_P2_PUEN_P10) >> 10) & 0x1) |
| 2148 | #define PORT_P2_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P10) | (((val) & 0x1) << 10)) |
| 2149 | /* Pull Up Device Enable at Port 2 Bit # (9) */ |
| 2150 | #define PORT_P2_PUEN_P9 (0x1 << 9) |
| 2151 | #define PORT_P2_PUEN_P9_VAL(val) (((val) & 0x1) << 9) |
| 2152 | #define PORT_P2_PUEN_P9_GET(val) ((((val) & PORT_P2_PUEN_P9) >> 9) & 0x1) |
| 2153 | #define PORT_P2_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P9) | (((val) & 0x1) << 9)) |
| 2154 | /* Pull Up Device Enable at Port 2 Bit # (8) */ |
| 2155 | #define PORT_P2_PUEN_P8 (0x1 << 8) |
| 2156 | #define PORT_P2_PUEN_P8_VAL(val) (((val) & 0x1) << 8) |
| 2157 | #define PORT_P2_PUEN_P8_GET(val) ((((val) & PORT_P2_PUEN_P8) >> 8) & 0x1) |
| 2158 | #define PORT_P2_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P8) | (((val) & 0x1) << 8)) |
| 2159 | /* Pull Up Device Enable at Port 2 Bit # (7) */ |
| 2160 | #define PORT_P2_PUEN_P7 (0x1 << 7) |
| 2161 | #define PORT_P2_PUEN_P7_VAL(val) (((val) & 0x1) << 7) |
| 2162 | #define PORT_P2_PUEN_P7_GET(val) ((((val) & PORT_P2_PUEN_P7) >> 7) & 0x1) |
| 2163 | #define PORT_P2_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P7) | (((val) & 0x1) << 7)) |
| 2164 | /* Pull Up Device Enable at Port 2 Bit # (6) */ |
| 2165 | #define PORT_P2_PUEN_P6 (0x1 << 6) |
| 2166 | #define PORT_P2_PUEN_P6_VAL(val) (((val) & 0x1) << 6) |
| 2167 | #define PORT_P2_PUEN_P6_GET(val) ((((val) & PORT_P2_PUEN_P6) >> 6) & 0x1) |
| 2168 | #define PORT_P2_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P6) | (((val) & 0x1) << 6)) |
| 2169 | /* Pull Up Device Enable at Port 2 Bit # (5) */ |
| 2170 | #define PORT_P2_PUEN_P5 (0x1 << 5) |
| 2171 | #define PORT_P2_PUEN_P5_VAL(val) (((val) & 0x1) << 5) |
| 2172 | #define PORT_P2_PUEN_P5_GET(val) ((((val) & PORT_P2_PUEN_P5) >> 5) & 0x1) |
| 2173 | #define PORT_P2_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P5) | (((val) & 0x1) << 5)) |
| 2174 | /* Pull Up Device Enable at Port 2 Bit # (4) */ |
| 2175 | #define PORT_P2_PUEN_P4 (0x1 << 4) |
| 2176 | #define PORT_P2_PUEN_P4_VAL(val) (((val) & 0x1) << 4) |
| 2177 | #define PORT_P2_PUEN_P4_GET(val) ((((val) & PORT_P2_PUEN_P4) >> 4) & 0x1) |
| 2178 | #define PORT_P2_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P4) | (((val) & 0x1) << 4)) |
| 2179 | /* Pull Up Device Enable at Port 2 Bit # (3) */ |
| 2180 | #define PORT_P2_PUEN_P3 (0x1 << 3) |
| 2181 | #define PORT_P2_PUEN_P3_VAL(val) (((val) & 0x1) << 3) |
| 2182 | #define PORT_P2_PUEN_P3_GET(val) ((((val) & PORT_P2_PUEN_P3) >> 3) & 0x1) |
| 2183 | #define PORT_P2_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P3) | (((val) & 0x1) << 3)) |
| 2184 | /* Pull Up Device Enable at Port 2 Bit # (2) */ |
| 2185 | #define PORT_P2_PUEN_P2 (0x1 << 2) |
| 2186 | #define PORT_P2_PUEN_P2_VAL(val) (((val) & 0x1) << 2) |
| 2187 | #define PORT_P2_PUEN_P2_GET(val) ((((val) & PORT_P2_PUEN_P2) >> 2) & 0x1) |
| 2188 | #define PORT_P2_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P2) | (((val) & 0x1) << 2)) |
| 2189 | /* Pull Up Device Enable at Port 2 Bit # (1) */ |
| 2190 | #define PORT_P2_PUEN_P1 (0x1 << 1) |
| 2191 | #define PORT_P2_PUEN_P1_VAL(val) (((val) & 0x1) << 1) |
| 2192 | #define PORT_P2_PUEN_P1_GET(val) ((((val) & PORT_P2_PUEN_P1) >> 1) & 0x1) |
| 2193 | #define PORT_P2_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P1) | (((val) & 0x1) << 1)) |
| 2194 | /* Pull Up Device Enable at Port 2 Bit # (0) */ |
| 2195 | #define PORT_P2_PUEN_P0 (0x1) |
| 2196 | #define PORT_P2_PUEN_P0_VAL(val) (((val) & 0x1) << 0) |
| 2197 | #define PORT_P2_PUEN_P0_GET(val) ((((val) & PORT_P2_PUEN_P0) >> 0) & 0x1) |
| 2198 | #define PORT_P2_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P0) | (((val) & 0x1) << 0)) |
| 2199 | |
| 2200 | /******************************************************************************* |
| 2201 | * Port 3 Data Output Register |
| 2202 | ******************************************************************************/ |
| 2203 | |
| 2204 | /* Port 3 Pin # Output Value (19) */ |
| 2205 | #define PORT_P3_OUT_P19 (0x1 << 19) |
| 2206 | #define PORT_P3_OUT_P19_VAL(val) (((val) & 0x1) << 19) |
| 2207 | #define PORT_P3_OUT_P19_GET(val) ((((val) & PORT_P3_OUT_P19) >> 19) & 0x1) |
| 2208 | #define PORT_P3_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P19) | (((val) & 0x1) << 19)) |
| 2209 | /* Port 3 Pin # Output Value (18) */ |
| 2210 | #define PORT_P3_OUT_P18 (0x1 << 18) |
| 2211 | #define PORT_P3_OUT_P18_VAL(val) (((val) & 0x1) << 18) |
| 2212 | #define PORT_P3_OUT_P18_GET(val) ((((val) & PORT_P3_OUT_P18) >> 18) & 0x1) |
| 2213 | #define PORT_P3_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P18) | (((val) & 0x1) << 18)) |
| 2214 | /* Port 3 Pin # Output Value (17) */ |
| 2215 | #define PORT_P3_OUT_P17 (0x1 << 17) |
| 2216 | #define PORT_P3_OUT_P17_VAL(val) (((val) & 0x1) << 17) |
| 2217 | #define PORT_P3_OUT_P17_GET(val) ((((val) & PORT_P3_OUT_P17) >> 17) & 0x1) |
| 2218 | #define PORT_P3_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P17) | (((val) & 0x1) << 17)) |
| 2219 | /* Port 3 Pin # Output Value (16) */ |
| 2220 | #define PORT_P3_OUT_P16 (0x1 << 16) |
| 2221 | #define PORT_P3_OUT_P16_VAL(val) (((val) & 0x1) << 16) |
| 2222 | #define PORT_P3_OUT_P16_GET(val) ((((val) & PORT_P3_OUT_P16) >> 16) & 0x1) |
| 2223 | #define PORT_P3_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P16) | (((val) & 0x1) << 16)) |
| 2224 | /* Port 3 Pin # Output Value (15) */ |
| 2225 | #define PORT_P3_OUT_P15 (0x1 << 15) |
| 2226 | #define PORT_P3_OUT_P15_VAL(val) (((val) & 0x1) << 15) |
| 2227 | #define PORT_P3_OUT_P15_GET(val) ((((val) & PORT_P3_OUT_P15) >> 15) & 0x1) |
| 2228 | #define PORT_P3_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P15) | (((val) & 0x1) << 15)) |
| 2229 | /* Port 3 Pin # Output Value (14) */ |
| 2230 | #define PORT_P3_OUT_P14 (0x1 << 14) |
| 2231 | #define PORT_P3_OUT_P14_VAL(val) (((val) & 0x1) << 14) |
| 2232 | #define PORT_P3_OUT_P14_GET(val) ((((val) & PORT_P3_OUT_P14) >> 14) & 0x1) |
| 2233 | #define PORT_P3_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P14) | (((val) & 0x1) << 14)) |
| 2234 | /* Port 3 Pin # Output Value (13) */ |
| 2235 | #define PORT_P3_OUT_P13 (0x1 << 13) |
| 2236 | #define PORT_P3_OUT_P13_VAL(val) (((val) & 0x1) << 13) |
| 2237 | #define PORT_P3_OUT_P13_GET(val) ((((val) & PORT_P3_OUT_P13) >> 13) & 0x1) |
| 2238 | #define PORT_P3_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P13) | (((val) & 0x1) << 13)) |
| 2239 | /* Port 3 Pin # Output Value (12) */ |
| 2240 | #define PORT_P3_OUT_P12 (0x1 << 12) |
| 2241 | #define PORT_P3_OUT_P12_VAL(val) (((val) & 0x1) << 12) |
| 2242 | #define PORT_P3_OUT_P12_GET(val) ((((val) & PORT_P3_OUT_P12) >> 12) & 0x1) |
| 2243 | #define PORT_P3_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P12) | (((val) & 0x1) << 12)) |
| 2244 | /* Port 3 Pin # Output Value (11) */ |
| 2245 | #define PORT_P3_OUT_P11 (0x1 << 11) |
| 2246 | #define PORT_P3_OUT_P11_VAL(val) (((val) & 0x1) << 11) |
| 2247 | #define PORT_P3_OUT_P11_GET(val) ((((val) & PORT_P3_OUT_P11) >> 11) & 0x1) |
| 2248 | #define PORT_P3_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P11) | (((val) & 0x1) << 11)) |
| 2249 | /* Port 3 Pin # Output Value (10) */ |
| 2250 | #define PORT_P3_OUT_P10 (0x1 << 10) |
| 2251 | #define PORT_P3_OUT_P10_VAL(val) (((val) & 0x1) << 10) |
| 2252 | #define PORT_P3_OUT_P10_GET(val) ((((val) & PORT_P3_OUT_P10) >> 10) & 0x1) |
| 2253 | #define PORT_P3_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P10) | (((val) & 0x1) << 10)) |
| 2254 | /* Port 3 Pin # Output Value (9) */ |
| 2255 | #define PORT_P3_OUT_P9 (0x1 << 9) |
| 2256 | #define PORT_P3_OUT_P9_VAL(val) (((val) & 0x1) << 9) |
| 2257 | #define PORT_P3_OUT_P9_GET(val) ((((val) & PORT_P3_OUT_P9) >> 9) & 0x1) |
| 2258 | #define PORT_P3_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P9) | (((val) & 0x1) << 9)) |
| 2259 | /* Port 3 Pin # Output Value (8) */ |
| 2260 | #define PORT_P3_OUT_P8 (0x1 << 8) |
| 2261 | #define PORT_P3_OUT_P8_VAL(val) (((val) & 0x1) << 8) |
| 2262 | #define PORT_P3_OUT_P8_GET(val) ((((val) & PORT_P3_OUT_P8) >> 8) & 0x1) |
| 2263 | #define PORT_P3_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P8) | (((val) & 0x1) << 8)) |
| 2264 | /* Port 3 Pin # Output Value (7) */ |
| 2265 | #define PORT_P3_OUT_P7 (0x1 << 7) |
| 2266 | #define PORT_P3_OUT_P7_VAL(val) (((val) & 0x1) << 7) |
| 2267 | #define PORT_P3_OUT_P7_GET(val) ((((val) & PORT_P3_OUT_P7) >> 7) & 0x1) |
| 2268 | #define PORT_P3_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P7) | (((val) & 0x1) << 7)) |
| 2269 | /* Port 3 Pin # Output Value (6) */ |
| 2270 | #define PORT_P3_OUT_P6 (0x1 << 6) |
| 2271 | #define PORT_P3_OUT_P6_VAL(val) (((val) & 0x1) << 6) |
| 2272 | #define PORT_P3_OUT_P6_GET(val) ((((val) & PORT_P3_OUT_P6) >> 6) & 0x1) |
| 2273 | #define PORT_P3_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P6) | (((val) & 0x1) << 6)) |
| 2274 | /* Port 3 Pin # Output Value (5) */ |
| 2275 | #define PORT_P3_OUT_P5 (0x1 << 5) |
| 2276 | #define PORT_P3_OUT_P5_VAL(val) (((val) & 0x1) << 5) |
| 2277 | #define PORT_P3_OUT_P5_GET(val) ((((val) & PORT_P3_OUT_P5) >> 5) & 0x1) |
| 2278 | #define PORT_P3_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P5) | (((val) & 0x1) << 5)) |
| 2279 | /* Port 3 Pin # Output Value (4) */ |
| 2280 | #define PORT_P3_OUT_P4 (0x1 << 4) |
| 2281 | #define PORT_P3_OUT_P4_VAL(val) (((val) & 0x1) << 4) |
| 2282 | #define PORT_P3_OUT_P4_GET(val) ((((val) & PORT_P3_OUT_P4) >> 4) & 0x1) |
| 2283 | #define PORT_P3_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P4) | (((val) & 0x1) << 4)) |
| 2284 | /* Port 3 Pin # Output Value (3) */ |
| 2285 | #define PORT_P3_OUT_P3 (0x1 << 3) |
| 2286 | #define PORT_P3_OUT_P3_VAL(val) (((val) & 0x1) << 3) |
| 2287 | #define PORT_P3_OUT_P3_GET(val) ((((val) & PORT_P3_OUT_P3) >> 3) & 0x1) |
| 2288 | #define PORT_P3_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P3) | (((val) & 0x1) << 3)) |
| 2289 | /* Port 3 Pin # Output Value (2) */ |
| 2290 | #define PORT_P3_OUT_P2 (0x1 << 2) |
| 2291 | #define PORT_P3_OUT_P2_VAL(val) (((val) & 0x1) << 2) |
| 2292 | #define PORT_P3_OUT_P2_GET(val) ((((val) & PORT_P3_OUT_P2) >> 2) & 0x1) |
| 2293 | #define PORT_P3_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P2) | (((val) & 0x1) << 2)) |
| 2294 | /* Port 3 Pin # Output Value (1) */ |
| 2295 | #define PORT_P3_OUT_P1 (0x1 << 1) |
| 2296 | #define PORT_P3_OUT_P1_VAL(val) (((val) & 0x1) << 1) |
| 2297 | #define PORT_P3_OUT_P1_GET(val) ((((val) & PORT_P3_OUT_P1) >> 1) & 0x1) |
| 2298 | #define PORT_P3_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P1) | (((val) & 0x1) << 1)) |
| 2299 | /* Port 3 Pin # Output Value (0) */ |
| 2300 | #define PORT_P3_OUT_P0 (0x1) |
| 2301 | #define PORT_P3_OUT_P0_VAL(val) (((val) & 0x1) << 0) |
| 2302 | #define PORT_P3_OUT_P0_GET(val) ((((val) & PORT_P3_OUT_P0) >> 0) & 0x1) |
| 2303 | #define PORT_P3_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P0) | (((val) & 0x1) << 0)) |
| 2304 | |
| 2305 | /******************************************************************************* |
| 2306 | * Port 3 Data Input Register |
| 2307 | ******************************************************************************/ |
| 2308 | |
| 2309 | /* Port 3 Pin # Latched Input Value (19) */ |
| 2310 | #define PORT_P3_IN_P19 (0x1 << 19) |
| 2311 | #define PORT_P3_IN_P19_GET(val) ((((val) & PORT_P3_IN_P19) >> 19) & 0x1) |
| 2312 | /* Port 3 Pin # Latched Input Value (18) */ |
| 2313 | #define PORT_P3_IN_P18 (0x1 << 18) |
| 2314 | #define PORT_P3_IN_P18_GET(val) ((((val) & PORT_P3_IN_P18) >> 18) & 0x1) |
| 2315 | /* Port 3 Pin # Latched Input Value (17) */ |
| 2316 | #define PORT_P3_IN_P17 (0x1 << 17) |
| 2317 | #define PORT_P3_IN_P17_GET(val) ((((val) & PORT_P3_IN_P17) >> 17) & 0x1) |
| 2318 | /* Port 3 Pin # Latched Input Value (16) */ |
| 2319 | #define PORT_P3_IN_P16 (0x1 << 16) |
| 2320 | #define PORT_P3_IN_P16_GET(val) ((((val) & PORT_P3_IN_P16) >> 16) & 0x1) |
| 2321 | /* Port 3 Pin # Latched Input Value (15) */ |
| 2322 | #define PORT_P3_IN_P15 (0x1 << 15) |
| 2323 | #define PORT_P3_IN_P15_GET(val) ((((val) & PORT_P3_IN_P15) >> 15) & 0x1) |
| 2324 | /* Port 3 Pin # Latched Input Value (14) */ |
| 2325 | #define PORT_P3_IN_P14 (0x1 << 14) |
| 2326 | #define PORT_P3_IN_P14_GET(val) ((((val) & PORT_P3_IN_P14) >> 14) & 0x1) |
| 2327 | /* Port 3 Pin # Latched Input Value (13) */ |
| 2328 | #define PORT_P3_IN_P13 (0x1 << 13) |
| 2329 | #define PORT_P3_IN_P13_GET(val) ((((val) & PORT_P3_IN_P13) >> 13) & 0x1) |
| 2330 | /* Port 3 Pin # Latched Input Value (12) */ |
| 2331 | #define PORT_P3_IN_P12 (0x1 << 12) |
| 2332 | #define PORT_P3_IN_P12_GET(val) ((((val) & PORT_P3_IN_P12) >> 12) & 0x1) |
| 2333 | /* Port 3 Pin # Latched Input Value (11) */ |
| 2334 | #define PORT_P3_IN_P11 (0x1 << 11) |
| 2335 | #define PORT_P3_IN_P11_GET(val) ((((val) & PORT_P3_IN_P11) >> 11) & 0x1) |
| 2336 | /* Port 3 Pin # Latched Input Value (10) */ |
| 2337 | #define PORT_P3_IN_P10 (0x1 << 10) |
| 2338 | #define PORT_P3_IN_P10_GET(val) ((((val) & PORT_P3_IN_P10) >> 10) & 0x1) |
| 2339 | /* Port 3 Pin # Latched Input Value (9) */ |
| 2340 | #define PORT_P3_IN_P9 (0x1 << 9) |
| 2341 | #define PORT_P3_IN_P9_GET(val) ((((val) & PORT_P3_IN_P9) >> 9) & 0x1) |
| 2342 | /* Port 3 Pin # Latched Input Value (8) */ |
| 2343 | #define PORT_P3_IN_P8 (0x1 << 8) |
| 2344 | #define PORT_P3_IN_P8_GET(val) ((((val) & PORT_P3_IN_P8) >> 8) & 0x1) |
| 2345 | /* Port 3 Pin # Latched Input Value (7) */ |
| 2346 | #define PORT_P3_IN_P7 (0x1 << 7) |
| 2347 | #define PORT_P3_IN_P7_GET(val) ((((val) & PORT_P3_IN_P7) >> 7) & 0x1) |
| 2348 | /* Port 3 Pin # Latched Input Value (6) */ |
| 2349 | #define PORT_P3_IN_P6 (0x1 << 6) |
| 2350 | #define PORT_P3_IN_P6_GET(val) ((((val) & PORT_P3_IN_P6) >> 6) & 0x1) |
| 2351 | /* Port 3 Pin # Latched Input Value (5) */ |
| 2352 | #define PORT_P3_IN_P5 (0x1 << 5) |
| 2353 | #define PORT_P3_IN_P5_GET(val) ((((val) & PORT_P3_IN_P5) >> 5) & 0x1) |
| 2354 | /* Port 3 Pin # Latched Input Value (4) */ |
| 2355 | #define PORT_P3_IN_P4 (0x1 << 4) |
| 2356 | #define PORT_P3_IN_P4_GET(val) ((((val) & PORT_P3_IN_P4) >> 4) & 0x1) |
| 2357 | /* Port 3 Pin # Latched Input Value (3) */ |
| 2358 | #define PORT_P3_IN_P3 (0x1 << 3) |
| 2359 | #define PORT_P3_IN_P3_GET(val) ((((val) & PORT_P3_IN_P3) >> 3) & 0x1) |
| 2360 | /* Port 3 Pin # Latched Input Value (2) */ |
| 2361 | #define PORT_P3_IN_P2 (0x1 << 2) |
| 2362 | #define PORT_P3_IN_P2_GET(val) ((((val) & PORT_P3_IN_P2) >> 2) & 0x1) |
| 2363 | /* Port 3 Pin # Latched Input Value (1) */ |
| 2364 | #define PORT_P3_IN_P1 (0x1 << 1) |
| 2365 | #define PORT_P3_IN_P1_GET(val) ((((val) & PORT_P3_IN_P1) >> 1) & 0x1) |
| 2366 | /* Port 3 Pin # Latched Input Value (0) */ |
| 2367 | #define PORT_P3_IN_P0 (0x1) |
| 2368 | #define PORT_P3_IN_P0_GET(val) ((((val) & PORT_P3_IN_P0) >> 0) & 0x1) |
| 2369 | |
| 2370 | /******************************************************************************* |
| 2371 | * Port 3 Direction Register |
| 2372 | ******************************************************************************/ |
| 2373 | |
| 2374 | /* Port 3 Pin #Direction Control (19) */ |
| 2375 | #define PORT_P3_DIR_P19 (0x1 << 19) |
| 2376 | #define PORT_P3_DIR_P19_VAL(val) (((val) & 0x1) << 19) |
| 2377 | #define PORT_P3_DIR_P19_GET(val) ((((val) & PORT_P3_DIR_P19) >> 19) & 0x1) |
| 2378 | #define PORT_P3_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P19) | (((val) & 0x1) << 19)) |
| 2379 | /* Port 3 Pin #Direction Control (18) */ |
| 2380 | #define PORT_P3_DIR_P18 (0x1 << 18) |
| 2381 | #define PORT_P3_DIR_P18_VAL(val) (((val) & 0x1) << 18) |
| 2382 | #define PORT_P3_DIR_P18_GET(val) ((((val) & PORT_P3_DIR_P18) >> 18) & 0x1) |
| 2383 | #define PORT_P3_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P18) | (((val) & 0x1) << 18)) |
| 2384 | /* Port 3 Pin #Direction Control (17) */ |
| 2385 | #define PORT_P3_DIR_P17 (0x1 << 17) |
| 2386 | #define PORT_P3_DIR_P17_VAL(val) (((val) & 0x1) << 17) |
| 2387 | #define PORT_P3_DIR_P17_GET(val) ((((val) & PORT_P3_DIR_P17) >> 17) & 0x1) |
| 2388 | #define PORT_P3_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P17) | (((val) & 0x1) << 17)) |
| 2389 | /* Port 3 Pin #Direction Control (16) */ |
| 2390 | #define PORT_P3_DIR_P16 (0x1 << 16) |
| 2391 | #define PORT_P3_DIR_P16_VAL(val) (((val) & 0x1) << 16) |
| 2392 | #define PORT_P3_DIR_P16_GET(val) ((((val) & PORT_P3_DIR_P16) >> 16) & 0x1) |
| 2393 | #define PORT_P3_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P16) | (((val) & 0x1) << 16)) |
| 2394 | /* Port 3 Pin #Direction Control (15) */ |
| 2395 | #define PORT_P3_DIR_P15 (0x1 << 15) |
| 2396 | #define PORT_P3_DIR_P15_VAL(val) (((val) & 0x1) << 15) |
| 2397 | #define PORT_P3_DIR_P15_GET(val) ((((val) & PORT_P3_DIR_P15) >> 15) & 0x1) |
| 2398 | #define PORT_P3_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P15) | (((val) & 0x1) << 15)) |
| 2399 | /* Port 3 Pin #Direction Control (14) */ |
| 2400 | #define PORT_P3_DIR_P14 (0x1 << 14) |
| 2401 | #define PORT_P3_DIR_P14_VAL(val) (((val) & 0x1) << 14) |
| 2402 | #define PORT_P3_DIR_P14_GET(val) ((((val) & PORT_P3_DIR_P14) >> 14) & 0x1) |
| 2403 | #define PORT_P3_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P14) | (((val) & 0x1) << 14)) |
| 2404 | /* Port 3 Pin #Direction Control (13) */ |
| 2405 | #define PORT_P3_DIR_P13 (0x1 << 13) |
| 2406 | #define PORT_P3_DIR_P13_VAL(val) (((val) & 0x1) << 13) |
| 2407 | #define PORT_P3_DIR_P13_GET(val) ((((val) & PORT_P3_DIR_P13) >> 13) & 0x1) |
| 2408 | #define PORT_P3_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P13) | (((val) & 0x1) << 13)) |
| 2409 | /* Port 3 Pin #Direction Control (12) */ |
| 2410 | #define PORT_P3_DIR_P12 (0x1 << 12) |
| 2411 | #define PORT_P3_DIR_P12_VAL(val) (((val) & 0x1) << 12) |
| 2412 | #define PORT_P3_DIR_P12_GET(val) ((((val) & PORT_P3_DIR_P12) >> 12) & 0x1) |
| 2413 | #define PORT_P3_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P12) | (((val) & 0x1) << 12)) |
| 2414 | /* Port 3 Pin #Direction Control (11) */ |
| 2415 | #define PORT_P3_DIR_P11 (0x1 << 11) |
| 2416 | #define PORT_P3_DIR_P11_VAL(val) (((val) & 0x1) << 11) |
| 2417 | #define PORT_P3_DIR_P11_GET(val) ((((val) & PORT_P3_DIR_P11) >> 11) & 0x1) |
| 2418 | #define PORT_P3_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P11) | (((val) & 0x1) << 11)) |
| 2419 | /* Port 3 Pin #Direction Control (10) */ |
| 2420 | #define PORT_P3_DIR_P10 (0x1 << 10) |
| 2421 | #define PORT_P3_DIR_P10_VAL(val) (((val) & 0x1) << 10) |
| 2422 | #define PORT_P3_DIR_P10_GET(val) ((((val) & PORT_P3_DIR_P10) >> 10) & 0x1) |
| 2423 | #define PORT_P3_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P10) | (((val) & 0x1) << 10)) |
| 2424 | /* Port 3 Pin #Direction Control (9) */ |
| 2425 | #define PORT_P3_DIR_P9 (0x1 << 9) |
| 2426 | #define PORT_P3_DIR_P9_VAL(val) (((val) & 0x1) << 9) |
| 2427 | #define PORT_P3_DIR_P9_GET(val) ((((val) & PORT_P3_DIR_P9) >> 9) & 0x1) |
| 2428 | #define PORT_P3_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P9) | (((val) & 0x1) << 9)) |
| 2429 | /* Port 3 Pin #Direction Control (8) */ |
| 2430 | #define PORT_P3_DIR_P8 (0x1 << 8) |
| 2431 | #define PORT_P3_DIR_P8_VAL(val) (((val) & 0x1) << 8) |
| 2432 | #define PORT_P3_DIR_P8_GET(val) ((((val) & PORT_P3_DIR_P8) >> 8) & 0x1) |
| 2433 | #define PORT_P3_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P8) | (((val) & 0x1) << 8)) |
| 2434 | /* Port 3 Pin #Direction Control (7) */ |
| 2435 | #define PORT_P3_DIR_P7 (0x1 << 7) |
| 2436 | #define PORT_P3_DIR_P7_VAL(val) (((val) & 0x1) << 7) |
| 2437 | #define PORT_P3_DIR_P7_GET(val) ((((val) & PORT_P3_DIR_P7) >> 7) & 0x1) |
| 2438 | #define PORT_P3_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P7) | (((val) & 0x1) << 7)) |
| 2439 | /* Port 3 Pin #Direction Control (6) */ |
| 2440 | #define PORT_P3_DIR_P6 (0x1 << 6) |
| 2441 | #define PORT_P3_DIR_P6_VAL(val) (((val) & 0x1) << 6) |
| 2442 | #define PORT_P3_DIR_P6_GET(val) ((((val) & PORT_P3_DIR_P6) >> 6) & 0x1) |
| 2443 | #define PORT_P3_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P6) | (((val) & 0x1) << 6)) |
| 2444 | /* Port 3 Pin #Direction Control (5) */ |
| 2445 | #define PORT_P3_DIR_P5 (0x1 << 5) |
| 2446 | #define PORT_P3_DIR_P5_VAL(val) (((val) & 0x1) << 5) |
| 2447 | #define PORT_P3_DIR_P5_GET(val) ((((val) & PORT_P3_DIR_P5) >> 5) & 0x1) |
| 2448 | #define PORT_P3_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P5) | (((val) & 0x1) << 5)) |
| 2449 | /* Port 3 Pin #Direction Control (4) */ |
| 2450 | #define PORT_P3_DIR_P4 (0x1 << 4) |
| 2451 | #define PORT_P3_DIR_P4_VAL(val) (((val) & 0x1) << 4) |
| 2452 | #define PORT_P3_DIR_P4_GET(val) ((((val) & PORT_P3_DIR_P4) >> 4) & 0x1) |
| 2453 | #define PORT_P3_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P4) | (((val) & 0x1) << 4)) |
| 2454 | /* Port 3 Pin #Direction Control (3) */ |
| 2455 | #define PORT_P3_DIR_P3 (0x1 << 3) |
| 2456 | #define PORT_P3_DIR_P3_VAL(val) (((val) & 0x1) << 3) |
| 2457 | #define PORT_P3_DIR_P3_GET(val) ((((val) & PORT_P3_DIR_P3) >> 3) & 0x1) |
| 2458 | #define PORT_P3_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P3) | (((val) & 0x1) << 3)) |
| 2459 | /* Port 3 Pin #Direction Control (2) */ |
| 2460 | #define PORT_P3_DIR_P2 (0x1 << 2) |
| 2461 | #define PORT_P3_DIR_P2_VAL(val) (((val) & 0x1) << 2) |
| 2462 | #define PORT_P3_DIR_P2_GET(val) ((((val) & PORT_P3_DIR_P2) >> 2) & 0x1) |
| 2463 | #define PORT_P3_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P2) | (((val) & 0x1) << 2)) |
| 2464 | /* Port 3 Pin #Direction Control (1) */ |
| 2465 | #define PORT_P3_DIR_P1 (0x1 << 1) |
| 2466 | #define PORT_P3_DIR_P1_VAL(val) (((val) & 0x1) << 1) |
| 2467 | #define PORT_P3_DIR_P1_GET(val) ((((val) & PORT_P3_DIR_P1) >> 1) & 0x1) |
| 2468 | #define PORT_P3_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P1) | (((val) & 0x1) << 1)) |
| 2469 | /* Port 3 Pin #Direction Control (0) */ |
| 2470 | #define PORT_P3_DIR_P0 (0x1) |
| 2471 | #define PORT_P3_DIR_P0_VAL(val) (((val) & 0x1) << 0) |
| 2472 | #define PORT_P3_DIR_P0_GET(val) ((((val) & PORT_P3_DIR_P0) >> 0) & 0x1) |
| 2473 | #define PORT_P3_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P0) | (((val) & 0x1) << 0)) |
| 2474 | |
| 2475 | /******************************************************************************* |
| 2476 | * Port 3 Alternate Function Select Register 0 |
| 2477 | ******************************************************************************/ |
| 2478 | |
| 2479 | /* Alternate Function at Port 3 Bit # (19) */ |
| 2480 | #define PORT_P3_ALTSEL0_P19 (0x1 << 19) |
| 2481 | #define PORT_P3_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) |
| 2482 | #define PORT_P3_ALTSEL0_P19_GET(val) ((((val) & PORT_P3_ALTSEL0_P19) >> 19) & 0x1) |
| 2483 | #define PORT_P3_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P19) | (((val) & 0x1) << 19)) |
| 2484 | /* Alternate Function at Port 3 Bit # (18) */ |
| 2485 | #define PORT_P3_ALTSEL0_P18 (0x1 << 18) |
| 2486 | #define PORT_P3_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) |
| 2487 | #define PORT_P3_ALTSEL0_P18_GET(val) ((((val) & PORT_P3_ALTSEL0_P18) >> 18) & 0x1) |
| 2488 | #define PORT_P3_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P18) | (((val) & 0x1) << 18)) |
| 2489 | /* Alternate Function at Port 3 Bit # (17) */ |
| 2490 | #define PORT_P3_ALTSEL0_P17 (0x1 << 17) |
| 2491 | #define PORT_P3_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) |
| 2492 | #define PORT_P3_ALTSEL0_P17_GET(val) ((((val) & PORT_P3_ALTSEL0_P17) >> 17) & 0x1) |
| 2493 | #define PORT_P3_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P17) | (((val) & 0x1) << 17)) |
| 2494 | /* Alternate Function at Port 3 Bit # (16) */ |
| 2495 | #define PORT_P3_ALTSEL0_P16 (0x1 << 16) |
| 2496 | #define PORT_P3_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) |
| 2497 | #define PORT_P3_ALTSEL0_P16_GET(val) ((((val) & PORT_P3_ALTSEL0_P16) >> 16) & 0x1) |
| 2498 | #define PORT_P3_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P16) | (((val) & 0x1) << 16)) |
| 2499 | /* Alternate Function at Port 3 Bit # (15) */ |
| 2500 | #define PORT_P3_ALTSEL0_P15 (0x1 << 15) |
| 2501 | #define PORT_P3_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) |
| 2502 | #define PORT_P3_ALTSEL0_P15_GET(val) ((((val) & PORT_P3_ALTSEL0_P15) >> 15) & 0x1) |
| 2503 | #define PORT_P3_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P15) | (((val) & 0x1) << 15)) |
| 2504 | /* Alternate Function at Port 3 Bit # (14) */ |
| 2505 | #define PORT_P3_ALTSEL0_P14 (0x1 << 14) |
| 2506 | #define PORT_P3_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) |
| 2507 | #define PORT_P3_ALTSEL0_P14_GET(val) ((((val) & PORT_P3_ALTSEL0_P14) >> 14) & 0x1) |
| 2508 | #define PORT_P3_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P14) | (((val) & 0x1) << 14)) |
| 2509 | /* Alternate Function at Port 3 Bit # (13) */ |
| 2510 | #define PORT_P3_ALTSEL0_P13 (0x1 << 13) |
| 2511 | #define PORT_P3_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) |
| 2512 | #define PORT_P3_ALTSEL0_P13_GET(val) ((((val) & PORT_P3_ALTSEL0_P13) >> 13) & 0x1) |
| 2513 | #define PORT_P3_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P13) | (((val) & 0x1) << 13)) |
| 2514 | /* Alternate Function at Port 3 Bit # (12) */ |
| 2515 | #define PORT_P3_ALTSEL0_P12 (0x1 << 12) |
| 2516 | #define PORT_P3_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) |
| 2517 | #define PORT_P3_ALTSEL0_P12_GET(val) ((((val) & PORT_P3_ALTSEL0_P12) >> 12) & 0x1) |
| 2518 | #define PORT_P3_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P12) | (((val) & 0x1) << 12)) |
| 2519 | /* Alternate Function at Port 3 Bit # (11) */ |
| 2520 | #define PORT_P3_ALTSEL0_P11 (0x1 << 11) |
| 2521 | #define PORT_P3_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) |
| 2522 | #define PORT_P3_ALTSEL0_P11_GET(val) ((((val) & PORT_P3_ALTSEL0_P11) >> 11) & 0x1) |
| 2523 | #define PORT_P3_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P11) | (((val) & 0x1) << 11)) |
| 2524 | /* Alternate Function at Port 3 Bit # (10) */ |
| 2525 | #define PORT_P3_ALTSEL0_P10 (0x1 << 10) |
| 2526 | #define PORT_P3_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) |
| 2527 | #define PORT_P3_ALTSEL0_P10_GET(val) ((((val) & PORT_P3_ALTSEL0_P10) >> 10) & 0x1) |
| 2528 | #define PORT_P3_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P10) | (((val) & 0x1) << 10)) |
| 2529 | /* Alternate Function at Port 3 Bit # (9) */ |
| 2530 | #define PORT_P3_ALTSEL0_P9 (0x1 << 9) |
| 2531 | #define PORT_P3_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) |
| 2532 | #define PORT_P3_ALTSEL0_P9_GET(val) ((((val) & PORT_P3_ALTSEL0_P9) >> 9) & 0x1) |
| 2533 | #define PORT_P3_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P9) | (((val) & 0x1) << 9)) |
| 2534 | /* Alternate Function at Port 3 Bit # (8) */ |
| 2535 | #define PORT_P3_ALTSEL0_P8 (0x1 << 8) |
| 2536 | #define PORT_P3_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) |
| 2537 | #define PORT_P3_ALTSEL0_P8_GET(val) ((((val) & PORT_P3_ALTSEL0_P8) >> 8) & 0x1) |
| 2538 | #define PORT_P3_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P8) | (((val) & 0x1) << 8)) |
| 2539 | /* Alternate Function at Port 3 Bit # (7) */ |
| 2540 | #define PORT_P3_ALTSEL0_P7 (0x1 << 7) |
| 2541 | #define PORT_P3_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) |
| 2542 | #define PORT_P3_ALTSEL0_P7_GET(val) ((((val) & PORT_P3_ALTSEL0_P7) >> 7) & 0x1) |
| 2543 | #define PORT_P3_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P7) | (((val) & 0x1) << 7)) |
| 2544 | /* Alternate Function at Port 3 Bit # (6) */ |
| 2545 | #define PORT_P3_ALTSEL0_P6 (0x1 << 6) |
| 2546 | #define PORT_P3_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) |
| 2547 | #define PORT_P3_ALTSEL0_P6_GET(val) ((((val) & PORT_P3_ALTSEL0_P6) >> 6) & 0x1) |
| 2548 | #define PORT_P3_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P6) | (((val) & 0x1) << 6)) |
| 2549 | /* Alternate Function at Port 3 Bit # (5) */ |
| 2550 | #define PORT_P3_ALTSEL0_P5 (0x1 << 5) |
| 2551 | #define PORT_P3_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) |
| 2552 | #define PORT_P3_ALTSEL0_P5_GET(val) ((((val) & PORT_P3_ALTSEL0_P5) >> 5) & 0x1) |
| 2553 | #define PORT_P3_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P5) | (((val) & 0x1) << 5)) |
| 2554 | /* Alternate Function at Port 3 Bit # (4) */ |
| 2555 | #define PORT_P3_ALTSEL0_P4 (0x1 << 4) |
| 2556 | #define PORT_P3_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) |
| 2557 | #define PORT_P3_ALTSEL0_P4_GET(val) ((((val) & PORT_P3_ALTSEL0_P4) >> 4) & 0x1) |
| 2558 | #define PORT_P3_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P4) | (((val) & 0x1) << 4)) |
| 2559 | /* Alternate Function at Port 3 Bit # (3) */ |
| 2560 | #define PORT_P3_ALTSEL0_P3 (0x1 << 3) |
| 2561 | #define PORT_P3_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) |
| 2562 | #define PORT_P3_ALTSEL0_P3_GET(val) ((((val) & PORT_P3_ALTSEL0_P3) >> 3) & 0x1) |
| 2563 | #define PORT_P3_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P3) | (((val) & 0x1) << 3)) |
| 2564 | /* Alternate Function at Port 3 Bit # (2) */ |
| 2565 | #define PORT_P3_ALTSEL0_P2 (0x1 << 2) |
| 2566 | #define PORT_P3_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) |
| 2567 | #define PORT_P3_ALTSEL0_P2_GET(val) ((((val) & PORT_P3_ALTSEL0_P2) >> 2) & 0x1) |
| 2568 | #define PORT_P3_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P2) | (((val) & 0x1) << 2)) |
| 2569 | /* Alternate Function at Port 3 Bit # (1) */ |
| 2570 | #define PORT_P3_ALTSEL0_P1 (0x1 << 1) |
| 2571 | #define PORT_P3_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) |
| 2572 | #define PORT_P3_ALTSEL0_P1_GET(val) ((((val) & PORT_P3_ALTSEL0_P1) >> 1) & 0x1) |
| 2573 | #define PORT_P3_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P1) | (((val) & 0x1) << 1)) |
| 2574 | /* Alternate Function at Port 3 Bit # (0) */ |
| 2575 | #define PORT_P3_ALTSEL0_P0 (0x1) |
| 2576 | #define PORT_P3_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) |
| 2577 | #define PORT_P3_ALTSEL0_P0_GET(val) ((((val) & PORT_P3_ALTSEL0_P0) >> 0) & 0x1) |
| 2578 | #define PORT_P3_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P0) | (((val) & 0x1) << 0)) |
| 2579 | |
| 2580 | /******************************************************************************* |
| 2581 | * Port 3 Pull Up Device Enable Register |
| 2582 | ******************************************************************************/ |
| 2583 | |
| 2584 | /* Pull Up Device Enable at Port 3 Bit # (19) */ |
| 2585 | #define PORT_P3_PUEN_P19 (0x1 << 19) |
| 2586 | #define PORT_P3_PUEN_P19_VAL(val) (((val) & 0x1) << 19) |
| 2587 | #define PORT_P3_PUEN_P19_GET(val) ((((val) & PORT_P3_PUEN_P19) >> 19) & 0x1) |
| 2588 | #define PORT_P3_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P19) | (((val) & 0x1) << 19)) |
| 2589 | /* Pull Up Device Enable at Port 3 Bit # (18) */ |
| 2590 | #define PORT_P3_PUEN_P18 (0x1 << 18) |
| 2591 | #define PORT_P3_PUEN_P18_VAL(val) (((val) & 0x1) << 18) |
| 2592 | #define PORT_P3_PUEN_P18_GET(val) ((((val) & PORT_P3_PUEN_P18) >> 18) & 0x1) |
| 2593 | #define PORT_P3_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P18) | (((val) & 0x1) << 18)) |
| 2594 | /* Pull Up Device Enable at Port 3 Bit # (17) */ |
| 2595 | #define PORT_P3_PUEN_P17 (0x1 << 17) |
| 2596 | #define PORT_P3_PUEN_P17_VAL(val) (((val) & 0x1) << 17) |
| 2597 | #define PORT_P3_PUEN_P17_GET(val) ((((val) & PORT_P3_PUEN_P17) >> 17) & 0x1) |
| 2598 | #define PORT_P3_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P17) | (((val) & 0x1) << 17)) |
| 2599 | /* Pull Up Device Enable at Port 3 Bit # (16) */ |
| 2600 | #define PORT_P3_PUEN_P16 (0x1 << 16) |
| 2601 | #define PORT_P3_PUEN_P16_VAL(val) (((val) & 0x1) << 16) |
| 2602 | #define PORT_P3_PUEN_P16_GET(val) ((((val) & PORT_P3_PUEN_P16) >> 16) & 0x1) |
| 2603 | #define PORT_P3_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P16) | (((val) & 0x1) << 16)) |
| 2604 | /* Pull Up Device Enable at Port 3 Bit # (15) */ |
| 2605 | #define PORT_P3_PUEN_P15 (0x1 << 15) |
| 2606 | #define PORT_P3_PUEN_P15_VAL(val) (((val) & 0x1) << 15) |
| 2607 | #define PORT_P3_PUEN_P15_GET(val) ((((val) & PORT_P3_PUEN_P15) >> 15) & 0x1) |
| 2608 | #define PORT_P3_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P15) | (((val) & 0x1) << 15)) |
| 2609 | /* Pull Up Device Enable at Port 3 Bit # (14) */ |
| 2610 | #define PORT_P3_PUEN_P14 (0x1 << 14) |
| 2611 | #define PORT_P3_PUEN_P14_VAL(val) (((val) & 0x1) << 14) |
| 2612 | #define PORT_P3_PUEN_P14_GET(val) ((((val) & PORT_P3_PUEN_P14) >> 14) & 0x1) |
| 2613 | #define PORT_P3_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P14) | (((val) & 0x1) << 14)) |
| 2614 | /* Pull Up Device Enable at Port 3 Bit # (13) */ |
| 2615 | #define PORT_P3_PUEN_P13 (0x1 << 13) |
| 2616 | #define PORT_P3_PUEN_P13_VAL(val) (((val) & 0x1) << 13) |
| 2617 | #define PORT_P3_PUEN_P13_GET(val) ((((val) & PORT_P3_PUEN_P13) >> 13) & 0x1) |
| 2618 | #define PORT_P3_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P13) | (((val) & 0x1) << 13)) |
| 2619 | /* Pull Up Device Enable at Port 3 Bit # (12) */ |
| 2620 | #define PORT_P3_PUEN_P12 (0x1 << 12) |
| 2621 | #define PORT_P3_PUEN_P12_VAL(val) (((val) & 0x1) << 12) |
| 2622 | #define PORT_P3_PUEN_P12_GET(val) ((((val) & PORT_P3_PUEN_P12) >> 12) & 0x1) |
| 2623 | #define PORT_P3_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P12) | (((val) & 0x1) << 12)) |
| 2624 | /* Pull Up Device Enable at Port 3 Bit # (11) */ |
| 2625 | #define PORT_P3_PUEN_P11 (0x1 << 11) |
| 2626 | #define PORT_P3_PUEN_P11_VAL(val) (((val) & 0x1) << 11) |
| 2627 | #define PORT_P3_PUEN_P11_GET(val) ((((val) & PORT_P3_PUEN_P11) >> 11) & 0x1) |
| 2628 | #define PORT_P3_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P11) | (((val) & 0x1) << 11)) |
| 2629 | /* Pull Up Device Enable at Port 3 Bit # (10) */ |
| 2630 | #define PORT_P3_PUEN_P10 (0x1 << 10) |
| 2631 | #define PORT_P3_PUEN_P10_VAL(val) (((val) & 0x1) << 10) |
| 2632 | #define PORT_P3_PUEN_P10_GET(val) ((((val) & PORT_P3_PUEN_P10) >> 10) & 0x1) |
| 2633 | #define PORT_P3_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P10) | (((val) & 0x1) << 10)) |
| 2634 | /* Pull Up Device Enable at Port 3 Bit # (9) */ |
| 2635 | #define PORT_P3_PUEN_P9 (0x1 << 9) |
| 2636 | #define PORT_P3_PUEN_P9_VAL(val) (((val) & 0x1) << 9) |
| 2637 | #define PORT_P3_PUEN_P9_GET(val) ((((val) & PORT_P3_PUEN_P9) >> 9) & 0x1) |
| 2638 | #define PORT_P3_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P9) | (((val) & 0x1) << 9)) |
| 2639 | /* Pull Up Device Enable at Port 3 Bit # (8) */ |
| 2640 | #define PORT_P3_PUEN_P8 (0x1 << 8) |
| 2641 | #define PORT_P3_PUEN_P8_VAL(val) (((val) & 0x1) << 8) |
| 2642 | #define PORT_P3_PUEN_P8_GET(val) ((((val) & PORT_P3_PUEN_P8) >> 8) & 0x1) |
| 2643 | #define PORT_P3_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P8) | (((val) & 0x1) << 8)) |
| 2644 | /* Pull Up Device Enable at Port 3 Bit # (7) */ |
| 2645 | #define PORT_P3_PUEN_P7 (0x1 << 7) |
| 2646 | #define PORT_P3_PUEN_P7_VAL(val) (((val) & 0x1) << 7) |
| 2647 | #define PORT_P3_PUEN_P7_GET(val) ((((val) & PORT_P3_PUEN_P7) >> 7) & 0x1) |
| 2648 | #define PORT_P3_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P7) | (((val) & 0x1) << 7)) |
| 2649 | /* Pull Up Device Enable at Port 3 Bit # (6) */ |
| 2650 | #define PORT_P3_PUEN_P6 (0x1 << 6) |
| 2651 | #define PORT_P3_PUEN_P6_VAL(val) (((val) & 0x1) << 6) |
| 2652 | #define PORT_P3_PUEN_P6_GET(val) ((((val) & PORT_P3_PUEN_P6) >> 6) & 0x1) |
| 2653 | #define PORT_P3_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P6) | (((val) & 0x1) << 6)) |
| 2654 | /* Pull Up Device Enable at Port 3 Bit # (5) */ |
| 2655 | #define PORT_P3_PUEN_P5 (0x1 << 5) |
| 2656 | #define PORT_P3_PUEN_P5_VAL(val) (((val) & 0x1) << 5) |
| 2657 | #define PORT_P3_PUEN_P5_GET(val) ((((val) & PORT_P3_PUEN_P5) >> 5) & 0x1) |
| 2658 | #define PORT_P3_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P5) | (((val) & 0x1) << 5)) |
| 2659 | /* Pull Up Device Enable at Port 3 Bit # (4) */ |
| 2660 | #define PORT_P3_PUEN_P4 (0x1 << 4) |
| 2661 | #define PORT_P3_PUEN_P4_VAL(val) (((val) & 0x1) << 4) |
| 2662 | #define PORT_P3_PUEN_P4_GET(val) ((((val) & PORT_P3_PUEN_P4) >> 4) & 0x1) |
| 2663 | #define PORT_P3_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P4) | (((val) & 0x1) << 4)) |
| 2664 | /* Pull Up Device Enable at Port 3 Bit # (3) */ |
| 2665 | #define PORT_P3_PUEN_P3 (0x1 << 3) |
| 2666 | #define PORT_P3_PUEN_P3_VAL(val) (((val) & 0x1) << 3) |
| 2667 | #define PORT_P3_PUEN_P3_GET(val) ((((val) & PORT_P3_PUEN_P3) >> 3) & 0x1) |
| 2668 | #define PORT_P3_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P3) | (((val) & 0x1) << 3)) |
| 2669 | /* Pull Up Device Enable at Port 3 Bit # (2) */ |
| 2670 | #define PORT_P3_PUEN_P2 (0x1 << 2) |
| 2671 | #define PORT_P3_PUEN_P2_VAL(val) (((val) & 0x1) << 2) |
| 2672 | #define PORT_P3_PUEN_P2_GET(val) ((((val) & PORT_P3_PUEN_P2) >> 2) & 0x1) |
| 2673 | #define PORT_P3_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P2) | (((val) & 0x1) << 2)) |
| 2674 | /* Pull Up Device Enable at Port 3 Bit # (1) */ |
| 2675 | #define PORT_P3_PUEN_P1 (0x1 << 1) |
| 2676 | #define PORT_P3_PUEN_P1_VAL(val) (((val) & 0x1) << 1) |
| 2677 | #define PORT_P3_PUEN_P1_GET(val) ((((val) & PORT_P3_PUEN_P1) >> 1) & 0x1) |
| 2678 | #define PORT_P3_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P1) | (((val) & 0x1) << 1)) |
| 2679 | /* Pull Up Device Enable at Port 3 Bit # (0) */ |
| 2680 | #define PORT_P3_PUEN_P0 (0x1) |
| 2681 | #define PORT_P3_PUEN_P0_VAL(val) (((val) & 0x1) << 0) |
| 2682 | #define PORT_P3_PUEN_P0_GET(val) ((((val) & PORT_P3_PUEN_P0) >> 0) & 0x1) |
| 2683 | #define PORT_P3_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P0) | (((val) & 0x1) << 0)) |
| 2684 | |
| 2685 | /******************************************************************************* |
| 2686 | * Port 4 Data Output Register |
| 2687 | ******************************************************************************/ |
| 2688 | |
| 2689 | /* Port 4 Pin # Output Value (23) */ |
| 2690 | #define PORT_P4_OUT_P23 (0x1 << 23) |
| 2691 | #define PORT_P4_OUT_P23_VAL(val) (((val) & 0x1) << 23) |
| 2692 | #define PORT_P4_OUT_P23_GET(val) ((((val) & PORT_P4_OUT_P23) >> 23) & 0x1) |
| 2693 | #define PORT_P4_OUT_P23_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P23) | (((val) & 0x1) << 23)) |
| 2694 | /* Port 4 Pin # Output Value (22) */ |
| 2695 | #define PORT_P4_OUT_P22 (0x1 << 22) |
| 2696 | #define PORT_P4_OUT_P22_VAL(val) (((val) & 0x1) << 22) |
| 2697 | #define PORT_P4_OUT_P22_GET(val) ((((val) & PORT_P4_OUT_P22) >> 22) & 0x1) |
| 2698 | #define PORT_P4_OUT_P22_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P22) | (((val) & 0x1) << 22)) |
| 2699 | /* Port 4 Pin # Output Value (21) */ |
| 2700 | #define PORT_P4_OUT_P21 (0x1 << 21) |
| 2701 | #define PORT_P4_OUT_P21_VAL(val) (((val) & 0x1) << 21) |
| 2702 | #define PORT_P4_OUT_P21_GET(val) ((((val) & PORT_P4_OUT_P21) >> 21) & 0x1) |
| 2703 | #define PORT_P4_OUT_P21_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P21) | (((val) & 0x1) << 21)) |
| 2704 | /* Port 4 Pin # Output Value (20) */ |
| 2705 | #define PORT_P4_OUT_P20 (0x1 << 20) |
| 2706 | #define PORT_P4_OUT_P20_VAL(val) (((val) & 0x1) << 20) |
| 2707 | #define PORT_P4_OUT_P20_GET(val) ((((val) & PORT_P4_OUT_P20) >> 20) & 0x1) |
| 2708 | #define PORT_P4_OUT_P20_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P20) | (((val) & 0x1) << 20)) |
| 2709 | /* Port 4 Pin # Output Value (19) */ |
| 2710 | #define PORT_P4_OUT_P19 (0x1 << 19) |
| 2711 | #define PORT_P4_OUT_P19_VAL(val) (((val) & 0x1) << 19) |
| 2712 | #define PORT_P4_OUT_P19_GET(val) ((((val) & PORT_P4_OUT_P19) >> 19) & 0x1) |
| 2713 | #define PORT_P4_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P19) | (((val) & 0x1) << 19)) |
| 2714 | /* Port 4 Pin # Output Value (18) */ |
| 2715 | #define PORT_P4_OUT_P18 (0x1 << 18) |
| 2716 | #define PORT_P4_OUT_P18_VAL(val) (((val) & 0x1) << 18) |
| 2717 | #define PORT_P4_OUT_P18_GET(val) ((((val) & PORT_P4_OUT_P18) >> 18) & 0x1) |
| 2718 | #define PORT_P4_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P18) | (((val) & 0x1) << 18)) |
| 2719 | /* Port 4 Pin # Output Value (17) */ |
| 2720 | #define PORT_P4_OUT_P17 (0x1 << 17) |
| 2721 | #define PORT_P4_OUT_P17_VAL(val) (((val) & 0x1) << 17) |
| 2722 | #define PORT_P4_OUT_P17_GET(val) ((((val) & PORT_P4_OUT_P17) >> 17) & 0x1) |
| 2723 | #define PORT_P4_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P17) | (((val) & 0x1) << 17)) |
| 2724 | /* Port 4 Pin # Output Value (16) */ |
| 2725 | #define PORT_P4_OUT_P16 (0x1 << 16) |
| 2726 | #define PORT_P4_OUT_P16_VAL(val) (((val) & 0x1) << 16) |
| 2727 | #define PORT_P4_OUT_P16_GET(val) ((((val) & PORT_P4_OUT_P16) >> 16) & 0x1) |
| 2728 | #define PORT_P4_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P16) | (((val) & 0x1) << 16)) |
| 2729 | /* Port 4 Pin # Output Value (15) */ |
| 2730 | #define PORT_P4_OUT_P15 (0x1 << 15) |
| 2731 | #define PORT_P4_OUT_P15_VAL(val) (((val) & 0x1) << 15) |
| 2732 | #define PORT_P4_OUT_P15_GET(val) ((((val) & PORT_P4_OUT_P15) >> 15) & 0x1) |
| 2733 | #define PORT_P4_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P15) | (((val) & 0x1) << 15)) |
| 2734 | /* Port 4 Pin # Output Value (14) */ |
| 2735 | #define PORT_P4_OUT_P14 (0x1 << 14) |
| 2736 | #define PORT_P4_OUT_P14_VAL(val) (((val) & 0x1) << 14) |
| 2737 | #define PORT_P4_OUT_P14_GET(val) ((((val) & PORT_P4_OUT_P14) >> 14) & 0x1) |
| 2738 | #define PORT_P4_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P14) | (((val) & 0x1) << 14)) |
| 2739 | /* Port 4 Pin # Output Value (13) */ |
| 2740 | #define PORT_P4_OUT_P13 (0x1 << 13) |
| 2741 | #define PORT_P4_OUT_P13_VAL(val) (((val) & 0x1) << 13) |
| 2742 | #define PORT_P4_OUT_P13_GET(val) ((((val) & PORT_P4_OUT_P13) >> 13) & 0x1) |
| 2743 | #define PORT_P4_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P13) | (((val) & 0x1) << 13)) |
| 2744 | /* Port 4 Pin # Output Value (12) */ |
| 2745 | #define PORT_P4_OUT_P12 (0x1 << 12) |
| 2746 | #define PORT_P4_OUT_P12_VAL(val) (((val) & 0x1) << 12) |
| 2747 | #define PORT_P4_OUT_P12_GET(val) ((((val) & PORT_P4_OUT_P12) >> 12) & 0x1) |
| 2748 | #define PORT_P4_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P12) | (((val) & 0x1) << 12)) |
| 2749 | /* Port 4 Pin # Output Value (11) */ |
| 2750 | #define PORT_P4_OUT_P11 (0x1 << 11) |
| 2751 | #define PORT_P4_OUT_P11_VAL(val) (((val) & 0x1) << 11) |
| 2752 | #define PORT_P4_OUT_P11_GET(val) ((((val) & PORT_P4_OUT_P11) >> 11) & 0x1) |
| 2753 | #define PORT_P4_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P11) | (((val) & 0x1) << 11)) |
| 2754 | /* Port 4 Pin # Output Value (10) */ |
| 2755 | #define PORT_P4_OUT_P10 (0x1 << 10) |
| 2756 | #define PORT_P4_OUT_P10_VAL(val) (((val) & 0x1) << 10) |
| 2757 | #define PORT_P4_OUT_P10_GET(val) ((((val) & PORT_P4_OUT_P10) >> 10) & 0x1) |
| 2758 | #define PORT_P4_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P10) | (((val) & 0x1) << 10)) |
| 2759 | /* Port 4 Pin # Output Value (9) */ |
| 2760 | #define PORT_P4_OUT_P9 (0x1 << 9) |
| 2761 | #define PORT_P4_OUT_P9_VAL(val) (((val) & 0x1) << 9) |
| 2762 | #define PORT_P4_OUT_P9_GET(val) ((((val) & PORT_P4_OUT_P9) >> 9) & 0x1) |
| 2763 | #define PORT_P4_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P9) | (((val) & 0x1) << 9)) |
| 2764 | /* Port 4 Pin # Output Value (8) */ |
| 2765 | #define PORT_P4_OUT_P8 (0x1 << 8) |
| 2766 | #define PORT_P4_OUT_P8_VAL(val) (((val) & 0x1) << 8) |
| 2767 | #define PORT_P4_OUT_P8_GET(val) ((((val) & PORT_P4_OUT_P8) >> 8) & 0x1) |
| 2768 | #define PORT_P4_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P8) | (((val) & 0x1) << 8)) |
| 2769 | /* Port 4 Pin # Output Value (7) */ |
| 2770 | #define PORT_P4_OUT_P7 (0x1 << 7) |
| 2771 | #define PORT_P4_OUT_P7_VAL(val) (((val) & 0x1) << 7) |
| 2772 | #define PORT_P4_OUT_P7_GET(val) ((((val) & PORT_P4_OUT_P7) >> 7) & 0x1) |
| 2773 | #define PORT_P4_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P7) | (((val) & 0x1) << 7)) |
| 2774 | /* Port 4 Pin # Output Value (6) */ |
| 2775 | #define PORT_P4_OUT_P6 (0x1 << 6) |
| 2776 | #define PORT_P4_OUT_P6_VAL(val) (((val) & 0x1) << 6) |
| 2777 | #define PORT_P4_OUT_P6_GET(val) ((((val) & PORT_P4_OUT_P6) >> 6) & 0x1) |
| 2778 | #define PORT_P4_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P6) | (((val) & 0x1) << 6)) |
| 2779 | /* Port 4 Pin # Output Value (5) */ |
| 2780 | #define PORT_P4_OUT_P5 (0x1 << 5) |
| 2781 | #define PORT_P4_OUT_P5_VAL(val) (((val) & 0x1) << 5) |
| 2782 | #define PORT_P4_OUT_P5_GET(val) ((((val) & PORT_P4_OUT_P5) >> 5) & 0x1) |
| 2783 | #define PORT_P4_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P5) | (((val) & 0x1) << 5)) |
| 2784 | /* Port 4 Pin # Output Value (4) */ |
| 2785 | #define PORT_P4_OUT_P4 (0x1 << 4) |
| 2786 | #define PORT_P4_OUT_P4_VAL(val) (((val) & 0x1) << 4) |
| 2787 | #define PORT_P4_OUT_P4_GET(val) ((((val) & PORT_P4_OUT_P4) >> 4) & 0x1) |
| 2788 | #define PORT_P4_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P4) | (((val) & 0x1) << 4)) |
| 2789 | /* Port 4 Pin # Output Value (3) */ |
| 2790 | #define PORT_P4_OUT_P3 (0x1 << 3) |
| 2791 | #define PORT_P4_OUT_P3_VAL(val) (((val) & 0x1) << 3) |
| 2792 | #define PORT_P4_OUT_P3_GET(val) ((((val) & PORT_P4_OUT_P3) >> 3) & 0x1) |
| 2793 | #define PORT_P4_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P3) | (((val) & 0x1) << 3)) |
| 2794 | /* Port 4 Pin # Output Value (2) */ |
| 2795 | #define PORT_P4_OUT_P2 (0x1 << 2) |
| 2796 | #define PORT_P4_OUT_P2_VAL(val) (((val) & 0x1) << 2) |
| 2797 | #define PORT_P4_OUT_P2_GET(val) ((((val) & PORT_P4_OUT_P2) >> 2) & 0x1) |
| 2798 | #define PORT_P4_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P2) | (((val) & 0x1) << 2)) |
| 2799 | /* Port 4 Pin # Output Value (1) */ |
| 2800 | #define PORT_P4_OUT_P1 (0x1 << 1) |
| 2801 | #define PORT_P4_OUT_P1_VAL(val) (((val) & 0x1) << 1) |
| 2802 | #define PORT_P4_OUT_P1_GET(val) ((((val) & PORT_P4_OUT_P1) >> 1) & 0x1) |
| 2803 | #define PORT_P4_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P1) | (((val) & 0x1) << 1)) |
| 2804 | /* Port 4 Pin # Output Value (0) */ |
| 2805 | #define PORT_P4_OUT_P0 (0x1) |
| 2806 | #define PORT_P4_OUT_P0_VAL(val) (((val) & 0x1) << 0) |
| 2807 | #define PORT_P4_OUT_P0_GET(val) ((((val) & PORT_P4_OUT_P0) >> 0) & 0x1) |
| 2808 | #define PORT_P4_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P0) | (((val) & 0x1) << 0)) |
| 2809 | |
| 2810 | /******************************************************************************* |
| 2811 | * Port 4 Data Input Register |
| 2812 | ******************************************************************************/ |
| 2813 | |
| 2814 | /* Port 4 Pin # Latched Input Value (23) */ |
| 2815 | #define PORT_P4_IN_P23 (0x1 << 23) |
| 2816 | #define PORT_P4_IN_P23_GET(val) ((((val) & PORT_P4_IN_P23) >> 23) & 0x1) |
| 2817 | /* Port 4 Pin # Latched Input Value (22) */ |
| 2818 | #define PORT_P4_IN_P22 (0x1 << 22) |
| 2819 | #define PORT_P4_IN_P22_GET(val) ((((val) & PORT_P4_IN_P22) >> 22) & 0x1) |
| 2820 | /* Port 4 Pin # Latched Input Value (21) */ |
| 2821 | #define PORT_P4_IN_P21 (0x1 << 21) |
| 2822 | #define PORT_P4_IN_P21_GET(val) ((((val) & PORT_P4_IN_P21) >> 21) & 0x1) |
| 2823 | /* Port 4 Pin # Latched Input Value (20) */ |
| 2824 | #define PORT_P4_IN_P20 (0x1 << 20) |
| 2825 | #define PORT_P4_IN_P20_GET(val) ((((val) & PORT_P4_IN_P20) >> 20) & 0x1) |
| 2826 | /* Port 4 Pin # Latched Input Value (19) */ |
| 2827 | #define PORT_P4_IN_P19 (0x1 << 19) |
| 2828 | #define PORT_P4_IN_P19_GET(val) ((((val) & PORT_P4_IN_P19) >> 19) & 0x1) |
| 2829 | /* Port 4 Pin # Latched Input Value (18) */ |
| 2830 | #define PORT_P4_IN_P18 (0x1 << 18) |
| 2831 | #define PORT_P4_IN_P18_GET(val) ((((val) & PORT_P4_IN_P18) >> 18) & 0x1) |
| 2832 | /* Port 4 Pin # Latched Input Value (17) */ |
| 2833 | #define PORT_P4_IN_P17 (0x1 << 17) |
| 2834 | #define PORT_P4_IN_P17_GET(val) ((((val) & PORT_P4_IN_P17) >> 17) & 0x1) |
| 2835 | /* Port 4 Pin # Latched Input Value (16) */ |
| 2836 | #define PORT_P4_IN_P16 (0x1 << 16) |
| 2837 | #define PORT_P4_IN_P16_GET(val) ((((val) & PORT_P4_IN_P16) >> 16) & 0x1) |
| 2838 | /* Port 4 Pin # Latched Input Value (15) */ |
| 2839 | #define PORT_P4_IN_P15 (0x1 << 15) |
| 2840 | #define PORT_P4_IN_P15_GET(val) ((((val) & PORT_P4_IN_P15) >> 15) & 0x1) |
| 2841 | /* Port 4 Pin # Latched Input Value (14) */ |
| 2842 | #define PORT_P4_IN_P14 (0x1 << 14) |
| 2843 | #define PORT_P4_IN_P14_GET(val) ((((val) & PORT_P4_IN_P14) >> 14) & 0x1) |
| 2844 | /* Port 4 Pin # Latched Input Value (13) */ |
| 2845 | #define PORT_P4_IN_P13 (0x1 << 13) |
| 2846 | #define PORT_P4_IN_P13_GET(val) ((((val) & PORT_P4_IN_P13) >> 13) & 0x1) |
| 2847 | /* Port 4 Pin # Latched Input Value (12) */ |
| 2848 | #define PORT_P4_IN_P12 (0x1 << 12) |
| 2849 | #define PORT_P4_IN_P12_GET(val) ((((val) & PORT_P4_IN_P12) >> 12) & 0x1) |
| 2850 | /* Port 4 Pin # Latched Input Value (11) */ |
| 2851 | #define PORT_P4_IN_P11 (0x1 << 11) |
| 2852 | #define PORT_P4_IN_P11_GET(val) ((((val) & PORT_P4_IN_P11) >> 11) & 0x1) |
| 2853 | /* Port 4 Pin # Latched Input Value (10) */ |
| 2854 | #define PORT_P4_IN_P10 (0x1 << 10) |
| 2855 | #define PORT_P4_IN_P10_GET(val) ((((val) & PORT_P4_IN_P10) >> 10) & 0x1) |
| 2856 | /* Port 4 Pin # Latched Input Value (9) */ |
| 2857 | #define PORT_P4_IN_P9 (0x1 << 9) |
| 2858 | #define PORT_P4_IN_P9_GET(val) ((((val) & PORT_P4_IN_P9) >> 9) & 0x1) |
| 2859 | /* Port 4 Pin # Latched Input Value (8) */ |
| 2860 | #define PORT_P4_IN_P8 (0x1 << 8) |
| 2861 | #define PORT_P4_IN_P8_GET(val) ((((val) & PORT_P4_IN_P8) >> 8) & 0x1) |
| 2862 | /* Port 4 Pin # Latched Input Value (7) */ |
| 2863 | #define PORT_P4_IN_P7 (0x1 << 7) |
| 2864 | #define PORT_P4_IN_P7_GET(val) ((((val) & PORT_P4_IN_P7) >> 7) & 0x1) |
| 2865 | /* Port 4 Pin # Latched Input Value (6) */ |
| 2866 | #define PORT_P4_IN_P6 (0x1 << 6) |
| 2867 | #define PORT_P4_IN_P6_GET(val) ((((val) & PORT_P4_IN_P6) >> 6) & 0x1) |
| 2868 | /* Port 4 Pin # Latched Input Value (5) */ |
| 2869 | #define PORT_P4_IN_P5 (0x1 << 5) |
| 2870 | #define PORT_P4_IN_P5_GET(val) ((((val) & PORT_P4_IN_P5) >> 5) & 0x1) |
| 2871 | /* Port 4 Pin # Latched Input Value (4) */ |
| 2872 | #define PORT_P4_IN_P4 (0x1 << 4) |
| 2873 | #define PORT_P4_IN_P4_GET(val) ((((val) & PORT_P4_IN_P4) >> 4) & 0x1) |
| 2874 | /* Port 4 Pin # Latched Input Value (3) */ |
| 2875 | #define PORT_P4_IN_P3 (0x1 << 3) |
| 2876 | #define PORT_P4_IN_P3_GET(val) ((((val) & PORT_P4_IN_P3) >> 3) & 0x1) |
| 2877 | /* Port 4 Pin # Latched Input Value (2) */ |
| 2878 | #define PORT_P4_IN_P2 (0x1 << 2) |
| 2879 | #define PORT_P4_IN_P2_GET(val) ((((val) & PORT_P4_IN_P2) >> 2) & 0x1) |
| 2880 | /* Port 4 Pin # Latched Input Value (1) */ |
| 2881 | #define PORT_P4_IN_P1 (0x1 << 1) |
| 2882 | #define PORT_P4_IN_P1_GET(val) ((((val) & PORT_P4_IN_P1) >> 1) & 0x1) |
| 2883 | /* Port 4 Pin # Latched Input Value (0) */ |
| 2884 | #define PORT_P4_IN_P0 (0x1) |
| 2885 | #define PORT_P4_IN_P0_GET(val) ((((val) & PORT_P4_IN_P0) >> 0) & 0x1) |
| 2886 | |
| 2887 | /******************************************************************************* |
| 2888 | * Port 4 Direction Register |
| 2889 | ******************************************************************************/ |
| 2890 | |
| 2891 | /* Port 4 Pin #Direction Control (23) */ |
| 2892 | #define PORT_P4_DIR_P23 (0x1 << 23) |
| 2893 | #define PORT_P4_DIR_P23_VAL(val) (((val) & 0x1) << 23) |
| 2894 | #define PORT_P4_DIR_P23_GET(val) ((((val) & PORT_P4_DIR_P23) >> 23) & 0x1) |
| 2895 | #define PORT_P4_DIR_P23_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P23) | (((val) & 0x1) << 23)) |
| 2896 | /* Port 4 Pin #Direction Control (22) */ |
| 2897 | #define PORT_P4_DIR_P22 (0x1 << 22) |
| 2898 | #define PORT_P4_DIR_P22_VAL(val) (((val) & 0x1) << 22) |
| 2899 | #define PORT_P4_DIR_P22_GET(val) ((((val) & PORT_P4_DIR_P22) >> 22) & 0x1) |
| 2900 | #define PORT_P4_DIR_P22_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P22) | (((val) & 0x1) << 22)) |
| 2901 | /* Port 4 Pin #Direction Control (21) */ |
| 2902 | #define PORT_P4_DIR_P21 (0x1 << 21) |
| 2903 | #define PORT_P4_DIR_P21_VAL(val) (((val) & 0x1) << 21) |
| 2904 | #define PORT_P4_DIR_P21_GET(val) ((((val) & PORT_P4_DIR_P21) >> 21) & 0x1) |
| 2905 | #define PORT_P4_DIR_P21_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P21) | (((val) & 0x1) << 21)) |
| 2906 | /* Port 4 Pin #Direction Control (20) */ |
| 2907 | #define PORT_P4_DIR_P20 (0x1 << 20) |
| 2908 | #define PORT_P4_DIR_P20_VAL(val) (((val) & 0x1) << 20) |
| 2909 | #define PORT_P4_DIR_P20_GET(val) ((((val) & PORT_P4_DIR_P20) >> 20) & 0x1) |
| 2910 | #define PORT_P4_DIR_P20_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P20) | (((val) & 0x1) << 20)) |
| 2911 | /* Port 4 Pin #Direction Control (19) */ |
| 2912 | #define PORT_P4_DIR_P19 (0x1 << 19) |
| 2913 | #define PORT_P4_DIR_P19_VAL(val) (((val) & 0x1) << 19) |
| 2914 | #define PORT_P4_DIR_P19_GET(val) ((((val) & PORT_P4_DIR_P19) >> 19) & 0x1) |
| 2915 | #define PORT_P4_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P19) | (((val) & 0x1) << 19)) |
| 2916 | /* Port 4 Pin #Direction Control (18) */ |
| 2917 | #define PORT_P4_DIR_P18 (0x1 << 18) |
| 2918 | #define PORT_P4_DIR_P18_VAL(val) (((val) & 0x1) << 18) |
| 2919 | #define PORT_P4_DIR_P18_GET(val) ((((val) & PORT_P4_DIR_P18) >> 18) & 0x1) |
| 2920 | #define PORT_P4_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P18) | (((val) & 0x1) << 18)) |
| 2921 | /* Port 4 Pin #Direction Control (17) */ |
| 2922 | #define PORT_P4_DIR_P17 (0x1 << 17) |
| 2923 | #define PORT_P4_DIR_P17_VAL(val) (((val) & 0x1) << 17) |
| 2924 | #define PORT_P4_DIR_P17_GET(val) ((((val) & PORT_P4_DIR_P17) >> 17) & 0x1) |
| 2925 | #define PORT_P4_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P17) | (((val) & 0x1) << 17)) |
| 2926 | /* Port 4 Pin #Direction Control (16) */ |
| 2927 | #define PORT_P4_DIR_P16 (0x1 << 16) |
| 2928 | #define PORT_P4_DIR_P16_VAL(val) (((val) & 0x1) << 16) |
| 2929 | #define PORT_P4_DIR_P16_GET(val) ((((val) & PORT_P4_DIR_P16) >> 16) & 0x1) |
| 2930 | #define PORT_P4_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P16) | (((val) & 0x1) << 16)) |
| 2931 | /* Port 4 Pin #Direction Control (15) */ |
| 2932 | #define PORT_P4_DIR_P15 (0x1 << 15) |
| 2933 | #define PORT_P4_DIR_P15_VAL(val) (((val) & 0x1) << 15) |
| 2934 | #define PORT_P4_DIR_P15_GET(val) ((((val) & PORT_P4_DIR_P15) >> 15) & 0x1) |
| 2935 | #define PORT_P4_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P15) | (((val) & 0x1) << 15)) |
| 2936 | /* Port 4 Pin #Direction Control (14) */ |
| 2937 | #define PORT_P4_DIR_P14 (0x1 << 14) |
| 2938 | #define PORT_P4_DIR_P14_VAL(val) (((val) & 0x1) << 14) |
| 2939 | #define PORT_P4_DIR_P14_GET(val) ((((val) & PORT_P4_DIR_P14) >> 14) & 0x1) |
| 2940 | #define PORT_P4_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P14) | (((val) & 0x1) << 14)) |
| 2941 | /* Port 4 Pin #Direction Control (13) */ |
| 2942 | #define PORT_P4_DIR_P13 (0x1 << 13) |
| 2943 | #define PORT_P4_DIR_P13_VAL(val) (((val) & 0x1) << 13) |
| 2944 | #define PORT_P4_DIR_P13_GET(val) ((((val) & PORT_P4_DIR_P13) >> 13) & 0x1) |
| 2945 | #define PORT_P4_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P13) | (((val) & 0x1) << 13)) |
| 2946 | /* Port 4 Pin #Direction Control (12) */ |
| 2947 | #define PORT_P4_DIR_P12 (0x1 << 12) |
| 2948 | #define PORT_P4_DIR_P12_VAL(val) (((val) & 0x1) << 12) |
| 2949 | #define PORT_P4_DIR_P12_GET(val) ((((val) & PORT_P4_DIR_P12) >> 12) & 0x1) |
| 2950 | #define PORT_P4_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P12) | (((val) & 0x1) << 12)) |
| 2951 | /* Port 4 Pin #Direction Control (11) */ |
| 2952 | #define PORT_P4_DIR_P11 (0x1 << 11) |
| 2953 | #define PORT_P4_DIR_P11_VAL(val) (((val) & 0x1) << 11) |
| 2954 | #define PORT_P4_DIR_P11_GET(val) ((((val) & PORT_P4_DIR_P11) >> 11) & 0x1) |
| 2955 | #define PORT_P4_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P11) | (((val) & 0x1) << 11)) |
| 2956 | /* Port 4 Pin #Direction Control (10) */ |
| 2957 | #define PORT_P4_DIR_P10 (0x1 << 10) |
| 2958 | #define PORT_P4_DIR_P10_VAL(val) (((val) & 0x1) << 10) |
| 2959 | #define PORT_P4_DIR_P10_GET(val) ((((val) & PORT_P4_DIR_P10) >> 10) & 0x1) |
| 2960 | #define PORT_P4_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P10) | (((val) & 0x1) << 10)) |
| 2961 | /* Port 4 Pin #Direction Control (9) */ |
| 2962 | #define PORT_P4_DIR_P9 (0x1 << 9) |
| 2963 | #define PORT_P4_DIR_P9_VAL(val) (((val) & 0x1) << 9) |
| 2964 | #define PORT_P4_DIR_P9_GET(val) ((((val) & PORT_P4_DIR_P9) >> 9) & 0x1) |
| 2965 | #define PORT_P4_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P9) | (((val) & 0x1) << 9)) |
| 2966 | /* Port 4 Pin #Direction Control (8) */ |
| 2967 | #define PORT_P4_DIR_P8 (0x1 << 8) |
| 2968 | #define PORT_P4_DIR_P8_VAL(val) (((val) & 0x1) << 8) |
| 2969 | #define PORT_P4_DIR_P8_GET(val) ((((val) & PORT_P4_DIR_P8) >> 8) & 0x1) |
| 2970 | #define PORT_P4_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P8) | (((val) & 0x1) << 8)) |
| 2971 | /* Port 4 Pin #Direction Control (7) */ |
| 2972 | #define PORT_P4_DIR_P7 (0x1 << 7) |
| 2973 | #define PORT_P4_DIR_P7_VAL(val) (((val) & 0x1) << 7) |
| 2974 | #define PORT_P4_DIR_P7_GET(val) ((((val) & PORT_P4_DIR_P7) >> 7) & 0x1) |
| 2975 | #define PORT_P4_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P7) | (((val) & 0x1) << 7)) |
| 2976 | /* Port 4 Pin #Direction Control (6) */ |
| 2977 | #define PORT_P4_DIR_P6 (0x1 << 6) |
| 2978 | #define PORT_P4_DIR_P6_VAL(val) (((val) & 0x1) << 6) |
| 2979 | #define PORT_P4_DIR_P6_GET(val) ((((val) & PORT_P4_DIR_P6) >> 6) & 0x1) |
| 2980 | #define PORT_P4_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P6) | (((val) & 0x1) << 6)) |
| 2981 | /* Port 4 Pin #Direction Control (5) */ |
| 2982 | #define PORT_P4_DIR_P5 (0x1 << 5) |
| 2983 | #define PORT_P4_DIR_P5_VAL(val) (((val) & 0x1) << 5) |
| 2984 | #define PORT_P4_DIR_P5_GET(val) ((((val) & PORT_P4_DIR_P5) >> 5) & 0x1) |
| 2985 | #define PORT_P4_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P5) | (((val) & 0x1) << 5)) |
| 2986 | /* Port 4 Pin #Direction Control (4) */ |
| 2987 | #define PORT_P4_DIR_P4 (0x1 << 4) |
| 2988 | #define PORT_P4_DIR_P4_VAL(val) (((val) & 0x1) << 4) |
| 2989 | #define PORT_P4_DIR_P4_GET(val) ((((val) & PORT_P4_DIR_P4) >> 4) & 0x1) |
| 2990 | #define PORT_P4_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P4) | (((val) & 0x1) << 4)) |
| 2991 | /* Port 4 Pin #Direction Control (3) */ |
| 2992 | #define PORT_P4_DIR_P3 (0x1 << 3) |
| 2993 | #define PORT_P4_DIR_P3_VAL(val) (((val) & 0x1) << 3) |
| 2994 | #define PORT_P4_DIR_P3_GET(val) ((((val) & PORT_P4_DIR_P3) >> 3) & 0x1) |
| 2995 | #define PORT_P4_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P3) | (((val) & 0x1) << 3)) |
| 2996 | /* Port 4 Pin #Direction Control (2) */ |
| 2997 | #define PORT_P4_DIR_P2 (0x1 << 2) |
| 2998 | #define PORT_P4_DIR_P2_VAL(val) (((val) & 0x1) << 2) |
| 2999 | #define PORT_P4_DIR_P2_GET(val) ((((val) & PORT_P4_DIR_P2) >> 2) & 0x1) |
| 3000 | #define PORT_P4_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P2) | (((val) & 0x1) << 2)) |
| 3001 | /* Port 4 Pin #Direction Control (1) */ |
| 3002 | #define PORT_P4_DIR_P1 (0x1 << 1) |
| 3003 | #define PORT_P4_DIR_P1_VAL(val) (((val) & 0x1) << 1) |
| 3004 | #define PORT_P4_DIR_P1_GET(val) ((((val) & PORT_P4_DIR_P1) >> 1) & 0x1) |
| 3005 | #define PORT_P4_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P1) | (((val) & 0x1) << 1)) |
| 3006 | /* Port 4 Pin #Direction Control (0) */ |
| 3007 | #define PORT_P4_DIR_P0 (0x1) |
| 3008 | #define PORT_P4_DIR_P0_VAL(val) (((val) & 0x1) << 0) |
| 3009 | #define PORT_P4_DIR_P0_GET(val) ((((val) & PORT_P4_DIR_P0) >> 0) & 0x1) |
| 3010 | #define PORT_P4_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P0) | (((val) & 0x1) << 0)) |
| 3011 | |
| 3012 | /******************************************************************************* |
| 3013 | * Port 4 Alternate Function Select Register 0 |
| 3014 | ******************************************************************************/ |
| 3015 | |
| 3016 | /* Alternate Function at Port 4 Bit # (23) */ |
| 3017 | #define PORT_P4_ALTSEL0_P23 (0x1 << 23) |
| 3018 | #define PORT_P4_ALTSEL0_P23_VAL(val) (((val) & 0x1) << 23) |
| 3019 | #define PORT_P4_ALTSEL0_P23_GET(val) ((((val) & PORT_P4_ALTSEL0_P23) >> 23) & 0x1) |
| 3020 | #define PORT_P4_ALTSEL0_P23_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P23) | (((val) & 0x1) << 23)) |
| 3021 | /* Alternate Function at Port 4 Bit # (22) */ |
| 3022 | #define PORT_P4_ALTSEL0_P22 (0x1 << 22) |
| 3023 | #define PORT_P4_ALTSEL0_P22_VAL(val) (((val) & 0x1) << 22) |
| 3024 | #define PORT_P4_ALTSEL0_P22_GET(val) ((((val) & PORT_P4_ALTSEL0_P22) >> 22) & 0x1) |
| 3025 | #define PORT_P4_ALTSEL0_P22_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P22) | (((val) & 0x1) << 22)) |
| 3026 | /* Alternate Function at Port 4 Bit # (21) */ |
| 3027 | #define PORT_P4_ALTSEL0_P21 (0x1 << 21) |
| 3028 | #define PORT_P4_ALTSEL0_P21_VAL(val) (((val) & 0x1) << 21) |
| 3029 | #define PORT_P4_ALTSEL0_P21_GET(val) ((((val) & PORT_P4_ALTSEL0_P21) >> 21) & 0x1) |
| 3030 | #define PORT_P4_ALTSEL0_P21_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P21) | (((val) & 0x1) << 21)) |
| 3031 | /* Alternate Function at Port 4 Bit # (20) */ |
| 3032 | #define PORT_P4_ALTSEL0_P20 (0x1 << 20) |
| 3033 | #define PORT_P4_ALTSEL0_P20_VAL(val) (((val) & 0x1) << 20) |
| 3034 | #define PORT_P4_ALTSEL0_P20_GET(val) ((((val) & PORT_P4_ALTSEL0_P20) >> 20) & 0x1) |
| 3035 | #define PORT_P4_ALTSEL0_P20_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P20) | (((val) & 0x1) << 20)) |
| 3036 | /* Alternate Function at Port 4 Bit # (19) */ |
| 3037 | #define PORT_P4_ALTSEL0_P19 (0x1 << 19) |
| 3038 | #define PORT_P4_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) |
| 3039 | #define PORT_P4_ALTSEL0_P19_GET(val) ((((val) & PORT_P4_ALTSEL0_P19) >> 19) & 0x1) |
| 3040 | #define PORT_P4_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P19) | (((val) & 0x1) << 19)) |
| 3041 | /* Alternate Function at Port 4 Bit # (18) */ |
| 3042 | #define PORT_P4_ALTSEL0_P18 (0x1 << 18) |
| 3043 | #define PORT_P4_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) |
| 3044 | #define PORT_P4_ALTSEL0_P18_GET(val) ((((val) & PORT_P4_ALTSEL0_P18) >> 18) & 0x1) |
| 3045 | #define PORT_P4_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P18) | (((val) & 0x1) << 18)) |
| 3046 | /* Alternate Function at Port 4 Bit # (17) */ |
| 3047 | #define PORT_P4_ALTSEL0_P17 (0x1 << 17) |
| 3048 | #define PORT_P4_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) |
| 3049 | #define PORT_P4_ALTSEL0_P17_GET(val) ((((val) & PORT_P4_ALTSEL0_P17) >> 17) & 0x1) |
| 3050 | #define PORT_P4_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P17) | (((val) & 0x1) << 17)) |
| 3051 | /* Alternate Function at Port 4 Bit # (16) */ |
| 3052 | #define PORT_P4_ALTSEL0_P16 (0x1 << 16) |
| 3053 | #define PORT_P4_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) |
| 3054 | #define PORT_P4_ALTSEL0_P16_GET(val) ((((val) & PORT_P4_ALTSEL0_P16) >> 16) & 0x1) |
| 3055 | #define PORT_P4_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P16) | (((val) & 0x1) << 16)) |
| 3056 | /* Alternate Function at Port 4 Bit # (15) */ |
| 3057 | #define PORT_P4_ALTSEL0_P15 (0x1 << 15) |
| 3058 | #define PORT_P4_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) |
| 3059 | #define PORT_P4_ALTSEL0_P15_GET(val) ((((val) & PORT_P4_ALTSEL0_P15) >> 15) & 0x1) |
| 3060 | #define PORT_P4_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P15) | (((val) & 0x1) << 15)) |
| 3061 | /* Alternate Function at Port 4 Bit # (14) */ |
| 3062 | #define PORT_P4_ALTSEL0_P14 (0x1 << 14) |
| 3063 | #define PORT_P4_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) |
| 3064 | #define PORT_P4_ALTSEL0_P14_GET(val) ((((val) & PORT_P4_ALTSEL0_P14) >> 14) & 0x1) |
| 3065 | #define PORT_P4_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P14) | (((val) & 0x1) << 14)) |
| 3066 | /* Alternate Function at Port 4 Bit # (13) */ |
| 3067 | #define PORT_P4_ALTSEL0_P13 (0x1 << 13) |
| 3068 | #define PORT_P4_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) |
| 3069 | #define PORT_P4_ALTSEL0_P13_GET(val) ((((val) & PORT_P4_ALTSEL0_P13) >> 13) & 0x1) |
| 3070 | #define PORT_P4_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P13) | (((val) & 0x1) << 13)) |
| 3071 | /* Alternate Function at Port 4 Bit # (12) */ |
| 3072 | #define PORT_P4_ALTSEL0_P12 (0x1 << 12) |
| 3073 | #define PORT_P4_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) |
| 3074 | #define PORT_P4_ALTSEL0_P12_GET(val) ((((val) & PORT_P4_ALTSEL0_P12) >> 12) & 0x1) |
| 3075 | #define PORT_P4_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P12) | (((val) & 0x1) << 12)) |
| 3076 | /* Alternate Function at Port 4 Bit # (11) */ |
| 3077 | #define PORT_P4_ALTSEL0_P11 (0x1 << 11) |
| 3078 | #define PORT_P4_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) |
| 3079 | #define PORT_P4_ALTSEL0_P11_GET(val) ((((val) & PORT_P4_ALTSEL0_P11) >> 11) & 0x1) |
| 3080 | #define PORT_P4_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P11) | (((val) & 0x1) << 11)) |
| 3081 | /* Alternate Function at Port 4 Bit # (10) */ |
| 3082 | #define PORT_P4_ALTSEL0_P10 (0x1 << 10) |
| 3083 | #define PORT_P4_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) |
| 3084 | #define PORT_P4_ALTSEL0_P10_GET(val) ((((val) & PORT_P4_ALTSEL0_P10) >> 10) & 0x1) |
| 3085 | #define PORT_P4_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P10) | (((val) & 0x1) << 10)) |
| 3086 | /* Alternate Function at Port 4 Bit # (9) */ |
| 3087 | #define PORT_P4_ALTSEL0_P9 (0x1 << 9) |
| 3088 | #define PORT_P4_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) |
| 3089 | #define PORT_P4_ALTSEL0_P9_GET(val) ((((val) & PORT_P4_ALTSEL0_P9) >> 9) & 0x1) |
| 3090 | #define PORT_P4_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P9) | (((val) & 0x1) << 9)) |
| 3091 | /* Alternate Function at Port 4 Bit # (8) */ |
| 3092 | #define PORT_P4_ALTSEL0_P8 (0x1 << 8) |
| 3093 | #define PORT_P4_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) |
| 3094 | #define PORT_P4_ALTSEL0_P8_GET(val) ((((val) & PORT_P4_ALTSEL0_P8) >> 8) & 0x1) |
| 3095 | #define PORT_P4_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P8) | (((val) & 0x1) << 8)) |
| 3096 | /* Alternate Function at Port 4 Bit # (7) */ |
| 3097 | #define PORT_P4_ALTSEL0_P7 (0x1 << 7) |
| 3098 | #define PORT_P4_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) |
| 3099 | #define PORT_P4_ALTSEL0_P7_GET(val) ((((val) & PORT_P4_ALTSEL0_P7) >> 7) & 0x1) |
| 3100 | #define PORT_P4_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P7) | (((val) & 0x1) << 7)) |
| 3101 | /* Alternate Function at Port 4 Bit # (6) */ |
| 3102 | #define PORT_P4_ALTSEL0_P6 (0x1 << 6) |
| 3103 | #define PORT_P4_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) |
| 3104 | #define PORT_P4_ALTSEL0_P6_GET(val) ((((val) & PORT_P4_ALTSEL0_P6) >> 6) & 0x1) |
| 3105 | #define PORT_P4_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P6) | (((val) & 0x1) << 6)) |
| 3106 | /* Alternate Function at Port 4 Bit # (5) */ |
| 3107 | #define PORT_P4_ALTSEL0_P5 (0x1 << 5) |
| 3108 | #define PORT_P4_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) |
| 3109 | #define PORT_P4_ALTSEL0_P5_GET(val) ((((val) & PORT_P4_ALTSEL0_P5) >> 5) & 0x1) |
| 3110 | #define PORT_P4_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P5) | (((val) & 0x1) << 5)) |
| 3111 | /* Alternate Function at Port 4 Bit # (4) */ |
| 3112 | #define PORT_P4_ALTSEL0_P4 (0x1 << 4) |
| 3113 | #define PORT_P4_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) |
| 3114 | #define PORT_P4_ALTSEL0_P4_GET(val) ((((val) & PORT_P4_ALTSEL0_P4) >> 4) & 0x1) |
| 3115 | #define PORT_P4_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P4) | (((val) & 0x1) << 4)) |
| 3116 | /* Alternate Function at Port 4 Bit # (3) */ |
| 3117 | #define PORT_P4_ALTSEL0_P3 (0x1 << 3) |
| 3118 | #define PORT_P4_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) |
| 3119 | #define PORT_P4_ALTSEL0_P3_GET(val) ((((val) & PORT_P4_ALTSEL0_P3) >> 3) & 0x1) |
| 3120 | #define PORT_P4_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P3) | (((val) & 0x1) << 3)) |
| 3121 | /* Alternate Function at Port 4 Bit # (2) */ |
| 3122 | #define PORT_P4_ALTSEL0_P2 (0x1 << 2) |
| 3123 | #define PORT_P4_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) |
| 3124 | #define PORT_P4_ALTSEL0_P2_GET(val) ((((val) & PORT_P4_ALTSEL0_P2) >> 2) & 0x1) |
| 3125 | #define PORT_P4_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P2) | (((val) & 0x1) << 2)) |
| 3126 | /* Alternate Function at Port 4 Bit # (1) */ |
| 3127 | #define PORT_P4_ALTSEL0_P1 (0x1 << 1) |
| 3128 | #define PORT_P4_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) |
| 3129 | #define PORT_P4_ALTSEL0_P1_GET(val) ((((val) & PORT_P4_ALTSEL0_P1) >> 1) & 0x1) |
| 3130 | #define PORT_P4_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P1) | (((val) & 0x1) << 1)) |
| 3131 | /* Alternate Function at Port 4 Bit # (0) */ |
| 3132 | #define PORT_P4_ALTSEL0_P0 (0x1) |
| 3133 | #define PORT_P4_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) |
| 3134 | #define PORT_P4_ALTSEL0_P0_GET(val) ((((val) & PORT_P4_ALTSEL0_P0) >> 0) & 0x1) |
| 3135 | #define PORT_P4_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P0) | (((val) & 0x1) << 0)) |
| 3136 | |
| 3137 | /******************************************************************************* |
| 3138 | * Port 4 Pull Up Device Enable Register |
| 3139 | ******************************************************************************/ |
| 3140 | |
| 3141 | /* Pull Up Device Enable at Port 4 Bit # (23) */ |
| 3142 | #define PORT_P4_PUEN_P23 (0x1 << 23) |
| 3143 | #define PORT_P4_PUEN_P23_VAL(val) (((val) & 0x1) << 23) |
| 3144 | #define PORT_P4_PUEN_P23_GET(val) ((((val) & PORT_P4_PUEN_P23) >> 23) & 0x1) |
| 3145 | #define PORT_P4_PUEN_P23_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P23) | (((val) & 0x1) << 23)) |
| 3146 | /* Pull Up Device Enable at Port 4 Bit # (22) */ |
| 3147 | #define PORT_P4_PUEN_P22 (0x1 << 22) |
| 3148 | #define PORT_P4_PUEN_P22_VAL(val) (((val) & 0x1) << 22) |
| 3149 | #define PORT_P4_PUEN_P22_GET(val) ((((val) & PORT_P4_PUEN_P22) >> 22) & 0x1) |
| 3150 | #define PORT_P4_PUEN_P22_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P22) | (((val) & 0x1) << 22)) |
| 3151 | /* Pull Up Device Enable at Port 4 Bit # (21) */ |
| 3152 | #define PORT_P4_PUEN_P21 (0x1 << 21) |
| 3153 | #define PORT_P4_PUEN_P21_VAL(val) (((val) & 0x1) << 21) |
| 3154 | #define PORT_P4_PUEN_P21_GET(val) ((((val) & PORT_P4_PUEN_P21) >> 21) & 0x1) |
| 3155 | #define PORT_P4_PUEN_P21_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P21) | (((val) & 0x1) << 21)) |
| 3156 | /* Pull Up Device Enable at Port 4 Bit # (20) */ |
| 3157 | #define PORT_P4_PUEN_P20 (0x1 << 20) |
| 3158 | #define PORT_P4_PUEN_P20_VAL(val) (((val) & 0x1) << 20) |
| 3159 | #define PORT_P4_PUEN_P20_GET(val) ((((val) & PORT_P4_PUEN_P20) >> 20) & 0x1) |
| 3160 | #define PORT_P4_PUEN_P20_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P20) | (((val) & 0x1) << 20)) |
| 3161 | /* Pull Up Device Enable at Port 4 Bit # (19) */ |
| 3162 | #define PORT_P4_PUEN_P19 (0x1 << 19) |
| 3163 | #define PORT_P4_PUEN_P19_VAL(val) (((val) & 0x1) << 19) |
| 3164 | #define PORT_P4_PUEN_P19_GET(val) ((((val) & PORT_P4_PUEN_P19) >> 19) & 0x1) |
| 3165 | #define PORT_P4_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P19) | (((val) & 0x1) << 19)) |
| 3166 | /* Pull Up Device Enable at Port 4 Bit # (18) */ |
| 3167 | #define PORT_P4_PUEN_P18 (0x1 << 18) |
| 3168 | #define PORT_P4_PUEN_P18_VAL(val) (((val) & 0x1) << 18) |
| 3169 | #define PORT_P4_PUEN_P18_GET(val) ((((val) & PORT_P4_PUEN_P18) >> 18) & 0x1) |
| 3170 | #define PORT_P4_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P18) | (((val) & 0x1) << 18)) |
| 3171 | /* Pull Up Device Enable at Port 4 Bit # (17) */ |
| 3172 | #define PORT_P4_PUEN_P17 (0x1 << 17) |
| 3173 | #define PORT_P4_PUEN_P17_VAL(val) (((val) & 0x1) << 17) |
| 3174 | #define PORT_P4_PUEN_P17_GET(val) ((((val) & PORT_P4_PUEN_P17) >> 17) & 0x1) |
| 3175 | #define PORT_P4_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P17) | (((val) & 0x1) << 17)) |
| 3176 | /* Pull Up Device Enable at Port 4 Bit # (16) */ |
| 3177 | #define PORT_P4_PUEN_P16 (0x1 << 16) |
| 3178 | #define PORT_P4_PUEN_P16_VAL(val) (((val) & 0x1) << 16) |
| 3179 | #define PORT_P4_PUEN_P16_GET(val) ((((val) & PORT_P4_PUEN_P16) >> 16) & 0x1) |
| 3180 | #define PORT_P4_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P16) | (((val) & 0x1) << 16)) |
| 3181 | /* Pull Up Device Enable at Port 4 Bit # (15) */ |
| 3182 | #define PORT_P4_PUEN_P15 (0x1 << 15) |
| 3183 | #define PORT_P4_PUEN_P15_VAL(val) (((val) & 0x1) << 15) |
| 3184 | #define PORT_P4_PUEN_P15_GET(val) ((((val) & PORT_P4_PUEN_P15) >> 15) & 0x1) |
| 3185 | #define PORT_P4_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P15) | (((val) & 0x1) << 15)) |
| 3186 | /* Pull Up Device Enable at Port 4 Bit # (14) */ |
| 3187 | #define PORT_P4_PUEN_P14 (0x1 << 14) |
| 3188 | #define PORT_P4_PUEN_P14_VAL(val) (((val) & 0x1) << 14) |
| 3189 | #define PORT_P4_PUEN_P14_GET(val) ((((val) & PORT_P4_PUEN_P14) >> 14) & 0x1) |
| 3190 | #define PORT_P4_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P14) | (((val) & 0x1) << 14)) |
| 3191 | /* Pull Up Device Enable at Port 4 Bit # (13) */ |
| 3192 | #define PORT_P4_PUEN_P13 (0x1 << 13) |
| 3193 | #define PORT_P4_PUEN_P13_VAL(val) (((val) & 0x1) << 13) |
| 3194 | #define PORT_P4_PUEN_P13_GET(val) ((((val) & PORT_P4_PUEN_P13) >> 13) & 0x1) |
| 3195 | #define PORT_P4_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P13) | (((val) & 0x1) << 13)) |
| 3196 | /* Pull Up Device Enable at Port 4 Bit # (12) */ |
| 3197 | #define PORT_P4_PUEN_P12 (0x1 << 12) |
| 3198 | #define PORT_P4_PUEN_P12_VAL(val) (((val) & 0x1) << 12) |
| 3199 | #define PORT_P4_PUEN_P12_GET(val) ((((val) & PORT_P4_PUEN_P12) >> 12) & 0x1) |
| 3200 | #define PORT_P4_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P12) | (((val) & 0x1) << 12)) |
| 3201 | /* Pull Up Device Enable at Port 4 Bit # (11) */ |
| 3202 | #define PORT_P4_PUEN_P11 (0x1 << 11) |
| 3203 | #define PORT_P4_PUEN_P11_VAL(val) (((val) & 0x1) << 11) |
| 3204 | #define PORT_P4_PUEN_P11_GET(val) ((((val) & PORT_P4_PUEN_P11) >> 11) & 0x1) |
| 3205 | #define PORT_P4_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P11) | (((val) & 0x1) << 11)) |
| 3206 | /* Pull Up Device Enable at Port 4 Bit # (10) */ |
| 3207 | #define PORT_P4_PUEN_P10 (0x1 << 10) |
| 3208 | #define PORT_P4_PUEN_P10_VAL(val) (((val) & 0x1) << 10) |
| 3209 | #define PORT_P4_PUEN_P10_GET(val) ((((val) & PORT_P4_PUEN_P10) >> 10) & 0x1) |
| 3210 | #define PORT_P4_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P10) | (((val) & 0x1) << 10)) |
| 3211 | /* Pull Up Device Enable at Port 4 Bit # (9) */ |
| 3212 | #define PORT_P4_PUEN_P9 (0x1 << 9) |
| 3213 | #define PORT_P4_PUEN_P9_VAL(val) (((val) & 0x1) << 9) |
| 3214 | #define PORT_P4_PUEN_P9_GET(val) ((((val) & PORT_P4_PUEN_P9) >> 9) & 0x1) |
| 3215 | #define PORT_P4_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P9) | (((val) & 0x1) << 9)) |
| 3216 | /* Pull Up Device Enable at Port 4 Bit # (8) */ |
| 3217 | #define PORT_P4_PUEN_P8 (0x1 << 8) |
| 3218 | #define PORT_P4_PUEN_P8_VAL(val) (((val) & 0x1) << 8) |
| 3219 | #define PORT_P4_PUEN_P8_GET(val) ((((val) & PORT_P4_PUEN_P8) >> 8) & 0x1) |
| 3220 | #define PORT_P4_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P8) | (((val) & 0x1) << 8)) |
| 3221 | /* Pull Up Device Enable at Port 4 Bit # (7) */ |
| 3222 | #define PORT_P4_PUEN_P7 (0x1 << 7) |
| 3223 | #define PORT_P4_PUEN_P7_VAL(val) (((val) & 0x1) << 7) |
| 3224 | #define PORT_P4_PUEN_P7_GET(val) ((((val) & PORT_P4_PUEN_P7) >> 7) & 0x1) |
| 3225 | #define PORT_P4_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P7) | (((val) & 0x1) << 7)) |
| 3226 | /* Pull Up Device Enable at Port 4 Bit # (6) */ |
| 3227 | #define PORT_P4_PUEN_P6 (0x1 << 6) |
| 3228 | #define PORT_P4_PUEN_P6_VAL(val) (((val) & 0x1) << 6) |
| 3229 | #define PORT_P4_PUEN_P6_GET(val) ((((val) & PORT_P4_PUEN_P6) >> 6) & 0x1) |
| 3230 | #define PORT_P4_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P6) | (((val) & 0x1) << 6)) |
| 3231 | /* Pull Up Device Enable at Port 4 Bit # (5) */ |
| 3232 | #define PORT_P4_PUEN_P5 (0x1 << 5) |
| 3233 | #define PORT_P4_PUEN_P5_VAL(val) (((val) & 0x1) << 5) |
| 3234 | #define PORT_P4_PUEN_P5_GET(val) ((((val) & PORT_P4_PUEN_P5) >> 5) & 0x1) |
| 3235 | #define PORT_P4_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P5) | (((val) & 0x1) << 5)) |
| 3236 | /* Pull Up Device Enable at Port 4 Bit # (4) */ |
| 3237 | #define PORT_P4_PUEN_P4 (0x1 << 4) |
| 3238 | #define PORT_P4_PUEN_P4_VAL(val) (((val) & 0x1) << 4) |
| 3239 | #define PORT_P4_PUEN_P4_GET(val) ((((val) & PORT_P4_PUEN_P4) >> 4) & 0x1) |
| 3240 | #define PORT_P4_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P4) | (((val) & 0x1) << 4)) |
| 3241 | /* Pull Up Device Enable at Port 4 Bit # (3) */ |
| 3242 | #define PORT_P4_PUEN_P3 (0x1 << 3) |
| 3243 | #define PORT_P4_PUEN_P3_VAL(val) (((val) & 0x1) << 3) |
| 3244 | #define PORT_P4_PUEN_P3_GET(val) ((((val) & PORT_P4_PUEN_P3) >> 3) & 0x1) |
| 3245 | #define PORT_P4_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P3) | (((val) & 0x1) << 3)) |
| 3246 | /* Pull Up Device Enable at Port 4 Bit # (2) */ |
| 3247 | #define PORT_P4_PUEN_P2 (0x1 << 2) |
| 3248 | #define PORT_P4_PUEN_P2_VAL(val) (((val) & 0x1) << 2) |
| 3249 | #define PORT_P4_PUEN_P2_GET(val) ((((val) & PORT_P4_PUEN_P2) >> 2) & 0x1) |
| 3250 | #define PORT_P4_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P2) | (((val) & 0x1) << 2)) |
| 3251 | /* Pull Up Device Enable at Port 4 Bit # (1) */ |
| 3252 | #define PORT_P4_PUEN_P1 (0x1 << 1) |
| 3253 | #define PORT_P4_PUEN_P1_VAL(val) (((val) & 0x1) << 1) |
| 3254 | #define PORT_P4_PUEN_P1_GET(val) ((((val) & PORT_P4_PUEN_P1) >> 1) & 0x1) |
| 3255 | #define PORT_P4_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P1) | (((val) & 0x1) << 1)) |
| 3256 | /* Pull Up Device Enable at Port 4 Bit # (0) */ |
| 3257 | #define PORT_P4_PUEN_P0 (0x1) |
| 3258 | #define PORT_P4_PUEN_P0_VAL(val) (((val) & 0x1) << 0) |
| 3259 | #define PORT_P4_PUEN_P0_GET(val) ((((val) & PORT_P4_PUEN_P0) >> 0) & 0x1) |
| 3260 | #define PORT_P4_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P0) | (((val) & 0x1) << 0)) |
| 3261 | |
| 3262 | #endif /* __PORT_H */ |
| 3263 | |
