| 1 | /****************************************************************************** |
| 2 | |
| 3 | Copyright (c) 2007 |
| 4 | Infineon Technologies AG |
| 5 | St. Martin Strasse 53; 81669 Munich, Germany |
| 6 | |
| 7 | Any use of this Software is subject to the conclusion of a respective |
| 8 | License Agreement. Without such a License Agreement no rights to the |
| 9 | Software are granted. |
| 10 | |
| 11 | ******************************************************************************/ |
| 12 | |
| 13 | #ifndef __SSC_REG_H |
| 14 | #define __SSC_REG_H |
| 15 | |
| 16 | /** SSC register structure */ |
| 17 | struct svip_reg_ssc { |
| 18 | volatile unsigned long clc; /* 0x00 */ |
| 19 | volatile unsigned long pisel; /* 0x04 */ |
| 20 | volatile unsigned long id; /* 0x08 */ |
| 21 | volatile unsigned long reserved0; /* 0x0c */ |
| 22 | volatile unsigned long mcon; /* 0x10 */ |
| 23 | volatile unsigned long state; /* 0x14 */ |
| 24 | volatile unsigned long whbstate; /* 0x18 */ |
| 25 | volatile unsigned long reserved1; /* 0x1c */ |
| 26 | volatile unsigned long tb; /* 0x20 */ |
| 27 | volatile unsigned long rb; /* 0x24 */ |
| 28 | volatile unsigned long reserved2[2]; /* 0x28 */ |
| 29 | volatile unsigned long rxfcon; /* 0x30 */ |
| 30 | volatile unsigned long txfcon; /* 0x34 */ |
| 31 | volatile unsigned long fstat; /* 0x38 */ |
| 32 | volatile unsigned long reserved3; /* 0x3c */ |
| 33 | volatile unsigned long br; /* 0x40 */ |
| 34 | volatile unsigned long brstat; /* 0x44 */ |
| 35 | volatile unsigned long reserved4[6]; /* 0x48 */ |
| 36 | volatile unsigned long sfcon; /* 0x60 */ |
| 37 | volatile unsigned long sfstat; /* 0x64 */ |
| 38 | volatile unsigned long reserved5[2]; /* 0x68 */ |
| 39 | volatile unsigned long gpocon; /* 0x70 */ |
| 40 | volatile unsigned long gpostat; /* 0x74 */ |
| 41 | volatile unsigned long whbgpostat; /* 0x78 */ |
| 42 | volatile unsigned long reserved6; /* 0x7c */ |
| 43 | volatile unsigned long rxreq; /* 0x80 */ |
| 44 | volatile unsigned long rxcnt; /* 0x84 */ |
| 45 | volatile unsigned long reserved7[25]; /* 0x88 */ |
| 46 | volatile unsigned long dma_con; /* 0xEC */ |
| 47 | volatile unsigned long reserved8; /* 0xf0 */ |
| 48 | volatile unsigned long irnen; /* 0xF4 */ |
| 49 | volatile unsigned long irncr; /* 0xF8 */ |
| 50 | volatile unsigned long irnicr; /* 0xFC */ |
| 51 | }; |
| 52 | |
| 53 | /******************************************************************************* |
| 54 | * CLC Register |
| 55 | ******************************************************************************/ |
| 56 | |
| 57 | /* Clock Divider for Sleep Mode (23:16) */ |
| 58 | #define SSC_CLC_SMC (0xff << 16) |
| 59 | #define SSC_CLC_SMC_VAL(val) (((val) & 0xff) << 16) |
| 60 | #define SSC_CLC_SMC_GET(val) ((((val) & SSC_CLC_SMC) >> 16) & 0xff) |
| 61 | #define SSC_CLC_SMC_SET(reg,val) (reg) = ((reg & ~SSC_CLC_SMC) | (((val) & 0xff) << 16)) |
| 62 | /* Clock Divider for Normal Run Mode (15:8) */ |
| 63 | #define SSC_CLC_RMC (0xff << 8) |
| 64 | #define SSC_CLC_RMC_VAL(val) (((val) & 0xff) << 8) |
| 65 | #define SSC_CLC_RMC_GET(val) ((((val) & SSC_CLC_RMC) >> 8) & 0xff) |
| 66 | #define SSC_CLC_RMC_SET(reg,val) (reg) = ((reg & ~SSC_CLC_RMC) | (((val) & 0xff) << 8)) |
| 67 | /* Fast Shut-Off Enable Bit (5) */ |
| 68 | #define SSC_CLC_FSOE (0x1 << 5) |
| 69 | #define SSC_CLC_FSOE_VAL(val) (((val) & 0x1) << 5) |
| 70 | #define SSC_CLC_FSOE_GET(val) ((((val) & SSC_CLC_FSOE) >> 5) & 0x1) |
| 71 | #define SSC_CLC_FSOE_SET(reg,val) (reg) = ((reg & ~SSC_CLC_FSOE) | (((val) & 0x1) << 5)) |
| 72 | /* Suspend Bit Write Enable for OCDS (4) */ |
| 73 | #define SSC_CLC_SBWE (0x1 << 4) |
| 74 | #define SSC_CLC_SBWE_VAL(val) (((val) & 0x1) << 4) |
| 75 | #define SSC_CLC_SBWE_SET(reg,val) (reg) = (((reg & ~SSC_CLC_SBWE) | (val) & 1) << 4) |
| 76 | /* External Request Disable (3) */ |
| 77 | #define SSC_CLC_EDIS (0x1 << 3) |
| 78 | #define SSC_CLC_EDIS_VAL(val) (((val) & 0x1) << 3) |
| 79 | #define SSC_CLC_EDIS_GET(val) ((((val) & SSC_CLC_EDIS) >> 3) & 0x1) |
| 80 | #define SSC_CLC_EDIS_SET(reg,val) (reg) = ((reg & ~SSC_CLC_EDIS) | (((val) & 0x1) << 3)) |
| 81 | /* Suspend Enable Bit for OCDS (2) */ |
| 82 | #define SSC_CLC_SPEN (0x1 << 2) |
| 83 | #define SSC_CLC_SPEN_VAL(val) (((val) & 0x1) << 2) |
| 84 | #define SSC_CLC_SPEN_GET(val) ((((val) & SSC_CLC_SPEN) >> 2) & 0x1) |
| 85 | #define SSC_CLC_SPEN_SET(reg,val) (reg) = ((reg & ~SSC_CLC_SPEN) | (((val) & 0x1) << 2)) |
| 86 | /* Disable Status Bit (1) */ |
| 87 | #define SSC_CLC_DISS (0x1 << 1) |
| 88 | #define SSC_CLC_DISS_GET(val) ((((val) & SSC_CLC_DISS) >> 1) & 0x1) |
| 89 | /* Disable Request Bit (0) */ |
| 90 | #define SSC_CLC_DISR (0x1) |
| 91 | #define SSC_CLC_DISR_VAL(val) (((val) & 0x1) << 0) |
| 92 | #define SSC_CLC_DISR_GET(val) ((((val) & SSC_CLC_DISR) >> 0) & 0x1) |
| 93 | #define SSC_CLC_DISR_SET(reg,val) (reg) = ((reg & ~SSC_CLC_DISR) | (((val) & 0x1) << 0)) |
| 94 | |
| 95 | /******************************************************************************* |
| 96 | * ID Register |
| 97 | ******************************************************************************/ |
| 98 | |
| 99 | /* Transmit FIFO Size (29:24) */ |
| 100 | #define SSC_ID_TXFS (0x3f << 24) |
| 101 | #define SSC_ID_TXFS_GET(val) ((((val) & SSC_ID_TXFS) >> 24) & 0x3f) |
| 102 | /* Receive FIFO Size (21:16) */ |
| 103 | #define SSC_ID_RXFS (0x3f << 16) |
| 104 | #define SSC_ID_RXFS_GET(val) ((((val) & SSC_ID_RXFS) >> 16) & 0x3f) |
| 105 | /* Module ID (15:8) */ |
| 106 | #define SSC_ID_ID (0xff << 8) |
| 107 | #define SSC_ID_ID_GET(val) ((((val) & SSC_ID_ID) >> 8) & 0xff) |
| 108 | /* Configuration (5) */ |
| 109 | #define SSC_ID_CFG (0x1 << 5) |
| 110 | #define SSC_ID_CFG_GET(val) ((((val) & SSC_ID_CFG) >> 5) & 0x1) |
| 111 | /* Revision (4:0) */ |
| 112 | #define SSC_ID_REV (0x1f) |
| 113 | #define SSC_ID_REV_GET(val) ((((val) & SSC_ID_REV) >> 0) & 0x1f) |
| 114 | |
| 115 | /******************************************************************************* |
| 116 | * MCON Register |
| 117 | ******************************************************************************/ |
| 118 | |
| 119 | /* Echo Mode (24) */ |
| 120 | #define SSC_MCON_EM (0x1 << 24) |
| 121 | #define SSC_MCON_EM_VAL(val) (((val) & 0x1) << 24) |
| 122 | #define SSC_MCON_EM_GET(val) ((((val) & SSC_MCON_EM) >> 24) & 0x1) |
| 123 | #define SSC_MCON_EM_SET(reg,val) (reg) = ((reg & ~SSC_MCON_EM) | (((val) & 0x1) << 24)) |
| 124 | /* Idle Bit Value (23) */ |
| 125 | #define SSC_MCON_IDLE (0x1 << 23) |
| 126 | #define SSC_MCON_IDLE_VAL(val) (((val) & 0x1) << 23) |
| 127 | #define SSC_MCON_IDLE_GET(val) ((((val) & SSC_MCON_IDLE) >> 23) & 0x1) |
| 128 | #define SSC_MCON_IDLE_SET(reg,val) (reg) = ((reg & ~SSC_MCON_IDLE) | (((val) & 0x1) << 23)) |
| 129 | /* Enable Byte Valid Control (22) */ |
| 130 | #define SSC_MCON_ENBV (0x1 << 22) |
| 131 | #define SSC_MCON_ENBV_VAL(val) (((val) & 0x1) << 22) |
| 132 | #define SSC_MCON_ENBV_GET(val) ((((val) & SSC_MCON_ENBV) >> 22) & 0x1) |
| 133 | #define SSC_MCON_ENBV_SET(reg,val) (reg) = ((reg & ~SSC_MCON_ENBV) | (((val) & 0x1) << 22)) |
| 134 | /* Data Width Selection (20:16) */ |
| 135 | #define SSC_MCON_BM (0x1f << 16) |
| 136 | #define SSC_MCON_BM_VAL(val) (((val) & 0x1f) << 16) |
| 137 | #define SSC_MCON_BM_GET(val) ((((val) & SSC_MCON_BM) >> 16) & 0x1f) |
| 138 | #define SSC_MCON_BM_SET(reg,val) (reg) = ((reg & ~SSC_MCON_BM) | (((val) & 0x1f) << 16)) |
| 139 | /* Receive Underflow Error Enable (12) */ |
| 140 | #define SSC_MCON_RUEN (0x1 << 12) |
| 141 | #define SSC_MCON_RUEN_VAL(val) (((val) & 0x1) << 12) |
| 142 | #define SSC_MCON_RUEN_GET(val) ((((val) & SSC_MCON_RUEN) >> 12) & 0x1) |
| 143 | #define SSC_MCON_RUEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_RUEN) | (((val) & 0x1) << 12)) |
| 144 | /* Transmit Underflow Error Enable (11) */ |
| 145 | #define SSC_MCON_TUEN (0x1 << 11) |
| 146 | #define SSC_MCON_TUEN_VAL(val) (((val) & 0x1) << 11) |
| 147 | #define SSC_MCON_TUEN_GET(val) ((((val) & SSC_MCON_TUEN) >> 11) & 0x1) |
| 148 | #define SSC_MCON_TUEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_TUEN) | (((val) & 0x1) << 11)) |
| 149 | /* Abort Error Enable (10) */ |
| 150 | #define SSC_MCON_AEN (0x1 << 10) |
| 151 | #define SSC_MCON_AEN_VAL(val) (((val) & 0x1) << 10) |
| 152 | #define SSC_MCON_AEN_GET(val) ((((val) & SSC_MCON_AEN) >> 10) & 0x1) |
| 153 | #define SSC_MCON_AEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_AEN) | (((val) & 0x1) << 10)) |
| 154 | /* Receive Overflow Error Enable (9) */ |
| 155 | #define SSC_MCON_REN (0x1 << 9) |
| 156 | #define SSC_MCON_REN_VAL(val) (((val) & 0x1) << 9) |
| 157 | #define SSC_MCON_REN_GET(val) ((((val) & SSC_MCON_REN) >> 9) & 0x1) |
| 158 | #define SSC_MCON_REN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_REN) | (((val) & 0x1) << 9)) |
| 159 | /* Transmit Overflow Error Enable (8) */ |
| 160 | #define SSC_MCON_TEN (0x1 << 8) |
| 161 | #define SSC_MCON_TEN_VAL(val) (((val) & 0x1) << 8) |
| 162 | #define SSC_MCON_TEN_GET(val) ((((val) & SSC_MCON_TEN) >> 8) & 0x1) |
| 163 | #define SSC_MCON_TEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_TEN) | (((val) & 0x1) << 8)) |
| 164 | /* Loop Back Control (7) */ |
| 165 | #define SSC_MCON_LB (0x1 << 7) |
| 166 | #define SSC_MCON_LB_VAL(val) (((val) & 0x1) << 7) |
| 167 | #define SSC_MCON_LB_GET(val) ((((val) & SSC_MCON_LB) >> 7) & 0x1) |
| 168 | #define SSC_MCON_LB_SET(reg,val) (reg) = ((reg & ~SSC_MCON_LB) | (((val) & 0x1) << 7)) |
| 169 | /* Clock Polarity Control (6) */ |
| 170 | #define SSC_MCON_PO (0x1 << 6) |
| 171 | #define SSC_MCON_PO_VAL(val) (((val) & 0x1) << 6) |
| 172 | #define SSC_MCON_PO_GET(val) ((((val) & SSC_MCON_PO) >> 6) & 0x1) |
| 173 | #define SSC_MCON_PO_SET(reg,val) (reg) = ((reg & ~SSC_MCON_PO) | (((val) & 0x1) << 6)) |
| 174 | /* Clock Phase Control (5) */ |
| 175 | #define SSC_MCON_PH (0x1 << 5) |
| 176 | #define SSC_MCON_PH_VAL(val) (((val) & 0x1) << 5) |
| 177 | #define SSC_MCON_PH_GET(val) ((((val) & SSC_MCON_PH) >> 5) & 0x1) |
| 178 | #define SSC_MCON_PH_SET(reg,val) (reg) = ((reg & ~SSC_MCON_PH) | (((val) & 0x1) << 5)) |
| 179 | /* Heading Control (4) */ |
| 180 | #define SSC_MCON_HB (0x1 << 4) |
| 181 | #define SSC_MCON_HB_VAL(val) (((val) & 0x1) << 4) |
| 182 | #define SSC_MCON_HB_GET(val) ((((val) & SSC_MCON_HB) >> 4) & 0x1) |
| 183 | #define SSC_MCON_HB_SET(reg,val) (reg) = ((reg & ~SSC_MCON_HB) | (((val) & 0x1) << 4)) |
| 184 | /* Chip Select Enable (3) */ |
| 185 | #define SSC_MCON_CSBEN (0x1 << 3) |
| 186 | #define SSC_MCON_CSBEN_VAL(val) (((val) & 0x1) << 3) |
| 187 | #define SSC_MCON_CSBEN_GET(val) ((((val) & SSC_MCON_CSBEN) >> 3) & 0x1) |
| 188 | #define SSC_MCON_CSBEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_CSBEN) | (((val) & 0x1) << 3)) |
| 189 | /* Chip Select Invert (2) */ |
| 190 | #define SSC_MCON_CSBINV (0x1 << 2) |
| 191 | #define SSC_MCON_CSBINV_VAL(val) (((val) & 0x1) << 2) |
| 192 | #define SSC_MCON_CSBINV_GET(val) ((((val) & SSC_MCON_CSBINV) >> 2) & 0x1) |
| 193 | #define SSC_MCON_CSBINV_SET(reg,val) (reg) = ((reg & ~SSC_MCON_CSBINV) | (((val) & 0x1) << 2)) |
| 194 | /* Receive Off (1) */ |
| 195 | #define SSC_MCON_RXOFF (0x1 << 1) |
| 196 | #define SSC_MCON_RXOFF_VAL(val) (((val) & 0x1) << 1) |
| 197 | #define SSC_MCON_RXOFF_GET(val) ((((val) & SSC_MCON_RXOFF) >> 1) & 0x1) |
| 198 | #define SSC_MCON_RXOFF_SET(reg,val) (reg) = ((reg & ~SSC_MCON_RXOFF) | (((val) & 0x1) << 1)) |
| 199 | /* Transmit Off (0) */ |
| 200 | #define SSC_MCON_TXOFF (0x1) |
| 201 | #define SSC_MCON_TXOFF_VAL(val) (((val) & 0x1) << 0) |
| 202 | #define SSC_MCON_TXOFF_GET(val) ((((val) & SSC_MCON_TXOFF) >> 0) & 0x1) |
| 203 | #define SSC_MCON_TXOFF_SET(reg,val) (reg) = ((reg & ~SSC_MCON_TXOFF) | (((val) & 0x1) << 0)) |
| 204 | |
| 205 | /******************************************************************************* |
| 206 | * STATE Register |
| 207 | ******************************************************************************/ |
| 208 | |
| 209 | /* Receive End-of-Message (31) */ |
| 210 | #define SSC_STATE_RXEOM (0x1 << 31) |
| 211 | #define SSC_STATE_RXEOM_GET(val) ((((val) & SSC_STATE_RXEOM) >> 31) & 0x1) |
| 212 | /* Receive Byte Valid (30:28) */ |
| 213 | #define SSC_STATE_RXBV (0x7 << 28) |
| 214 | #define SSC_STATE_RXBV_GET(val) ((((val) & SSC_STATE_RXBV) >> 28) & 0x7) |
| 215 | /* Transmit End-of-Message (27) */ |
| 216 | #define SSC_STATE_TXEOM (0x1 << 27) |
| 217 | #define SSC_STATE_TXEOM_GET(val) ((((val) & SSC_STATE_TXEOM) >> 27) & 0x1) |
| 218 | /* Transmit Byte Valid (26:24) */ |
| 219 | #define SSC_STATE_TXBV (0x7 << 24) |
| 220 | #define SSC_STATE_TXBV_GET(val) ((((val) & SSC_STATE_TXBV) >> 24) & 0x7) |
| 221 | /* Bit Count Field (20:16) */ |
| 222 | #define SSC_STATE_BC (0x1f << 16) |
| 223 | #define SSC_STATE_BC_GET(val) ((((val) & SSC_STATE_BC) >> 16) & 0x1f) |
| 224 | /* Busy Flag (13) */ |
| 225 | #define SSC_STATE_BSY (0x1 << 13) |
| 226 | #define SSC_STATE_BSY_GET(val) ((((val) & SSC_STATE_BSY) >> 13) & 0x1) |
| 227 | /* Receive Underflow Error Flag (12) */ |
| 228 | #define SSC_STATE_RUE (0x1 << 12) |
| 229 | #define SSC_STATE_RUE_GET(val) ((((val) & SSC_STATE_RUE) >> 12) & 0x1) |
| 230 | /* Transmit Underflow Error Flag (11) */ |
| 231 | #define SSC_STATE_TUE (0x1 << 11) |
| 232 | #define SSC_STATE_TUE_GET(val) ((((val) & SSC_STATE_TUE) >> 11) & 0x1) |
| 233 | /* Abort Error Flag (10) */ |
| 234 | #define SSC_STATE_AE (0x1 << 10) |
| 235 | #define SSC_STATE_AE_GET(val) ((((val) & SSC_STATE_AE) >> 10) & 0x1) |
| 236 | /* Receive Error Flag (9) */ |
| 237 | #define SSC_STATE_RE (0x1 << 9) |
| 238 | #define SSC_STATE_RE_GET(val) ((((val) & SSC_STATE_RE) >> 9) & 0x1) |
| 239 | /* Transmit Error Flag (8) */ |
| 240 | #define SSC_STATE_TE (0x1 << 8) |
| 241 | #define SSC_STATE_TE_GET(val) ((((val) & SSC_STATE_TE) >> 8) & 0x1) |
| 242 | /* Mode Error Flag (7) */ |
| 243 | #define SSC_STATE_ME (0x1 << 7) |
| 244 | #define SSC_STATE_ME_GET(val) ((((val) & SSC_STATE_ME) >> 7) & 0x1) |
| 245 | /* Slave Selected (2) */ |
| 246 | #define SSC_STATE_SSEL (0x1 << 2) |
| 247 | #define SSC_STATE_SSEL_GET(val) ((((val) & SSC_STATE_SSEL) >> 2) & 0x1) |
| 248 | /* Master Select Bit (1) */ |
| 249 | #define SSC_STATE_MS (0x1 << 1) |
| 250 | #define SSC_STATE_MS_GET(val) ((((val) & SSC_STATE_MS) >> 1) & 0x1) |
| 251 | /* Enable Bit (0) */ |
| 252 | #define SSC_STATE_EN (0x1) |
| 253 | #define SSC_STATE_EN_GET(val) ((((val) & SSC_STATE_EN) >> 0) & 0x1) |
| 254 | |
| 255 | /******************************************************************************* |
| 256 | * WHBSTATE Register |
| 257 | ******************************************************************************/ |
| 258 | |
| 259 | /* Set Transmit Underflow Error Flag Bit (15) */ |
| 260 | #define SSC_WHBSTATE_SETTUE (0x1 << 15) |
| 261 | #define SSC_WHBSTATE_SETTUE_VAL(val) (((val) & 0x1) << 15) |
| 262 | #define SSC_WHBSTATE_SETTUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETTUE) | (val) & 1) << 15) |
| 263 | /* Set Abort Error Flag Bit (14) */ |
| 264 | #define SSC_WHBSTATE_SETAE (0x1 << 14) |
| 265 | #define SSC_WHBSTATE_SETAE_VAL(val) (((val) & 0x1) << 14) |
| 266 | #define SSC_WHBSTATE_SETAE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETAE) | (val) & 1) << 14) |
| 267 | /* Set Receive Error Flag Bit (13) */ |
| 268 | #define SSC_WHBSTATE_SETRE (0x1 << 13) |
| 269 | #define SSC_WHBSTATE_SETRE_VAL(val) (((val) & 0x1) << 13) |
| 270 | #define SSC_WHBSTATE_SETRE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETRE) | (val) & 1) << 13) |
| 271 | /* Set Transmit Error Flag Bit (12) */ |
| 272 | #define SSC_WHBSTATE_SETTE (0x1 << 12) |
| 273 | #define SSC_WHBSTATE_SETTE_VAL(val) (((val) & 0x1) << 12) |
| 274 | #define SSC_WHBSTATE_SETTE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETTE) | (val) & 1) << 12) |
| 275 | /* Clear Transmit Underflow Error Flag Bit (11) */ |
| 276 | #define SSC_WHBSTATE_CLRTUE (0x1 << 11) |
| 277 | #define SSC_WHBSTATE_CLRTUE_VAL(val) (((val) & 0x1) << 11) |
| 278 | #define SSC_WHBSTATE_CLRTUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRTUE) | (val) & 1) << 11) |
| 279 | /* Clear Abort Error Flag Bit (10) */ |
| 280 | #define SSC_WHBSTATE_CLRAE (0x1 << 10) |
| 281 | #define SSC_WHBSTATE_CLRAE_VAL(val) (((val) & 0x1) << 10) |
| 282 | #define SSC_WHBSTATE_CLRAE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRAE) | (val) & 1) << 10) |
| 283 | /* Clear Receive Error Flag Bit (9) */ |
| 284 | #define SSC_WHBSTATE_CLRRE (0x1 << 9) |
| 285 | #define SSC_WHBSTATE_CLRRE_VAL(val) (((val) & 0x1) << 9) |
| 286 | #define SSC_WHBSTATE_CLRRE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRRE) | (val) & 1) << 9) |
| 287 | /* Clear Transmit Error Flag Bit (8) */ |
| 288 | #define SSC_WHBSTATE_CLRTE (0x1 << 8) |
| 289 | #define SSC_WHBSTATE_CLRTE_VAL(val) (((val) & 0x1) << 8) |
| 290 | #define SSC_WHBSTATE_CLRTE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRTE) | (val) & 1) << 8) |
| 291 | /* Set Mode Error Flag Bit (7) */ |
| 292 | #define SSC_WHBSTATE_SETME (0x1 << 7) |
| 293 | #define SSC_WHBSTATE_SETME_VAL(val) (((val) & 0x1) << 7) |
| 294 | #define SSC_WHBSTATE_SETME_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETME) | (val) & 1) << 7) |
| 295 | /* Clear Mode Error Flag Bit (6) */ |
| 296 | #define SSC_WHBSTATE_CLRME (0x1 << 6) |
| 297 | #define SSC_WHBSTATE_CLRME_VAL(val) (((val) & 0x1) << 6) |
| 298 | #define SSC_WHBSTATE_CLRME_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRME) | (val) & 1) << 6) |
| 299 | /* Set Receive Underflow Error Bit (5) */ |
| 300 | #define SSC_WHBSTATE_SETRUE (0x1 << 5) |
| 301 | #define SSC_WHBSTATE_SETRUE_VAL(val) (((val) & 0x1) << 5) |
| 302 | #define SSC_WHBSTATE_SETRUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETRUE) | (val) & 1) << 5) |
| 303 | /* Clear Receive Underflow Error Bit (4) */ |
| 304 | #define SSC_WHBSTATE_CLRRUE (0x1 << 4) |
| 305 | #define SSC_WHBSTATE_CLRRUE_VAL(val) (((val) & 0x1) << 4) |
| 306 | #define SSC_WHBSTATE_CLRRUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRRUE) | (val) & 1) << 4) |
| 307 | /* Set Master Select Bit (3) */ |
| 308 | #define SSC_WHBSTATE_SETMS (0x1 << 3) |
| 309 | #define SSC_WHBSTATE_SETMS_VAL(val) (((val) & 0x1) << 3) |
| 310 | #define SSC_WHBSTATE_SETMS_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETMS) | (val) & 1) << 3) |
| 311 | /* Clear Master Select Bit (2) */ |
| 312 | #define SSC_WHBSTATE_CLRMS (0x1 << 2) |
| 313 | #define SSC_WHBSTATE_CLRMS_VAL(val) (((val) & 0x1) << 2) |
| 314 | #define SSC_WHBSTATE_CLRMS_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRMS) | (val) & 1) << 2) |
| 315 | /* Set Enable Bit (1) */ |
| 316 | #define SSC_WHBSTATE_SETEN (0x1 << 1) |
| 317 | #define SSC_WHBSTATE_SETEN_VAL(val) (((val) & 0x1) << 1) |
| 318 | #define SSC_WHBSTATE_SETEN_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETEN) | (val) & 1) << 1) |
| 319 | /* Clear Enable Bit (0) */ |
| 320 | #define SSC_WHBSTATE_CLREN (0x1) |
| 321 | #define SSC_WHBSTATE_CLREN_VAL(val) (((val) & 0x1) << 0) |
| 322 | #define SSC_WHBSTATE_CLREN_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLREN) | (val) & 1) << 0) |
| 323 | |
| 324 | /******************************************************************************* |
| 325 | * TB Register |
| 326 | ******************************************************************************/ |
| 327 | |
| 328 | /* Transmit Data Register Value (31:0) */ |
| 329 | #define SSC_TB_TB_VAL (0xFFFFFFFFL) |
| 330 | #define SSC_TB_TB_VAL_VAL(val) (((val) & 0xFFFFFFFFL) << 0) |
| 331 | #define SSC_TB_TB_VAL_GET(val) ((((val) & SSC_TB_TB_VAL) >> 0) & 0xFFFFFFFFL) |
| 332 | #define SSC_TB_TB_VAL_SET(reg,val) (reg) = ((reg & ~SSC_TB_TB_VAL) | (((val) & 0xFFFFFFFFL) << 0)) |
| 333 | |
| 334 | /******************************************************************************* |
| 335 | * RB Register |
| 336 | ******************************************************************************/ |
| 337 | |
| 338 | /* Receive Data Register Value (31:0) */ |
| 339 | #define SSC_RB_RB_VAL (0xFFFFFFFFL) |
| 340 | #define SSC_RB_RB_VAL_GET(val) ((((val) & SSC_RB_RB_VAL) >> 0) & 0xFFFFFFFFL) |
| 341 | |
| 342 | /******************************************************************************* |
| 343 | * FSTAT Register |
| 344 | ******************************************************************************/ |
| 345 | |
| 346 | /* Transmit FIFO Filling Level (13:8) */ |
| 347 | #define SSC_FSTAT_TXFFL (0x3f << 8) |
| 348 | #define SSC_FSTAT_TXFFL_GET(val) ((((val) & SSC_FSTAT_TXFFL) >> 8) & 0x3f) |
| 349 | /* Receive FIFO Filling Level (5:0) */ |
| 350 | #define SSC_FSTAT_RXFFL (0x3f) |
| 351 | #define SSC_FSTAT_RXFFL_GET(val) ((((val) & SSC_FSTAT_RXFFL) >> 0) & 0x3f) |
| 352 | |
| 353 | /******************************************************************************* |
| 354 | * PISEL Register |
| 355 | ******************************************************************************/ |
| 356 | |
| 357 | /* Slave Mode Clock Input Select (2) */ |
| 358 | #define SSC_PISEL_CIS (0x1 << 2) |
| 359 | #define SSC_PISEL_CIS_VAL(val) (((val) & 0x1) << 2) |
| 360 | #define SSC_PISEL_CIS_GET(val) ((((val) & SSC_PISEL_CIS) >> 2) & 0x1) |
| 361 | #define SSC_PISEL_CIS_SET(reg,val) (reg) = ((reg & ~SSC_PISEL_CIS) | (((val) & 0x1) << 2)) |
| 362 | /* Slave Mode Receiver Input Select (1) */ |
| 363 | #define SSC_PISEL_SIS (0x1 << 1) |
| 364 | #define SSC_PISEL_SIS_VAL(val) (((val) & 0x1) << 1) |
| 365 | #define SSC_PISEL_SIS_GET(val) ((((val) & SSC_PISEL_SIS) >> 1) & 0x1) |
| 366 | #define SSC_PISEL_SIS_SET(reg,val) (reg) = ((reg & ~SSC_PISEL_SIS) | (((val) & 0x1) << 1)) |
| 367 | /* Master Mode Receiver Input Select (0) */ |
| 368 | #define SSC_PISEL_MIS (0x1) |
| 369 | #define SSC_PISEL_MIS_VAL(val) (((val) & 0x1) << 0) |
| 370 | #define SSC_PISEL_MIS_GET(val) ((((val) & SSC_PISEL_MIS) >> 0) & 0x1) |
| 371 | #define SSC_PISEL_MIS_SET(reg,val) (reg) = ((reg & ~SSC_PISEL_MIS) | (((val) & 0x1) << 0)) |
| 372 | |
| 373 | /******************************************************************************* |
| 374 | * RXFCON Register |
| 375 | ******************************************************************************/ |
| 376 | |
| 377 | /* Receive FIFO Interrupt Trigger Level (13:8) */ |
| 378 | #define SSC_RXFCON_RXFITL (0x3f << 8) |
| 379 | #define SSC_RXFCON_RXFITL_VAL(val) (((val) & 0x3f) << 8) |
| 380 | #define SSC_RXFCON_RXFITL_GET(val) ((((val) & SSC_RXFCON_RXFITL) >> 8) & 0x3f) |
| 381 | #define SSC_RXFCON_RXFITL_SET(reg,val) (reg) = ((reg & ~SSC_RXFCON_RXFITL) | (((val) & 0x3f) << 8)) |
| 382 | /* Receive FIFO Flush (1) */ |
| 383 | #define SSC_RXFCON_RXFLU (0x1 << 1) |
| 384 | #define SSC_RXFCON_RXFLU_VAL(val) (((val) & 0x1) << 1) |
| 385 | #define SSC_RXFCON_RXFLU_SET(reg,val) (reg) = (((reg & ~SSC_RXFCON_RXFLU) | (val) & 1) << 1) |
| 386 | /* Receive FIFO Enable (0) */ |
| 387 | #define SSC_RXFCON_RXFEN (0x1) |
| 388 | #define SSC_RXFCON_RXFEN_VAL(val) (((val) & 0x1) << 0) |
| 389 | #define SSC_RXFCON_RXFEN_GET(val) ((((val) & SSC_RXFCON_RXFEN) >> 0) & 0x1) |
| 390 | #define SSC_RXFCON_RXFEN_SET(reg,val) (reg) = ((reg & ~SSC_RXFCON_RXFEN) | (((val) & 0x1) << 0)) |
| 391 | |
| 392 | /******************************************************************************* |
| 393 | * TXFCON Register |
| 394 | ******************************************************************************/ |
| 395 | |
| 396 | /* Transmit FIFO Interrupt Trigger Level (13:8) */ |
| 397 | #define SSC_TXFCON_TXFITL (0x3f << 8) |
| 398 | #define SSC_TXFCON_TXFITL_VAL(val) (((val) & 0x3f) << 8) |
| 399 | #define SSC_TXFCON_TXFITL_GET(val) ((((val) & SSC_TXFCON_TXFITL) >> 8) & 0x3f) |
| 400 | #define SSC_TXFCON_TXFITL_SET(reg,val) (reg) = ((reg & ~SSC_TXFCON_TXFITL) | (((val) & 0x3f) << 8)) |
| 401 | /* Transmit FIFO Flush (1) */ |
| 402 | #define SSC_TXFCON_TXFLU (0x1 << 1) |
| 403 | #define SSC_TXFCON_TXFLU_VAL(val) (((val) & 0x1) << 1) |
| 404 | #define SSC_TXFCON_TXFLU_SET(reg,val) (reg) = (((reg & ~SSC_TXFCON_TXFLU) | (val) & 1) << 1) |
| 405 | /* Transmit FIFO Enable (0) */ |
| 406 | #define SSC_TXFCON_TXFEN (0x1) |
| 407 | #define SSC_TXFCON_TXFEN_VAL(val) (((val) & 0x1) << 0) |
| 408 | #define SSC_TXFCON_TXFEN_GET(val) ((((val) & SSC_TXFCON_TXFEN) >> 0) & 0x1) |
| 409 | #define SSC_TXFCON_TXFEN_SET(reg,val) (reg) = ((reg & ~SSC_TXFCON_TXFEN) | (((val) & 0x1) << 0)) |
| 410 | |
| 411 | /******************************************************************************* |
| 412 | * BR Register |
| 413 | ******************************************************************************/ |
| 414 | |
| 415 | /* Baudrate Timer Reload Register Value (15:0) */ |
| 416 | #define SSC_BR_BR_VAL (0xffff) |
| 417 | #define SSC_BR_BR_VAL_VAL(val) (((val) & 0xffff) << 0) |
| 418 | #define SSC_BR_BR_VAL_GET(val) ((((val) & SSC_BR_BR_VAL) >> 0) & 0xffff) |
| 419 | #define SSC_BR_BR_VAL_SET(reg,val) (reg) = ((reg & ~SSC_BR_BR_VAL) | (((val) & 0xffff) << 0)) |
| 420 | |
| 421 | /******************************************************************************* |
| 422 | * BRSTAT Register |
| 423 | ******************************************************************************/ |
| 424 | |
| 425 | /* Baudrate Timer Register Value (15:0) */ |
| 426 | #define SSC_BRSTAT_BT_VAL (0xffff) |
| 427 | #define SSC_BRSTAT_BT_VAL_GET(val) ((((val) & SSC_BRSTAT_BT_VAL) >> 0) & 0xffff) |
| 428 | |
| 429 | /******************************************************************************* |
| 430 | * SFCON Register |
| 431 | ******************************************************************************/ |
| 432 | |
| 433 | /* Pause Length (31:22) */ |
| 434 | #define SSC_SFCON_PLEN (0x3ff << 22) |
| 435 | #define SSC_SFCON_PLEN_VAL(val) (((val) & 0x3ff) << 22) |
| 436 | #define SSC_SFCON_PLEN_GET(val) ((((val) & SSC_SFCON_PLEN) >> 22) & 0x3ff) |
| 437 | #define SSC_SFCON_PLEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_PLEN) | (((val) & 0x3ff) << 22)) |
| 438 | /* Stop After Pause (20) */ |
| 439 | #define SSC_SFCON_STOP (0x1 << 20) |
| 440 | #define SSC_SFCON_STOP_VAL(val) (((val) & 0x1) << 20) |
| 441 | #define SSC_SFCON_STOP_GET(val) ((((val) & SSC_SFCON_STOP) >> 20) & 0x1) |
| 442 | #define SSC_SFCON_STOP_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_STOP) | (((val) & 0x1) << 20)) |
| 443 | /* Idle Clock Configuration (19:18) */ |
| 444 | #define SSC_SFCON_ICLK (0x3 << 18) |
| 445 | #define SSC_SFCON_ICLK_VAL(val) (((val) & 0x3) << 18) |
| 446 | #define SSC_SFCON_ICLK_GET(val) ((((val) & SSC_SFCON_ICLK) >> 18) & 0x3) |
| 447 | #define SSC_SFCON_ICLK_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_ICLK) | (((val) & 0x3) << 18)) |
| 448 | /* Idle Data Configuration (17:16) */ |
| 449 | #define SSC_SFCON_IDAT (0x3 << 16) |
| 450 | #define SSC_SFCON_IDAT_VAL(val) (((val) & 0x3) << 16) |
| 451 | #define SSC_SFCON_IDAT_GET(val) ((((val) & SSC_SFCON_IDAT) >> 16) & 0x3) |
| 452 | #define SSC_SFCON_IDAT_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_IDAT) | (((val) & 0x3) << 16)) |
| 453 | /* Data Length (15:4) */ |
| 454 | #define SSC_SFCON_DLEN (0xfff << 4) |
| 455 | #define SSC_SFCON_DLEN_VAL(val) (((val) & 0xfff) << 4) |
| 456 | #define SSC_SFCON_DLEN_GET(val) ((((val) & SSC_SFCON_DLEN) >> 4) & 0xfff) |
| 457 | #define SSC_SFCON_DLEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_DLEN) | (((val) & 0xfff) << 4)) |
| 458 | /* Enable Interrupt After Pause (3) */ |
| 459 | #define SSC_SFCON_IAEN (0x1 << 3) |
| 460 | #define SSC_SFCON_IAEN_VAL(val) (((val) & 0x1) << 3) |
| 461 | #define SSC_SFCON_IAEN_GET(val) ((((val) & SSC_SFCON_IAEN) >> 3) & 0x1) |
| 462 | #define SSC_SFCON_IAEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_IAEN) | (((val) & 0x1) << 3)) |
| 463 | /* Enable Interrupt Before Pause (2) */ |
| 464 | #define SSC_SFCON_IBEN (0x1 << 2) |
| 465 | #define SSC_SFCON_IBEN_VAL(val) (((val) & 0x1) << 2) |
| 466 | #define SSC_SFCON_IBEN_GET(val) ((((val) & SSC_SFCON_IBEN) >> 2) & 0x1) |
| 467 | #define SSC_SFCON_IBEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_IBEN) | (((val) & 0x1) << 2)) |
| 468 | /* Serial Frame Enable (0) */ |
| 469 | #define SSC_SFCON_SFEN (0x1) |
| 470 | #define SSC_SFCON_SFEN_VAL(val) (((val) & 0x1) << 0) |
| 471 | #define SSC_SFCON_SFEN_GET(val) ((((val) & SSC_SFCON_SFEN) >> 0) & 0x1) |
| 472 | #define SSC_SFCON_SFEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_SFEN) | (((val) & 0x1) << 0)) |
| 473 | |
| 474 | /******************************************************************************* |
| 475 | * SFSTAT Register |
| 476 | ******************************************************************************/ |
| 477 | |
| 478 | /* Pause Count (31:22) */ |
| 479 | #define SSC_SFSTAT_PCNT (0x3ff << 22) |
| 480 | #define SSC_SFSTAT_PCNT_GET(val) ((((val) & SSC_SFSTAT_PCNT) >> 22) & 0x3ff) |
| 481 | /* Data Bit Count (15:4) */ |
| 482 | #define SSC_SFSTAT_DCNT (0xfff << 4) |
| 483 | #define SSC_SFSTAT_DCNT_GET(val) ((((val) & SSC_SFSTAT_DCNT) >> 4) & 0xfff) |
| 484 | /* Pause Busy (1) */ |
| 485 | #define SSC_SFSTAT_PBSY (0x1 << 1) |
| 486 | #define SSC_SFSTAT_PBSY_GET(val) ((((val) & SSC_SFSTAT_PBSY) >> 1) & 0x1) |
| 487 | /* Data Busy (0) */ |
| 488 | #define SSC_SFSTAT_DBSY (0x1) |
| 489 | #define SSC_SFSTAT_DBSY_GET(val) ((((val) & SSC_SFSTAT_DBSY) >> 0) & 0x1) |
| 490 | |
| 491 | /******************************************************************************* |
| 492 | * GPOCON Register |
| 493 | ******************************************************************************/ |
| 494 | |
| 495 | /* Output OUTn Is Chip Select (15:8) */ |
| 496 | #define SSC_GPOCON_ISCSBN (0xff << 8) |
| 497 | #define SSC_GPOCON_ISCSBN_VAL(val) (((val) & 0xff) << 8) |
| 498 | #define SSC_GPOCON_ISCSBN_GET(val) ((((val) & SSC_GPOCON_ISCSBN) >> 8) & 0xff) |
| 499 | #define SSC_GPOCON_ISCSBN_SET(reg,val) (reg) = ((reg & ~SSC_GPOCON_ISCSBN) | (((val) & 0xff) << 8)) |
| 500 | /* Invert Output OUTn (7:0) */ |
| 501 | #define SSC_GPOCON_INVOUTN (0xff) |
| 502 | #define SSC_GPOCON_INVOUTN_VAL(val) (((val) & 0xff) << 0) |
| 503 | #define SSC_GPOCON_INVOUTN_GET(val) ((((val) & SSC_GPOCON_INVOUTN) >> 0) & 0xff) |
| 504 | #define SSC_GPOCON_INVOUTN_SET(reg,val) (reg) = ((reg & ~SSC_GPOCON_INVOUTN) | (((val) & 0xff) << 0)) |
| 505 | |
| 506 | /******************************************************************************* |
| 507 | * GPOSTAT Register |
| 508 | ******************************************************************************/ |
| 509 | |
| 510 | /* Output Register Bit n (7:0) */ |
| 511 | #define SSC_GPOSTAT_OUTN (0xff) |
| 512 | #define SSC_GPOSTAT_OUTN_GET(val) ((((val) & SSC_GPOSTAT_OUTN) >> 0) & 0xff) |
| 513 | |
| 514 | /******************************************************************************* |
| 515 | * WHBGPOSTAT |
| 516 | ******************************************************************************/ |
| 517 | |
| 518 | /* Set Output Register Bit n (15:8) */ |
| 519 | #define SSC_WHBGPOSTAT_SETOUTN (0xff << 8) |
| 520 | #define SSC_WHBGPOSTAT_SETOUTN_VAL(val) (((val) & 0xff) << 8) |
| 521 | #define SSC_WHBGPOSTAT_SETOUTN_SET(reg,val) (reg) = (((reg & ~SSC_WHBGPOSTAT_SETOUTN) | (val) & 1) << 8) |
| 522 | /* Clear Output Register Bit n (7:0) */ |
| 523 | #define SSC_WHBGPOSTAT_CLROUTN (0xff) |
| 524 | #define SSC_WHBGPOSTAT_CLROUTN_VAL(val) (((val) & 0xff) << 0) |
| 525 | #define SSC_WHBGPOSTAT_CLROUTN_SET(reg,val) (reg) = (((reg & ~SSC_WHBGPOSTAT_CLROUTN) | (val) & 1) << 0) |
| 526 | |
| 527 | /******************************************************************************* |
| 528 | * RXREQ Register |
| 529 | ******************************************************************************/ |
| 530 | |
| 531 | /* Receive Count Value (15:0) */ |
| 532 | #define SSC_RXREQ_RXCNT (0xffff) |
| 533 | #define SSC_RXREQ_RXCNT_VAL(val) (((val) & 0xffff) << 0) |
| 534 | #define SSC_RXREQ_RXCNT_GET(val) ((((val) & SSC_RXREQ_RXCNT) >> 0) & 0xffff) |
| 535 | #define SSC_RXREQ_RXCNT_SET(reg,val) (reg) = ((reg & ~SSC_RXREQ_RXCNT) | (((val) & 0xffff) << 0)) |
| 536 | |
| 537 | /******************************************************************************* |
| 538 | * RXCNT Register |
| 539 | ******************************************************************************/ |
| 540 | |
| 541 | /* Receive To Do Value (15:0) */ |
| 542 | #define SSC_RXCNT_TODO (0xffff) |
| 543 | #define SSC_RXCNT_TODO_GET(val) ((((val) & SSC_RXCNT_TODO) >> 0) & 0xffff) |
| 544 | |
| 545 | /******************************************************************************* |
| 546 | * DMA_CON Register |
| 547 | ******************************************************************************/ |
| 548 | |
| 549 | /* Receive Class (3:2) */ |
| 550 | #define SSC_DMA_CON_RXCLS (0x3 << 2) |
| 551 | #define SSC_DMA_CON_RXCLS_VAL(val) (((val) & 0x3) << 2) |
| 552 | #define SSC_DMA_CON_RXCLS_GET(val) ((((val) & SSC_DMA_CON_RXCLS) >> 2) & 0x3) |
| 553 | #define SSC_DMA_CON_RXCLS_SET(reg,val) (reg) = ((reg & ~SSC_DMA_CON_RXCLS) | (((val) & 0x3) << 2)) |
| 554 | /* Transmit Path On (1) */ |
| 555 | #define SSC_DMA_CON_TXON (0x1 << 1) |
| 556 | #define SSC_DMA_CON_TXON_VAL(val) (((val) & 0x1) << 1) |
| 557 | #define SSC_DMA_CON_TXON_GET(val) ((((val) & SSC_DMA_CON_TXON) >> 1) & 0x1) |
| 558 | #define SSC_DMA_CON_TXON_SET(reg,val) (reg) = ((reg & ~SSC_DMA_CON_TXON) | (((val) & 0x1) << 1)) |
| 559 | /* Receive Path On (0) */ |
| 560 | #define SSC_DMA_CON_RXON (0x1) |
| 561 | #define SSC_DMA_CON_RXON_VAL(val) (((val) & 0x1) << 0) |
| 562 | #define SSC_DMA_CON_RXON_GET(val) ((((val) & SSC_DMA_CON_RXON) >> 0) & 0x1) |
| 563 | #define SSC_DMA_CON_RXON_SET(reg,val) (reg) = ((reg & ~SSC_DMA_CON_RXON) | (((val) & 0x1) << 0)) |
| 564 | |
| 565 | /******************************************************************************* |
| 566 | * IRNEN Register |
| 567 | ******************************************************************************/ |
| 568 | |
| 569 | /* Frame End Interrupt Request Enable (3) */ |
| 570 | #define SSC_IRNEN_F (0x1 << 3) |
| 571 | #define SSC_IRNEN_F_VAL(val) (((val) & 0x1) << 3) |
| 572 | #define SSC_IRNEN_F_GET(val) ((((val) & SSC_IRNEN_F) >> 3) & 0x1) |
| 573 | #define SSC_IRNEN_F_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_F) | (((val) & 0x1) << 3)) |
| 574 | /* Error Interrupt Request Enable (2) */ |
| 575 | #define SSC_IRNEN_E (0x1 << 2) |
| 576 | #define SSC_IRNEN_E_VAL(val) (((val) & 0x1) << 2) |
| 577 | #define SSC_IRNEN_E_GET(val) ((((val) & SSC_IRNEN_E) >> 2) & 0x1) |
| 578 | #define SSC_IRNEN_E_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_E) | (((val) & 0x1) << 2)) |
| 579 | /* Receive Interrupt Request Enable (1) */ |
| 580 | #define SSC_IRNEN_R (0x1 << 1) |
| 581 | #define SSC_IRNEN_R_VAL(val) (((val) & 0x1) << 1) |
| 582 | #define SSC_IRNEN_R_GET(val) ((((val) & SSC_IRNEN_R) >> 1) & 0x1) |
| 583 | #define SSC_IRNEN_R_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_R) | (((val) & 0x1) << 1)) |
| 584 | /* Transmit Interrupt Request Enable (0) */ |
| 585 | #define SSC_IRNEN_T (0x1) |
| 586 | #define SSC_IRNEN_T_VAL(val) (((val) & 0x1) << 0) |
| 587 | #define SSC_IRNEN_T_GET(val) ((((val) & SSC_IRNEN_T) >> 0) & 0x1) |
| 588 | #define SSC_IRNEN_T_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_T) | (((val) & 0x1) << 0)) |
| 589 | |
| 590 | /******************************************************************************* |
| 591 | * IRNICR Register |
| 592 | ******************************************************************************/ |
| 593 | |
| 594 | /* Frame End Interrupt Request (3) */ |
| 595 | #define SSC_IRNICR_F (0x1 << 3) |
| 596 | #define SSC_IRNICR_F_GET(val) ((((val) & SSC_IRNICR_F) >> 3) & 0x1) |
| 597 | /* Error Interrupt Request (2) */ |
| 598 | #define SSC_IRNICR_E (0x1 << 2) |
| 599 | #define SSC_IRNICR_E_GET(val) ((((val) & SSC_IRNICR_E) >> 2) & 0x1) |
| 600 | /* Receive Interrupt Request (1) */ |
| 601 | #define SSC_IRNICR_R (0x1 << 1) |
| 602 | #define SSC_IRNICR_R_GET(val) ((((val) & SSC_IRNICR_R) >> 1) & 0x1) |
| 603 | /* Transmit Interrupt Request (0) */ |
| 604 | #define SSC_IRNICR_T (0x1) |
| 605 | #define SSC_IRNICR_T_GET(val) ((((val) & SSC_IRNICR_T) >> 0) & 0x1) |
| 606 | |
| 607 | /******************************************************************************* |
| 608 | * IRNCR Register |
| 609 | ******************************************************************************/ |
| 610 | |
| 611 | /* Frame End Interrupt Request (3) */ |
| 612 | #define SSC_IRNCR_F (0x1 << 3) |
| 613 | #define SSC_IRNCR_F_GET(val) ((((val) & SSC_IRNCR_F) >> 3) & 0x1) |
| 614 | /* Error Interrupt Request (2) */ |
| 615 | #define SSC_IRNCR_E (0x1 << 2) |
| 616 | #define SSC_IRNCR_E_GET(val) ((((val) & SSC_IRNCR_E) >> 2) & 0x1) |
| 617 | /* Receive Interrupt Request (1) */ |
| 618 | #define SSC_IRNCR_R (0x1 << 1) |
| 619 | #define SSC_IRNCR_R_GET(val) ((((val) & SSC_IRNCR_R) >> 1) & 0x1) |
| 620 | /* Transmit Interrupt Request (0) */ |
| 621 | #define SSC_IRNCR_T (0x1) |
| 622 | #define SSC_IRNCR_T_GET(val) ((((val) & SSC_IRNCR_T) >> 0) & 0x1) |
| 623 | |
| 624 | #endif /* __SSC_H */ |
| 625 | |
