| 1 | /****************************************************************************** |
| 2 | |
| 3 | Copyright (c) 2007 |
| 4 | Infineon Technologies AG |
| 5 | St. Martin Strasse 53; 81669 Munich, Germany |
| 6 | |
| 7 | Any use of this Software is subject to the conclusion of a respective |
| 8 | License Agreement. Without such a License Agreement no rights to the |
| 9 | Software are granted. |
| 10 | |
| 11 | ******************************************************************************/ |
| 12 | |
| 13 | #ifndef __STATUS_REG_H |
| 14 | #define __STATUS_REG_H |
| 15 | |
| 16 | #define status_r32(reg) ltq_r32(&status->reg) |
| 17 | #define status_w32(val, reg) ltq_w32(val, &status->reg) |
| 18 | #define status_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &status->reg) |
| 19 | |
| 20 | /** STATUS register structure */ |
| 21 | struct svip_reg_status { |
| 22 | unsigned long fuse_deu; /* 0x0000 */ |
| 23 | unsigned long fuse_cpu; /* 0x0004 */ |
| 24 | unsigned long fuse_pll; /* 0x0008 */ |
| 25 | unsigned long chipid; /* 0x000C */ |
| 26 | unsigned long config; /* 0x0010 */ |
| 27 | unsigned long chip_loc; /* 0x0014 */ |
| 28 | unsigned long fuse_spare; /* 0x0018 */ |
| 29 | }; |
| 30 | |
| 31 | /******************************************************************************* |
| 32 | * Fuse for DEU Settings |
| 33 | ******************************************************************************/ |
| 34 | |
| 35 | /* Fuse for Enabling the TRNG (6) */ |
| 36 | #define STATUS_FUSE_DEU_TRNG (0x1 << 6) |
| 37 | #define STATUS_FUSE_DEU_TRNG_GET(val) ((((val) & STATUS_FUSE_DEU_TRNG) >> 6) & 0x1) |
| 38 | /* Fuse for Enabling the DES Submodule (5) */ |
| 39 | #define STATUS_FUSE_DEU_DES (0x1 << 5) |
| 40 | #define STATUS_FUSE_DEU_DES_GET(val) ((((val) & STATUS_FUSE_DEU_DES) >> 5) & 0x1) |
| 41 | /* Fuse for Enabling the 3DES Submodule (4) */ |
| 42 | #define STATUS_FUSE_DEU_3DES (0x1 << 4) |
| 43 | #define STATUS_FUSE_DEU_3DES_GET(val) ((((val) & STATUS_FUSE_DEU_3DES) >> 4) & 0x1) |
| 44 | /* Fuse for Enabling the AES Submodule (3) */ |
| 45 | #define STATUS_FUSE_DEU_AES (0x1 << 3) |
| 46 | #define STATUS_FUSE_DEU_AES_GET(val) ((((val) & STATUS_FUSE_DEU_AES) >> 3) & 0x1) |
| 47 | /* Fuse for Enabling the HASH Submodule (2) */ |
| 48 | #define STATUS_FUSE_DEU_HASH (0x1 << 2) |
| 49 | #define STATUS_FUSE_DEU_HASH_GET(val) ((((val) & STATUS_FUSE_DEU_HASH) >> 2) & 0x1) |
| 50 | /* Fuse for Enabling the ARC4 Submodule (1) */ |
| 51 | #define STATUS_FUSE_DEU_ARC4 (0x1 << 1) |
| 52 | #define STATUS_FUSE_DEU_ARC4_GET(val) ((((val) & STATUS_FUSE_DEU_ARC4) >> 1) & 0x1) |
| 53 | /* Fuse for Enabling the DEU Module (0) */ |
| 54 | #define STATUS_FUSE_DEU_DEU (0x1) |
| 55 | #define STATUS_FUSE_DEU_DEU_GET(val) ((((val) & STATUS_FUSE_DEU_DEU) >> 0) & 0x1) |
| 56 | |
| 57 | /******************************************************************************* |
| 58 | * Fuse for CPU Settings |
| 59 | ******************************************************************************/ |
| 60 | |
| 61 | /* Fuse for Enabling CPU5 (5) */ |
| 62 | #define STATUS_FUSE_CPU_CPU5 (0x1 << 5) |
| 63 | #define STATUS_FUSE_CPU_CPU5_GET(val) ((((val) & STATUS_FUSE_CPU_CPU5) >> 5) & 0x1) |
| 64 | /* Fuse for Enabling the CPU4 (4) */ |
| 65 | #define STATUS_FUSE_CPU_CPU4 (0x1 << 4) |
| 66 | #define STATUS_FUSE_CPU_CPU4_GET(val) ((((val) & STATUS_FUSE_CPU_CPU4) >> 4) & 0x1) |
| 67 | /* Fuse for Enabling the CPU3 (3) */ |
| 68 | #define STATUS_FUSE_CPU_CPU3 (0x1 << 3) |
| 69 | #define STATUS_FUSE_CPU_CPU3_GET(val) ((((val) & STATUS_FUSE_CPU_CPU3) >> 3) & 0x1) |
| 70 | /* Fuse for Enabling the CPU2 (2) */ |
| 71 | #define STATUS_FUSE_CPU_CPU2 (0x1 << 2) |
| 72 | #define STATUS_FUSE_CPU_CPU2_GET(val) ((((val) & STATUS_FUSE_CPU_CPU2) >> 2) & 0x1) |
| 73 | /* Fuse for Enabling the CPU1 (1) */ |
| 74 | #define STATUS_FUSE_CPU_CPU1 (0x1 << 1) |
| 75 | #define STATUS_FUSE_CPU_CPU1_GET(val) ((((val) & STATUS_FUSE_CPU_CPU1) >> 1) & 0x1) |
| 76 | /* Fuse for Enabling the CPU0 (0) */ |
| 77 | #define STATUS_FUSE_CPU_CPU0 (0x1) |
| 78 | #define STATUS_FUSE_CPU_CPU0_GET(val) ((((val) & STATUS_FUSE_CPU_CPU0) >> 0) & 0x1) |
| 79 | |
| 80 | /******************************************************************************* |
| 81 | * Fuse for PLL Settings |
| 82 | ******************************************************************************/ |
| 83 | |
| 84 | /* Fuse for Enabling PLL (7:0) */ |
| 85 | #define STATUS_FUSE_PLL_PLL (0xff) |
| 86 | #define STATUS_FUSE_PLL_PLL_GET(val) ((((val) & STATUS_FUSE_PLL_PLL) >> 0) & 0xff) |
| 87 | |
| 88 | /******************************************************************************* |
| 89 | * Chip Identification Register |
| 90 | ******************************************************************************/ |
| 91 | |
| 92 | /* Chip Version Number (31:28) */ |
| 93 | #define STATUS_CHIPID_VERSION (0xf << 28) |
| 94 | #define STATUS_CHIPID_VERSION_GET(val) ((((val) & STATUS_CHIPID_VERSION) >> 28) & 0xf) |
| 95 | /* Part Number (27:12) */ |
| 96 | #define STATUS_CHIPID_PART_NUMBER (0xffff << 12) |
| 97 | #define STATUS_CHIPID_PART_NUMBER_GET(val) ((((val) & STATUS_CHIPID_PART_NUMBER) >> 12) & 0xffff) |
| 98 | /* Manufacturer ID (11:1) */ |
| 99 | #define STATUS_CHIPID_MANID (0x7ff << 1) |
| 100 | #define STATUS_CHIPID_MANID_GET(val) ((((val) & STATUS_CHIPID_MANID) >> 1) & 0x7ff) |
| 101 | |
| 102 | /******************************************************************************* |
| 103 | * Chip Configuration Register |
| 104 | ******************************************************************************/ |
| 105 | |
| 106 | /* Number of Analog Channels (8:5) */ |
| 107 | #define STATUS_CONFIG_ANA_CHAN (0xf << 5) |
| 108 | #define STATUS_CONFIG_ANA_CHAN_GET(val) ((((val) & STATUS_CONFIG_ANA_CHAN) >> 5) & 0xf) |
| 109 | /* Clock Mode (4) */ |
| 110 | #define STATUS_CONFIG_CLK_MODE (0x1 << 1) |
| 111 | #define STATUS_CONFIG_CLK_MODE_GET(val) ((((val) & STATUS_CONFIG_CLK_MODE) >> 4) & 0x1) |
| 112 | /* Subversion Number (3:0) */ |
| 113 | #define STATUS_CONFIG_SUB_VERS (0xF) |
| 114 | #define STATUS_CONFIG_SUB_VERS_GET(val) ((((val) & STATUS_SUBVER_SUB_VERS) >> 0) & 0xF) |
| 115 | |
| 116 | /******************************************************************************* |
| 117 | * Chip Location Register |
| 118 | ******************************************************************************/ |
| 119 | |
| 120 | /* Chip Lot ID (31:16) */ |
| 121 | #define STATUS_CHIP_LOC_CHIP_LOT (0xffff << 16) |
| 122 | #define STATUS_CHIP_LOC_CHIP_LOT_GET(val) ((((val) & STATUS_CHIP_LOC_CHIP_LOT) >> 16) & 0xffff) |
| 123 | /* Chip X Coordinate (15:8) */ |
| 124 | #define STATUS_CHIP_LOC_CHIP_X (0xff << 8) |
| 125 | #define STATUS_CHIP_LOC_CHIP_X_GET(val) ((((val) & STATUS_CHIP_LOC_CHIP_X) >> 8) & 0xff) |
| 126 | /* Chip Y Coordinate (7:0) */ |
| 127 | #define STATUS_CHIP_LOC_CHIP_Y (0xff) |
| 128 | #define STATUS_CHIP_LOC_CHIP_Y_GET(val) ((((val) & STATUS_CHIP_LOC_CHIP_Y) >> 0) & 0xff) |
| 129 | |
| 130 | #endif |
| 131 | |