Root/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys0_reg.h

1/******************************************************************************
2
3  Copyright (c) 2007
4  Infineon Technologies AG
5  St. Martin Strasse 53; 81669 Munich, Germany
6
7  Any use of this Software is subject to the conclusion of a respective
8  License Agreement. Without such a License Agreement no rights to the
9  Software are granted.
10
11 ******************************************************************************/
12
13#ifndef __SYS0_REG_H
14#define __SYS0_REG_H
15
16#define sys0_r32(reg) ltq_r32(&sys0->reg)
17#define sys0_w32(val, reg) ltq_w32(val, &sys0->reg)
18#define sys0_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &sys0->reg)
19
20/** SYS0 register structure */
21struct svip_reg_sys0 {
22    unsigned long sr; /* 0x0000 */
23    unsigned long bcr; /* 0x0004 */
24    unsigned long pll1cr; /* 0x0008 */
25    unsigned long pll2cr; /* 0x000c */
26    unsigned long tscr; /* 0x0010 */
27    unsigned long phyclkr; /* 0x0014 */
28};
29
30/*******************************************************************************
31 * SYS0 Status Register
32 ******************************************************************************/
33
34/* Endian select pin (31) */
35#define SYS0_SR_ESEL (0x1 << 31)
36#define SYS0_SR_ESEL_GET(val) ((((val) & SYS0_SR_ESEL) >> 31) & 0x1)
37/* Boot mode pins (27:24) */
38#define SYS0_SR_BMODE (0xf << 24)
39#define SYS0_SR_BMODE_GET(val) ((((val) & SYS0_SR_BMODE) >> 24) & 0xf)
40/* PLL2 Lock (18) */
41#define SYS0_SR_PLL2LOCK (0x1 << 18)
42#define SYS0_SR_PLL2LOCK_GET(val) ((((val) & SYS0_SR_PLL2LOCK) >> 18) & 0x1)
43/* PLL1 Lock (17) */
44#define SYS0_SR_PLL1LOCK (0x1 << 17)
45#define SYS0_SR_PLL1LOCK_GET(val) ((((val) & SYS0_SR_PLL1LOCK) >> 17) & 0x1)
46/* Discrete Timing Oscillator Lock (16) */
47#define SYS0_SR_DTOLOCK (0x1 << 16)
48#define SYS0_SR_DTOLOCK_GET(val) ((((val) & SYS0_SR_DTOLOCK) >> 16) & 0x1)
49/* Hardware Reset Indication (1) */
50#define SYS0_SR_HRSTIN (0x1 << 1)
51#define SYS0_SR_HRSTIN_VAL(val) (((val) & 0x1) << 1)
52#define SYS0_SR_HRSTIN_GET(val) ((((val) & SYS0_SR_HRSTIN) >> 1) & 0x1)
53#define SYS0_SR_HRSTIN_SET(reg,val) (reg) = ((reg & ~SYS0_SR_HRSTIN) | (((val) & 0x1) << 1))
54/* Power-on Reset Indication (0) */
55#define SYS0_SR_POR (0x1 << 0)
56#define SYS0_SR_POR_VAL(val) (((val) & 0x1) << 0)
57#define SYS0_SR_POR_GET(val) ((((val) & SYS0_SR_POR) >> 0) & 0x1)
58#define SYS0_SR_POR_SET(reg,val) (reg) = ((reg & ~SYS0_SR_POR) | (((val) & 0x1) << 0))
59
60/*******************************************************************************
61 * SYS0 Boot Control Register
62 ******************************************************************************/
63
64/* Configuration of Boot Source for CPU5 (25) */
65#define SYS0_BCR_BMODECPU5 (0x1 << 25)
66#define SYS0_BCR_BMODECPU5_VAL(val) (((val) & 0x1) << 25)
67#define SYS0_BCR_BMODECPU5_GET(val) ((((val) & SYS0_BCR_BMODECPU5) >> 25) & 0x1)
68#define SYS0_BCR_BMODECPU5_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU5) | (((val) & 0x1) << 25))
69/* Configuration of Boot Source for CPU4 (24) */
70#define SYS0_BCR_BMODECPU4 (0x1 << 24)
71#define SYS0_BCR_BMODECPU4_VAL(val) (((val) & 0x1) << 24)
72#define SYS0_BCR_BMODECPU4_GET(val) ((((val) & SYS0_BCR_BMODECPU4) >> 24) & 0x1)
73#define SYS0_BCR_BMODECPU4_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU4) | (((val) & 0x1) << 24))
74/* Configuration of Boot Source for CPU3 (23) */
75#define SYS0_BCR_BMODECPU3 (0x1 << 23)
76#define SYS0_BCR_BMODECPU3_VAL(val) (((val) & 0x1) << 23)
77#define SYS0_BCR_BMODECPU3_GET(val) ((((val) & SYS0_BCR_BMODECPU3) >> 23) & 0x1)
78#define SYS0_BCR_BMODECPU3_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU3) | (((val) & 0x1) << 23))
79/* Configuration of Boot Source for CPU2 (22) */
80#define SYS0_BCR_BMODECPU2 (0x1 << 22)
81#define SYS0_BCR_BMODECPU2_VAL(val) (((val) & 0x1) << 22)
82#define SYS0_BCR_BMODECPU2_GET(val) ((((val) & SYS0_BCR_BMODECPU2) >> 22) & 0x1)
83#define SYS0_BCR_BMODECPU2_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU2) | (((val) & 0x1) << 22))
84/* Configuration of Boot Source for CPU1 (21) */
85#define SYS0_BCR_BMODECPU1 (0x1 << 21)
86#define SYS0_BCR_BMODECPU1_VAL(val) (((val) & 0x1) << 21)
87#define SYS0_BCR_BMODECPU1_GET(val) ((((val) & SYS0_BCR_BMODECPU1) >> 21) & 0x1)
88#define SYS0_BCR_BMODECPU1_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU1) | (((val) & 0x1) << 21))
89/* Configuration of Boot Source for CPU0 (20:16) */
90#define SYS0_BCR_BMODECPU0 (0x1f << 16)
91#define SYS0_BCR_BMODECPU0_VAL(val) (((val) & 0x1f) << 16)
92#define SYS0_BCR_BMODECPU0_GET(val) ((((val) & SYS0_BCR_BMODECPU0) >> 16) & 0x1f)
93#define SYS0_BCR_BMODECPU0_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU0) | (((val) & 0x1f) << 16))
94/* Configuration of Endianess for CPU5 (5) */
95#define SYS0_BCR_ESELCPU5 (0x1 << 5)
96#define SYS0_BCR_ESELCPU5_VAL(val) (((val) & 0x1) << 5)
97#define SYS0_BCR_ESELCPU5_GET(val) ((((val) & SYS0_BCR_ESELCPU5) >> 5) & 0x1)
98#define SYS0_BCR_ESELCPU5_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU5) | (((val) & 0x1) << 5))
99/* Configuration of Endianess for CPU4 (4) */
100#define SYS0_BCR_ESELCPU4 (0x1 << 4)
101#define SYS0_BCR_ESELCPU4_VAL(val) (((val) & 0x1) << 4)
102#define SYS0_BCR_ESELCPU4_GET(val) ((((val) & SYS0_BCR_ESELCPU4) >> 4) & 0x1)
103#define SYS0_BCR_ESELCPU4_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU4) | (((val) & 0x1) << 4))
104/* Configuration of Endianess for CPU3 (3) */
105#define SYS0_BCR_ESELCPU3 (0x1 << 3)
106#define SYS0_BCR_ESELCPU3_VAL(val) (((val) & 0x1) << 3)
107#define SYS0_BCR_ESELCPU3_GET(val) ((((val) & SYS0_BCR_ESELCPU3) >> 3) & 0x1)
108#define SYS0_BCR_ESELCPU3_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU3) | (((val) & 0x1) << 3))
109/* Configuration of Endianess for CPU2 (2) */
110#define SYS0_BCR_ESELCPU2 (0x1 << 2)
111#define SYS0_BCR_ESELCPU2_VAL(val) (((val) & 0x1) << 2)
112#define SYS0_BCR_ESELCPU2_GET(val) ((((val) & SYS0_BCR_ESELCPU2) >> 2) & 0x1)
113#define SYS0_BCR_ESELCPU2_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU2) | (((val) & 0x1) << 2))
114/* Configuration of Endianess for CPU1 (1) */
115#define SYS0_BCR_ESELCPU1 (0x1 << 1)
116#define SYS0_BCR_ESELCPU1_VAL(val) (((val) & 0x1) << 1)
117#define SYS0_BCR_ESELCPU1_GET(val) ((((val) & SYS0_BCR_ESELCPU1) >> 1) & 0x1)
118#define SYS0_BCR_ESELCPU1_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU1) | (((val) & 0x1) << 1))
119/* Configuration of Endianess for CPU0 (0) */
120#define SYS0_BCR_ESELCPU0 (0x1)
121#define SYS0_BCR_ESELCPU0_VAL(val) (((val) & 0x1) << 0)
122#define SYS0_BCR_ESELCPU0_GET(val) ((((val) & SYS0_BCR_ESELCPU0) >> 0) & 0x1)
123#define SYS0_BCR_ESELCPU0_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU0) | (((val) & 0x1) << 0))
124
125/*******************************************************************************
126 * PLL1 Control Register
127 ******************************************************************************/
128
129/* PLL1 Bypass Enable (31) */
130#define SYS0_PLL1CR_OSCBYP (0x1 << 31)
131#define SYS0_PLL1CR_OSCBYP_VAL(val) (((val) & 0x1) << 31)
132#define SYS0_PLL1CR_OSCBYP_GET(val) ((((val) & SYS0_PLL1CR_OSCBYP) >> 31) & 0x1)
133#define SYS0_PLL1CR_OSCBYP_SET(reg,val) (reg) = ((reg & ~SYS0_PLL1CR_OSCBYP) | (((val) & 0x1) << 31))
134/* PLL1 Divider Value (1:0) */
135#define SYS0_PLL1CR_PLLDIV (0x3)
136#define SYS0_PLL1CR_PLLDIV_VAL(val) (((val) & 0x3) << 0)
137#define SYS0_PLL1CR_PLLDIV_GET(val) ((((val) & SYS0_PLL1CR_PLLDIV) >> 0) & 0x3)
138#define SYS0_PLL1CR_PLLDIV_SET(reg,val) (reg) = ((reg & ~SYS0_PLL1CR_PLLDIV) | (((val) & 0x3) << 0))
139
140/*******************************************************************************
141 * PLL2 Control Register
142 ******************************************************************************/
143
144/* PLL2 clear deepsleep (31) */
145#define SYS0_PLL2CR_CLRDS (0x1 << 31)
146#define SYS0_PLL2CR_CLRDS_VAL(val) (((val) & 0x1) << 31)
147#define SYS0_PLL2CR_CLRDS_GET(val) ((((val) & SYS0_PLL2CR_CLRDS) >> 31) & 0x1)
148#define SYS0_PLL2CR_CLRDS_SET(reg,val) (reg) = ((reg & ~SYS0_PLL2CR_CLRDS) | (((val) & 0x1) << 31))
149/* PLL2 set deepsleep (30) */
150#define SYS0_PLL2CR_SETDS (0x1 << 30)
151#define SYS0_PLL2CR_SETDS_VAL(val) (((val) & 0x1) << 30)
152#define SYS0_PLL2CR_SETDS_GET(val) ((((val) & SYS0_PLL2CR_SETDS) >> 30) & 0x1)
153#define SYS0_PLL2CR_SETDS_SET(reg,val) (reg) = ((reg & ~SYS0_PLL2CR_SETDS) | (((val) & 0x1) << 30))
154/* PLL2 Fractional division enable (16) */
155#define SYS0_PLL2CR_FRACTEN (0x1 << 16)
156#define SYS0_PLL2CR_FRACTEN_VAL(val) (((val) & 0x1) << 16)
157#define SYS0_PLL2CR_FRACTEN_GET(val) ((((val) & SYS0_PLL2CR_FRACTEN) >> 16) & 0x1)
158#define SYS0_PLL2CR_FRACTEN_SET(reg,val) (reg) = ((reg & ~SYS0_PLL2CR_FRACTEN) | (((val) & 0x1) << 16))
159/* PLL2 Fractional division value (9:0) */
160#define SYS0_FRACTVAL (0x3f)
161#define SYS0_FRACTVAL_VAL(val) (((val) & 0x3f) << 0)
162#define SYS0_FRACTVAL_GET(val) ((((val) & SYS0_FRACTVAL) >> 0) & 0x3f)
163#define SYS0_FRACTVAL_SET(reg,val) (reg) = ((reg & ~SYS0_FRACTVAL) | (((val) & 0x3f) << 0))
164
165#endif
166

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