| 1 | /****************************************************************************** |
| 2 | |
| 3 | Copyright (c) 2007 |
| 4 | Infineon Technologies AG |
| 5 | St. Martin Strasse 53; 81669 Munich, Germany |
| 6 | |
| 7 | Any use of this Software is subject to the conclusion of a respective |
| 8 | License Agreement. Without such a License Agreement no rights to the |
| 9 | Software are granted. |
| 10 | |
| 11 | ******************************************************************************/ |
| 12 | |
| 13 | #ifndef __SYS1_REG_H |
| 14 | #define __SYS1_REG_H |
| 15 | |
| 16 | #define sys1_r32(reg) ltq_r32(&sys1->reg) |
| 17 | #define sys1_w32(val, reg) ltq_w32(val, &sys1->reg) |
| 18 | #define sys1_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &sys1->reg) |
| 19 | |
| 20 | /** SYS1 register structure */ |
| 21 | struct svip_reg_sys1 { |
| 22 | unsigned long clksr; /* 0x0000 */ |
| 23 | unsigned long clkenr; /* 0x0004 */ |
| 24 | unsigned long clkclr; /* 0x0008 */ |
| 25 | unsigned long reserved0[1]; |
| 26 | unsigned long l2ccr; /* 0x0010 */ |
| 27 | unsigned long fpicr; /* 0x0014 */ |
| 28 | unsigned long wdtcr; /* 0x0018 */ |
| 29 | unsigned long reserved1[1]; |
| 30 | unsigned long cpucr[6]; /* 0x0020 */ |
| 31 | unsigned long reserved2[2]; |
| 32 | unsigned long rsr; /* 0x0040 */ |
| 33 | unsigned long rreqr; /* 0x0044 */ |
| 34 | unsigned long rrlsr; /* 0x0048 */ |
| 35 | unsigned long rbtr; /* 0x004c */ |
| 36 | unsigned long irncr; /* 0x0050 */ |
| 37 | unsigned long irnicr; /* 0x0054 */ |
| 38 | unsigned long irnen; /* 0x0058 */ |
| 39 | unsigned long reserved3[1]; |
| 40 | unsigned long cpursr[6]; /* 0x0060 */ |
| 41 | unsigned long reserved4[2]; |
| 42 | unsigned long cpusrssr[6]; /* 0x0080 */ |
| 43 | unsigned long reserved5[2]; |
| 44 | unsigned long cpuwrssr[6]; /* 0x00a0 */ |
| 45 | }; |
| 46 | |
| 47 | /******************************************************************************* |
| 48 | * SYS1 Clock Status Register |
| 49 | ******************************************************************************/ |
| 50 | /* (r) Clock Enable for L2C */ |
| 51 | #define SYS1_CLKSR_L2C (0x1 << 31) |
| 52 | /* (r) Clock Enable for DDR2 */ |
| 53 | #define SYS1_CLKSR_DDR2 (0x1 << 30) |
| 54 | /* (r) Clock Enable for SMI2 */ |
| 55 | #define SYS1_CLKSR_SMI2 (0x1 << 29) |
| 56 | /* (r) Clock Enable for SMI1 */ |
| 57 | #define SYS1_CLKSR_SMI1 (0x1 << 28) |
| 58 | /* (r) Clock Enable for SMI0 */ |
| 59 | #define SYS1_CLKSR_SMI0 (0x1 << 27) |
| 60 | /* (r) Clock Enable for FMI0 */ |
| 61 | #define SYS1_CLKSR_FMI0 (0x1 << 26) |
| 62 | /* (r) Clock Enable for PORT0 */ |
| 63 | #define SYS1_CLKSR_PORT0 (0x1 << 0) |
| 64 | /* (r) Clock Enable for PCM3 */ |
| 65 | #define SYS1_CLKSR_PCM3 (0x1 << 19) |
| 66 | /* (r) Clock Enable for PCM2 */ |
| 67 | #define SYS1_CLKSR_PCM2 (0x1 << 18) |
| 68 | /* (r) Clock Enable for PCM1 */ |
| 69 | #define SYS1_CLKSR_PCM1 (0x1 << 17) |
| 70 | /* (r) Clock Enable for PCM0 */ |
| 71 | #define SYS1_CLKSR_PCM0 (0x1 << 16) |
| 72 | /* (r) Clock Enable for ASC1 */ |
| 73 | #define SYS1_CLKSR_ASC1 (0x1 << 15) |
| 74 | /* (r) Clock Enable for ASC0 */ |
| 75 | #define SYS1_CLKSR_ASC0 (0x1 << 14) |
| 76 | /* (r) Clock Enable for SSC2 */ |
| 77 | #define SYS1_CLKSR_SSC2 (0x1 << 13) |
| 78 | /* (r) Clock Enable for SSC1 */ |
| 79 | #define SYS1_CLKSR_SSC1 (0x1 << 12) |
| 80 | /* (r) Clock Enable for SSC0 */ |
| 81 | #define SYS1_CLKSR_SSC0 (0x1 << 11) |
| 82 | /* (r) Clock Enable for GPTC */ |
| 83 | #define SYS1_CLKSR_GPTC (0x1 << 10) |
| 84 | /* (r) Clock Enable for DMA */ |
| 85 | #define SYS1_CLKSR_DMA (0x1 << 9) |
| 86 | /* (r) Clock Enable for FSCT */ |
| 87 | #define SYS1_CLKSR_FSCT (0x1 << 8) |
| 88 | /* (r) Clock Enable for ETHSW */ |
| 89 | #define SYS1_CLKSR_ETHSW (0x1 << 7) |
| 90 | /* (r) Clock Enable for EBU */ |
| 91 | #define SYS1_CLKSR_EBU (0x1 << 6) |
| 92 | /* (r) Clock Enable for TRNG */ |
| 93 | #define SYS1_CLKSR_TRNG (0x1 << 5) |
| 94 | /* (r) Clock Enable for DEU */ |
| 95 | #define SYS1_CLKSR_DEU (0x1 << 4) |
| 96 | /* (r) Clock Enable for PORT3 */ |
| 97 | #define SYS1_CLKSR_PORT3 (0x1 << 3) |
| 98 | /* (r) Clock Enable for PORT2 */ |
| 99 | #define SYS1_CLKSR_PORT2 (0x1 << 2) |
| 100 | /* (r) Clock Enable for PORT1 */ |
| 101 | #define SYS1_CLKSR_PORT1 (0x1 << 1) |
| 102 | |
| 103 | /******************************************************************************* |
| 104 | * SYS1 Clock Enable Register |
| 105 | ******************************************************************************/ |
| 106 | /* (w) Clock Enable Request for L2C */ |
| 107 | #define SYS1_CLKENR_L2C (0x1 << 31) |
| 108 | /* (w) Clock Enable Request for DDR2 */ |
| 109 | #define SYS1_CLKENR_DDR2 (0x1 << 30) |
| 110 | /* (w) Clock Enable Request for SMI2 */ |
| 111 | #define SYS1_CLKENR_SMI2 (0x1 << 29) |
| 112 | /* (w) Clock Enable Request for SMI1 */ |
| 113 | #define SYS1_CLKENR_SMI1 (0x1 << 28) |
| 114 | /* (w) Clock Enable Request for SMI0 */ |
| 115 | #define SYS1_CLKENR_SMI0 (0x1 << 27) |
| 116 | /* (w) Clock Enable Request for FMI0 */ |
| 117 | #define SYS1_CLKENR_FMI0 (0x1 << 26) |
| 118 | /* (w) Clock Enable Request for PORT0 */ |
| 119 | #define SYS1_CLKENR_PORT0 (0x1 << 0) |
| 120 | /* (w) Clock Enable Request for PCM3 */ |
| 121 | #define SYS1_CLKENR_PCM3 (0x1 << 19) |
| 122 | /* (w) Clock Enable Request for PCM2 */ |
| 123 | #define SYS1_CLKENR_PCM2 (0x1 << 18) |
| 124 | /* (w) Clock Enable Request for PCM1 */ |
| 125 | #define SYS1_CLKENR_PCM1 (0x1 << 17) |
| 126 | /* (w) Clock Enable Request for PCM0 */ |
| 127 | #define SYS1_CLKENR_PCM0 (0x1 << 16) |
| 128 | /* (w) Clock Enable Request for ASC1 */ |
| 129 | #define SYS1_CLKENR_ASC1 (0x1 << 15) |
| 130 | /* (w) Clock Enable Request for ASC0 */ |
| 131 | #define SYS1_CLKENR_ASC0 (0x1 << 14) |
| 132 | /* (w) Clock Enable Request for SSC2 */ |
| 133 | #define SYS1_CLKENR_SSC2 (0x1 << 13) |
| 134 | /* (w) Clock Enable Request for SSC1 */ |
| 135 | #define SYS1_CLKENR_SSC1 (0x1 << 12) |
| 136 | /* (w) Clock Enable Request for SSC0 */ |
| 137 | #define SYS1_CLKENR_SSC0 (0x1 << 11) |
| 138 | /* (w) Clock Enable Request for GPTC */ |
| 139 | #define SYS1_CLKENR_GPTC (0x1 << 10) |
| 140 | /* (w) Clock Enable Request for DMA */ |
| 141 | #define SYS1_CLKENR_DMA (0x1 << 9) |
| 142 | /* (w) Clock Enable Request for FSCT */ |
| 143 | #define SYS1_CLKENR_FSCT (0x1 << 8) |
| 144 | /* (w) Clock Enable Request for ETHSW */ |
| 145 | #define SYS1_CLKENR_ETHSW (0x1 << 7) |
| 146 | /* (w) Clock Enable Request for EBU */ |
| 147 | #define SYS1_CLKENR_EBU (0x1 << 6) |
| 148 | /* (w) Clock Enable Request for TRNG */ |
| 149 | #define SYS1_CLKENR_TRNG (0x1 << 5) |
| 150 | /* (w) Clock Enable Request for DEU */ |
| 151 | #define SYS1_CLKENR_DEU (0x1 << 4) |
| 152 | /* (w) Clock Enable Request for PORT3 */ |
| 153 | #define SYS1_CLKENR_PORT3 (0x1 << 3) |
| 154 | /* (w) Clock Enable Request for PORT2 */ |
| 155 | #define SYS1_CLKENR_PORT2 (0x1 << 2) |
| 156 | /* (w) Clock Enable Request for PORT1 */ |
| 157 | #define SYS1_CLKENR_PORT1 (0x1 << 1) |
| 158 | |
| 159 | /******************************************************************************* |
| 160 | * SYS1 Clock Clear Register |
| 161 | ******************************************************************************/ |
| 162 | /* (w) Clock Disable Request for L2C */ |
| 163 | #define SYS1_CLKCLR_L2C (0x1 << 31) |
| 164 | /* (w) Clock Disable Request for DDR2 */ |
| 165 | #define SYS1_CLKCLR_DDR2 (0x1 << 30) |
| 166 | /* (w) Clock Disable Request for SMI2 */ |
| 167 | #define SYS1_CLKCLR_SMI2 (0x1 << 29) |
| 168 | /* (w) Clock Disable Request for SMI1 */ |
| 169 | #define SYS1_CLKCLR_SMI1 (0x1 << 28) |
| 170 | /* (w) Clock Disable Request for SMI0 */ |
| 171 | #define SYS1_CLKCLR_SMI0 (0x1 << 27) |
| 172 | /* (w) Clock Disable Request for FMI0 */ |
| 173 | #define SYS1_CLKCLR_FMI0 (0x1 << 26) |
| 174 | /* (w) Clock Disable Request for PORT0 */ |
| 175 | #define SYS1_CLKCLR_PORT0 (0x1 << 0) |
| 176 | /* (w) Clock Disable Request for PCM3 */ |
| 177 | #define SYS1_CLKCLR_PCM3 (0x1 << 19) |
| 178 | /* (w) Clock Disable Request for PCM2 */ |
| 179 | #define SYS1_CLKCLR_PCM2 (0x1 << 18) |
| 180 | /* (w) Clock Disable Request for PCM1 */ |
| 181 | #define SYS1_CLKCLR_PCM1 (0x1 << 17) |
| 182 | /* (w) Clock Disable Request for PCM0 */ |
| 183 | #define SYS1_CLKCLR_PCM0 (0x1 << 16) |
| 184 | /* (w) Clock Disable Request for ASC1 */ |
| 185 | #define SYS1_CLKCLR_ASC1 (0x1 << 15) |
| 186 | /* (w) Clock Disable Request for ASC0 */ |
| 187 | #define SYS1_CLKCLR_ASC0 (0x1 << 14) |
| 188 | /* (w) Clock Disable Request for SSC2 */ |
| 189 | #define SYS1_CLKCLR_SSC2 (0x1 << 13) |
| 190 | /* (w) Clock Disable Request for SSC1 */ |
| 191 | #define SYS1_CLKCLR_SSC1 (0x1 << 12) |
| 192 | /* (w) Clock Disable Request for SSC0 */ |
| 193 | #define SYS1_CLKCLR_SSC0 (0x1 << 11) |
| 194 | /* (w) Clock Disable Request for GPTC */ |
| 195 | #define SYS1_CLKCLR_GPTC (0x1 << 10) |
| 196 | /* (w) Clock Disable Request for DMA */ |
| 197 | #define SYS1_CLKCLR_DMA (0x1 << 9) |
| 198 | /* (w) Clock Disable Request for FSCT */ |
| 199 | #define SYS1_CLKCLR_FSCT (0x1 << 8) |
| 200 | /* (w) Clock Disable Request for ETHSW */ |
| 201 | #define SYS1_CLKCLR_ETHSW (0x1 << 7) |
| 202 | /* (w) Clock Disable Request for EBU */ |
| 203 | #define SYS1_CLKCLR_EBU (0x1 << 6) |
| 204 | /* (w) Clock Disable Request for TRNG */ |
| 205 | #define SYS1_CLKCLR_TRNG (0x1 << 5) |
| 206 | /* (w) Clock Disable Request for DEU */ |
| 207 | #define SYS1_CLKCLR_DEU (0x1 << 4) |
| 208 | /* (w) Clock Disable Request for PORT3 */ |
| 209 | #define SYS1_CLKCLR_PORT3 (0x1 << 3) |
| 210 | /* (w) Clock Disable Request for PORT2 */ |
| 211 | #define SYS1_CLKCLR_PORT2 (0x1 << 2) |
| 212 | /* (w) Clock Disable Request for PORT1 */ |
| 213 | #define SYS1_CLKCLR_PORT1 (0x1 << 1) |
| 214 | |
| 215 | /******************************************************************************* |
| 216 | * SYS1 FPI Control Register |
| 217 | ******************************************************************************/ |
| 218 | |
| 219 | /* FPI Bus Clock divider (0) */ |
| 220 | #define SYS1_FPICR_FPIDIV (0x1) |
| 221 | #define SYS1_FPICR_FPIDIV_VAL(val) (((val) & 0x1) << 0) |
| 222 | #define SYS1_FPICR_FPIDIV_GET(val) ((((val) & SYS1_FPICR_FPIDIV) >> 0) & 0x1) |
| 223 | #define SYS1_FPICR_FPIDIV_SET(reg,val) (reg) = ((reg & ~SYS1_FPICR_FPIDIV) | (((val) & 0x1) << 0)) |
| 224 | |
| 225 | /******************************************************************************* |
| 226 | * SYS1 Clock Control Register for CPUn |
| 227 | ******************************************************************************/ |
| 228 | |
| 229 | /* Enable bit for clock of CPUn (1) */ |
| 230 | #define SYS1_CPUCR_CPUCLKEN (0x1 << 1) |
| 231 | #define SYS1_CPUCR_CPUCLKEN_VAL(val) (((val) & 0x1) << 1) |
| 232 | #define SYS1_CPUCR_CPUCLKEN_GET(val) ((((val) & SYS1_CPUCR_CPUCLKEN) >> 1) & 0x1) |
| 233 | #define SYS1_CPUCR_CPUCLKEN_SET(reg,val) (reg) = ((reg & ~SYS1_CPUCR_CPUCLKEN) | (((val) & 0x1) << 1)) |
| 234 | /* Divider factor for clock of CPUn (0) */ |
| 235 | #define SYS1_CPUCR_CPUDIV (0x1) |
| 236 | #define SYS1_CPUCR_CPUDIV_VAL(val) (((val) & 0x1) << 0) |
| 237 | #define SYS1_CPUCR_CPUDIV_GET(val) ((((val) & SYS1_CPUCR_CPUDIV) >> 0) & 0x1) |
| 238 | #define SYS1_CPUCR_CPUDIV_SET(reg,val) (reg) = ((reg & ~SYS1_CPUCR_CPUDIV) | (((val) & 0x1) << 0)) |
| 239 | |
| 240 | /******************************************************************************* |
| 241 | * SYS1 Reset Request Register |
| 242 | ******************************************************************************/ |
| 243 | |
| 244 | /* HRSTOUT Reset Request (18) */ |
| 245 | #define SYS1_RREQ_HRSTOUT (0x1 << 18) |
| 246 | #define SYS1_RREQ_HRSTOUT_VAL(val) (((val) & 0x1) << 18) |
| 247 | #define SYS1_RREQ_HRSTOUT_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_HRSTOUT) | (((val) & 1) << 18)) |
| 248 | /* FBS0 Reset Request (17) */ |
| 249 | #define SYS1_RREQ_FBS0 (0x1 << 17) |
| 250 | #define SYS1_RREQ_FBS0_VAL(val) (((val) & 0x1) << 17) |
| 251 | #define SYS1_RREQ_FBS0_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_FBS0) | (((val) & 1) << 17)) |
| 252 | /* SUBSYS Reset Request (16) */ |
| 253 | #define SYS1_RREQ_SUBSYS (0x1 << 16) |
| 254 | #define SYS1_RREQ_SUBSYS_VAL(val) (((val) & 0x1) << 16) |
| 255 | #define SYS1_RREQ_SUBSYS_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_SUBSYS) | (((val) & 1) << 16)) |
| 256 | /* Watchdog5 Reset Request (13) */ |
| 257 | #define SYS1_RREQ_WDT5 (0x1 << 13) |
| 258 | #define SYS1_RREQ_WDT5_VAL(val) (((val) & 0x1) << 13) |
| 259 | #define SYS1_RREQ_WDT5_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT5) | (((val) & 1) << 13)) |
| 260 | /* Watchdog4 Reset Request (12) */ |
| 261 | #define SYS1_RREQ_WDT4 (0x1 << 12) |
| 262 | #define SYS1_RREQ_WDT4_VAL(val) (((val) & 0x1) << 12) |
| 263 | #define SYS1_RREQ_WDT4_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT4) | (((val) & 1) << 12)) |
| 264 | /* Watchdog3 Reset Request (11) */ |
| 265 | #define SYS1_RREQ_WDT3 (0x1 << 11) |
| 266 | #define SYS1_RREQ_WDT3_VAL(val) (((val) & 0x1) << 11) |
| 267 | #define SYS1_RREQ_WDT3_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT3) | (((val) & 1) << 11)) |
| 268 | /* Watchdog2 Reset Request (10) */ |
| 269 | #define SYS1_RREQ_WDT2 (0x1 << 10) |
| 270 | #define SYS1_RREQ_WDT2_VAL(val) (((val) & 0x1) << 10) |
| 271 | #define SYS1_RREQ_WDT2_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT2) | (((val) & 1) << 10)) |
| 272 | /* Watchdog1 Reset Request (9) */ |
| 273 | #define SYS1_RREQ_WDT1 (0x1 << 9) |
| 274 | #define SYS1_RREQ_WDT1_VAL(val) (((val) & 0x1) << 9) |
| 275 | #define SYS1_RREQ_WDT1_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT1) | (((val) & 1) << 9)) |
| 276 | /* Watchdog0 Reset Request (8) */ |
| 277 | #define SYS1_RREQ_WDT0 (0x1 << 8) |
| 278 | #define SYS1_RREQ_WDT0_VAL(val) (((val) & 0x1) << 8) |
| 279 | #define SYS1_RREQ_WDT0_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT0) | (((val) & 1) << 8)) |
| 280 | /* CPU5 Reset Request (5) */ |
| 281 | #define SYS1_RREQ_CPU5 (0x1 << 5) |
| 282 | #define SYS1_RREQ_CPU5_VAL(val) (((val) & 0x1) << 5) |
| 283 | #define SYS1_RREQ_CPU5_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU5) | (((val) & 1) << 5)) |
| 284 | /* CPU4 Reset Request (4) */ |
| 285 | #define SYS1_RREQ_CPU4 (0x1 << 4) |
| 286 | #define SYS1_RREQ_CPU4_VAL(val) (((val) & 0x1) << 4) |
| 287 | #define SYS1_RREQ_CPU4_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU4) | (((val) & 1) << 4)) |
| 288 | /* CPU3 Reset Request (3) */ |
| 289 | #define SYS1_RREQ_CPU3 (0x1 << 3) |
| 290 | #define SYS1_RREQ_CPU3_VAL(val) (((val) & 0x1) << 3) |
| 291 | #define SYS1_RREQ_CPU3_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU3) | (((val) & 1) << 3)) |
| 292 | /* CPU2 Reset Request (2) */ |
| 293 | #define SYS1_RREQ_CPU2 (0x1 << 2) |
| 294 | #define SYS1_RREQ_CPU2_VAL(val) (((val) & 0x1) << 2) |
| 295 | #define SYS1_RREQ_CPU2_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU2) | (((val) & 1) << 2)) |
| 296 | /* CPU1 Reset Request (1) */ |
| 297 | #define SYS1_RREQ_CPU1 (0x1 << 1) |
| 298 | #define SYS1_RREQ_CPU1_VAL(val) (((val) & 0x1) << 1) |
| 299 | #define SYS1_RREQ_CPU1_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU1) | (((val) & 1) << 1)) |
| 300 | /* CPU0 Reset Request (0) */ |
| 301 | #define SYS1_RREQ_CPU0 (0x1) |
| 302 | #define SYS1_RREQ_CPU0_VAL(val) (((val) & 0x1) << 0) |
| 303 | #define SYS1_RREQ_CPU0_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU0) | (((val) & 1) << 0)) |
| 304 | |
| 305 | /******************************************************************************* |
| 306 | * SYS1 Reset Release Register |
| 307 | ******************************************************************************/ |
| 308 | |
| 309 | /* HRSTOUT Reset Release (18) */ |
| 310 | #define SYS1_RRLSR_HRSTOUT (0x1 << 18) |
| 311 | #define SYS1_RRLSR_HRSTOUT_VAL(val) (((val) & 0x1) << 18) |
| 312 | #define SYS1_RRLSR_HRSTOUT_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_HRSTOUT) | (((val) & 1) << 18)) |
| 313 | /* FBS0 Reset Release (17) */ |
| 314 | #define SYS1_RRLSR_FBS0 (0x1 << 17) |
| 315 | #define SYS1_RRLSR_FBS0_VAL(val) (((val) & 0x1) << 17) |
| 316 | #define SYS1_RRLSR_FBS0_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_FBS0) | (((val) & 1) << 17)) |
| 317 | /* SUBSYS Reset Release (16) */ |
| 318 | #define SYS1_RRLSR_SUBSYS (0x1 << 16) |
| 319 | #define SYS1_RRLSR_SUBSYS_VAL(val) (((val) & 0x1) << 16) |
| 320 | #define SYS1_RRLSR_SUBSYS_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_SUBSYS) | (((val) & 1) << 16)) |
| 321 | /* Watchdog5 Reset Release (13) */ |
| 322 | #define SYS1_RRLSR_WDT5 (0x1 << 13) |
| 323 | #define SYS1_RRLSR_WDT5_VAL(val) (((val) & 0x1) << 13) |
| 324 | #define SYS1_RRLSR_WDT5_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT5) | (((val) & 1) << 13)) |
| 325 | /* Watchdog4 Reset Release (12) */ |
| 326 | #define SYS1_RRLSR_WDT4 (0x1 << 12) |
| 327 | #define SYS1_RRLSR_WDT4_VAL(val) (((val) & 0x1) << 12) |
| 328 | #define SYS1_RRLSR_WDT4_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT4) | (((val) & 1) << 12)) |
| 329 | /* Watchdog3 Reset Release (11) */ |
| 330 | #define SYS1_RRLSR_WDT3 (0x1 << 11) |
| 331 | #define SYS1_RRLSR_WDT3_VAL(val) (((val) & 0x1) << 11) |
| 332 | #define SYS1_RRLSR_WDT3_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT3) | (((val) & 1) << 11)) |
| 333 | /* Watchdog2 Reset Release (10) */ |
| 334 | #define SYS1_RRLSR_WDT2 (0x1 << 10) |
| 335 | #define SYS1_RRLSR_WDT2_VAL(val) (((val) & 0x1) << 10) |
| 336 | #define SYS1_RRLSR_WDT2_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT2) | (((val) & 1) << 10)) |
| 337 | /* Watchdog1 Reset Release (9) */ |
| 338 | #define SYS1_RRLSR_WDT1 (0x1 << 9) |
| 339 | #define SYS1_RRLSR_WDT1_VAL(val) (((val) & 0x1) << 9) |
| 340 | #define SYS1_RRLSR_WDT1_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT1) | (((val) & 1) << 9)) |
| 341 | /* Watchdog0 Reset Release (8) */ |
| 342 | #define SYS1_RRLSR_WDT0 (0x1 << 8) |
| 343 | #define SYS1_RRLSR_WDT0_VAL(val) (((val) & 0x1) << 8) |
| 344 | #define SYS1_RRLSR_WDT0_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT0) | (((val) & 1) << 8)) |
| 345 | /* CPU5 Reset Release (5) */ |
| 346 | #define SYS1_RRLSR_CPU5 (0x1 << 5) |
| 347 | #define SYS1_RRLSR_CPU5_VAL(val) (((val) & 0x1) << 5) |
| 348 | #define SYS1_RRLSR_CPU5_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU5) | (((val) & 1) << 5)) |
| 349 | /* CPU4 Reset Release (4) */ |
| 350 | #define SYS1_RRLSR_CPU4 (0x1 << 4) |
| 351 | #define SYS1_RRLSR_CPU4_VAL(val) (((val) & 0x1) << 4) |
| 352 | #define SYS1_RRLSR_CPU4_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU4) | (((val) & 1) << 4)) |
| 353 | /* CPU3 Reset Release (3) */ |
| 354 | #define SYS1_RRLSR_CPU3 (0x1 << 3) |
| 355 | #define SYS1_RRLSR_CPU3_VAL(val) (((val) & 0x1) << 3) |
| 356 | #define SYS1_RRLSR_CPU3_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU3) | (((val) & 1) << 3)) |
| 357 | /* CPU2 Reset Release (2) */ |
| 358 | #define SYS1_RRLSR_CPU2 (0x1 << 2) |
| 359 | #define SYS1_RRLSR_CPU2_VAL(val) (((val) & 0x1) << 2) |
| 360 | #define SYS1_RRLSR_CPU2_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU2) | (((val) & 1) << 2)) |
| 361 | /* CPU1 Reset Release (1) */ |
| 362 | #define SYS1_RRLSR_CPU1 (0x1 << 1) |
| 363 | #define SYS1_RRLSR_CPU1_VAL(val) (((val) & 0x1) << 1) |
| 364 | #define SYS1_RRLSR_CPU1_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU1) | (((val) & 1) << 1)) |
| 365 | /* CPU0 Reset Release (0) */ |
| 366 | #define SYS1_RRLSR_CPU0 (0x1) |
| 367 | #define SYS1_RRLSR_CPU0_VAL(val) (((val) & 0x1) << 0) |
| 368 | #define SYS1_RRLSR_CPU0_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU0) | (((val) & 1) << 0)) |
| 369 | |
| 370 | #endif |
| 371 | |
