| 1 | /****************************************************************************** |
| 2 | |
| 3 | Copyright (c) 2007 |
| 4 | Infineon Technologies AG |
| 5 | St. Martin Strasse 53; 81669 Munich, Germany |
| 6 | |
| 7 | Any use of this Software is subject to the conclusion of a respective |
| 8 | License Agreement. Without such a License Agreement no rights to the |
| 9 | Software are granted. |
| 10 | |
| 11 | ******************************************************************************/ |
| 12 | |
| 13 | #ifndef __SYS2_REG_H |
| 14 | #define __SYS2_REG_H |
| 15 | |
| 16 | #define sys2_r32(reg) ltq_r32(&sys2->reg) |
| 17 | #define sys2_w32(val, reg) ltq_w32(val, &sys2->reg) |
| 18 | #define sys2_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &sys2->reg) |
| 19 | |
| 20 | /** SYS2 register structure */ |
| 21 | struct svip_reg_sys2 { |
| 22 | volatile unsigned long clksr; /* 0x0000 */ |
| 23 | volatile unsigned long clkenr; /* 0x0004 */ |
| 24 | volatile unsigned long clkclr; /* 0x0008 */ |
| 25 | volatile unsigned long reserved0[1]; |
| 26 | volatile unsigned long rsr; /* 0x0010 */ |
| 27 | volatile unsigned long rreqr; /* 0x0014 */ |
| 28 | volatile unsigned long rrlsr; /* 0x0018 */ |
| 29 | }; |
| 30 | |
| 31 | /******************************************************************************* |
| 32 | * SYS2 Clock Status Register |
| 33 | ******************************************************************************/ |
| 34 | |
| 35 | /* Clock Enable for PORT4 */ |
| 36 | #define SYS2_CLKSR_PORT4 (0x1 << 27) |
| 37 | #define SYS2_CLKSR_PORT4_VAL(val) (((val) & 0x1) << 27) |
| 38 | #define SYS2_CLKSR_PORT4_GET(val) (((val) & SYS2_CLKSR_PORT4) >> 27) |
| 39 | /* Clock Enable for HWSYNC */ |
| 40 | #define SYS2_CLKSR_HWSYNC (0x1 << 26) |
| 41 | #define SYS2_CLKSR_HWSYNC_VAL(val) (((val) & |
| 42 | #define SYS2_CLKSR_HWSYNC_GET(val) (((val) & SYS2_CLKSR_HWSYNC) >> 26) |
| 43 | /* Clock Enable for MBS */ |
| 44 | #define SYS2_CLKSR_MBS (0x1 << 25) |
| 45 | #define SYS2_CLKSR_MBS_VAL(val) (((val) & 0x1) << 25) |
| 46 | #define SYS2_CLKSR_MBS_GET(val) (((val) & SYS2_CLKSR_MBS) >> 25) |
| 47 | /* Clock Enable for SWINT */ |
| 48 | #define SYS2_CLKSR_SWINT (0x1 << 24) |
| 49 | #define SYS2_CLKSR_SWINT_VAL(val) (((val) & 0x1) << 24) |
| 50 | #define SYS2_CLKSR_SWINT_GET(val) (((val) & SYS2_CLKSR_SWINT) >> 24) |
| 51 | /* Clock Enable for HWACC3 */ |
| 52 | #define SYS2_CLKSR_HWACC3 (0x1 << 19) |
| 53 | #define SYS2_CLKSR_HWACC3_VAL(val) (((val) & |
| 54 | #define SYS2_CLKSR_HWACC3_GET(val) (((val) & SYS2_CLKSR_HWACC3) >> 19) |
| 55 | /* Clock Enable for HWACC2 */ |
| 56 | #define SYS2_CLKSR_HWACC2 (0x1 << 18) |
| 57 | #define SYS2_CLKSR_HWACC2_VAL(val) (((val) & |
| 58 | #define SYS2_CLKSR_HWACC2_GET(val) (((val) & SYS2_CLKSR_HWACC2) >> 18) |
| 59 | /* Clock Enable for HWACC1 */ |
| 60 | #define SYS2_CLKSR_HWACC1 (0x1 << 17) |
| 61 | #define SYS2_CLKSR_HWACC1_VAL(val) (((val) & |
| 62 | #define SYS2_CLKSR_HWACC1_GET(val) (((val) & SYS2_CLKSR_HWACC1) >> 17) |
| 63 | /* Clock Enable for HWACC0 */ |
| 64 | #define SYS2_CLKSR_HWACC0 (0x1 << 16) |
| 65 | #define SYS2_CLKSR_HWACC0_VAL(val) (((val) & |
| 66 | #define SYS2_CLKSR_HWACC0_GET(val) (((val) & SYS2_CLKSR_HWACC0) >> 16) |
| 67 | /* Clock Enable for SIF7 */ |
| 68 | #define SYS2_CLKSR_SIF7 (0x1 << 15) |
| 69 | #define SYS2_CLKSR_SIF7_VAL(val) (((val) & 0x1) << 15) |
| 70 | #define SYS2_CLKSR_SIF7_GET(val) (((val) & SYS2_CLKSR_SIF7) >> 15) |
| 71 | /* Clock Enable for SIF6 */ |
| 72 | #define SYS2_CLKSR_SIF6 (0x1 << 14) |
| 73 | #define SYS2_CLKSR_SIF6_VAL(val) (((val) & 0x1) << 14) |
| 74 | #define SYS2_CLKSR_SIF6_GET(val) (((val) & SYS2_CLKSR_SIF6) >> 14) |
| 75 | /* Clock Enable for SIF5 */ |
| 76 | #define SYS2_CLKSR_SIF5 (0x1 << 13) |
| 77 | #define SYS2_CLKSR_SIF5_VAL(val) (((val) & 0x1) << 13) |
| 78 | #define SYS2_CLKSR_SIF5_GET(val) (((val) & SYS2_CLKSR_SIF5) >> 13) |
| 79 | /* Clock Enable for SIF4 */ |
| 80 | #define SYS2_CLKSR_SIF4 (0x1 << 12) |
| 81 | #define SYS2_CLKSR_SIF4_VAL(val) (((val) & 0x1) << 12) |
| 82 | #define SYS2_CLKSR_SIF4_GET(val) (((val) & SYS2_CLKSR_SIF4) >> 12) |
| 83 | /* Clock Enable for SIF3 */ |
| 84 | #define SYS2_CLKSR_SIF3 (0x1 << 11) |
| 85 | #define SYS2_CLKSR_SIF3_VAL(val) (((val) & 0x1) << 11) |
| 86 | #define SYS2_CLKSR_SIF3_GET(val) (((val) & SYS2_CLKSR_SIF3) >> 11) |
| 87 | /* Clock Enable for SIF2 */ |
| 88 | #define SYS2_CLKSR_SIF2 (0x1 << 10) |
| 89 | #define SYS2_CLKSR_SIF2_VAL(val) (((val) & 0x1) << 10) |
| 90 | #define SYS2_CLKSR_SIF2_GET(val) (((val) & SYS2_CLKSR_SIF2) >> 10) |
| 91 | /* Clock Enable for SIF1 */ |
| 92 | #define SYS2_CLKSR_SIF1 (0x1 << 9) |
| 93 | #define SYS2_CLKSR_SIF1_VAL(val) (((val) & 0x1) << 9) |
| 94 | #define SYS2_CLKSR_SIF1_GET(val) (((val) & SYS2_CLKSR_SIF1) >> 9) |
| 95 | /* Clock Enable for SIF0 */ |
| 96 | #define SYS2_CLKSR_SIF0 (0x1 << 8) |
| 97 | #define SYS2_CLKSR_SIF0_VAL(val) (((val) & 0x1) << 8) |
| 98 | #define SYS2_CLKSR_SIF0_GET(val) (((val) & SYS2_CLKSR_SIF0) >> 8) |
| 99 | /* Clock Enable for DFEV7 */ |
| 100 | #define SYS2_CLKSR_DFEV7 (0x1 << 7) |
| 101 | #define SYS2_CLKSR_DFEV7_VAL(val) (((val) & 0x1) << 7) |
| 102 | #define SYS2_CLKSR_DFEV7_GET(val) (((val) & SYS2_CLKSR_DFEV7) >> 7) |
| 103 | /* Clock Enable for DFEV6 */ |
| 104 | #define SYS2_CLKSR_DFEV6 (0x1 << 6) |
| 105 | #define SYS2_CLKSR_DFEV6_VAL(val) (((val) & 0x1) << 6) |
| 106 | #define SYS2_CLKSR_DFEV6_GET(val) (((val) & SYS2_CLKSR_DFEV6) >> 6) |
| 107 | /* Clock Enable for DFEV5 */ |
| 108 | #define SYS2_CLKSR_DFEV5 (0x1 << 5) |
| 109 | #define SYS2_CLKSR_DFEV5_VAL(val) (((val) & 0x1) << 5) |
| 110 | #define SYS2_CLKSR_DFEV5_GET(val) (((val) & SYS2_CLKSR_DFEV5) >> 5) |
| 111 | /* Clock Enable for DFEV4 */ |
| 112 | #define SYS2_CLKSR_DFEV4 (0x1 << 4) |
| 113 | #define SYS2_CLKSR_DFEV4_VAL(val) (((val) & 0x1) << 4) |
| 114 | #define SYS2_CLKSR_DFEV4_GET(val) (((val) & SYS2_CLKSR_DFEV4) >> 4) |
| 115 | /* Clock Enable for DFEV3 */ |
| 116 | #define SYS2_CLKSR_DFEV3 (0x1 << 3) |
| 117 | #define SYS2_CLKSR_DFEV3_VAL(val) (((val) & 0x1) << 3) |
| 118 | #define SYS2_CLKSR_DFEV3_GET(val) (((val) & SYS2_CLKSR_DFEV3) >> 3) |
| 119 | /* Clock Enable for DFEV2 */ |
| 120 | #define SYS2_CLKSR_DFEV2 (0x1 << 2) |
| 121 | #define SYS2_CLKSR_DFEV2_VAL(val) (((val) & 0x1) << 2) |
| 122 | #define SYS2_CLKSR_DFEV2_GET(val) (((val) & SYS2_CLKSR_DFEV2) >> 2) |
| 123 | /* Clock Enable for DFEV1 */ |
| 124 | #define SYS2_CLKSR_DFEV1 (0x1 << 1) |
| 125 | #define SYS2_CLKSR_DFEV1_VAL(val) (((val) & 0x1) << 1) |
| 126 | #define SYS2_CLKSR_DFEV1_GET(val) (((val) & SYS2_CLKSR_DFEV1) >> 1) |
| 127 | /* Clock Enable for DFEV0 */ |
| 128 | #define SYS2_CLKSR_DFEV0 (0x1) |
| 129 | #define SYS2_CLKSR_DFEV0_VAL(val) (((val) & 0x1)) |
| 130 | #define SYS2_CLKSR_DFEV0_GET(val) ((val) & SYS2_CLKSR_DFEV0) |
| 131 | |
| 132 | /******************************************************************************* |
| 133 | * SYS2 Clock Enable Register |
| 134 | ******************************************************************************/ |
| 135 | |
| 136 | /* Clock Enable Request for PORT4 */ |
| 137 | #define SYS2_CLKENR_PORT4 (0x1 << 27) |
| 138 | #define SYS2_CLKENR_PORT4_VAL(val) (((val) & 0x1) << 27) |
| 139 | #define SYS2_CLKENR_PORT4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_PORT4) | ((val & 0x1) << 27)) |
| 140 | /* Clock Enable Request for HWSYNC */ |
| 141 | #define SYS2_CLKENR_HWSYNC (0x1 << 26) |
| 142 | #define SYS2_CLKENR_HWSYNC_VAL(val) (((val) & 0x1) << 26) |
| 143 | #define SYS2_CLKENR_HWSYNC_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWSYNC) | ((val & 0x1) << 26)) |
| 144 | /* Clock Enable Request for MBS */ |
| 145 | #define SYS2_CLKENR_MBS (0x1 << 25) |
| 146 | #define SYS2_CLKENR_MBS_VAL(val) (((val) & 0x1) << 25) |
| 147 | #define SYS2_CLKENR_MBS_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_MBS) | ((val & 0x1) << 25)) |
| 148 | /* Clock Enable Request for SWINT */ |
| 149 | #define SYS2_CLKENR_SWINT (0x1 << 24) |
| 150 | #define SYS2_CLKENR_SWINT_VAL(val) (((val) & 0x1) << 24) |
| 151 | #define SYS2_CLKENR_SWINT_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SWINT) | ((val & 0x1) << 24)) |
| 152 | /* Clock Enable Request for HWACC3 */ |
| 153 | #define SYS2_CLKENR_HWACC3 (0x1 << 19) |
| 154 | #define SYS2_CLKENR_HWACC3_VAL(val) (((val) & 0x1) << 19) |
| 155 | #define SYS2_CLKENR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC3) | ((val & 0x1) << 19)) |
| 156 | /* Clock Enable Request for HWACC2 */ |
| 157 | #define SYS2_CLKENR_HWACC2 (0x1 << 18) |
| 158 | #define SYS2_CLKENR_HWACC2_VAL(val) (((val) & 0x1) << 18) |
| 159 | #define SYS2_CLKENR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC2) | ((val & 0x1) << 18)) |
| 160 | /* Clock Enable Request for HWACC1 */ |
| 161 | #define SYS2_CLKENR_HWACC1 (0x1 << 17) |
| 162 | #define SYS2_CLKENR_HWACC1_VAL(val) (((val) & 0x1) << 17) |
| 163 | #define SYS2_CLKENR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC1) | ((val & 0x1) << 17)) |
| 164 | /* Clock Enable Request for HWACC0 */ |
| 165 | #define SYS2_CLKENR_HWACC0 (0x1 << 16) |
| 166 | #define SYS2_CLKENR_HWACC0_VAL(val) (((val) & 0x1) << 16) |
| 167 | #define SYS2_CLKENR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC0) | ((val & 0x1) << 16)) |
| 168 | /* Clock Enable Request for SIF7 */ |
| 169 | #define SYS2_CLKENR_SIF7 (0x1 << 15) |
| 170 | #define SYS2_CLKENR_SIF7_VAL(val) (((val) & 0x1) << 15) |
| 171 | #define SYS2_CLKENR_SIF7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF7) | ((val & 0x1) << 15)) |
| 172 | /* Clock Enable Request for SIF6 */ |
| 173 | #define SYS2_CLKENR_SIF6 (0x1 << 14) |
| 174 | #define SYS2_CLKENR_SIF6_VAL(val) (((val) & 0x1) << 14) |
| 175 | #define SYS2_CLKENR_SIF6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF6) | ((val & 0x1) << 14)) |
| 176 | /* Clock Enable Request for SIF5 */ |
| 177 | #define SYS2_CLKENR_SIF5 (0x1 << 13) |
| 178 | #define SYS2_CLKENR_SIF5_VAL(val) (((val) & 0x1) << 13) |
| 179 | #define SYS2_CLKENR_SIF5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF5) | ((val & 0x1) << 13)) |
| 180 | /* Clock Enable Request for SIF4 */ |
| 181 | #define SYS2_CLKENR_SIF4 (0x1 << 12) |
| 182 | #define SYS2_CLKENR_SIF4_VAL(val) (((val) & 0x1) << 12) |
| 183 | #define SYS2_CLKENR_SIF4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF4) | ((val & 0x1) << 12)) |
| 184 | /* Clock Enable Request for SIF3 */ |
| 185 | #define SYS2_CLKENR_SIF3 (0x1 << 11) |
| 186 | #define SYS2_CLKENR_SIF3_VAL(val) (((val) & 0x1) << 11) |
| 187 | #define SYS2_CLKENR_SIF3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF3) | ((val & 0x1) << 11)) |
| 188 | /* Clock Enable Request for SIF2 */ |
| 189 | #define SYS2_CLKENR_SIF2 (0x1 << 10) |
| 190 | #define SYS2_CLKENR_SIF2_VAL(val) (((val) & 0x1) << 10) |
| 191 | #define SYS2_CLKENR_SIF2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF2) | ((val & 0x1) << 10)) |
| 192 | /* Clock Enable Request for SIF1 */ |
| 193 | #define SYS2_CLKENR_SIF1 (0x1 << 9) |
| 194 | #define SYS2_CLKENR_SIF1_VAL(val) (((val) & 0x1) << 9) |
| 195 | #define SYS2_CLKENR_SIF1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF1) | ((val & 0x1) << 9)) |
| 196 | /* Clock Enable Request for SIF0 */ |
| 197 | #define SYS2_CLKENR_SIF0 (0x1 << 8) |
| 198 | #define SYS2_CLKENR_SIF0_VAL(val) (((val) & 0x1) << 8) |
| 199 | #define SYS2_CLKENR_SIF0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF0) | ((val & 0x1) << 8)) |
| 200 | /* Clock Enable Request for DFEV7 */ |
| 201 | #define SYS2_CLKENR_DFEV7 (0x1 << 7) |
| 202 | #define SYS2_CLKENR_DFEV7_VAL(val) (((val) & 0x1) << 7) |
| 203 | #define SYS2_CLKENR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV7) | ((val & 0x1) << 7)) |
| 204 | /* Clock Enable Request for DFEV6 */ |
| 205 | #define SYS2_CLKENR_DFEV6 (0x1 << 6) |
| 206 | #define SYS2_CLKENR_DFEV6_VAL(val) (((val) & 0x1) << 6) |
| 207 | #define SYS2_CLKENR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV6) | ((val & 0x1) << 6)) |
| 208 | /* Clock Enable Request for DFEV5 */ |
| 209 | #define SYS2_CLKENR_DFEV5 (0x1 << 5) |
| 210 | #define SYS2_CLKENR_DFEV5_VAL(val) (((val) & 0x1) << 5) |
| 211 | #define SYS2_CLKENR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV5) | ((val & 0x1) << 5)) |
| 212 | /* Clock Enable Request for DFEV4 */ |
| 213 | #define SYS2_CLKENR_DFEV4 (0x1 << 4) |
| 214 | #define SYS2_CLKENR_DFEV4_VAL(val) (((val) & 0x1) << 4) |
| 215 | #define SYS2_CLKENR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV4) | ((val & 0x1) << 4)) |
| 216 | /* Clock Enable Request for DFEV3 */ |
| 217 | #define SYS2_CLKENR_DFEV3 (0x1 << 3) |
| 218 | #define SYS2_CLKENR_DFEV3_VAL(val) (((val) & 0x1) << 3) |
| 219 | #define SYS2_CLKENR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV3) | ((val & 0x1) << 3)) |
| 220 | /* Clock Enable Request for DFEV2 */ |
| 221 | #define SYS2_CLKENR_DFEV2 (0x1 << 2) |
| 222 | #define SYS2_CLKENR_DFEV2_VAL(val) (((val) & 0x1) << 2) |
| 223 | #define SYS2_CLKENR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV2) | ((val & 0x1) << 2)) |
| 224 | /* Clock Enable Request for DFEV1 */ |
| 225 | #define SYS2_CLKENR_DFEV1 (0x1 << 1) |
| 226 | #define SYS2_CLKENR_DFEV1_VAL(val) (((val) & 0x1) << 1) |
| 227 | #define SYS2_CLKENR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV1) | ((val & 0x1) << 1)) |
| 228 | /* Clock Enable Request for DFEV0 */ |
| 229 | #define SYS2_CLKENR_DFEV0 (0x1) |
| 230 | #define SYS2_CLKENR_DFEV0_VAL(val) (((val) & 0x1)) |
| 231 | #define SYS2_CLKENR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV0) | ((val & 0x1))) |
| 232 | |
| 233 | /******************************************************************************* |
| 234 | * SYS2 Clock Clear Register |
| 235 | ******************************************************************************/ |
| 236 | |
| 237 | /* Clock Disable Request for PORT4 */ |
| 238 | #define SYS2_CLKCLR_PORT4 (0x1 << 27) |
| 239 | #define SYS2_CLKCLR_PORT4_VAL(val) (((val) & 0x1) << 27) |
| 240 | #define SYS2_CLKCLR_PORT4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_PORT4) | ((val & 0x1) << 27)) |
| 241 | /* Clock Disable Request for HWSYNC */ |
| 242 | #define SYS2_CLKCLR_HWSYNC (0x1 << 26) |
| 243 | #define SYS2_CLKCLR_HWSYNC_VAL(val) (((val) & 0x1) << 26) |
| 244 | #define SYS2_CLKCLR_HWSYNC_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWSYNC) | ((val & 0x1) << 26)) |
| 245 | /* Clock Disable Request for MBS */ |
| 246 | #define SYS2_CLKCLR_MBS (0x1 << 25) |
| 247 | #define SYS2_CLKCLR_MBS_VAL(val) (((val) & 0x1) << 25) |
| 248 | #define SYS2_CLKCLR_MBS_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_MBS) | ((val & 0x1) << 25)) |
| 249 | /* Clock Disable Request for SWINT */ |
| 250 | #define SYS2_CLKCLR_SWINT (0x1 << 24) |
| 251 | #define SYS2_CLKCLR_SWINT_VAL(val) (((val) & 0x1) << 24) |
| 252 | #define SYS2_CLKCLR_SWINT_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SWINT) | ((val & 0x1) << 24)) |
| 253 | /* Clock Disable Request for HWACC3 */ |
| 254 | #define SYS2_CLKCLR_HWACC3 (0x1 << 19) |
| 255 | #define SYS2_CLKCLR_HWACC3_VAL(val) (((val) & 0x1) << 19) |
| 256 | #define SYS2_CLKCLR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC3) | ((val & 0x1) << 19)) |
| 257 | /* Clock Disable Request for HWACC2 */ |
| 258 | #define SYS2_CLKCLR_HWACC2 (0x1 << 18) |
| 259 | #define SYS2_CLKCLR_HWACC2_VAL(val) (((val) & 0x1) << 18) |
| 260 | #define SYS2_CLKCLR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC2) | ((val & 0x1) << 18)) |
| 261 | /* Clock Disable Request for HWACC1 */ |
| 262 | #define SYS2_CLKCLR_HWACC1 (0x1 << 17) |
| 263 | #define SYS2_CLKCLR_HWACC1_VAL(val) (((val) & 0x1) << 17) |
| 264 | #define SYS2_CLKCLR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC1) | ((val & 0x1) << 17)) |
| 265 | /* Clock Disable Request for HWACC0 */ |
| 266 | #define SYS2_CLKCLR_HWACC0 (0x1 << 16) |
| 267 | #define SYS2_CLKCLR_HWACC0_VAL(val) (((val) & 0x1) << 16) |
| 268 | #define SYS2_CLKCLR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC0) | ((val & 0x1) << 16)) |
| 269 | /* Clock Disable Request for SIF7 */ |
| 270 | #define SYS2_CLKCLR_SIF7 (0x1 << 15) |
| 271 | #define SYS2_CLKCLR_SIF7_VAL(val) (((val) & 0x1) << 15) |
| 272 | #define SYS2_CLKCLR_SIF7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF7) | ((val & 0x1) << 15)) |
| 273 | /* Clock Disable Request for SIF6 */ |
| 274 | #define SYS2_CLKCLR_SIF6 (0x1 << 14) |
| 275 | #define SYS2_CLKCLR_SIF6_VAL(val) (((val) & 0x1) << 14) |
| 276 | #define SYS2_CLKCLR_SIF6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF6) | ((val & 0x1) << 14)) |
| 277 | /* Clock Disable Request for SIF5 */ |
| 278 | #define SYS2_CLKCLR_SIF5 (0x1 << 13) |
| 279 | #define SYS2_CLKCLR_SIF5_VAL(val) (((val) & 0x1) << 13) |
| 280 | #define SYS2_CLKCLR_SIF5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF5) | ((val & 0x1) << 13)) |
| 281 | /* Clock Disable Request for SIF4 */ |
| 282 | #define SYS2_CLKCLR_SIF4 (0x1 << 12) |
| 283 | #define SYS2_CLKCLR_SIF4_VAL(val) (((val) & 0x1) << 12) |
| 284 | #define SYS2_CLKCLR_SIF4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF4) | ((val & 0x1) << 12)) |
| 285 | /* Clock Disable Request for SIF3 */ |
| 286 | #define SYS2_CLKCLR_SIF3 (0x1 << 11) |
| 287 | #define SYS2_CLKCLR_SIF3_VAL(val) (((val) & 0x1) << 11) |
| 288 | #define SYS2_CLKCLR_SIF3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF3) | ((val & 0x1) << 11)) |
| 289 | /* Clock Disable Request for SIF2 */ |
| 290 | #define SYS2_CLKCLR_SIF2 (0x1 << 10) |
| 291 | #define SYS2_CLKCLR_SIF2_VAL(val) (((val) & 0x1) << 10) |
| 292 | #define SYS2_CLKCLR_SIF2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF2) | ((val & 0x1) << 10)) |
| 293 | /* Clock Disable Request for SIF1 */ |
| 294 | #define SYS2_CLKCLR_SIF1 (0x1 << 9) |
| 295 | #define SYS2_CLKCLR_SIF1_VAL(val) (((val) & 0x1) << 9) |
| 296 | #define SYS2_CLKCLR_SIF1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF1) | ((val & 0x1) << 9)) |
| 297 | /* Clock Disable Request for SIF0 */ |
| 298 | #define SYS2_CLKCLR_SIF0 (0x1 << 8) |
| 299 | #define SYS2_CLKCLR_SIF0_VAL(val) (((val) & 0x1) << 8) |
| 300 | #define SYS2_CLKCLR_SIF0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF0) | ((val & 0x1) << 8)) |
| 301 | /* Clock Disable Request for DFEV7 */ |
| 302 | #define SYS2_CLKCLR_DFEV7 (0x1 << 7) |
| 303 | #define SYS2_CLKCLR_DFEV7_VAL(val) (((val) & 0x1) << 7) |
| 304 | #define SYS2_CLKCLR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV7) | ((val & 0x1) << 7)) |
| 305 | /* Clock Disable Request for DFEV6 */ |
| 306 | #define SYS2_CLKCLR_DFEV6 (0x1 << 6) |
| 307 | #define SYS2_CLKCLR_DFEV6_VAL(val) (((val) & 0x1) << 6) |
| 308 | #define SYS2_CLKCLR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV6) | ((val & 0x1) << 6)) |
| 309 | /* Clock Disable Request for DFEV5 */ |
| 310 | #define SYS2_CLKCLR_DFEV5 (0x1 << 5) |
| 311 | #define SYS2_CLKCLR_DFEV5_VAL(val) (((val) & 0x1) << 5) |
| 312 | #define SYS2_CLKCLR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV5) | ((val & 0x1) << 5)) |
| 313 | /* Clock Disable Request for DFEV4 */ |
| 314 | #define SYS2_CLKCLR_DFEV4 (0x1 << 4) |
| 315 | #define SYS2_CLKCLR_DFEV4_VAL(val) (((val) & 0x1) << 4) |
| 316 | #define SYS2_CLKCLR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV4) | ((val & 0x1) << 4)) |
| 317 | /* Clock Disable Request for DFEV3 */ |
| 318 | #define SYS2_CLKCLR_DFEV3 (0x1 << 3) |
| 319 | #define SYS2_CLKCLR_DFEV3_VAL(val) (((val) & 0x1) << 3) |
| 320 | #define SYS2_CLKCLR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV3) | ((val & 0x1) << 3)) |
| 321 | /* Clock Disable Request for DFEV2 */ |
| 322 | #define SYS2_CLKCLR_DFEV2 (0x1 << 2) |
| 323 | #define SYS2_CLKCLR_DFEV2_VAL(val) (((val) & 0x1) << 2) |
| 324 | #define SYS2_CLKCLR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV2) | ((val & 0x1) << 2)) |
| 325 | /* Clock Disable Request for DFEV1 */ |
| 326 | #define SYS2_CLKCLR_DFEV1 (0x1 << 1) |
| 327 | #define SYS2_CLKCLR_DFEV1_VAL(val) (((val) & 0x1) << 1) |
| 328 | #define SYS2_CLKCLR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV1) | ((val & 0x1) << 1)) |
| 329 | /* Clock Disable Request for DFEV0 */ |
| 330 | #define SYS2_CLKCLR_DFEV0 (0x1) |
| 331 | #define SYS2_CLKCLR_DFEV0_VAL(val) (((val) & 0x1)) |
| 332 | #define SYS2_CLKCLR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV0) | ((val & 0x1))) |
| 333 | |
| 334 | /******************************************************************************* |
| 335 | * SYS2 Reset Status Register |
| 336 | ******************************************************************************/ |
| 337 | |
| 338 | /* HWACC3 Reset */ |
| 339 | #define SYS2_RSR_HWACC3 (0x1 << 11) |
| 340 | #define SYS2_RSR_HWACC3_VAL(val) (((val) & 0x1) << 11) |
| 341 | #define SYS2_RSR_HWACC3_GET(val) (((val) & SYS2_RSR_HWACC3) >> 11) |
| 342 | /* HWACC2 Reset */ |
| 343 | #define SYS2_RSR_HWACC2 (0x1 << 10) |
| 344 | #define SYS2_RSR_HWACC2_VAL(val) (((val) & 0x1) << 10) |
| 345 | #define SYS2_RSR_HWACC2_GET(val) (((val) & SYS2_RSR_HWACC2) >> 10) |
| 346 | /* HWACC1 Reset */ |
| 347 | #define SYS2_RSR_HWACC1 (0x1 << 9) |
| 348 | #define SYS2_RSR_HWACC1_VAL(val) (((val) & 0x1) << 9) |
| 349 | #define SYS2_RSR_HWACC1_GET(val) (((val) & SYS2_RSR_HWACC1) >> 9) |
| 350 | /* HWACC0 Reset */ |
| 351 | #define SYS2_RSR_HWACC0 (0x1 << 8) |
| 352 | #define SYS2_RSR_HWACC0_VAL(val) (((val) & 0x1) << 8) |
| 353 | #define SYS2_RSR_HWACC0_GET(val) (((val) & SYS2_RSR_HWACC0) >> 8) |
| 354 | /* DFEV7 Reset */ |
| 355 | #define SYS2_RSR_DFEV7 (0x1 << 7) |
| 356 | #define SYS2_RSR_DFEV7_VAL(val) (((val) & 0x1) << 7) |
| 357 | #define SYS2_RSR_DFEV7_GET(val) (((val) & SYS2_RSR_DFEV7) >> 7) |
| 358 | /* DFEV6 Reset */ |
| 359 | #define SYS2_RSR_DFEV6 (0x1 << 6) |
| 360 | #define SYS2_RSR_DFEV6_VAL(val) (((val) & 0x1) << 6) |
| 361 | #define SYS2_RSR_DFEV6_GET(val) (((val) & SYS2_RSR_DFEV6) >> 6) |
| 362 | /* DFEV5 Reset */ |
| 363 | #define SYS2_RSR_DFEV5 (0x1 << 5) |
| 364 | #define SYS2_RSR_DFEV5_VAL(val) (((val) & 0x1) << 5) |
| 365 | #define SYS2_RSR_DFEV5_GET(val) (((val) & SYS2_RSR_DFEV5) >> 5) |
| 366 | /* DFEV4 Reset */ |
| 367 | #define SYS2_RSR_DFEV4 (0x1 << 4) |
| 368 | #define SYS2_RSR_DFEV4_VAL(val) (((val) & 0x1) << 4) |
| 369 | #define SYS2_RSR_DFEV4_GET(val) (((val) & SYS2_RSR_DFEV4) >> 4) |
| 370 | /* DFEV3 Reset */ |
| 371 | #define SYS2_RSR_DFEV3 (0x1 << 3) |
| 372 | #define SYS2_RSR_DFEV3_VAL(val) (((val) & 0x1) << 3) |
| 373 | #define SYS2_RSR_DFEV3_GET(val) (((val) & SYS2_RSR_DFEV3) >> 3) |
| 374 | /* DFEV2 Reset */ |
| 375 | #define SYS2_RSR_DFEV2 (0x1 << 2) |
| 376 | #define SYS2_RSR_DFEV2_VAL(val) (((val) & 0x1) << 2) |
| 377 | #define SYS2_RSR_DFEV2_GET(val) (((val) & SYS2_RSR_DFEV2) >> 2) |
| 378 | /* DFEV1 Reset */ |
| 379 | #define SYS2_RSR_DFEV1 (0x1 << 1) |
| 380 | #define SYS2_RSR_DFEV1_VAL(val) (((val) & 0x1) << 1) |
| 381 | #define SYS2_RSR_DFEV1_GET(val) (((val) & SYS2_RSR_DFEV1) >> 1) |
| 382 | /* DFEV0 Reset */ |
| 383 | #define SYS2_RSR_DFEV0 (0x1) |
| 384 | #define SYS2_RSR_DFEV0_VAL(val) (((val) & 0x1)) |
| 385 | #define SYS2_RSR_DFEV0_GET(val) ((val) & SYS2_RSR_DFEV0) |
| 386 | |
| 387 | /****************************************************************************** |
| 388 | * SYS2 Reset Request Register |
| 389 | ******************************************************************************/ |
| 390 | |
| 391 | /* HWACC3 Reset Request */ |
| 392 | #define SYS2_RREQR_HWACC3 (0x1 << 11) |
| 393 | #define SYS2_RREQR_HWACC3_VAL(val) (((val) & 0x1) << 11) |
| 394 | #define SYS2_RREQR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC3) | ((val & 0x1) << 11)) |
| 395 | /* HWACC2 Reset Request */ |
| 396 | #define SYS2_RREQR_HWACC2 (0x1 << 10) |
| 397 | #define SYS2_RREQR_HWACC2_VAL(val) (((val) & 0x1) << 10) |
| 398 | #define SYS2_RREQR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC2) | ((val & 0x1) << 10)) |
| 399 | /* HWACC1 Reset Request */ |
| 400 | #define SYS2_RREQR_HWACC1 (0x1 << 9) |
| 401 | #define SYS2_RREQR_HWACC1_VAL(val) (((val) & 0x1) << 9) |
| 402 | #define SYS2_RREQR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC1) | ((val & 0x1) << 9)) |
| 403 | /* HWACC0 Reset Request */ |
| 404 | #define SYS2_RREQR_HWACC0 (0x1 << 8) |
| 405 | #define SYS2_RREQR_HWACC0_VAL(val) (((val) & 0x1) << 8) |
| 406 | #define SYS2_RREQR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC0) | ((val & 0x1) << 8)) |
| 407 | /* DFEV7 Reset Request */ |
| 408 | #define SYS2_RREQR_DFEV7 (0x1 << 7) |
| 409 | #define SYS2_RREQR_DFEV7_VAL(val) (((val) & 0x1) << 7) |
| 410 | #define SYS2_RREQR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV7) | ((val & 0x1) << 7)) |
| 411 | /* DFEV6 Reset Request */ |
| 412 | #define SYS2_RREQR_DFEV6 (0x1 << 6) |
| 413 | #define SYS2_RREQR_DFEV6_VAL(val) (((val) & 0x1) << 6) |
| 414 | #define SYS2_RREQR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV6) | ((val & 0x1) << 6)) |
| 415 | /* DFEV5 Reset Request */ |
| 416 | #define SYS2_RREQR_DFEV5 (0x1 << 5) |
| 417 | #define SYS2_RREQR_DFEV5_VAL(val) (((val) & 0x1) << 5) |
| 418 | #define SYS2_RREQR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV5) | ((val & 0x1) << 5)) |
| 419 | /* DFEV4 Reset Request */ |
| 420 | #define SYS2_RREQR_DFEV4 (0x1 << 4) |
| 421 | #define SYS2_RREQR_DFEV4_VAL(val) (((val) & 0x1) << 4) |
| 422 | #define SYS2_RREQR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV4) | ((val & 0x1) << 4)) |
| 423 | /* DFEV3 Reset Request */ |
| 424 | #define SYS2_RREQR_DFEV3 (0x1 << 3) |
| 425 | #define SYS2_RREQR_DFEV3_VAL(val) (((val) & 0x1) << 3) |
| 426 | #define SYS2_RREQR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV3) | ((val & 0x1) << 3)) |
| 427 | /* DFEV2 Reset Request */ |
| 428 | #define SYS2_RREQR_DFEV2 (0x1 << 2) |
| 429 | #define SYS2_RREQR_DFEV2_VAL(val) (((val) & 0x1) << 2) |
| 430 | #define SYS2_RREQR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV2) | ((val & 0x1) << 2)) |
| 431 | /* DFEV1 Reset Request */ |
| 432 | #define SYS2_RREQR_DFEV1 (0x1 << 1) |
| 433 | #define SYS2_RREQR_DFEV1_VAL(val) (((val) & 0x1) << 1) |
| 434 | #define SYS2_RREQR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV1) | ((val & 0x1) << 1)) |
| 435 | /* DFEV0 Reset Request */ |
| 436 | #define SYS2_RREQR_DFEV0 (0x1) |
| 437 | #define SYS2_RREQR_DFEV0_VAL(val) (((val) & 0x1)) |
| 438 | #define SYS2_RREQR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV0) | ((val & 0x1))) |
| 439 | |
| 440 | /******************************************************************************* |
| 441 | * SYS2 Reset Release Register |
| 442 | ******************************************************************************/ |
| 443 | |
| 444 | /* HWACC3 Reset Release */ |
| 445 | #define SYS2_RRLSR_HWACC3 (0x1 << 11) |
| 446 | #define SYS2_RRLSR_HWACC3_VAL(val) (((val) & 0x1) << 11) |
| 447 | #define SYS2_RRLSR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC3) | ((val & 0x1) << 11)) |
| 448 | /* HWACC2 Reset Release */ |
| 449 | #define SYS2_RRLSR_HWACC2 (0x1 << 10) |
| 450 | #define SYS2_RRLSR_HWACC2_VAL(val) (((val) & 0x1) << 10) |
| 451 | #define SYS2_RRLSR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC2) | ((val & 0x1) << 10)) |
| 452 | /* HWACC1 Reset Release */ |
| 453 | #define SYS2_RRLSR_HWACC1 (0x1 << 9) |
| 454 | #define SYS2_RRLSR_HWACC1_VAL(val) (((val) & 0x1) << 9) |
| 455 | #define SYS2_RRLSR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC1) | ((val & 0x1) << 9)) |
| 456 | /* HWACC0 Reset Release */ |
| 457 | #define SYS2_RRLSR_HWACC0 (0x1 << 8) |
| 458 | #define SYS2_RRLSR_HWACC0_VAL(val) (((val) & 0x1) << 8) |
| 459 | #define SYS2_RRLSR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC0) | ((val & 0x1) << 8)) |
| 460 | /* DFEV7 Reset Release */ |
| 461 | #define SYS2_RRLSR_DFEV7 (0x1 << 7) |
| 462 | #define SYS2_RRLSR_DFEV7_VAL(val) (((val) & 0x1) << 7) |
| 463 | #define SYS2_RRLSR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV7) | ((val & 0x1) << 7)) |
| 464 | /* DFEV6 Reset Release */ |
| 465 | #define SYS2_RRLSR_DFEV6 (0x1 << 6) |
| 466 | #define SYS2_RRLSR_DFEV6_VAL(val) (((val) & 0x1) << 6) |
| 467 | #define SYS2_RRLSR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV6) | ((val & 0x1) << 6)) |
| 468 | /* DFEV5 Reset Release */ |
| 469 | #define SYS2_RRLSR_DFEV5 (0x1 << 5) |
| 470 | #define SYS2_RRLSR_DFEV5_VAL(val) (((val) & 0x1) << 5) |
| 471 | #define SYS2_RRLSR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV5) | ((val & 0x1) << 5)) |
| 472 | /* DFEV4 Reset Release */ |
| 473 | #define SYS2_RRLSR_DFEV4 (0x1 << 4) |
| 474 | #define SYS2_RRLSR_DFEV4_VAL(val) (((val) & 0x1) << 4) |
| 475 | #define SYS2_RRLSR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV4) | ((val & 0x1) << 4)) |
| 476 | /* DFEV3 Reset Release */ |
| 477 | #define SYS2_RRLSR_DFEV3 (0x1 << 3) |
| 478 | #define SYS2_RRLSR_DFEV3_VAL(val) (((val) & 0x1) << 3) |
| 479 | #define SYS2_RRLSR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV3) | ((val & 0x1) << 3)) |
| 480 | /* DFEV2 Reset Release */ |
| 481 | #define SYS2_RRLSR_DFEV2 (0x1 << 2) |
| 482 | #define SYS2_RRLSR_DFEV2_VAL(val) (((val) & 0x1) << 2) |
| 483 | #define SYS2_RRLSR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV2) | ((val & 0x1) << 2)) |
| 484 | /* DFEV1 Reset Release */ |
| 485 | #define SYS2_RRLSR_DFEV1 (0x1 << 1) |
| 486 | #define SYS2_RRLSR_DFEV1_VAL(val) (((val) & 0x1) << 1) |
| 487 | #define SYS2_RRLSR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV1) | ((val & 0x1) << 1)) |
| 488 | /* DFEV0 Reset Release */ |
| 489 | #define SYS2_RRLSR_DFEV0 (0x1) |
| 490 | #define SYS2_RRLSR_DFEV0_VAL(val) (((val) & 0x1)) |
| 491 | #define SYS2_RRLSR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV0) | ((val & 0x1))) |
| 492 | |
| 493 | #endif /* __SYS2_H */ |
| 494 | |
| 495 | |
