Root/target/linux/lantiq/files/arch/mips/lantiq/xway/clk.c

1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/io.h>
10#include <linux/export.h>
11#include <linux/init.h>
12#include <linux/clk.h>
13
14#include <asm/time.h>
15#include <asm/irq.h>
16#include <asm/div64.h>
17
18#include <lantiq_soc.h>
19
20#include "../clk.h"
21
22static unsigned int ltq_ram_clocks[] = {
23    CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
24#define DDR_HZ ltq_ram_clocks[ltq_cgu_r32(LTQ_CGU_SYS) & 0x3]
25
26#define BASIC_FREQUENCY_1 35328000
27#define BASIC_FREQUENCY_2 36000000
28#define BASIS_REQUENCY_USB 12000000
29
30#define GET_BITS(x, msb, lsb) \
31    (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
32
33/* legacy xway clock */
34#define LTQ_CGU_PLL0_CFG 0x0004
35#define LTQ_CGU_PLL1_CFG 0x0008
36#define LTQ_CGU_PLL2_CFG 0x000C
37#define LTQ_CGU_SYS 0x0010
38#define LTQ_CGU_UPDATE 0x0014
39#define LTQ_CGU_IF_CLK 0x0018
40#define LTQ_CGU_OSC_CON 0x001C
41#define LTQ_CGU_SMD 0x0020
42#define LTQ_CGU_CT1SR 0x0028
43#define LTQ_CGU_CT2SR 0x002C
44#define LTQ_CGU_PCMCR 0x0030
45#define LTQ_CGU_PCI_CR 0x0034
46#define LTQ_CGU_PD_PC 0x0038
47#define LTQ_CGU_FMR 0x003C
48
49#define CGU_PLL0_PHASE_DIVIDER_ENABLE \
50    (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 31))
51#define CGU_PLL0_BYPASS \
52    (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 30))
53#define CGU_PLL0_CFG_DSMSEL \
54    (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 28))
55#define CGU_PLL0_CFG_FRAC_EN \
56    (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 27))
57#define CGU_PLL1_SRC \
58    (ltq_cgu_r32(LTQ_CGU_PLL1_CFG) & (1 << 31))
59#define CGU_PLL2_PHASE_DIVIDER_ENABLE \
60    (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & (1 << 20))
61#define CGU_SYS_FPI_SEL (1 << 6)
62#define CGU_SYS_DDR_SEL 0x3
63#define CGU_PLL0_SRC (1 << 29)
64
65#define CGU_PLL0_CFG_PLLK GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 26, 17)
66#define CGU_PLL0_CFG_PLLN GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 12, 6)
67#define CGU_PLL0_CFG_PLLM GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 5, 2)
68#define CGU_PLL2_SRC GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 18, 17)
69#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 16, 13)
70
71/* vr9 clock */
72#define LTQ_CGU_SYS_VR9 0x0c
73#define LTQ_CGU_IF_CLK_VR9 0x24
74
75
76static unsigned int ltq_get_pll0_fdiv(void);
77
78static inline unsigned int get_input_clock(int pll)
79{
80    switch (pll) {
81    case 0:
82        if (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & CGU_PLL0_SRC)
83            return BASIS_REQUENCY_USB;
84        else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
85            return BASIC_FREQUENCY_1;
86        else
87            return BASIC_FREQUENCY_2;
88    case 1:
89        if (CGU_PLL1_SRC)
90            return BASIS_REQUENCY_USB;
91        else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
92            return BASIC_FREQUENCY_1;
93        else
94            return BASIC_FREQUENCY_2;
95    case 2:
96        switch (CGU_PLL2_SRC) {
97        case 0:
98            return ltq_get_pll0_fdiv();
99        case 1:
100            return CGU_PLL2_PHASE_DIVIDER_ENABLE ?
101                BASIC_FREQUENCY_1 :
102                BASIC_FREQUENCY_2;
103        case 2:
104            return BASIS_REQUENCY_USB;
105        }
106    default:
107        return 0;
108    }
109}
110
111static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den)
112{
113    u64 res, clock = get_input_clock(pll);
114
115    res = num * clock;
116    do_div(res, den);
117    return res;
118}
119
120static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N,
121    unsigned int K)
122{
123    unsigned int num = ((N + 1) << 10) + K;
124    unsigned int den = (M + 1) << 10;
125
126    return cal_dsm(pll, num, den);
127}
128
129static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N,
130    unsigned int K)
131{
132    unsigned int num = ((N + 1) << 11) + K + 512;
133    unsigned int den = (M + 1) << 11;
134
135    return cal_dsm(pll, num, den);
136}
137
138static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N,
139    unsigned int K)
140{
141    unsigned int num = K >= 512 ?
142        ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
143    unsigned int den = (M + 1) << 12;
144
145    return cal_dsm(pll, num, den);
146}
147
148static inline unsigned int dsm(int pll, unsigned int M, unsigned int N,
149    unsigned int K, unsigned int dsmsel, unsigned int phase_div_en)
150{
151    if (!dsmsel)
152        return mash_dsm(pll, M, N, K);
153    else if (!phase_div_en)
154        return mash_dsm(pll, M, N, K);
155    else
156        return ssff_dsm_2(pll, M, N, K);
157}
158
159static inline unsigned int ltq_get_pll0_fosc(void)
160{
161    if (CGU_PLL0_BYPASS)
162        return get_input_clock(0);
163    else
164        return !CGU_PLL0_CFG_FRAC_EN
165            ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0,
166                CGU_PLL0_CFG_DSMSEL,
167                CGU_PLL0_PHASE_DIVIDER_ENABLE)
168            : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN,
169                CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL,
170                CGU_PLL0_PHASE_DIVIDER_ENABLE);
171}
172
173static unsigned int ltq_get_pll0_fdiv(void)
174{
175    unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
176
177    return (ltq_get_pll0_fosc() + (div >> 1)) / div;
178}
179
180unsigned long ltq_danube_io_region_clock(void)
181{
182    unsigned int ret = ltq_get_pll0_fosc();
183
184    switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0x3) {
185    default:
186    case 0:
187        return (ret + 1) / 2;
188    case 1:
189        return (ret * 2 + 2) / 5;
190    case 2:
191        return (ret + 1) / 3;
192    case 3:
193        return (ret + 2) / 4;
194    }
195}
196
197unsigned long ltq_danube_fpi_bus_clock(int fpi)
198{
199    unsigned long ret = ltq_danube_io_region_clock();
200
201    if ((fpi == 2) && (ltq_cgu_r32(LTQ_CGU_SYS) & CGU_SYS_FPI_SEL))
202        ret >>= 1;
203    return ret;
204}
205
206unsigned long ltq_danube_fpi_hz(void)
207{
208    unsigned long ddr_clock = DDR_HZ;
209
210    if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40)
211        return ddr_clock >> 1;
212    return ddr_clock;
213}
214
215unsigned long ltq_danube_cpu_hz(void)
216{
217    switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0xc) {
218    case 0:
219        return CLOCK_333M;
220    case 4:
221        return DDR_HZ;
222    case 8:
223        return DDR_HZ << 1;
224    default:
225        return DDR_HZ >> 1;
226    }
227}
228
229unsigned long ltq_ar9_sys_hz(void)
230{
231    if (((ltq_cgu_r32(LTQ_CGU_SYS) >> 3) & 0x3) == 0x2)
232        return CLOCK_393M;
233    return CLOCK_333M;
234}
235
236unsigned long ltq_ar9_fpi_hz(void)
237{
238    unsigned long sys = ltq_ar9_sys_hz();
239
240    if (ltq_cgu_r32(LTQ_CGU_SYS) & BIT(0))
241        return sys;
242    return sys >> 1;
243}
244
245unsigned long ltq_ar9_cpu_hz(void)
246{
247    if (ltq_cgu_r32(LTQ_CGU_SYS) & BIT(2))
248        return ltq_ar9_fpi_hz();
249    else
250        return ltq_ar9_sys_hz();
251}
252
253unsigned long ltq_vr9_cpu_hz(void)
254{
255    unsigned int cpu_sel;
256    unsigned long clk;
257
258    cpu_sel = (ltq_cgu_r32(LTQ_CGU_SYS_VR9) >> 4) & 0xf;
259
260    switch (cpu_sel) {
261    case 0:
262        clk = CLOCK_600M;
263        break;
264    case 1:
265        clk = CLOCK_500M;
266        break;
267    case 2:
268        clk = CLOCK_393M;
269        break;
270    case 3:
271        clk = CLOCK_333M;
272        break;
273    case 5:
274    case 6:
275        clk = CLOCK_196_608M;
276        break;
277    case 7:
278        clk = CLOCK_167M;
279        break;
280    case 4:
281    case 8:
282    case 9:
283        clk = CLOCK_125M;
284        break;
285    default:
286        clk = 0;
287        break;
288    }
289
290    return clk;
291}
292
293unsigned long ltq_vr9_fpi_hz(void)
294{
295    unsigned int ocp_sel, cpu_clk;
296    unsigned long clk;
297
298    cpu_clk = ltq_vr9_cpu_hz();
299    ocp_sel = ltq_cgu_r32(LTQ_CGU_SYS_VR9) & 0x3;
300
301    switch (ocp_sel) {
302    case 0:
303        /* OCP ratio 1 */
304        clk = cpu_clk;
305        break;
306    case 2:
307        /* OCP ratio 2 */
308        clk = cpu_clk / 2;
309        break;
310    case 3:
311        /* OCP ratio 2.5 */
312        clk = (cpu_clk * 2) / 5;
313        break;
314    case 4:
315        /* OCP ratio 3 */
316        clk = cpu_clk / 3;
317        break;
318    default:
319        clk = 0;
320        break;
321    }
322
323    return clk;
324}
325
326unsigned long ltq_vr9_fpi_bus_clock(int fpi)
327{
328    return ltq_vr9_fpi_hz();
329}
330

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