Root/target/linux/lantiq/files/drivers/i2c/busses/i2c-falcon.c

1/*
2 * Lantiq FALC(tm) ON - I2C bus adapter
3 *
4 * Parts based on i2c-designware.c and other i2c drivers from Linux 2.6.33
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 *
20 * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
21 */
22
23/*
24 * CURRENT ISSUES:
25 * - no high speed support
26 * - supports only master mode
27 * - ten bit mode is not tested (no slave devices)
28 */
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/delay.h>
33#include <linux/slab.h>
34#include <linux/i2c.h>
35#include <linux/clk.h>
36#include <linux/errno.h>
37#include <linux/sched.h>
38#include <linux/err.h>
39#include <linux/interrupt.h>
40#include <linux/platform_device.h>
41#include <linux/io.h>
42#include <linux/err.h>
43#include <linux/gpio.h>
44
45#include <lantiq_soc.h>
46
47/* I2C Identification Register */
48/* Module ID */
49#define I2C_ID_ID_MASK 0x0000FF00
50/* field offset */
51#define I2C_ID_ID_OFFSET 8
52/* Revision */
53#define I2C_ID_REV_MASK 0x000000FF
54/* field offset */
55#define I2C_ID_REV_OFFSET 0
56
57/* I2C Error Interrupt Request Source Status Register */
58/* TXF_OFL */
59#define I2C_ERR_IRQSS_TXF_OFL 0x00000008
60/* TXF_UFL */
61#define I2C_ERR_IRQSS_TXF_UFL 0x00000004
62/* RXF_OFL */
63#define I2C_ERR_IRQSS_RXF_OFL 0x00000002
64/* RXF_UFL */
65#define I2C_ERR_IRQSS_RXF_UFL 0x00000001
66
67/* I2C Bus Status Register */
68/* Bus Status */
69#define I2C_BUS_STAT_BS_MASK 0x00000003
70/* I2C Bus is free. */
71#define I2C_BUS_STAT_BS_FREE 0x00000000
72/*
73 * The device is working as master and has claimed the control
74 * on the I2C-bus (busy master).
75 */
76#define I2C_BUS_STAT_BS_BM 0x00000002
77
78/* I2C Interrupt Clear Register */
79/* Clear */
80#define I2C_ICR_BREQ_INT_CLR 0x00000008
81/* Clear */
82#define I2C_ICR_LBREQ_INT_CLR 0x00000004
83
84/* I2C RUN Control Register */
85/* Enable */
86#define I2C_RUN_CTRL_RUN_EN 0x00000001
87
88/* I2C Kernel Clock Control Register */
89/* field offset */
90#define I2C_CLC_RMC_OFFSET 8
91/* Enable */
92#define I2C_IMSC_I2C_P_INT_EN 0x00000020
93/* Enable */
94#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010
95/* Enable */
96#define I2C_IMSC_BREQ_INT_EN 0x00000008
97/* Enable */
98#define I2C_IMSC_LBREQ_INT_EN 0x00000004
99
100/* I2C Fractional Divider Configuration Register */
101/* field offset */
102#define I2C_FDIV_CFG_INC_OFFSET 16
103/* field offset */
104#define I2C_FDIV_CFG_DEC_OFFSET 0
105
106/* I2C Fractional Divider (highspeed mode) Configuration Register */
107/* field offset */
108#define I2C_FDIV_HIGH_CFG_INC_OFFSET 16
109/* field offset */
110#define I2C_FDIV_HIGH_CFG_DEC_OFFSET 0
111
112/* I2C Address Register */
113/* Enable */
114#define I2C_ADDR_CFG_SOPE_EN 0x00200000
115/* Enable */
116#define I2C_ADDR_CFG_SONA_EN 0x00100000
117/* Enable */
118#define I2C_ADDR_CFG_MnS_EN 0x00080000
119
120/* I2C Protocol Interrupt Request Source Status Register */
121/* RX */
122#define I2C_P_IRQSS_RX 0x00000040
123/* TX_END */
124#define I2C_P_IRQSS_TX_END 0x00000020
125/* NACK */
126#define I2C_P_IRQSS_NACK 0x00000010
127/* AL */
128#define I2C_P_IRQSS_AL 0x00000008
129
130/* I2C Raw Interrupt Status Register */
131/* Read: Interrupt occurred. */
132#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020
133/* Read: Interrupt occurred. */
134#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010
135
136/* I2C End Data Control Register */
137/*
138 * Set End of Transmission - Note: Do not write '1' to this bit when bus is
139 * free. This will cause an abort after the first byte when a new transfer
140 * is started.
141 */
142#define I2C_ENDD_CTRL_SETEND 0x00000002
143/* TX FIFO Flow Control */
144#define I2C_FIFO_CFG_TXFC 0x00020000
145/* RX FIFO Flow Control */
146#define I2C_FIFO_CFG_RXFC 0x00010000
147/* Word aligned (character alignment of four characters) */
148#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000
149/* Word aligned (character alignment of four characters) */
150#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200
151/* 1 word */
152#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000
153/* 1 word */
154#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000
155
156
157/* I2C register structure */
158struct gpon_reg_i2c {
159    /* I2C Kernel Clock Control Register */
160    unsigned int clc; /* 0x00000000 */
161    /* Reserved */
162    unsigned int res_0; /* 0x00000004 */
163    /* I2C Identification Register */
164    unsigned int id; /* 0x00000008 */
165    /* Reserved */
166    unsigned int res_1; /* 0x0000000C */
167    /*
168     * I2C RUN Control Register - This register enables and disables the I2C
169     * peripheral. Before enabling, the I2C has to be configured properly.
170     * After enabling no configuration is possible
171     */
172    unsigned int run_ctrl; /* 0x00000010 */
173    /*
174     * I2C End Data Control Register - This register is used to either turn
175     * around the data transmission direction or to address another slave
176     * without sending a stop condition. Also the software can stop the
177     * slave-transmitter by sending a not-accolade when working as
178     * master-receiver or even stop data transmission immediately when
179     * operating as master-transmitter. The writing to the bits of this
180     * control register is only effective when in MASTER RECEIVES BYTES,
181     * MASTER TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state
182     */
183    unsigned int endd_ctrl; /* 0x00000014 */
184    /*
185     * I2C Fractional Divider Configuration Register - These register is
186     * used to program the fractional divider of the I2C bus. Before the
187     * peripheral is switched on by setting the RUN-bit the two (fixed)
188     * values for the two operating frequencies are programmed into these
189     * (configuration) registers. The Register FDIV_HIGH_CFG has the same
190     * layout as I2C_FDIV_CFG.
191     */
192    unsigned int fdiv_cfg; /* 0x00000018 */
193    /*
194     * I2C Fractional Divider (highspeed mode) Configuration Register
195     * These register is used to program the fractional divider of the I2C
196     * bus. Before the peripheral is switched on by setting the RUN-bit the
197     * two (fixed) values for the two operating frequencies are programmed
198     * into these (configuration) registers. The Register FDIV_CFG has the
199     * same layout as I2C_FDIV_CFG.
200     */
201    unsigned int fdiv_high_cfg; /* 0x0000001C */
202    /* I2C Address Configuration Register */
203    unsigned int addr_cfg; /* 0x00000020 */
204    /*
205     * I2C Bus Status Register - This register gives a status information
206     * of the I2C. This additional information can be used by the software
207     * to start proper actions.
208     */
209    unsigned int bus_stat; /* 0x00000024 */
210    /* I2C FIFO Configuration Register */
211    unsigned int fifo_cfg; /* 0x00000028 */
212    /* I2C Maximum Received Packet Size Register */
213    unsigned int mrps_ctrl; /* 0x0000002C */
214    /* I2C Received Packet Size Status Register */
215    unsigned int rps_stat; /* 0x00000030 */
216    /* I2C Transmit Packet Size Register */
217    unsigned int tps_ctrl; /* 0x00000034 */
218    /* I2C Filled FIFO Stages Status Register */
219    unsigned int ffs_stat; /* 0x00000038 */
220    /* Reserved */
221    unsigned int res_2; /* 0x0000003C */
222    /* I2C Timing Configuration Register */
223    unsigned int tim_cfg; /* 0x00000040 */
224    /* Reserved */
225        unsigned int res_3[7]; /* 0x00000044 */
226    /* I2C Error Interrupt Request Source Mask Register */
227    unsigned int err_irqsm; /* 0x00000060 */
228    /* I2C Error Interrupt Request Source Status Register */
229    unsigned int err_irqss; /* 0x00000064 */
230    /* I2C Error Interrupt Request Source Clear Register */
231    unsigned int err_irqsc; /* 0x00000068 */
232    /* Reserved */
233    unsigned int res_4; /* 0x0000006C */
234    /* I2C Protocol Interrupt Request Source Mask Register */
235    unsigned int p_irqsm; /* 0x00000070 */
236    /* I2C Protocol Interrupt Request Source Status Register */
237    unsigned int p_irqss; /* 0x00000074 */
238    /* I2C Protocol Interrupt Request Source Clear Register */
239    unsigned int p_irqsc; /* 0x00000078 */
240    /* Reserved */
241    unsigned int res_5; /* 0x0000007C */
242    /* I2C Raw Interrupt Status Register */
243    unsigned int ris; /* 0x00000080 */
244    /* I2C Interrupt Mask Control Register */
245    unsigned int imsc; /* 0x00000084 */
246    /* I2C Masked Interrupt Status Register */
247    unsigned int mis; /* 0x00000088 */
248    /* I2C Interrupt Clear Register */
249    unsigned int icr; /* 0x0000008C */
250    /* I2C Interrupt Set Register */
251    unsigned int isr; /* 0x00000090 */
252    /* I2C DMA Enable Register */
253    unsigned int dmae; /* 0x00000094 */
254    /* Reserved */
255    unsigned int res_6[8154]; /* 0x00000098 */
256    /* I2C Transmit Data Register */
257    unsigned int txd; /* 0x00008000 */
258    /* Reserved */
259    unsigned int res_7[4095]; /* 0x00008004 */
260    /* I2C Receive Data Register */
261    unsigned int rxd; /* 0x0000C000 */
262    /* Reserved */
263    unsigned int res_8[4095]; /* 0x0000C004 */
264};
265
266/* mapping for access macros */
267#define i2c ((struct gpon_reg_i2c *)priv->membase)
268#define reg_r32(reg) __raw_readl(reg)
269#define reg_w32(val, reg) __raw_writel(val, reg)
270#define reg_w32_mask(clear, set, reg) \
271                reg_w32((reg_r32(reg) & ~(clear)) | (set), reg)
272#define reg_r32_table(reg, idx) reg_r32(&((uint32_t *)&reg)[idx])
273#define reg_w32_table(val, reg, idx) reg_w32(val, &((uint32_t *)&reg)[idx])
274
275#define i2c_r32(reg) reg_r32(&i2c->reg)
276#define i2c_w32(val, reg) reg_w32(val, &i2c->reg)
277#define i2c_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &i2c->reg)
278
279#define DRV_NAME "i2c-falcon"
280#define DRV_VERSION "1.01"
281
282#define FALCON_I2C_BUSY_TIMEOUT 20 /* ms */
283
284#ifdef DEBUG
285#define FALCON_I2C_XFER_TIMEOUT (25 * HZ)
286#else
287#define FALCON_I2C_XFER_TIMEOUT HZ
288#endif
289#if defined(DEBUG) && 0
290#define PRINTK(arg...) pr_info(arg)
291#else
292#define PRINTK(arg...) do {} while (0)
293#endif
294
295#define FALCON_I2C_IMSC_DEFAULT_MASK (I2C_IMSC_I2C_P_INT_EN | \
296                     I2C_IMSC_I2C_ERR_INT_EN)
297
298#define FALCON_I2C_ARB_LOST (1 << 0)
299#define FALCON_I2C_NACK (1 << 1)
300#define FALCON_I2C_RX_UFL (1 << 2)
301#define FALCON_I2C_RX_OFL (1 << 3)
302#define FALCON_I2C_TX_UFL (1 << 4)
303#define FALCON_I2C_TX_OFL (1 << 5)
304
305struct falcon_i2c {
306    struct mutex mutex;
307
308    enum {
309        FALCON_I2C_MODE_100 = 1,
310        FALCON_I2C_MODE_400 = 2,
311        FALCON_I2C_MODE_3400 = 3
312    } mode; /* current speed mode */
313
314    struct clk *clk; /* clock input for i2c hardware block */
315    struct gpon_reg_i2c __iomem *membase; /* base of mapped registers */
316    int irq_lb, irq_b, irq_err, irq_p; /* last burst, burst, error,
317                           protocol IRQs */
318
319    struct i2c_adapter adap;
320    struct device *dev;
321
322    struct completion cmd_complete;
323
324    /* message transfer data */
325    /* current message */
326    struct i2c_msg *current_msg;
327    /* number of messages to handle */
328    int msgs_num;
329    /* current buffer */
330    u8 *msg_buf;
331    /* remaining length of current buffer */
332    u32 msg_buf_len;
333    /* error status of the current transfer */
334    int msg_err;
335
336    /* master status codes */
337    enum {
338        STATUS_IDLE,
339        STATUS_ADDR, /* address phase */
340        STATUS_WRITE,
341        STATUS_READ,
342        STATUS_READ_END,
343        STATUS_STOP
344    } status;
345};
346
347static irqreturn_t falcon_i2c_isr(int irq, void *dev_id);
348
349static inline void enable_burst_irq(struct falcon_i2c *priv)
350{
351    i2c_w32_mask(0, I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, imsc);
352}
353static inline void disable_burst_irq(struct falcon_i2c *priv)
354{
355    i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, 0, imsc);
356}
357
358static void prepare_msg_send_addr(struct falcon_i2c *priv)
359{
360    struct i2c_msg *msg = priv->current_msg;
361    int rd = !!(msg->flags & I2C_M_RD);
362    u16 addr = msg->addr;
363
364    /* new i2c_msg */
365    priv->msg_buf = msg->buf;
366    priv->msg_buf_len = msg->len;
367    if (rd)
368        priv->status = STATUS_READ;
369    else
370        priv->status = STATUS_WRITE;
371
372    /* send slave address */
373    if (msg->flags & I2C_M_TEN) {
374        i2c_w32(0xf0 | ((addr & 0x300) >> 7) | rd, txd);
375        i2c_w32(addr & 0xff, txd);
376    } else
377        i2c_w32((addr & 0x7f) << 1 | rd, txd);
378}
379
380static void set_tx_len(struct falcon_i2c *priv)
381{
382    struct i2c_msg *msg = priv->current_msg;
383    int len = (msg->flags & I2C_M_TEN) ? 2 : 1;
384
385    PRINTK("set_tx_len %cX\n", (msg->flags & I2C_M_RD) ? ('R') : ('T'));
386
387    priv->status = STATUS_ADDR;
388
389    if (!(msg->flags & I2C_M_RD)) {
390        len += msg->len;
391    } else {
392        /* set maximum received packet size (before rx int!) */
393        i2c_w32(msg->len, mrps_ctrl);
394    }
395    i2c_w32(len, tps_ctrl);
396    enable_burst_irq(priv);
397}
398
399static int falcon_i2c_hw_init(struct i2c_adapter *adap)
400{
401    struct falcon_i2c *priv = i2c_get_adapdata(adap);
402
403    /* disable bus */
404    i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
405
406#ifndef DEBUG
407    /* set normal operation clock divider */
408    i2c_w32(1 << I2C_CLC_RMC_OFFSET, clc);
409#else
410    /* for debugging a higher divider value! */
411    i2c_w32(0xF0 << I2C_CLC_RMC_OFFSET, clc);
412#endif
413
414    /* set frequency */
415    if (priv->mode == FALCON_I2C_MODE_100) {
416        dev_dbg(priv->dev, "set standard mode (100 kHz)\n");
417        i2c_w32(0, fdiv_high_cfg);
418        i2c_w32((1 << I2C_FDIV_CFG_INC_OFFSET) |
419            (499 << I2C_FDIV_CFG_DEC_OFFSET),
420            fdiv_cfg);
421    } else if (priv->mode == FALCON_I2C_MODE_400) {
422        dev_dbg(priv->dev, "set fast mode (400 kHz)\n");
423        i2c_w32(0, fdiv_high_cfg);
424        i2c_w32((1 << I2C_FDIV_CFG_INC_OFFSET) |
425            (124 << I2C_FDIV_CFG_DEC_OFFSET),
426            fdiv_cfg);
427    } else if (priv->mode == FALCON_I2C_MODE_3400) {
428        dev_dbg(priv->dev, "set high mode (3.4 MHz)\n");
429        i2c_w32(0, fdiv_cfg);
430        /* TODO recalculate value for 100MHz input */
431        i2c_w32((41 << I2C_FDIV_HIGH_CFG_INC_OFFSET) |
432            (152 << I2C_FDIV_HIGH_CFG_DEC_OFFSET),
433            fdiv_high_cfg);
434    } else {
435        dev_warn(priv->dev, "unknown mode\n");
436        return -ENODEV;
437    }
438
439    /* configure fifo */
440    i2c_w32(I2C_FIFO_CFG_TXFC | /* tx fifo as flow controller */
441        I2C_FIFO_CFG_RXFC | /* rx fifo as flow controller */
442        I2C_FIFO_CFG_TXFA_TXFA2 | /* tx fifo 4-byte aligned */
443        I2C_FIFO_CFG_RXFA_RXFA2 | /* rx fifo 4-byte aligned */
444        I2C_FIFO_CFG_TXBS_TXBS0 | /* tx fifo burst size is 1 word */
445        I2C_FIFO_CFG_RXBS_RXBS0, /* rx fifo burst size is 1 word */
446        fifo_cfg);
447
448    /* configure address */
449    i2c_w32(I2C_ADDR_CFG_SOPE_EN | /* generate stop when no more data
450                       in the fifo */
451        I2C_ADDR_CFG_SONA_EN | /* generate stop when NA received */
452        I2C_ADDR_CFG_MnS_EN | /* we are master device */
453        0, /* our slave address (not used!) */
454        addr_cfg);
455
456    /* enable bus */
457    i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl);
458
459    return 0;
460}
461
462static int falcon_i2c_wait_bus_not_busy(struct falcon_i2c *priv)
463{
464    int timeout = FALCON_I2C_BUSY_TIMEOUT;
465
466    while ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK)
467                 != I2C_BUS_STAT_BS_FREE) {
468        if (timeout <= 0) {
469            dev_warn(priv->dev, "timeout waiting for bus ready\n");
470            return -ETIMEDOUT;
471        }
472        timeout--;
473        mdelay(1);
474    }
475
476    return 0;
477}
478
479static void falcon_i2c_tx(struct falcon_i2c *priv, int last)
480{
481    if (priv->msg_buf_len && priv->msg_buf) {
482        i2c_w32(*priv->msg_buf, txd);
483
484        if (--priv->msg_buf_len)
485            priv->msg_buf++;
486        else
487            priv->msg_buf = NULL;
488    } else
489        last = 1;
490
491    if (last)
492        disable_burst_irq(priv);
493}
494
495static void falcon_i2c_rx(struct falcon_i2c *priv, int last)
496{
497    u32 fifo_stat, timeout;
498    if (priv->msg_buf_len && priv->msg_buf) {
499        timeout = 5000000;
500        do {
501            fifo_stat = i2c_r32(ffs_stat);
502        } while (!fifo_stat && --timeout);
503        if (!timeout) {
504            last = 1;
505            PRINTK("\nrx timeout\n");
506            goto err;
507        }
508        while (fifo_stat) {
509            *priv->msg_buf = i2c_r32(rxd);
510            if (--priv->msg_buf_len)
511                priv->msg_buf++;
512            else {
513                priv->msg_buf = NULL;
514                last = 1;
515                break;
516            }
517            #if 0
518            fifo_stat = i2c_r32(ffs_stat);
519            #else
520            /* do not read more than burst size, otherwise no "last
521            burst" is generated and the transaction is blocked! */
522            fifo_stat = 0;
523            #endif
524        }
525    } else {
526        last = 1;
527    }
528err:
529    if (last) {
530        disable_burst_irq(priv);
531
532        if (priv->status == STATUS_READ_END) {
533            /* do the STATUS_STOP and complete() here, as sometimes
534               the tx_end is already seen before this is finished */
535            priv->status = STATUS_STOP;
536            complete(&priv->cmd_complete);
537        } else {
538            i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl);
539            priv->status = STATUS_READ_END;
540        }
541    }
542}
543
544static void falcon_i2c_xfer_init(struct falcon_i2c *priv)
545{
546    /* enable interrupts */
547    i2c_w32(FALCON_I2C_IMSC_DEFAULT_MASK, imsc);
548
549    /* trigger transfer of first msg */
550    set_tx_len(priv);
551}
552
553static void dump_msgs(struct i2c_msg msgs[], int num, int rx)
554{
555#if defined(DEBUG)
556    int i, j;
557    pr_info("Messages %d %s\n", num, rx ? "out" : "in");
558    for (i = 0; i < num; i++) {
559        pr_info("%2d %cX Msg(%d) addr=0x%X: ", i,
560            (msgs[i].flags & I2C_M_RD) ? ('R') : ('T'),
561            msgs[i].len, msgs[i].addr);
562        if (!(msgs[i].flags & I2C_M_RD) || rx) {
563            for (j = 0; j < msgs[i].len; j++)
564                printk("%02X ", msgs[i].buf[j]);
565        }
566        printk("\n");
567    }
568#endif
569}
570
571static void falcon_i2c_release_bus(struct falcon_i2c *priv)
572{
573    if ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_BM)
574        i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl);
575}
576
577static int falcon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
578               int num)
579{
580    struct falcon_i2c *priv = i2c_get_adapdata(adap);
581    int ret;
582
583    dev_dbg(priv->dev, "xfer %u messages\n", num);
584    dump_msgs(msgs, num, 0);
585
586    mutex_lock(&priv->mutex);
587
588    INIT_COMPLETION(priv->cmd_complete);
589    priv->current_msg = msgs;
590    priv->msgs_num = num;
591    priv->msg_err = 0;
592    priv->status = STATUS_IDLE;
593
594    /* wait for the bus to become ready */
595    ret = falcon_i2c_wait_bus_not_busy(priv);
596    if (ret)
597        goto done;
598
599    while (priv->msgs_num) {
600        /* start the transfers */
601        falcon_i2c_xfer_init(priv);
602
603        /* wait for transfers to complete */
604        ret = wait_for_completion_interruptible_timeout(
605            &priv->cmd_complete, FALCON_I2C_XFER_TIMEOUT);
606        if (ret == 0) {
607            dev_err(priv->dev, "controller timed out\n");
608            falcon_i2c_hw_init(adap);
609            ret = -ETIMEDOUT;
610            goto done;
611        } else if (ret < 0)
612            goto done;
613
614        if (priv->msg_err) {
615            if (priv->msg_err & FALCON_I2C_NACK)
616                ret = -ENXIO;
617            else
618                ret = -EREMOTEIO;
619            goto done;
620        }
621        if (--priv->msgs_num)
622            priv->current_msg++;
623    }
624    /* no error? */
625    ret = num;
626
627done:
628    falcon_i2c_release_bus(priv);
629
630    mutex_unlock(&priv->mutex);
631
632    if (ret >= 0)
633        dump_msgs(msgs, num, 1);
634
635    PRINTK("XFER ret %d\n", ret);
636    return ret;
637}
638
639static irqreturn_t falcon_i2c_isr_burst(int irq, void *dev_id)
640{
641    struct falcon_i2c *priv = dev_id;
642    struct i2c_msg *msg = priv->current_msg;
643    int last = (irq == priv->irq_lb);
644
645    if (last)
646        PRINTK("LB ");
647    else
648        PRINTK("B ");
649
650    if (msg->flags & I2C_M_RD) {
651        switch (priv->status) {
652        case STATUS_ADDR:
653            PRINTK("X");
654            prepare_msg_send_addr(priv);
655            disable_burst_irq(priv);
656            break;
657        case STATUS_READ:
658        case STATUS_READ_END:
659            PRINTK("R");
660            falcon_i2c_rx(priv, last);
661            break;
662        default:
663            disable_burst_irq(priv);
664            PRINTK("Status R %d\n", priv->status);
665            break;
666        }
667    } else {
668        switch (priv->status) {
669        case STATUS_ADDR:
670            PRINTK("x");
671            prepare_msg_send_addr(priv);
672            break;
673        case STATUS_WRITE:
674            PRINTK("w");
675            falcon_i2c_tx(priv, last);
676            break;
677        default:
678            disable_burst_irq(priv);
679            PRINTK("Status W %d\n", priv->status);
680            break;
681        }
682    }
683
684    i2c_w32(I2C_ICR_BREQ_INT_CLR | I2C_ICR_LBREQ_INT_CLR, icr);
685    return IRQ_HANDLED;
686}
687
688static void falcon_i2c_isr_prot(struct falcon_i2c *priv)
689{
690    u32 i_pro = i2c_r32(p_irqss);
691
692    PRINTK("i2c-p");
693
694    /* not acknowledge */
695    if (i_pro & I2C_P_IRQSS_NACK) {
696        priv->msg_err |= FALCON_I2C_NACK;
697        PRINTK(" nack");
698    }
699
700    /* arbitration lost */
701    if (i_pro & I2C_P_IRQSS_AL) {
702        priv->msg_err |= FALCON_I2C_ARB_LOST;
703        PRINTK(" arb-lost");
704    }
705    /* tx -> rx switch */
706    if (i_pro & I2C_P_IRQSS_RX)
707        PRINTK(" rx");
708
709    /* tx end */
710    if (i_pro & I2C_P_IRQSS_TX_END)
711        PRINTK(" txend");
712    PRINTK("\n");
713
714    if (!priv->msg_err) {
715        /* tx -> rx switch */
716        if (i_pro & I2C_P_IRQSS_RX) {
717            priv->status = STATUS_READ;
718            enable_burst_irq(priv);
719        }
720        if (i_pro & I2C_P_IRQSS_TX_END) {
721            if (priv->status == STATUS_READ)
722                priv->status = STATUS_READ_END;
723            else {
724                disable_burst_irq(priv);
725                priv->status = STATUS_STOP;
726            }
727        }
728    }
729
730    i2c_w32(i_pro, p_irqsc);
731}
732
733static irqreturn_t falcon_i2c_isr(int irq, void *dev_id)
734{
735    u32 i_raw, i_err = 0;
736    struct falcon_i2c *priv = dev_id;
737
738    i_raw = i2c_r32(mis);
739    PRINTK("i_raw 0x%08X\n", i_raw);
740
741    /* error interrupt */
742    if (i_raw & I2C_RIS_I2C_ERR_INT_INTOCC) {
743        i_err = i2c_r32(err_irqss);
744        PRINTK("i_err 0x%08X bus_stat 0x%04X\n",
745            i_err, i2c_r32(bus_stat));
746
747        /* tx fifo overflow (8) */
748        if (i_err & I2C_ERR_IRQSS_TXF_OFL)
749            priv->msg_err |= FALCON_I2C_TX_OFL;
750
751        /* tx fifo underflow (4) */
752        if (i_err & I2C_ERR_IRQSS_TXF_UFL)
753            priv->msg_err |= FALCON_I2C_TX_UFL;
754
755        /* rx fifo overflow (2) */
756        if (i_err & I2C_ERR_IRQSS_RXF_OFL)
757            priv->msg_err |= FALCON_I2C_RX_OFL;
758
759        /* rx fifo underflow (1) */
760        if (i_err & I2C_ERR_IRQSS_RXF_UFL)
761            priv->msg_err |= FALCON_I2C_RX_UFL;
762
763        i2c_w32(i_err, err_irqsc);
764    }
765
766    /* protocol interrupt */
767    if (i_raw & I2C_RIS_I2C_P_INT_INTOCC)
768        falcon_i2c_isr_prot(priv);
769
770    if ((priv->msg_err) || (priv->status == STATUS_STOP))
771        complete(&priv->cmd_complete);
772
773    return IRQ_HANDLED;
774}
775
776static u32 falcon_i2c_functionality(struct i2c_adapter *adap)
777{
778    return I2C_FUNC_I2C |
779        I2C_FUNC_10BIT_ADDR |
780        I2C_FUNC_SMBUS_EMUL;
781}
782
783static struct i2c_algorithm falcon_i2c_algorithm = {
784    .master_xfer = falcon_i2c_xfer,
785    .functionality = falcon_i2c_functionality,
786};
787
788static int __devinit falcon_i2c_probe(struct platform_device *pdev)
789{
790    int ret = 0;
791    struct falcon_i2c *priv;
792    struct i2c_adapter *adap;
793    struct resource *mmres, *ioarea,
794            *irqres_lb, *irqres_b, *irqres_err, *irqres_p;
795    struct clk *clk;
796
797    dev_dbg(&pdev->dev, "probing\n");
798
799    mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
800    irqres_lb = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
801                         "i2c_lb");
802    irqres_b = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "i2c_b");
803    irqres_err = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
804                          "i2c_err");
805    irqres_p = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "i2c_p");
806
807    if (!mmres || !irqres_lb || !irqres_b || !irqres_err || !irqres_p) {
808        dev_err(&pdev->dev, "no resources\n");
809        return -ENODEV;
810    }
811
812    clk = clk_get_fpi();
813    if (IS_ERR(clk)) {
814        dev_err(&pdev->dev, "failed to get fpi clk\n");
815        return -ENOENT;
816    }
817
818    if (clk_get_rate(clk) != 100000000) {
819        dev_err(&pdev->dev, "input clock is not 100MHz\n");
820        return -ENOENT;
821    }
822    clk = clk_get(&pdev->dev, NULL);
823    if (IS_ERR(clk)) {
824        dev_err(&pdev->dev, "failed to get i2c clk\n");
825        return -ENOENT;
826    }
827    clk_activate(clk);
828    /* allocate private data */
829    priv = kzalloc(sizeof(*priv), GFP_KERNEL);
830    if (!priv) {
831        dev_err(&pdev->dev, "can't allocate private data\n");
832        return -ENOMEM;
833    }
834
835    adap = &priv->adap;
836    i2c_set_adapdata(adap, priv);
837    adap->owner = THIS_MODULE;
838    adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
839    strlcpy(adap->name, DRV_NAME "-adapter", sizeof(adap->name));
840    adap->algo = &falcon_i2c_algorithm;
841
842    priv->mode = FALCON_I2C_MODE_100;
843    priv->clk = clk;
844    priv->dev = &pdev->dev;
845
846    init_completion(&priv->cmd_complete);
847    mutex_init(&priv->mutex);
848
849    if (ltq_gpio_request(&pdev->dev, 107, 0, 0, DRV_NAME":sda") ||
850        ltq_gpio_request(&pdev->dev, 108, 0, 0, DRV_NAME":scl"))
851    {
852        dev_err(&pdev->dev, "I2C gpios not available\n");
853        ret = -ENXIO;
854        goto err_free_priv;
855    }
856
857    ioarea = request_mem_region(mmres->start, resource_size(mmres),
858                     pdev->name);
859
860    if (ioarea == NULL) {
861        dev_err(&pdev->dev, "I2C region already claimed\n");
862        ret = -ENXIO;
863        goto err_free_gpio;
864    }
865
866    /* map memory */
867    priv->membase = ioremap_nocache(mmres->start & ~KSEG1,
868        resource_size(mmres));
869    if (priv->membase == NULL) {
870        ret = -ENOMEM;
871        goto err_release_region;
872    }
873
874    priv->irq_lb = irqres_lb->start;
875    ret = request_irq(priv->irq_lb, falcon_i2c_isr_burst, IRQF_DISABLED,
876              irqres_lb->name, priv);
877    if (ret) {
878        dev_err(&pdev->dev, "can't get last burst IRQ %d\n",
879                    irqres_lb->start);
880        ret = -ENODEV;
881        goto err_unmap_mem;
882    }
883
884    priv->irq_b = irqres_b->start;
885    ret = request_irq(priv->irq_b, falcon_i2c_isr_burst, IRQF_DISABLED,
886              irqres_b->name, priv);
887    if (ret) {
888        dev_err(&pdev->dev, "can't get burst IRQ %d\n",
889                    irqres_b->start);
890        ret = -ENODEV;
891        goto err_free_lb_irq;
892    }
893
894    priv->irq_err = irqres_err->start;
895    ret = request_irq(priv->irq_err, falcon_i2c_isr, IRQF_DISABLED,
896              irqres_err->name, priv);
897    if (ret) {
898        dev_err(&pdev->dev, "can't get error IRQ %d\n",
899                    irqres_err->start);
900        ret = -ENODEV;
901        goto err_free_b_irq;
902    }
903
904    priv->irq_p = irqres_p->start;
905    ret = request_irq(priv->irq_p, falcon_i2c_isr, IRQF_DISABLED,
906              irqres_p->name, priv);
907    if (ret) {
908        dev_err(&pdev->dev, "can't get protocol IRQ %d\n",
909                    irqres_p->start);
910        ret = -ENODEV;
911        goto err_free_err_irq;
912    }
913
914    dev_dbg(&pdev->dev, "mapped io-space to %p\n", priv->membase);
915    dev_dbg(&pdev->dev, "use IRQs %d, %d, %d, %d\n", irqres_lb->start,
916        irqres_b->start, irqres_err->start, irqres_p->start);
917
918    /* add our adapter to the i2c stack */
919    ret = i2c_add_numbered_adapter(adap);
920    if (ret) {
921        dev_err(&pdev->dev, "can't register I2C adapter\n");
922        goto err_free_p_irq;
923    }
924
925    platform_set_drvdata(pdev, priv);
926    i2c_set_adapdata(adap, priv);
927
928    /* print module version information */
929    dev_dbg(&pdev->dev, "module id=%u revision=%u\n",
930        (i2c_r32(id) & I2C_ID_ID_MASK) >> I2C_ID_ID_OFFSET,
931        (i2c_r32(id) & I2C_ID_REV_MASK) >> I2C_ID_REV_OFFSET);
932
933    /* initialize HW */
934    ret = falcon_i2c_hw_init(adap);
935    if (ret) {
936        dev_err(&pdev->dev, "can't configure adapter\n");
937        goto err_remove_adapter;
938    }
939
940    dev_info(&pdev->dev, "version %s\n", DRV_VERSION);
941
942    return 0;
943
944err_remove_adapter:
945    i2c_del_adapter(adap);
946    platform_set_drvdata(pdev, NULL);
947
948err_free_p_irq:
949    free_irq(priv->irq_p, priv);
950
951err_free_err_irq:
952    free_irq(priv->irq_err, priv);
953
954err_free_b_irq:
955    free_irq(priv->irq_b, priv);
956
957err_free_lb_irq:
958    free_irq(priv->irq_lb, priv);
959
960err_unmap_mem:
961    iounmap(priv->membase);
962
963err_release_region:
964    release_mem_region(mmres->start, resource_size(mmres));
965
966err_free_gpio:
967    gpio_free(108);
968    gpio_free(107);
969
970err_free_priv:
971    kfree(priv);
972
973    return ret;
974}
975
976static int __devexit falcon_i2c_remove(struct platform_device *pdev)
977{
978    struct falcon_i2c *priv = platform_get_drvdata(pdev);
979    struct resource *mmres;
980
981    /* disable bus */
982    i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
983
984    /* remove driver */
985    platform_set_drvdata(pdev, NULL);
986    i2c_del_adapter(&priv->adap);
987
988    free_irq(priv->irq_lb, priv);
989    free_irq(priv->irq_b, priv);
990    free_irq(priv->irq_err, priv);
991    free_irq(priv->irq_p, priv);
992
993    iounmap(priv->membase);
994
995    gpio_free(108);
996    gpio_free(107);
997
998    kfree(priv);
999
1000    mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1001    release_mem_region(mmres->start, resource_size(mmres));
1002
1003    dev_dbg(&pdev->dev, "removed\n");
1004
1005    return 0;
1006}
1007
1008static struct platform_driver falcon_i2c_driver = {
1009    .probe = falcon_i2c_probe,
1010    .remove = __devexit_p(falcon_i2c_remove),
1011    .driver = {
1012        .name = DRV_NAME,
1013        .owner = THIS_MODULE,
1014    },
1015};
1016
1017static int __init falcon_i2c_init(void)
1018{
1019    int ret;
1020
1021    ret = platform_driver_register(&falcon_i2c_driver);
1022
1023    if (ret)
1024        pr_debug(DRV_NAME ": can't register platform driver\n");
1025
1026    return ret;
1027}
1028
1029static void __exit falcon_i2c_exit(void)
1030{
1031    platform_driver_unregister(&falcon_i2c_driver);
1032}
1033
1034module_init(falcon_i2c_init);
1035module_exit(falcon_i2c_exit);
1036
1037MODULE_DESCRIPTION("Lantiq FALC(tm) ON - I2C bus adapter");
1038MODULE_ALIAS("platform:" DRV_NAME);
1039MODULE_LICENSE("GPL");
1040MODULE_VERSION(DRV_VERSION);
1041

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