Root/target/linux/lantiq/files/drivers/net/ethernet/lantiq_vrx200.c

1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
16 */
17
18#include <linux/kernel.h>
19#include <linux/slab.h>
20#include <linux/errno.h>
21#include <linux/types.h>
22#include <linux/interrupt.h>
23#include <linux/uaccess.h>
24#include <linux/in.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/phy.h>
28#include <linux/ip.h>
29#include <linux/tcp.h>
30#include <linux/skbuff.h>
31#include <linux/mm.h>
32#include <linux/platform_device.h>
33#include <linux/ethtool.h>
34#include <linux/init.h>
35#include <linux/delay.h>
36#include <linux/io.h>
37#include <linux/dma-mapping.h>
38#include <linux/module.h>
39#include <linux/clk.h>
40
41#include <asm/checksum.h>
42
43#include <lantiq_soc.h>
44#include <xway_dma.h>
45#include <lantiq_platform.h>
46
47#define LTQ_SWITCH_BASE 0x1E108000
48#define LTQ_SWITCH_CORE_BASE LTQ_SWITCH_BASE
49#define LTQ_SWITCH_TOP_PDI_BASE LTQ_SWITCH_CORE_BASE
50#define LTQ_SWITCH_BM_PDI_BASE (LTQ_SWITCH_CORE_BASE + 4 * 0x40)
51#define LTQ_SWITCH_MAC_PDI_0_BASE (LTQ_SWITCH_CORE_BASE + 4 * 0x900)
52#define LTQ_SWITCH_MAC_PDI_X_BASE(x) (LTQ_SWITCH_MAC_PDI_0_BASE + x * 0x30)
53#define LTQ_SWITCH_TOPLEVEL_BASE (LTQ_SWITCH_BASE + 4 * 0xC40)
54#define LTQ_SWITCH_MDIO_PDI_BASE (LTQ_SWITCH_TOPLEVEL_BASE)
55#define LTQ_SWITCH_MII_PDI_BASE (LTQ_SWITCH_TOPLEVEL_BASE + 4 * 0x36)
56#define LTQ_SWITCH_PMAC_PDI_BASE (LTQ_SWITCH_TOPLEVEL_BASE + 4 * 0x82)
57
58#define LTQ_ETHSW_MAC_CTRL0_PADEN (1 << 8)
59#define LTQ_ETHSW_MAC_CTRL0_FCS (1 << 7)
60#define LTQ_ETHSW_MAC_CTRL1_SHORTPRE (1 << 8)
61#define LTQ_ETHSW_MAC_CTRL2_MLEN (1 << 3)
62#define LTQ_ETHSW_MAC_CTRL2_LCHKL (1 << 2)
63#define LTQ_ETHSW_MAC_CTRL2_LCHKS_DIS 0
64#define LTQ_ETHSW_MAC_CTRL2_LCHKS_UNTAG 1
65#define LTQ_ETHSW_MAC_CTRL2_LCHKS_TAG 2
66#define LTQ_ETHSW_MAC_CTRL6_RBUF_DLY_WP_SHIFT 9
67#define LTQ_ETHSW_MAC_CTRL6_RXBUF_BYPASS (1 << 6)
68#define LTQ_ETHSW_GLOB_CTRL_SE (1 << 15)
69#define LTQ_ETHSW_MDC_CFG1_MCEN (1 << 8)
70#define LTQ_ETHSW_PMAC_HD_CTL_FC (1 << 10)
71#define LTQ_ETHSW_PMAC_HD_CTL_RC (1 << 4)
72#define LTQ_ETHSW_PMAC_HD_CTL_AC (1 << 2)
73#define ADVERTIZE_MPD (1 << 10)
74
75#define MDIO_DEVAD_NONE (-1)
76
77#define LTQ_ETH_RX_BUFFER_CNT PKTBUFSRX
78
79#define LTQ_MDIO_DRV_NAME "ltq-mdio"
80#define LTQ_ETH_DRV_NAME "ltq-eth"
81
82#define LTQ_ETHSW_MAX_GMAC 1
83#define LTQ_ETHSW_PMAC 1
84
85#define ltq_setbits(a, set) \
86        ltq_w32(ltq_r32(a) | (set), a)
87
88enum ltq_reset_modules {
89    LTQ_RESET_CORE,
90    LTQ_RESET_DMA,
91    LTQ_RESET_ETH,
92    LTQ_RESET_PHY,
93    LTQ_RESET_HARD,
94    LTQ_RESET_SOFT,
95};
96
97static inline void
98dbg_ltq_writel(void *a, unsigned int b)
99{
100    ltq_w32(b, a);
101}
102
103int ltq_reset_once(enum ltq_reset_modules module, ulong usec);
104
105struct ltq_ethsw_mac_pdi_x_regs {
106    u32 pstat; /* Port status */
107    u32 pisr; /* Interrupt status */
108    u32 pier; /* Interrupt enable */
109    u32 ctrl_0; /* Control 0 */
110    u32 ctrl_1; /* Control 1 */
111    u32 ctrl_2; /* Control 2 */
112    u32 ctrl_3; /* Control 3 */
113    u32 ctrl_4; /* Control 4 */
114    u32 ctrl_5; /* Control 5 */
115    u32 ctrl_6; /* Control 6 */
116    u32 bufst; /* TX/RX buffer control */
117    u32 testen; /* Test enable */
118};
119
120struct ltq_ethsw_mac_pdi_regs {
121    struct ltq_ethsw_mac_pdi_x_regs mac[12];
122};
123
124struct ltq_ethsw_mdio_pdi_regs {
125    u32 glob_ctrl; /* Global control 0 */
126    u32 rsvd0[7];
127    u32 mdio_ctrl; /* MDIO control */
128    u32 mdio_read; /* MDIO read data */
129    u32 mdio_write; /* MDIO write data */
130    u32 mdc_cfg_0; /* MDC clock configuration 0 */
131    u32 mdc_cfg_1; /* MDC clock configuration 1 */
132    u32 rsvd[3];
133    u32 phy_addr_5; /* PHY address port 5 */
134    u32 phy_addr_4; /* PHY address port 4 */
135    u32 phy_addr_3; /* PHY address port 3 */
136    u32 phy_addr_2; /* PHY address port 2 */
137    u32 phy_addr_1; /* PHY address port 1 */
138    u32 phy_addr_0; /* PHY address port 0 */
139    u32 mdio_stat_0; /* MDIO PHY polling status port 0 */
140    u32 mdio_stat_1; /* MDIO PHY polling status port 1 */
141    u32 mdio_stat_2; /* MDIO PHY polling status port 2 */
142    u32 mdio_stat_3; /* MDIO PHY polling status port 3 */
143    u32 mdio_stat_4; /* MDIO PHY polling status port 4 */
144    u32 mdio_stat_5; /* MDIO PHY polling status port 5 */
145};
146
147struct ltq_ethsw_mii_pdi_regs {
148    u32 mii_cfg0; /* xMII port 0 configuration */
149    u32 pcdu0; /* Port 0 clock delay configuration */
150    u32 mii_cfg1; /* xMII port 1 configuration */
151    u32 pcdu1; /* Port 1 clock delay configuration */
152    u32 mii_cfg2; /* xMII port 2 configuration */
153    u32 rsvd0;
154    u32 mii_cfg3; /* xMII port 3 configuration */
155    u32 rsvd1;
156    u32 mii_cfg4; /* xMII port 4 configuration */
157    u32 rsvd2;
158    u32 mii_cfg5; /* xMII port 5 configuration */
159    u32 pcdu5; /* Port 5 clock delay configuration */
160};
161
162struct ltq_ethsw_pmac_pdi_regs {
163    u32 hd_ctl; /* PMAC header control */
164    u32 tl; /* PMAC type/length */
165    u32 sa1; /* PMAC source address 1 */
166    u32 sa2; /* PMAC source address 2 */
167    u32 sa3; /* PMAC source address 3 */
168    u32 da1; /* PMAC destination address 1 */
169    u32 da2; /* PMAC destination address 2 */
170    u32 da3; /* PMAC destination address 3 */
171    u32 vlan; /* PMAC VLAN */
172    u32 rx_ipg; /* PMAC interpacket gap in RX direction */
173    u32 st_etype; /* PMAC special tag ethertype */
174    u32 ewan; /* PMAC ethernet WAN group */
175};
176
177struct ltq_mdio_phy_addr_reg {
178    union {
179        struct {
180            unsigned rsvd:1;
181            unsigned lnkst:2; /* Link status control */
182            unsigned speed:2; /* Speed control */
183            unsigned fdup:2; /* Full duplex control */
184            unsigned fcontx:2; /* Flow control mode TX */
185            unsigned fconrx:2; /* Flow control mode RX */
186            unsigned addr:5; /* PHY address */
187        } bits;
188        u16 val;
189    };
190};
191
192enum ltq_mdio_phy_addr_lnkst {
193    LTQ_MDIO_PHY_ADDR_LNKST_AUTO = 0,
194    LTQ_MDIO_PHY_ADDR_LNKST_UP = 1,
195    LTQ_MDIO_PHY_ADDR_LNKST_DOWN = 2,
196};
197
198enum ltq_mdio_phy_addr_speed {
199    LTQ_MDIO_PHY_ADDR_SPEED_M10 = 0,
200    LTQ_MDIO_PHY_ADDR_SPEED_M100 = 1,
201    LTQ_MDIO_PHY_ADDR_SPEED_G1 = 2,
202    LTQ_MDIO_PHY_ADDR_SPEED_AUTO = 3,
203};
204
205enum ltq_mdio_phy_addr_fdup {
206    LTQ_MDIO_PHY_ADDR_FDUP_AUTO = 0,
207    LTQ_MDIO_PHY_ADDR_FDUP_ENABLE = 1,
208    LTQ_MDIO_PHY_ADDR_FDUP_DISABLE = 3,
209};
210
211enum ltq_mdio_phy_addr_fcon {
212    LTQ_MDIO_PHY_ADDR_FCON_AUTO = 0,
213    LTQ_MDIO_PHY_ADDR_FCON_ENABLE = 1,
214    LTQ_MDIO_PHY_ADDR_FCON_DISABLE = 3,
215};
216
217struct ltq_mii_mii_cfg_reg {
218    union {
219        struct {
220            unsigned res:1; /* Hardware reset */
221            unsigned en:1; /* xMII interface enable */
222            unsigned isol:1; /* xMII interface isolate */
223            unsigned ldclkdis:1; /* Link down clock disable */
224            unsigned rsvd:1;
225            unsigned crs:2; /* CRS sensitivity config */
226            unsigned rgmii_ibs:1; /* RGMII In Band status */
227            unsigned rmii:1; /* RMII ref clock direction */
228            unsigned miirate:3; /* xMII interface clock rate */
229            unsigned miimode:4; /* xMII interface mode */
230        } bits;
231        u16 val;
232    };
233};
234
235enum ltq_mii_mii_cfg_miirate {
236    LTQ_MII_MII_CFG_MIIRATE_M2P5 = 0,
237    LTQ_MII_MII_CFG_MIIRATE_M25 = 1,
238    LTQ_MII_MII_CFG_MIIRATE_M125 = 2,
239    LTQ_MII_MII_CFG_MIIRATE_M50 = 3,
240    LTQ_MII_MII_CFG_MIIRATE_AUTO = 4,
241};
242
243enum ltq_mii_mii_cfg_miimode {
244    LTQ_MII_MII_CFG_MIIMODE_MIIP = 0,
245    LTQ_MII_MII_CFG_MIIMODE_MIIM = 1,
246    LTQ_MII_MII_CFG_MIIMODE_RMIIP = 2,
247    LTQ_MII_MII_CFG_MIIMODE_RMIIM = 3,
248    LTQ_MII_MII_CFG_MIIMODE_RGMII = 4,
249};
250
251struct ltq_eth_priv {
252    struct ltq_dma_device *dma_dev;
253    struct mii_dev *bus;
254    struct eth_device *dev;
255    struct phy_device *phymap[LTQ_ETHSW_MAX_GMAC];
256    int rx_num;
257};
258
259enum ltq_mdio_mbusy {
260    LTQ_MDIO_MBUSY_IDLE = 0,
261    LTQ_MDIO_MBUSY_BUSY = 1,
262};
263
264enum ltq_mdio_op {
265    LTQ_MDIO_OP_WRITE = 1,
266    LTQ_MDIO_OP_READ = 2,
267};
268
269struct ltq_mdio_access {
270    union {
271        struct {
272            unsigned rsvd:3;
273            unsigned mbusy:1;
274            unsigned op:2;
275            unsigned phyad:5;
276            unsigned regad:5;
277        } bits;
278        u16 val;
279    };
280};
281
282enum LTQ_ETH_PORT_FLAGS {
283    LTQ_ETH_PORT_NONE = 0,
284    LTQ_ETH_PORT_PHY = 1,
285    LTQ_ETH_PORT_SWITCH = (1 << 1),
286    LTQ_ETH_PORT_MAC = (1 << 2),
287};
288
289struct ltq_eth_port_config {
290    u8 num;
291    u8 phy_addr;
292    u16 flags;
293    phy_interface_t phy_if;
294};
295
296struct ltq_eth_board_config {
297    const struct ltq_eth_port_config *ports;
298    int num_ports;
299};
300
301static const struct ltq_eth_port_config eth_port_config[] = {
302    /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */
303    { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
304    /* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */
305    { 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
306};
307
308static const struct ltq_eth_board_config board_config = {
309    .ports = eth_port_config,
310    .num_ports = ARRAY_SIZE(eth_port_config),
311};
312
313static struct ltq_ethsw_mac_pdi_regs *ltq_ethsw_mac_pdi_regs =
314    (struct ltq_ethsw_mac_pdi_regs *) CKSEG1ADDR(LTQ_SWITCH_MAC_PDI_0_BASE);
315
316static struct ltq_ethsw_mdio_pdi_regs *ltq_ethsw_mdio_pdi_regs =
317    (struct ltq_ethsw_mdio_pdi_regs *) CKSEG1ADDR(LTQ_SWITCH_MDIO_PDI_BASE);
318
319static struct ltq_ethsw_mii_pdi_regs *ltq_ethsw_mii_pdi_regs =
320    (struct ltq_ethsw_mii_pdi_regs *) CKSEG1ADDR(LTQ_SWITCH_MII_PDI_BASE);
321
322static struct ltq_ethsw_pmac_pdi_regs *ltq_ethsw_pmac_pdi_regs =
323    (struct ltq_ethsw_pmac_pdi_regs *) CKSEG1ADDR(LTQ_SWITCH_PMAC_PDI_BASE);
324
325
326#define MAX_DMA_CHAN 0x8
327#define MAX_DMA_CRC_LEN 0x4
328#define MAX_DMA_DATA_LEN 0x600
329
330/* use 2 static channels for TX/RX
331   depending on the SoC we need to use different DMA channels for ethernet */
332#define LTQ_ETOP_TX_CHANNEL 1
333#define LTQ_ETOP_RX_CHANNEL 0
334
335#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL)
336#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL)
337
338#define DRV_VERSION "1.0"
339
340static void __iomem *ltq_vrx200_membase;
341
342struct ltq_vrx200_chan {
343    int idx;
344    int tx_free;
345    struct net_device *netdev;
346    struct napi_struct napi;
347    struct ltq_dma_channel dma;
348    struct sk_buff *skb[LTQ_DESC_NUM];
349};
350
351struct ltq_vrx200_priv {
352    struct net_device *netdev;
353    struct ltq_eth_data *pldata;
354    struct resource *res;
355
356    struct mii_bus *mii_bus;
357    struct phy_device *phydev;
358
359    struct ltq_vrx200_chan ch[MAX_DMA_CHAN];
360    int tx_free[MAX_DMA_CHAN >> 1];
361
362    spinlock_t lock;
363
364    struct clk *clk_ppe;
365};
366
367static int ltq_vrx200_mdio_wr(struct mii_bus *bus, int phy_addr,
368                int phy_reg, u16 phy_data);
369
370static int
371ltq_vrx200_alloc_skb(struct ltq_vrx200_chan *ch)
372{
373    ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN);
374    if (!ch->skb[ch->dma.desc])
375        return -ENOMEM;
376    ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
377        ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN,
378        DMA_FROM_DEVICE);
379    ch->dma.desc_base[ch->dma.desc].addr =
380        CPHYSADDR(ch->skb[ch->dma.desc]->data);
381    ch->dma.desc_base[ch->dma.desc].ctl =
382        LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
383        MAX_DMA_DATA_LEN;
384    skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN);
385    return 0;
386}
387
388static void
389ltq_vrx200_hw_receive(struct ltq_vrx200_chan *ch)
390{
391    struct ltq_vrx200_priv *priv = netdev_priv(ch->netdev);
392    struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
393    struct sk_buff *skb = ch->skb[ch->dma.desc];
394    int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN;
395    unsigned long flags;
396
397    spin_lock_irqsave(&priv->lock, flags);
398    if (ltq_vrx200_alloc_skb(ch)) {
399        netdev_err(ch->netdev,
400            "failed to allocate new rx buffer, stopping DMA\n");
401        ltq_dma_close(&ch->dma);
402    }
403    ch->dma.desc++;
404    ch->dma.desc %= LTQ_DESC_NUM;
405    spin_unlock_irqrestore(&priv->lock, flags);
406
407    skb_put(skb, len);
408    skb->dev = ch->netdev;
409    skb->protocol = eth_type_trans(skb, ch->netdev);
410    netif_receive_skb(skb);
411}
412
413static int
414ltq_vrx200_poll_rx(struct napi_struct *napi, int budget)
415{
416    struct ltq_vrx200_chan *ch = container_of(napi,
417                struct ltq_vrx200_chan, napi);
418    struct ltq_vrx200_priv *priv = netdev_priv(ch->netdev);
419    int rx = 0;
420    int complete = 0;
421    unsigned long flags;
422
423    while ((rx < budget) && !complete) {
424        struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
425
426        if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
427            ltq_vrx200_hw_receive(ch);
428            rx++;
429        } else {
430            complete = 1;
431        }
432    }
433    if (complete || !rx) {
434        napi_complete(&ch->napi);
435        spin_lock_irqsave(&priv->lock, flags);
436        ltq_dma_ack_irq(&ch->dma);
437        spin_unlock_irqrestore(&priv->lock, flags);
438    }
439    return rx;
440}
441
442static int
443ltq_vrx200_poll_tx(struct napi_struct *napi, int budget)
444{
445    struct ltq_vrx200_chan *ch =
446        container_of(napi, struct ltq_vrx200_chan, napi);
447    struct ltq_vrx200_priv *priv = netdev_priv(ch->netdev);
448    struct netdev_queue *txq =
449        netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
450    unsigned long flags;
451
452    spin_lock_irqsave(&priv->lock, flags);
453    while ((ch->dma.desc_base[ch->tx_free].ctl &
454            (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
455        dev_kfree_skb_any(ch->skb[ch->tx_free]);
456        ch->skb[ch->tx_free] = NULL;
457        memset(&ch->dma.desc_base[ch->tx_free], 0,
458            sizeof(struct ltq_dma_desc));
459        ch->tx_free++;
460        ch->tx_free %= LTQ_DESC_NUM;
461    }
462    spin_unlock_irqrestore(&priv->lock, flags);
463
464    if (netif_tx_queue_stopped(txq))
465        netif_tx_start_queue(txq);
466    napi_complete(&ch->napi);
467    spin_lock_irqsave(&priv->lock, flags);
468    ltq_dma_ack_irq(&ch->dma);
469    spin_unlock_irqrestore(&priv->lock, flags);
470    return 1;
471}
472
473static irqreturn_t
474ltq_vrx200_dma_irq(int irq, void *_priv)
475{
476    struct ltq_vrx200_priv *priv = _priv;
477    int ch = irq - LTQ_DMA_ETOP;
478
479    napi_schedule(&priv->ch[ch].napi);
480    return IRQ_HANDLED;
481}
482
483static void
484ltq_vrx200_free_channel(struct net_device *dev, struct ltq_vrx200_chan *ch)
485{
486    struct ltq_vrx200_priv *priv = netdev_priv(dev);
487
488    ltq_dma_free(&ch->dma);
489    if (ch->dma.irq)
490        free_irq(ch->dma.irq, priv);
491    if (IS_RX(ch->idx)) {
492        int desc;
493        for (desc = 0; desc < LTQ_DESC_NUM; desc++)
494            dev_kfree_skb_any(ch->skb[ch->dma.desc]);
495    }
496}
497
498static void
499ltq_vrx200_hw_exit(struct net_device *dev)
500{
501    struct ltq_vrx200_priv *priv = netdev_priv(dev);
502    int i;
503
504    clk_disable(priv->clk_ppe);
505
506    for (i = 0; i < MAX_DMA_CHAN; i++)
507        if (IS_TX(i) || IS_RX(i))
508            ltq_vrx200_free_channel(dev, &priv->ch[i]);
509}
510
511static void *ltq_eth_phy_addr_reg(int num)
512{
513    switch (num) {
514    case 0:
515        return &ltq_ethsw_mdio_pdi_regs->phy_addr_0;
516    case 1:
517        return &ltq_ethsw_mdio_pdi_regs->phy_addr_1;
518    case 2:
519        return &ltq_ethsw_mdio_pdi_regs->phy_addr_2;
520    case 3:
521        return &ltq_ethsw_mdio_pdi_regs->phy_addr_3;
522    case 4:
523        return &ltq_ethsw_mdio_pdi_regs->phy_addr_4;
524    case 5:
525        return &ltq_ethsw_mdio_pdi_regs->phy_addr_5;
526    }
527
528    return NULL;
529}
530
531static void *ltq_eth_mii_cfg_reg(int num)
532{
533    switch (num) {
534    case 0:
535        return &ltq_ethsw_mii_pdi_regs->mii_cfg0;
536    case 1:
537        return &ltq_ethsw_mii_pdi_regs->mii_cfg1;
538    case 2:
539        return &ltq_ethsw_mii_pdi_regs->mii_cfg2;
540    case 3:
541        return &ltq_ethsw_mii_pdi_regs->mii_cfg3;
542    case 4:
543        return &ltq_ethsw_mii_pdi_regs->mii_cfg4;
544    case 5:
545        return &ltq_ethsw_mii_pdi_regs->mii_cfg5;
546    }
547
548    return NULL;
549}
550
551static void ltq_eth_gmac_update(struct phy_device *phydev, int num)
552{
553    struct ltq_mdio_phy_addr_reg phy_addr_reg;
554    struct ltq_mii_mii_cfg_reg mii_cfg_reg;
555    void *phy_addr = ltq_eth_phy_addr_reg(num);
556    void *mii_cfg = ltq_eth_mii_cfg_reg(num);
557
558    phy_addr_reg.val = ltq_r32(phy_addr);
559    mii_cfg_reg.val = ltq_r32(mii_cfg);
560
561    phy_addr_reg.bits.addr = phydev->addr;
562
563    if (phydev->link)
564        phy_addr_reg.bits.lnkst = LTQ_MDIO_PHY_ADDR_LNKST_UP;
565    else
566        phy_addr_reg.bits.lnkst = LTQ_MDIO_PHY_ADDR_LNKST_DOWN;
567
568    switch (phydev->speed) {
569    case SPEED_1000:
570        phy_addr_reg.bits.speed = LTQ_MDIO_PHY_ADDR_SPEED_G1;
571        mii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M125;
572        break;
573    case SPEED_100:
574        phy_addr_reg.bits.speed = LTQ_MDIO_PHY_ADDR_SPEED_M100;
575        switch (mii_cfg_reg.bits.miimode) {
576        case LTQ_MII_MII_CFG_MIIMODE_RMIIM:
577        case LTQ_MII_MII_CFG_MIIMODE_RMIIP:
578            mii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M50;
579            break;
580        default:
581            mii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M25;
582            break;
583        }
584        break;
585    default:
586        phy_addr_reg.bits.speed = LTQ_MDIO_PHY_ADDR_SPEED_M10;
587        mii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M2P5;
588        break;
589    }
590
591    if (phydev->duplex == DUPLEX_FULL)
592        phy_addr_reg.bits.fdup = LTQ_MDIO_PHY_ADDR_FDUP_ENABLE;
593    else
594        phy_addr_reg.bits.fdup = LTQ_MDIO_PHY_ADDR_FDUP_DISABLE;
595
596    dbg_ltq_writel(phy_addr, phy_addr_reg.val);
597    dbg_ltq_writel(mii_cfg, mii_cfg_reg.val);
598    udelay(1);
599}
600
601
602static void ltq_eth_port_config(struct ltq_vrx200_priv *priv,
603    const struct ltq_eth_port_config *port)
604{
605    struct ltq_mii_mii_cfg_reg mii_cfg_reg;
606    void *mii_cfg = ltq_eth_mii_cfg_reg(port->num);
607    int setup_gpio = 0;
608
609    mii_cfg_reg.val = ltq_r32(mii_cfg);
610
611
612    switch (port->num) {
613    case 0: /* xMII0 */
614    case 1: /* xMII1 */
615        switch (port->phy_if) {
616        case PHY_INTERFACE_MODE_MII:
617            if (port->flags & LTQ_ETH_PORT_PHY)
618                /* MII MAC mode, connected to external PHY */
619                mii_cfg_reg.bits.miimode =
620                    LTQ_MII_MII_CFG_MIIMODE_MIIM;
621            else
622                /* MII PHY mode, connected to external MAC */
623                mii_cfg_reg.bits.miimode =
624                    LTQ_MII_MII_CFG_MIIMODE_MIIP;
625                setup_gpio = 1;
626            break;
627        case PHY_INTERFACE_MODE_RMII:
628            if (port->flags & LTQ_ETH_PORT_PHY)
629                /* RMII MAC mode, connected to external PHY */
630                mii_cfg_reg.bits.miimode =
631                    LTQ_MII_MII_CFG_MIIMODE_RMIIM;
632            else
633                /* RMII PHY mode, connected to external MAC */
634                mii_cfg_reg.bits.miimode =
635                    LTQ_MII_MII_CFG_MIIMODE_RMIIP;
636                setup_gpio = 1;
637                break;
638        case PHY_INTERFACE_MODE_RGMII:
639            /* RGMII MAC mode, connected to external PHY */
640            mii_cfg_reg.bits.miimode =
641                LTQ_MII_MII_CFG_MIIMODE_RGMII;
642            setup_gpio = 1;
643            break;
644        default:
645            break;
646        }
647        break;
648    case 2: /* internal GPHY0 */
649    case 3: /* internal GPHY0 */
650    case 4: /* internal GPHY1 */
651        switch (port->phy_if) {
652            case PHY_INTERFACE_MODE_MII:
653            case PHY_INTERFACE_MODE_GMII:
654                /* MII MAC mode, connected to internal GPHY */
655                mii_cfg_reg.bits.miimode =
656                    LTQ_MII_MII_CFG_MIIMODE_MIIM;
657                setup_gpio = 1;
658                break;
659            default:
660                break;
661        }
662        break;
663    case 5: /* internal GPHY1 or xMII2 */
664        switch (port->phy_if) {
665        case PHY_INTERFACE_MODE_MII:
666            /* MII MAC mode, connected to internal GPHY */
667            mii_cfg_reg.bits.miimode =
668                LTQ_MII_MII_CFG_MIIMODE_MIIM;
669            setup_gpio = 1;
670            break;
671        case PHY_INTERFACE_MODE_RGMII:
672            /* RGMII MAC mode, connected to external PHY */
673            mii_cfg_reg.bits.miimode =
674                LTQ_MII_MII_CFG_MIIMODE_RGMII;
675            setup_gpio = 1;
676            break;
677        default:
678            break;
679        }
680        break;
681    default:
682        break;
683    }
684
685    /* Enable MII interface */
686    mii_cfg_reg.bits.en = port->flags ? 1 : 0;
687    dbg_ltq_writel(mii_cfg, mii_cfg_reg.val);
688
689}
690
691static void ltq_eth_gmac_init(int num)
692{
693    struct ltq_mdio_phy_addr_reg phy_addr_reg;
694    struct ltq_mii_mii_cfg_reg mii_cfg_reg;
695    void *phy_addr = ltq_eth_phy_addr_reg(num);
696    void *mii_cfg = ltq_eth_mii_cfg_reg(num);
697    struct ltq_ethsw_mac_pdi_x_regs *mac_pdi_regs;
698
699    mac_pdi_regs = &ltq_ethsw_mac_pdi_regs->mac[num];
700
701    /* Reset PHY status to link down */
702    phy_addr_reg.val = ltq_r32(phy_addr);
703    phy_addr_reg.bits.addr = num;
704    phy_addr_reg.bits.lnkst = LTQ_MDIO_PHY_ADDR_LNKST_DOWN;
705    phy_addr_reg.bits.speed = LTQ_MDIO_PHY_ADDR_SPEED_M10;
706    phy_addr_reg.bits.fdup = LTQ_MDIO_PHY_ADDR_FDUP_DISABLE;
707    dbg_ltq_writel(phy_addr, phy_addr_reg.val);
708
709    /* Reset and disable MII interface */
710    mii_cfg_reg.val = ltq_r32(mii_cfg);
711    mii_cfg_reg.bits.en = 0;
712    mii_cfg_reg.bits.res = 1;
713    mii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M2P5;
714    dbg_ltq_writel(mii_cfg, mii_cfg_reg.val);
715
716    /*
717    * Enable padding of short frames, enable frame checksum generation
718    * in transmit direction
719    */
720    dbg_ltq_writel(&mac_pdi_regs->ctrl_0, LTQ_ETHSW_MAC_CTRL0_PADEN |
721        LTQ_ETHSW_MAC_CTRL0_FCS);
722
723    /* Set inter packet gap size to 12 bytes */
724    dbg_ltq_writel(&mac_pdi_regs->ctrl_1, 12);
725
726    /*
727    * Configure frame length checks:
728    * - allow jumbo frames
729    * - enable long length check
730    * - enable short length without VLAN tags
731    */
732    dbg_ltq_writel(&mac_pdi_regs->ctrl_2, LTQ_ETHSW_MAC_CTRL2_MLEN |
733        LTQ_ETHSW_MAC_CTRL2_LCHKL |
734        LTQ_ETHSW_MAC_CTRL2_LCHKS_UNTAG);
735}
736
737
738static void ltq_eth_pmac_init(void)
739{
740    struct ltq_ethsw_mac_pdi_x_regs *mac_pdi_regs;
741
742    mac_pdi_regs = &ltq_ethsw_mac_pdi_regs->mac[LTQ_ETHSW_PMAC];
743
744    /*
745    * Enable padding of short frames, enable frame checksum generation
746    * in transmit direction
747    */
748    dbg_ltq_writel(&mac_pdi_regs->ctrl_0, LTQ_ETHSW_MAC_CTRL0_PADEN |
749        LTQ_ETHSW_MAC_CTRL0_FCS);
750
751    /*
752    * Configure frame length checks:
753    * - allow jumbo frames
754    * - enable long length check
755    * - enable short length without VLAN tags
756    */
757    dbg_ltq_writel(&mac_pdi_regs->ctrl_2, LTQ_ETHSW_MAC_CTRL2_MLEN |
758        LTQ_ETHSW_MAC_CTRL2_LCHKL |
759        LTQ_ETHSW_MAC_CTRL2_LCHKS_UNTAG);
760
761    /*
762    * Apply workaround for buffer congestion:
763    * - shorten preambel to 1 byte
764    * - set minimum inter packet gap size to 7 bytes
765    * - enable receive buffer bypass mode
766    */
767    dbg_ltq_writel(&mac_pdi_regs->ctrl_1, LTQ_ETHSW_MAC_CTRL1_SHORTPRE | 7);
768    dbg_ltq_writel(&mac_pdi_regs->ctrl_6,
769        (6 << LTQ_ETHSW_MAC_CTRL6_RBUF_DLY_WP_SHIFT) |
770        LTQ_ETHSW_MAC_CTRL6_RXBUF_BYPASS);
771
772    /* Set request assertion threshold to 8, IPG counter to 11 */
773    dbg_ltq_writel(&ltq_ethsw_pmac_pdi_regs->rx_ipg, 0x8B);
774
775    /*
776    * Configure frame header control:
777    * - enable reaction on pause frames (flow control)
778    * - remove CRC for packets from PMAC to DMA
779    * - add CRC for packets from DMA to PMAC
780    */
781    dbg_ltq_writel(&ltq_ethsw_pmac_pdi_regs->hd_ctl, LTQ_ETHSW_PMAC_HD_CTL_FC |
782        /*LTQ_ETHSW_PMAC_HD_CTL_RC | */LTQ_ETHSW_PMAC_HD_CTL_AC);
783}
784
785static int
786ltq_vrx200_hw_init(struct net_device *dev)
787{
788    struct ltq_vrx200_priv *priv = netdev_priv(dev);
789    int err = 0;
790    int i;
791
792    netdev_info(dev, "setting up dma\n");
793    ltq_dma_init_port(DMA_PORT_ETOP);
794
795    netdev_info(dev, "setting up pmu\n");
796    clk_enable(priv->clk_ppe);
797
798    /* Reset ethernet and switch subsystems */
799    netdev_info(dev, "reset core\n");
800    ltq_reset_once(BIT(8), 10);
801
802    /* Enable switch macro */
803    ltq_setbits(&ltq_ethsw_mdio_pdi_regs->glob_ctrl,
804        LTQ_ETHSW_GLOB_CTRL_SE);
805
806    /* Disable MDIO auto-polling for all ports */
807    dbg_ltq_writel(&ltq_ethsw_mdio_pdi_regs->mdc_cfg_0, 0);
808
809    /*
810     * Enable and set MDIO management clock to 2.5 MHz. This is the
811     * maximum clock for FE PHYs.
812     * Formula for clock is:
813     *
814     * 50 MHz
815     * x = ----------- - 1
816     * 2 * f_MDC
817     */
818    dbg_ltq_writel(&ltq_ethsw_mdio_pdi_regs->mdc_cfg_1,
819        LTQ_ETHSW_MDC_CFG1_MCEN | 9);
820
821    /* Init MAC connected to CPU */
822    ltq_eth_pmac_init();
823
824    /* Init MACs connected to external MII interfaces */
825    for (i = 0; i < LTQ_ETHSW_MAX_GMAC; i++)
826        ltq_eth_gmac_init(i);
827
828    for (i = 0; i < MAX_DMA_CHAN && !err; i++) {
829        int irq = LTQ_DMA_ETOP + i;
830        struct ltq_vrx200_chan *ch = &priv->ch[i];
831
832        ch->idx = ch->dma.nr = i;
833
834        if (IS_TX(i)) {
835            ltq_dma_alloc_tx(&ch->dma);
836            err = request_irq(irq, ltq_vrx200_dma_irq, IRQF_DISABLED,
837                "vrx200_tx", priv);
838        } else if (IS_RX(i)) {
839            ltq_dma_alloc_rx(&ch->dma);
840            for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
841                    ch->dma.desc++)
842                if (ltq_vrx200_alloc_skb(ch))
843                    err = -ENOMEM;
844            ch->dma.desc = 0;
845            err = request_irq(irq, ltq_vrx200_dma_irq, IRQF_DISABLED,
846                "vrx200_rx", priv);
847        }
848        if (!err)
849            ch->dma.irq = irq;
850    }
851    for (i = 0; i < board_config.num_ports; i++)
852        ltq_eth_port_config(priv, &board_config.ports[i]);
853    return err;
854}
855
856static void
857ltq_vrx200_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
858{
859    strcpy(info->driver, "Lantiq ETOP");
860    strcpy(info->bus_info, "internal");
861    strcpy(info->version, DRV_VERSION);
862}
863
864static int
865ltq_vrx200_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
866{
867    struct ltq_vrx200_priv *priv = netdev_priv(dev);
868
869    return phy_ethtool_gset(priv->phydev, cmd);
870}
871
872static int
873ltq_vrx200_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
874{
875    struct ltq_vrx200_priv *priv = netdev_priv(dev);
876
877    return phy_ethtool_sset(priv->phydev, cmd);
878}
879
880static int
881ltq_vrx200_nway_reset(struct net_device *dev)
882{
883    struct ltq_vrx200_priv *priv = netdev_priv(dev);
884
885    return phy_start_aneg(priv->phydev);
886}
887
888static const struct ethtool_ops ltq_vrx200_ethtool_ops = {
889    .get_drvinfo = ltq_vrx200_get_drvinfo,
890    .get_settings = ltq_vrx200_get_settings,
891    .set_settings = ltq_vrx200_set_settings,
892    .nway_reset = ltq_vrx200_nway_reset,
893};
894
895static inline int ltq_mdio_poll(struct mii_bus *bus)
896{
897    struct ltq_mdio_access acc;
898    unsigned cnt = 10000;
899
900    while (likely(cnt--)) {
901        acc.val = ltq_r32(&ltq_ethsw_mdio_pdi_regs->mdio_ctrl);
902        if (!acc.bits.mbusy)
903            return 0;
904    }
905
906    return 1;
907}
908
909static int
910ltq_vrx200_mdio_wr(struct mii_bus *bus, int addr, int regnum, u16 val)
911{
912    struct ltq_mdio_access acc;
913    int ret;
914
915    acc.val = 0;
916    acc.bits.mbusy = LTQ_MDIO_MBUSY_BUSY;
917    acc.bits.op = LTQ_MDIO_OP_WRITE;
918    acc.bits.phyad = addr;
919    acc.bits.regad = regnum;
920
921    ret = ltq_mdio_poll(bus);
922    if (ret)
923        return ret;
924
925    dbg_ltq_writel(&ltq_ethsw_mdio_pdi_regs->mdio_write, val);
926    dbg_ltq_writel(&ltq_ethsw_mdio_pdi_regs->mdio_ctrl, acc.val);
927
928    return 0;
929}
930
931static int
932ltq_vrx200_mdio_rd(struct mii_bus *bus, int addr, int regnum)
933{
934    struct ltq_mdio_access acc;
935    int ret;
936
937    acc.val = 0;
938    acc.bits.mbusy = LTQ_MDIO_MBUSY_BUSY;
939    acc.bits.op = LTQ_MDIO_OP_READ;
940    acc.bits.phyad = addr;
941    acc.bits.regad = regnum;
942
943    ret = ltq_mdio_poll(bus);
944    if (ret)
945        goto timeout;
946
947    dbg_ltq_writel(&ltq_ethsw_mdio_pdi_regs->mdio_ctrl, acc.val);
948
949    ret = ltq_mdio_poll(bus);
950    if (ret)
951        goto timeout;
952
953    ret = ltq_r32(&ltq_ethsw_mdio_pdi_regs->mdio_read);
954
955    return ret;
956timeout:
957    return -1;
958}
959
960static void
961ltq_vrx200_mdio_link(struct net_device *dev)
962{
963    struct ltq_vrx200_priv *priv = netdev_priv(dev);
964    ltq_eth_gmac_update(priv->phydev, 0);
965}
966
967static int
968ltq_vrx200_mdio_probe(struct net_device *dev)
969{
970    struct ltq_vrx200_priv *priv = netdev_priv(dev);
971    struct phy_device *phydev = NULL;
972    int val;
973
974    phydev = priv->mii_bus->phy_map[0];
975
976    if (!phydev) {
977        netdev_err(dev, "no PHY found\n");
978        return -ENODEV;
979    }
980
981    phydev = phy_connect(dev, dev_name(&phydev->dev), &ltq_vrx200_mdio_link,
982            0, 0);
983
984    if (IS_ERR(phydev)) {
985        netdev_err(dev, "Could not attach to PHY\n");
986        return PTR_ERR(phydev);
987    }
988
989    phydev->supported &= (SUPPORTED_10baseT_Half
990                  | SUPPORTED_10baseT_Full
991                  | SUPPORTED_100baseT_Half
992                  | SUPPORTED_100baseT_Full
993                  | SUPPORTED_1000baseT_Half
994                  | SUPPORTED_1000baseT_Full
995                  | SUPPORTED_Autoneg
996                  | SUPPORTED_MII
997                  | SUPPORTED_TP);
998    phydev->advertising = phydev->supported;
999    priv->phydev = phydev;
1000
1001    pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n",
1002           dev->name, phydev->drv->name,
1003           dev_name(&phydev->dev), phydev->irq);
1004
1005    val = ltq_vrx200_mdio_rd(priv->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000);
1006    val |= ADVERTIZE_MPD;
1007    ltq_vrx200_mdio_wr(priv->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000, val);
1008    ltq_vrx200_mdio_wr(priv->mii_bus, 0, 0, 0x1040);
1009
1010        phy_start_aneg(phydev);
1011
1012    return 0;
1013}
1014
1015static int
1016ltq_vrx200_mdio_init(struct net_device *dev)
1017{
1018    struct ltq_vrx200_priv *priv = netdev_priv(dev);
1019    int i;
1020    int err;
1021
1022    priv->mii_bus = mdiobus_alloc();
1023    if (!priv->mii_bus) {
1024        netdev_err(dev, "failed to allocate mii bus\n");
1025        err = -ENOMEM;
1026        goto err_out;
1027    }
1028
1029    priv->mii_bus->priv = dev;
1030    priv->mii_bus->read = ltq_vrx200_mdio_rd;
1031    priv->mii_bus->write = ltq_vrx200_mdio_wr;
1032    priv->mii_bus->name = "ltq_mii";
1033    snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0);
1034    priv->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1035    if (!priv->mii_bus->irq) {
1036        err = -ENOMEM;
1037        goto err_out_free_mdiobus;
1038    }
1039
1040    for (i = 0; i < PHY_MAX_ADDR; ++i)
1041        priv->mii_bus->irq[i] = PHY_POLL;
1042
1043    if (mdiobus_register(priv->mii_bus)) {
1044        err = -ENXIO;
1045        goto err_out_free_mdio_irq;
1046    }
1047
1048    if (ltq_vrx200_mdio_probe(dev)) {
1049        err = -ENXIO;
1050        goto err_out_unregister_bus;
1051    }
1052    return 0;
1053
1054err_out_unregister_bus:
1055    mdiobus_unregister(priv->mii_bus);
1056err_out_free_mdio_irq:
1057    kfree(priv->mii_bus->irq);
1058err_out_free_mdiobus:
1059    mdiobus_free(priv->mii_bus);
1060err_out:
1061    return err;
1062}
1063
1064static void
1065ltq_vrx200_mdio_cleanup(struct net_device *dev)
1066{
1067    struct ltq_vrx200_priv *priv = netdev_priv(dev);
1068
1069    phy_disconnect(priv->phydev);
1070    mdiobus_unregister(priv->mii_bus);
1071    kfree(priv->mii_bus->irq);
1072    mdiobus_free(priv->mii_bus);
1073}
1074
1075void phy_dump(struct net_device *dev)
1076{
1077        struct ltq_vrx200_priv *priv = netdev_priv(dev);
1078    int i;
1079    for (i = 0; i < 0x1F; i++) {
1080        unsigned int val = ltq_vrx200_mdio_rd(priv->mii_bus, 0, i);
1081        printk("%d %4X\n", i, val);
1082    }
1083}
1084
1085static int
1086ltq_vrx200_open(struct net_device *dev)
1087{
1088    struct ltq_vrx200_priv *priv = netdev_priv(dev);
1089    int i;
1090    unsigned long flags;
1091
1092    for (i = 0; i < MAX_DMA_CHAN; i++) {
1093        struct ltq_vrx200_chan *ch = &priv->ch[i];
1094
1095        if (!IS_TX(i) && (!IS_RX(i)))
1096            continue;
1097        napi_enable(&ch->napi);
1098        spin_lock_irqsave(&priv->lock, flags);
1099        ltq_dma_open(&ch->dma);
1100        spin_unlock_irqrestore(&priv->lock, flags);
1101    }
1102    if (priv->phydev) {
1103        phy_start(priv->phydev);
1104        phy_dump(dev);
1105    }
1106    netif_tx_start_all_queues(dev);
1107    return 0;
1108}
1109
1110static int
1111ltq_vrx200_stop(struct net_device *dev)
1112{
1113    struct ltq_vrx200_priv *priv = netdev_priv(dev);
1114    int i;
1115    unsigned long flags;
1116
1117    netif_tx_stop_all_queues(dev);
1118    if (priv->phydev)
1119        phy_stop(priv->phydev);
1120    for (i = 0; i < MAX_DMA_CHAN; i++) {
1121        struct ltq_vrx200_chan *ch = &priv->ch[i];
1122
1123        if (!IS_RX(i) && !IS_TX(i))
1124            continue;
1125        napi_disable(&ch->napi);
1126        spin_lock_irqsave(&priv->lock, flags);
1127        ltq_dma_close(&ch->dma);
1128        spin_unlock_irqrestore(&priv->lock, flags);
1129    }
1130    return 0;
1131}
1132
1133static int
1134ltq_vrx200_tx(struct sk_buff *skb, struct net_device *dev)
1135{
1136    int queue = skb_get_queue_mapping(skb);
1137    struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
1138    struct ltq_vrx200_priv *priv = netdev_priv(dev);
1139    struct ltq_vrx200_chan *ch = &priv->ch[(queue << 1) | 1];
1140    struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
1141    unsigned long flags;
1142    u32 byte_offset;
1143    int len;
1144
1145    len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
1146
1147    if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
1148        netdev_err(dev, "tx ring full\n");
1149        netif_tx_stop_queue(txq);
1150        return NETDEV_TX_BUSY;
1151    }
1152
1153    /* dma needs to start on a 16 byte aligned address */
1154    byte_offset = CPHYSADDR(skb->data) % 16;
1155    ch->skb[ch->dma.desc] = skb;
1156
1157    dev->trans_start = jiffies;
1158
1159    spin_lock_irqsave(&priv->lock, flags);
1160    desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len,
1161                        DMA_TO_DEVICE)) - byte_offset;
1162    wmb();
1163    desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
1164        LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
1165    ch->dma.desc++;
1166    ch->dma.desc %= LTQ_DESC_NUM;
1167    spin_unlock_irqrestore(&priv->lock, flags);
1168
1169    if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
1170        netif_tx_stop_queue(txq);
1171
1172    return NETDEV_TX_OK;
1173}
1174
1175static int
1176ltq_vrx200_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1177{
1178    struct ltq_vrx200_priv *priv = netdev_priv(dev);
1179
1180    /* TODO: mii-toll reports "No MII transceiver present!." ?!*/
1181    return phy_mii_ioctl(priv->phydev, rq, cmd);
1182}
1183
1184static u16
1185ltq_vrx200_select_queue(struct net_device *dev, struct sk_buff *skb)
1186{
1187    /* we are currently only using the first queue */
1188    return 0;
1189}
1190
1191static int
1192ltq_vrx200_init(struct net_device *dev)
1193{
1194    struct ltq_vrx200_priv *priv = netdev_priv(dev);
1195    struct sockaddr mac;
1196    int err;
1197
1198    ether_setup(dev);
1199    dev->watchdog_timeo = 10 * HZ;
1200
1201    err = ltq_vrx200_hw_init(dev);
1202    if (err)
1203        goto err_hw;
1204
1205    memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
1206    if (!is_valid_ether_addr(mac.sa_data)) {
1207        pr_warn("vrx200: invalid MAC, using random\n");
1208        random_ether_addr(mac.sa_data);
1209    }
1210    eth_mac_addr(dev, &mac);
1211
1212    if (!ltq_vrx200_mdio_init(dev))
1213        dev->ethtool_ops = &ltq_vrx200_ethtool_ops;
1214    else
1215        pr_warn("vrx200: mdio probe failed\n");;
1216    return 0;
1217
1218err_hw:
1219    ltq_vrx200_hw_exit(dev);
1220    return err;
1221}
1222
1223static void
1224ltq_vrx200_tx_timeout(struct net_device *dev)
1225{
1226    int err;
1227
1228    ltq_vrx200_hw_exit(dev);
1229    err = ltq_vrx200_hw_init(dev);
1230    if (err)
1231        goto err_hw;
1232    dev->trans_start = jiffies;
1233    netif_wake_queue(dev);
1234    return;
1235
1236err_hw:
1237    ltq_vrx200_hw_exit(dev);
1238    netdev_err(dev, "failed to restart vrx200 after TX timeout\n");
1239}
1240
1241static const struct net_device_ops ltq_eth_netdev_ops = {
1242    .ndo_open = ltq_vrx200_open,
1243    .ndo_stop = ltq_vrx200_stop,
1244    .ndo_start_xmit = ltq_vrx200_tx,
1245    .ndo_change_mtu = eth_change_mtu,
1246    .ndo_do_ioctl = ltq_vrx200_ioctl,
1247    .ndo_set_mac_address = eth_mac_addr,
1248    .ndo_validate_addr = eth_validate_addr,
1249    .ndo_select_queue = ltq_vrx200_select_queue,
1250    .ndo_init = ltq_vrx200_init,
1251    .ndo_tx_timeout = ltq_vrx200_tx_timeout,
1252};
1253
1254static int __devinit
1255ltq_vrx200_probe(struct platform_device *pdev)
1256{
1257    struct net_device *dev;
1258    struct ltq_vrx200_priv *priv;
1259    struct resource *res;
1260    int err;
1261    int i;
1262
1263    res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1264    if (!res) {
1265        dev_err(&pdev->dev, "failed to get vrx200 resource\n");
1266        err = -ENOENT;
1267        goto err_out;
1268    }
1269
1270    res = devm_request_mem_region(&pdev->dev, res->start,
1271        resource_size(res), dev_name(&pdev->dev));
1272    if (!res) {
1273        dev_err(&pdev->dev, "failed to request vrx200 resource\n");
1274        err = -EBUSY;
1275        goto err_out;
1276    }
1277
1278    ltq_vrx200_membase = devm_ioremap_nocache(&pdev->dev,
1279        res->start, resource_size(res));
1280    if (!ltq_vrx200_membase) {
1281        dev_err(&pdev->dev, "failed to remap vrx200 engine %d\n",
1282            pdev->id);
1283        err = -ENOMEM;
1284        goto err_out;
1285    }
1286
1287    if (ltq_gpio_request(&pdev->dev, 42, 2, 1, "MDIO") ||
1288            ltq_gpio_request(&pdev->dev, 43, 2, 1, "MDC")) {
1289        dev_err(&pdev->dev, "failed to request MDIO gpios\n");
1290        err = -EBUSY;
1291        goto err_out;
1292    }
1293
1294    dev = alloc_etherdev_mq(sizeof(struct ltq_vrx200_priv), 4);
1295    strcpy(dev->name, "eth%d");
1296    dev->netdev_ops = &ltq_eth_netdev_ops;
1297    priv = netdev_priv(dev);
1298    priv->res = res;
1299    priv->pldata = dev_get_platdata(&pdev->dev);
1300    priv->netdev = dev;
1301
1302    priv->clk_ppe = clk_get(&pdev->dev, NULL);
1303    if (IS_ERR(priv->clk_ppe))
1304        return PTR_ERR(priv->clk_ppe);
1305
1306    spin_lock_init(&priv->lock);
1307
1308    for (i = 0; i < MAX_DMA_CHAN; i++) {
1309        if (IS_TX(i))
1310            netif_napi_add(dev, &priv->ch[i].napi,
1311                ltq_vrx200_poll_tx, 8);
1312        else if (IS_RX(i))
1313            netif_napi_add(dev, &priv->ch[i].napi,
1314                ltq_vrx200_poll_rx, 32);
1315        priv->ch[i].netdev = dev;
1316    }
1317
1318    err = register_netdev(dev);
1319    if (err)
1320        goto err_free;
1321
1322    platform_set_drvdata(pdev, dev);
1323    return 0;
1324
1325err_free:
1326    kfree(dev);
1327err_out:
1328    return err;
1329}
1330
1331static int __devexit
1332ltq_vrx200_remove(struct platform_device *pdev)
1333{
1334    struct net_device *dev = platform_get_drvdata(pdev);
1335
1336    if (dev) {
1337        netif_tx_stop_all_queues(dev);
1338        ltq_vrx200_hw_exit(dev);
1339        ltq_vrx200_mdio_cleanup(dev);
1340        unregister_netdev(dev);
1341    }
1342    return 0;
1343}
1344
1345static struct platform_driver ltq_mii_driver = {
1346    .probe = ltq_vrx200_probe,
1347    .remove = __devexit_p(ltq_vrx200_remove),
1348    .driver = {
1349        .name = "ltq_vrx200",
1350        .owner = THIS_MODULE,
1351    },
1352};
1353
1354module_platform_driver(ltq_mii_driver);
1355
1356MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1357MODULE_DESCRIPTION("Lantiq SoC ETOP");
1358MODULE_LICENSE("GPL");
1359

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