Root/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_cil.h

1/* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_cil.h $
3 * $Revision: 1.1.1.1 $
4 * $Date: 2009-04-17 06:15:34 $
5 * $Change: 631780 $
6 *
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
10 *
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
20 *
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
31 * DAMAGE.
32 * ========================================================================== */
33
34#if !defined(__DWC_CIL_H__)
35#define __DWC_CIL_H__
36
37#include "dwc_otg_plat.h"
38
39#include "dwc_otg_regs.h"
40#ifdef DEBUG
41#include "linux/timer.h"
42#endif
43
44/* the OTG capabilities. */
45#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
46#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
47#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
48/* the maximum speed of operation in host and device mode. */
49#define DWC_SPEED_PARAM_HIGH 0
50#define DWC_SPEED_PARAM_FULL 1
51/* the PHY clock rate in low power mode when connected to a
52 * Low Speed device in host mode. */
53#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
54#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
55/* the type of PHY interface to use. */
56#define DWC_PHY_TYPE_PARAM_FS 0
57#define DWC_PHY_TYPE_PARAM_UTMI 1
58#define DWC_PHY_TYPE_PARAM_ULPI 2
59/* whether to use the internal or external supply to
60 * drive the vbus with a ULPI phy. */
61#define DWC_PHY_ULPI_INTERNAL_VBUS 0
62#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
63/* EP type. */
64
65/**
66 * @file
67 * This file contains the interface to the Core Interface Layer.
68 */
69
70/**
71 * The <code>dwc_ep</code> structure represents the state of a single
72 * endpoint when acting in device mode. It contains the data items
73 * needed for an endpoint to be activated and transfer packets.
74 */
75typedef struct dwc_ep {
76        /** EP number used for register address lookup */
77        uint8_t num;
78        /** EP direction 0 = OUT */
79        unsigned is_in : 1;
80        /** EP active. */
81        unsigned active : 1;
82
83    /** Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO
84        If dedicated Tx FIFOs are enabled for all IN Eps - Tx FIFO # FOR IN EPs*/
85        unsigned tx_fifo_num : 4;
86        /** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */
87        unsigned type : 2;
88#define DWC_OTG_EP_TYPE_CONTROL 0
89#define DWC_OTG_EP_TYPE_ISOC 1
90#define DWC_OTG_EP_TYPE_BULK 2
91#define DWC_OTG_EP_TYPE_INTR 3
92
93        /** DATA start PID for INTR and BULK EP */
94        unsigned data_pid_start : 1;
95        /** Frame (even/odd) for ISOC EP */
96        unsigned even_odd_frame : 1;
97        /** Max Packet bytes */
98        unsigned maxpacket : 11;
99
100        /** @name Transfer state */
101    /** @{ */
102
103    /**
104     * Pointer to the beginning of the transfer buffer -- do not modify
105     * during transfer.
106     */
107    
108    uint32_t dma_addr;
109
110    uint8_t *start_xfer_buff;
111        /** pointer to the transfer buffer */
112        uint8_t *xfer_buff;
113        /** Number of bytes to transfer */
114        unsigned xfer_len : 19;
115        /** Number of bytes transferred. */
116        unsigned xfer_count : 19;
117        /** Sent ZLP */
118        unsigned sent_zlp : 1;
119        /** Total len for control transfer */
120        unsigned total_len : 19;
121
122        /** stall clear flag */
123        unsigned stall_clear_flag : 1;
124
125    /** @} */
126} dwc_ep_t;
127
128/*
129 * Reasons for halting a host channel.
130 */
131typedef enum dwc_otg_halt_status {
132    DWC_OTG_HC_XFER_NO_HALT_STATUS,
133    DWC_OTG_HC_XFER_COMPLETE,
134    DWC_OTG_HC_XFER_URB_COMPLETE,
135    DWC_OTG_HC_XFER_ACK,
136    DWC_OTG_HC_XFER_NAK,
137    DWC_OTG_HC_XFER_NYET,
138    DWC_OTG_HC_XFER_STALL,
139    DWC_OTG_HC_XFER_XACT_ERR,
140    DWC_OTG_HC_XFER_FRAME_OVERRUN,
141    DWC_OTG_HC_XFER_BABBLE_ERR,
142    DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
143    DWC_OTG_HC_XFER_AHB_ERR,
144    DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
145    DWC_OTG_HC_XFER_URB_DEQUEUE
146} dwc_otg_halt_status_e;
147    
148/**
149 * Host channel descriptor. This structure represents the state of a single
150 * host channel when acting in host mode. It contains the data items needed to
151 * transfer packets to an endpoint via a host channel.
152 */
153typedef struct dwc_hc {
154    /** Host channel number used for register address lookup */
155    uint8_t hc_num;
156
157    /** Device to access */
158    unsigned dev_addr : 7;
159
160    /** EP to access */
161    unsigned ep_num : 4;
162
163    /** EP direction. 0: OUT, 1: IN */
164    unsigned ep_is_in : 1;
165
166    /**
167     * EP speed.
168     * One of the following values:
169     * - DWC_OTG_EP_SPEED_LOW
170     * - DWC_OTG_EP_SPEED_FULL
171     * - DWC_OTG_EP_SPEED_HIGH
172     */
173    unsigned speed : 2;
174#define DWC_OTG_EP_SPEED_LOW 0
175#define DWC_OTG_EP_SPEED_FULL 1
176#define DWC_OTG_EP_SPEED_HIGH 2
177
178    /**
179     * Endpoint type.
180     * One of the following values:
181     * - DWC_OTG_EP_TYPE_CONTROL: 0
182     * - DWC_OTG_EP_TYPE_ISOC: 1
183     * - DWC_OTG_EP_TYPE_BULK: 2
184     * - DWC_OTG_EP_TYPE_INTR: 3
185     */
186    unsigned ep_type : 2;
187
188    /** Max packet size in bytes */
189    unsigned max_packet : 11;
190
191    /**
192     * PID for initial transaction.
193     * 0: DATA0,<br>
194     * 1: DATA2,<br>
195     * 2: DATA1,<br>
196     * 3: MDATA (non-Control EP),
197     * SETUP (Control EP)
198     */
199    unsigned data_pid_start : 2;
200#define DWC_OTG_HC_PID_DATA0 0
201#define DWC_OTG_HC_PID_DATA2 1
202#define DWC_OTG_HC_PID_DATA1 2
203#define DWC_OTG_HC_PID_MDATA 3
204#define DWC_OTG_HC_PID_SETUP 3
205
206    /** Number of periodic transactions per (micro)frame */
207    unsigned multi_count: 2;
208
209    /** @name Transfer State */
210    /** @{ */
211
212    /** Pointer to the current transfer buffer position. */
213    uint8_t *xfer_buff;
214    /** Total number of bytes to transfer. */
215    uint32_t xfer_len;
216    /** Number of bytes transferred so far. */
217    uint32_t xfer_count;
218    /** Packet count at start of transfer.*/
219    uint16_t start_pkt_count;
220
221    /**
222     * Flag to indicate whether the transfer has been started. Set to 1 if
223     * it has been started, 0 otherwise.
224     */
225    uint8_t xfer_started;
226
227    /**
228     * Set to 1 to indicate that a PING request should be issued on this
229     * channel. If 0, process normally.
230     */
231    uint8_t do_ping;
232
233    /**
234     * Set to 1 to indicate that the error count for this transaction is
235     * non-zero. Set to 0 if the error count is 0.
236     */
237    uint8_t error_state;
238
239    /**
240     * Set to 1 to indicate that this channel should be halted the next
241     * time a request is queued for the channel. This is necessary in
242     * slave mode if no request queue space is available when an attempt
243     * is made to halt the channel.
244     */
245    uint8_t halt_on_queue;
246
247    /**
248     * Set to 1 if the host channel has been halted, but the core is not
249     * finished flushing queued requests. Otherwise 0.
250     */
251    uint8_t halt_pending;
252
253    /**
254     * Reason for halting the host channel.
255     */
256    dwc_otg_halt_status_e halt_status;
257
258    /*
259     * Split settings for the host channel
260     */
261    uint8_t do_split; /**< Enable split for the channel */
262    uint8_t complete_split; /**< Enable complete split */
263    uint8_t hub_addr; /**< Address of high speed hub */
264
265    uint8_t port_addr; /**< Port of the low/full speed device */
266    /** Split transaction position
267     * One of the following values:
268     * - DWC_HCSPLIT_XACTPOS_MID
269     * - DWC_HCSPLIT_XACTPOS_BEGIN
270     * - DWC_HCSPLIT_XACTPOS_END
271     * - DWC_HCSPLIT_XACTPOS_ALL */
272    uint8_t xact_pos;
273
274    /** Set when the host channel does a short read. */
275    uint8_t short_read;
276
277    /**
278     * Number of requests issued for this channel since it was assigned to
279     * the current transfer (not counting PINGs).
280     */
281    uint8_t requests;
282
283    /**
284     * Queue Head for the transfer being processed by this channel.
285     */
286    struct dwc_otg_qh *qh;
287
288    /** @} */
289
290    /** Entry in list of host channels. */
291    struct list_head hc_list_entry;
292} dwc_hc_t;
293
294/**
295 * The following parameters may be specified when starting the module. These
296 * parameters define how the DWC_otg controller should be configured.
297 * Parameter values are passed to the CIL initialization function
298 * dwc_otg_cil_init.
299 */
300
301typedef struct dwc_otg_core_params
302{
303    int32_t opt;
304//#define dwc_param_opt_default 1
305        /**
306     * Specifies the OTG capabilities. The driver will automatically
307     * detect the value for this parameter if none is specified.
308         * 0 - HNP and SRP capable (default)
309         * 1 - SRP Only capable
310         * 2 - No HNP/SRP capable
311         */
312        int32_t otg_cap;
313#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
314#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
315#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
316//#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
317    /**
318         * Specifies whether to use slave or DMA mode for accessing the data
319         * FIFOs. The driver will automatically detect the value for this
320         * parameter if none is specified.
321         * 0 - Slave
322         * 1 - DMA (default, if available)
323         */
324    int32_t dma_enable;
325//#define dwc_param_dma_enable_default 1
326    /** The DMA Burst size (applicable only for External DMA
327         * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
328         */
329        int32_t dma_burst_size; /* Translate this to GAHBCFG values */
330//#define dwc_param_dma_burst_size_default 32
331    /**
332     * Specifies the maximum speed of operation in host and device mode.
333     * The actual speed depends on the speed of the attached device and
334     * the value of phy_type. The actual speed depends on the speed of the
335     * attached device.
336     * 0 - High Speed (default)
337     * 1 - Full Speed
338     */
339        int32_t speed;
340//#define dwc_param_speed_default 0
341#define DWC_SPEED_PARAM_HIGH 0
342#define DWC_SPEED_PARAM_FULL 1
343
344    /** Specifies whether low power mode is supported when attached
345     * to a Full Speed or Low Speed device in host mode.
346     * 0 - Don't support low power mode (default)
347     * 1 - Support low power mode
348     */
349    int32_t host_support_fs_ls_low_power;
350//#define dwc_param_host_support_fs_ls_low_power_default 0
351    /** Specifies the PHY clock rate in low power mode when connected to a
352     * Low Speed device in host mode. This parameter is applicable only if
353     * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
354     * then defaults to 6 MHZ otherwise 48 MHZ.
355     *
356     * 0 - 48 MHz
357     * 1 - 6 MHz
358     */
359    int32_t host_ls_low_power_phy_clk;
360//#define dwc_param_host_ls_low_power_phy_clk_default 0
361#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
362#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
363    /**
364     * 0 - Use cC FIFO size parameters
365     * 1 - Allow dynamic FIFO sizing (default)
366     */
367    int32_t enable_dynamic_fifo;
368//#define dwc_param_enable_dynamic_fifo_default 1
369    /** Total number of 4-byte words in the data FIFO memory. This
370     * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
371     * Tx FIFOs.
372     * 32 to 32768 (default 8192)
373     * Note: The total FIFO memory depth in the FPGA configuration is 8192.
374     */
375    int32_t data_fifo_size;
376//#define dwc_param_data_fifo_size_default 8192
377    /** Number of 4-byte words in the Rx FIFO in device mode when dynamic
378     * FIFO sizing is enabled.
379     * 16 to 32768 (default 1064)
380     */
381    int32_t dev_rx_fifo_size;
382//#define dwc_param_dev_rx_fifo_size_default 1064
383    /** Number of 4-byte words in the non-periodic Tx FIFO in device mode
384     * when dynamic FIFO sizing is enabled.
385     * 16 to 32768 (default 1024)
386     */
387    int32_t dev_nperio_tx_fifo_size;
388//#define dwc_param_dev_nperio_tx_fifo_size_default 1024
389    /** Number of 4-byte words in each of the periodic Tx FIFOs in device
390     * mode when dynamic FIFO sizing is enabled.
391     * 4 to 768 (default 256)
392     */
393    uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
394//#define dwc_param_dev_perio_tx_fifo_size_default 256
395    /** Number of 4-byte words in the Rx FIFO in host mode when dynamic
396     * FIFO sizing is enabled.
397     * 16 to 32768 (default 1024)
398     */
399    int32_t host_rx_fifo_size;
400//#define dwc_param_host_rx_fifo_size_default 1024
401        /** Number of 4-byte words in the non-periodic Tx FIFO in host mode
402     * when Dynamic FIFO sizing is enabled in the core.
403     * 16 to 32768 (default 1024)
404     */
405    int32_t host_nperio_tx_fifo_size;
406//#define dwc_param_host_nperio_tx_fifo_size_default 1024
407    /** Number of 4-byte words in the host periodic Tx FIFO when dynamic
408     * FIFO sizing is enabled.
409     * 16 to 32768 (default 1024)
410     */
411    int32_t host_perio_tx_fifo_size;
412//#define dwc_param_host_perio_tx_fifo_size_default 1024
413    /** The maximum transfer size supported in bytes.
414     * 2047 to 65,535 (default 65,535)
415     */
416    int32_t max_transfer_size;
417//#define dwc_param_max_transfer_size_default 65535
418    /** The maximum number of packets in a transfer.
419     * 15 to 511 (default 511)
420     */
421    int32_t max_packet_count;
422//#define dwc_param_max_packet_count_default 511
423    /** The number of host channel registers to use.
424     * 1 to 16 (default 12)
425     * Note: The FPGA configuration supports a maximum of 12 host channels.
426     */
427    int32_t host_channels;
428//#define dwc_param_host_channels_default 12
429    /** The number of endpoints in addition to EP0 available for device
430     * mode operations.
431     * 1 to 15 (default 6 IN and OUT)
432     * Note: The FPGA configuration supports a maximum of 6 IN and OUT
433     * endpoints in addition to EP0.
434     */
435    int32_t dev_endpoints;
436//#define dwc_param_dev_endpoints_default 6
437        /**
438         * Specifies the type of PHY interface to use. By default, the driver
439         * will automatically detect the phy_type.
440         *
441         * 0 - Full Speed PHY
442         * 1 - UTMI+ (default)
443         * 2 - ULPI
444         */
445    int32_t phy_type;
446#define DWC_PHY_TYPE_PARAM_FS 0
447#define DWC_PHY_TYPE_PARAM_UTMI 1
448#define DWC_PHY_TYPE_PARAM_ULPI 2
449//#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
450    /**
451         * Specifies the UTMI+ Data Width. This parameter is
452         * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
453         * PHY_TYPE, this parameter indicates the data width between
454         * the MAC and the ULPI Wrapper.) Also, this parameter is
455         * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
456         * to "8 and 16 bits", meaning that the core has been
457         * configured to work at either data path width.
458         *
459         * 8 or 16 bits (default 16)
460         */
461        int32_t phy_utmi_width;
462//#define dwc_param_phy_utmi_width_default 16
463        /**
464         * Specifies whether the ULPI operates at double or single
465         * data rate. This parameter is only applicable if PHY_TYPE is
466         * ULPI.
467         *
468         * 0 - single data rate ULPI interface with 8 bit wide data
469         * bus (default)
470         * 1 - double data rate ULPI interface with 4 bit wide data
471         * bus
472         */
473        int32_t phy_ulpi_ddr;
474//#define dwc_param_phy_ulpi_ddr_default 0
475    /**
476     * Specifies whether to use the internal or external supply to
477     * drive the vbus with a ULPI phy.
478     */
479    int32_t phy_ulpi_ext_vbus;
480#define DWC_PHY_ULPI_INTERNAL_VBUS 0
481#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
482//#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
483        /**
484     * Specifies whether to use the I2Cinterface for full speed PHY. This
485     * parameter is only applicable if PHY_TYPE is FS.
486         * 0 - No (default)
487         * 1 - Yes
488         */
489        int32_t i2c_enable;
490//#define dwc_param_i2c_enable_default 0
491
492        int32_t ulpi_fs_ls;
493//#define dwc_param_ulpi_fs_ls_default 0
494
495    int32_t ts_dline;
496//#define dwc_param_ts_dline_default 0
497
498    /**
499     * Specifies whether dedicated transmit FIFOs are
500     * enabled for non periodic IN endpoints in device mode
501     * 0 - No
502     * 1 - Yes
503     */
504     int32_t en_multiple_tx_fifo;
505#define dwc_param_en_multiple_tx_fifo_default 1
506
507    /** Number of 4-byte words in each of the Tx FIFOs in device
508     * mode when dynamic FIFO sizing is enabled.
509     * 4 to 768 (default 256)
510     */
511    uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
512#define dwc_param_dev_tx_fifo_size_default 256
513
514    /** Thresholding enable flag-
515     * bit 0 - enable non-ISO Tx thresholding
516     * bit 1 - enable ISO Tx thresholding
517     * bit 2 - enable Rx thresholding
518     */
519    uint32_t thr_ctl;
520#define dwc_param_thr_ctl_default 0
521
522    /** Thresholding length for Tx
523     * FIFOs in 32 bit DWORDs
524     */
525    uint32_t tx_thr_length;
526#define dwc_param_tx_thr_length_default 64
527
528    /** Thresholding length for Rx
529     * FIFOs in 32 bit DWORDs
530     */
531    uint32_t rx_thr_length;
532#define dwc_param_rx_thr_length_default 64
533} dwc_otg_core_params_t;
534
535#ifdef DEBUG
536struct dwc_otg_core_if;
537typedef struct hc_xfer_info
538{
539    struct dwc_otg_core_if *core_if;
540    dwc_hc_t *hc;
541} hc_xfer_info_t;
542#endif
543
544/**
545 * The <code>dwc_otg_core_if</code> structure contains information needed to manage
546 * the DWC_otg controller acting in either host or device mode. It
547 * represents the programming view of the controller as a whole.
548 */
549typedef struct dwc_otg_core_if
550{
551    /** Parameters that define how the core should be configured.*/
552    dwc_otg_core_params_t *core_params;
553
554    /** Core Global registers starting at offset 000h. */
555    dwc_otg_core_global_regs_t *core_global_regs;
556
557    /** Device-specific information */
558    dwc_otg_dev_if_t *dev_if;
559    /** Host-specific information */
560    dwc_otg_host_if_t *host_if;
561
562    /*
563     * Set to 1 if the core PHY interface bits in USBCFG have been
564     * initialized.
565     */
566    uint8_t phy_init_done;
567
568    /*
569     * SRP Success flag, set by srp success interrupt in FS I2C mode
570     */
571    uint8_t srp_success;
572    uint8_t srp_timer_started;
573
574    /* Common configuration information */
575    /** Power and Clock Gating Control Register */
576    volatile uint32_t *pcgcctl;
577#define DWC_OTG_PCGCCTL_OFFSET 0xE00
578
579    /** Push/pop addresses for endpoints or host channels.*/
580    uint32_t *data_fifo[MAX_EPS_CHANNELS];
581#define DWC_OTG_DATA_FIFO_OFFSET 0x1000
582#define DWC_OTG_DATA_FIFO_SIZE 0x1000
583
584    /** Total RAM for FIFOs (Bytes) */
585    uint16_t total_fifo_size;
586    /** Size of Rx FIFO (Bytes) */
587    uint16_t rx_fifo_size;
588    /** Size of Non-periodic Tx FIFO (Bytes) */
589    uint16_t nperio_tx_fifo_size;
590        
591    /** 1 if DMA is enabled, 0 otherwise. */
592    uint8_t dma_enable;
593
594    /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */
595    uint8_t en_multiple_tx_fifo;
596
597    /** Set to 1 if multiple packets of a high-bandwidth transfer is in
598     * process of being queued */
599    uint8_t queuing_high_bandwidth;
600
601    /** Hardware Configuration -- stored here for convenience.*/
602    hwcfg1_data_t hwcfg1;
603    hwcfg2_data_t hwcfg2;
604    hwcfg3_data_t hwcfg3;
605    hwcfg4_data_t hwcfg4;
606
607    /** The operational State, during transations
608     * (a_host>>a_peripherial and b_device=>b_host) this may not
609     * match the core but allows the software to determine
610     * transitions.
611     */
612    uint8_t op_state;
613        
614    /**
615     * Set to 1 if the HCD needs to be restarted on a session request
616     * interrupt. This is required if no connector ID status change has
617     * occurred since the HCD was last disconnected.
618     */
619    uint8_t restart_hcd_on_session_req;
620
621    /** HCD callbacks */
622    /** A-Device is a_host */
623#define A_HOST (1)
624    /** A-Device is a_suspend */
625#define A_SUSPEND (2)
626    /** A-Device is a_peripherial */
627#define A_PERIPHERAL (3)
628    /** B-Device is operating as a Peripheral. */
629#define B_PERIPHERAL (4)
630    /** B-Device is operating as a Host. */
631#define B_HOST (5)
632
633    /** HCD callbacks */
634    struct dwc_otg_cil_callbacks *hcd_cb;
635    /** PCD callbacks */
636    struct dwc_otg_cil_callbacks *pcd_cb;
637
638    /** Device mode Periodic Tx FIFO Mask */
639    uint32_t p_tx_msk;
640    /** Device mode Periodic Tx FIFO Mask */
641    uint32_t tx_msk;
642
643#ifdef DEBUG
644    uint32_t start_hcchar_val[MAX_EPS_CHANNELS];
645
646    hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS];
647    struct timer_list hc_xfer_timer[MAX_EPS_CHANNELS];
648
649#if 1 // winder
650    uint32_t hfnum_7_samples;
651    uint32_t hfnum_7_frrem_accum;
652    uint32_t hfnum_0_samples;
653    uint32_t hfnum_0_frrem_accum;
654    uint32_t hfnum_other_samples;
655    uint32_t hfnum_other_frrem_accum;
656#else
657    uint32_t hfnum_7_samples;
658    uint64_t hfnum_7_frrem_accum;
659    uint32_t hfnum_0_samples;
660    uint64_t hfnum_0_frrem_accum;
661    uint32_t hfnum_other_samples;
662    uint64_t hfnum_other_frrem_accum;
663#endif
664    resource_size_t phys_addr; /* Added to support PLB DMA : phys-virt mapping */
665#endif
666
667} dwc_otg_core_if_t;
668
669/*
670 * The following functions support initialization of the CIL driver component
671 * and the DWC_otg controller.
672 */
673extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *_reg_base_addr,
674                                           dwc_otg_core_params_t *_core_params);
675extern void dwc_otg_cil_remove(dwc_otg_core_if_t *_core_if);
676extern void dwc_otg_core_init(dwc_otg_core_if_t *_core_if);
677extern void dwc_otg_core_host_init(dwc_otg_core_if_t *_core_if);
678extern void dwc_otg_core_dev_init(dwc_otg_core_if_t *_core_if);
679extern void dwc_otg_enable_global_interrupts( dwc_otg_core_if_t *_core_if );
680extern void dwc_otg_disable_global_interrupts( dwc_otg_core_if_t *_core_if );
681
682/** @name Device CIL Functions
683 * The following functions support managing the DWC_otg controller in device
684 * mode.
685 */
686/**@{*/
687extern void dwc_otg_wakeup(dwc_otg_core_if_t *_core_if);
688extern void dwc_otg_read_setup_packet (dwc_otg_core_if_t *_core_if, uint32_t *_dest);
689extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *_core_if);
690extern void dwc_otg_ep0_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
691extern void dwc_otg_ep_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
692extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
693extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
694extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
695extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
696extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma);
697extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
698extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
699extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *_core_if);
700extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *_core_if);
701/**@}*/
702
703/** @name Host CIL Functions
704 * The following functions support managing the DWC_otg controller in host
705 * mode.
706 */
707/**@{*/
708extern void dwc_otg_hc_init(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
709extern void dwc_otg_hc_halt(dwc_otg_core_if_t *_core_if,
710                dwc_hc_t *_hc,
711                dwc_otg_halt_status_e _halt_status);
712extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
713extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
714extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
715extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
716extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
717extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *_core_if);
718extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *_core_if);
719
720/**
721 * This function Reads HPRT0 in preparation to modify. It keeps the
722 * WC bits 0 so that if they are read as 1, they won't clear when you
723 * write it back
724 */
725static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t *_core_if)
726{
727        hprt0_data_t hprt0;
728        hprt0.d32 = dwc_read_reg32(_core_if->host_if->hprt0);
729        hprt0.b.prtena = 0;
730        hprt0.b.prtconndet = 0;
731        hprt0.b.prtenchng = 0;
732        hprt0.b.prtovrcurrchng = 0;
733        return hprt0.d32;
734}
735
736extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t *_core_if);
737/**@}*/
738
739/** @name Common CIL Functions
740 * The following functions support managing the DWC_otg controller in either
741 * device or host mode.
742 */
743/**@{*/
744
745extern void dwc_otg_read_packet(dwc_otg_core_if_t *core_if,
746                uint8_t *dest,
747                uint16_t bytes);
748
749extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t *_core_if);
750
751extern void dwc_otg_flush_tx_fifo( dwc_otg_core_if_t *_core_if,
752                                   const int _num );
753extern void dwc_otg_flush_rx_fifo( dwc_otg_core_if_t *_core_if );
754extern void dwc_otg_core_reset( dwc_otg_core_if_t *_core_if );
755
756#define NP_TXFIFO_EMPTY -1
757#define MAX_NP_TXREQUEST_Q_SLOTS 8
758/**
759 * This function returns the endpoint number of the request at
760 * the top of non-periodic TX FIFO, or -1 if the request FIFO is
761 * empty.
762 */
763static inline int dwc_otg_top_nptxfifo_epnum(dwc_otg_core_if_t *_core_if) {
764    gnptxsts_data_t txstatus = {.d32 = 0};
765
766    txstatus.d32 = dwc_read_reg32(&_core_if->core_global_regs->gnptxsts);
767    return (txstatus.b.nptxqspcavail == MAX_NP_TXREQUEST_Q_SLOTS ?
768        -1 : txstatus.b.nptxqtop_chnep);
769}
770/**
771 * This function returns the Core Interrupt register.
772 */
773static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t *_core_if) {
774    return (dwc_read_reg32(&_core_if->core_global_regs->gintsts) &
775                dwc_read_reg32(&_core_if->core_global_regs->gintmsk));
776}
777
778/**
779 * This function returns the OTG Interrupt register.
780 */
781static inline uint32_t dwc_otg_read_otg_intr (dwc_otg_core_if_t *_core_if) {
782    return (dwc_read_reg32 (&_core_if->core_global_regs->gotgint));
783}
784
785/**
786 * This function reads the Device All Endpoints Interrupt register and
787 * returns the IN endpoint interrupt bits.
788 */
789static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *_core_if) {
790        uint32_t v;
791        v = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daint) &
792                dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk);
793        return (v & 0xffff);
794        
795}
796
797/**
798 * This function reads the Device All Endpoints Interrupt register and
799 * returns the OUT endpoint interrupt bits.
800 */
801static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *_core_if) {
802        uint32_t v;
803        v = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daint) &
804                dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk);
805        return ((v & 0xffff0000) >> 16);
806}
807
808/**
809 * This function returns the Device IN EP Interrupt register
810 */
811static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t *_core_if,
812                                                   dwc_ep_t *_ep)
813{
814        dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
815    uint32_t v, msk, emp;
816    msk = dwc_read_reg32(&dev_if->dev_global_regs->diepmsk);
817    emp = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk);
818    msk |= ((emp >> _ep->num) & 0x1) << 7;
819    v = dwc_read_reg32(&dev_if->in_ep_regs[_ep->num]->diepint) & msk;
820/*
821    dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
822        uint32_t v;
823        v = dwc_read_reg32(&dev_if->in_ep_regs[_ep->num]->diepint) &
824                dwc_read_reg32(&dev_if->dev_global_regs->diepmsk);
825*/
826        return v;
827}
828/**
829 * This function returns the Device OUT EP Interrupt register
830 */
831static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *_core_if,
832                                                    dwc_ep_t *_ep)
833{
834        dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
835        uint32_t v;
836        v = dwc_read_reg32( &dev_if->out_ep_regs[_ep->num]->doepint) &
837            dwc_read_reg32(&dev_if->dev_global_regs->doepmsk);
838        return v;
839}
840
841/**
842 * This function returns the Host All Channel Interrupt register
843 */
844static inline uint32_t dwc_otg_read_host_all_channels_intr (dwc_otg_core_if_t *_core_if)
845{
846    return (dwc_read_reg32 (&_core_if->host_if->host_global_regs->haint));
847}
848
849static inline uint32_t dwc_otg_read_host_channel_intr (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
850{
851    return (dwc_read_reg32 (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint));
852}
853
854
855/**
856 * This function returns the mode of the operation, host or device.
857 *
858 * @return 0 - Device Mode, 1 - Host Mode
859 */
860static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t *_core_if) {
861        return (dwc_read_reg32( &_core_if->core_global_regs->gintsts ) & 0x1);
862}
863
864static inline uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t *_core_if)
865{
866        return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
867}
868static inline uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t *_core_if)
869{
870        return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
871}
872
873extern int32_t dwc_otg_handle_common_intr( dwc_otg_core_if_t *_core_if );
874
875
876/**@}*/
877
878/**
879 * DWC_otg CIL callback structure. This structure allows the HCD and
880 * PCD to register functions used for starting and stopping the PCD
881 * and HCD for role change on for a DRD.
882 */
883typedef struct dwc_otg_cil_callbacks
884{
885        /** Start function for role change */
886        int (*start) (void *_p);
887        /** Stop Function for role change */
888        int (*stop) (void *_p);
889        /** Disconnect Function for role change */
890        int (*disconnect) (void *_p);
891        /** Resume/Remote wakeup Function */
892        int (*resume_wakeup) (void *_p);
893        /** Suspend function */
894        int (*suspend) (void *_p);
895        /** Session Start (SRP) */
896        int (*session_start) (void *_p);
897        /** Pointer passed to start() and stop() */
898        void *p;
899} dwc_otg_cil_callbacks_t;
900
901
902
903extern void dwc_otg_cil_register_pcd_callbacks( dwc_otg_core_if_t *_core_if,
904                                                dwc_otg_cil_callbacks_t *_cb,
905                                                void *_p);
906extern void dwc_otg_cil_register_hcd_callbacks( dwc_otg_core_if_t *_core_if,
907                                                dwc_otg_cil_callbacks_t *_cb,
908                                                void *_p);
909
910
911#endif
912

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