Root/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_driver.c

1/* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_driver.c $
3 * $Revision: 1.1.1.1 $
4 * $Date: 2009-04-17 06:15:34 $
5 * $Change: 631780 $
6 *
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
10 *
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
20 *
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
31 * DAMAGE.
32 * ========================================================================== */
33
34/** @file
35 * The dwc_otg_driver module provides the initialization and cleanup entry
36 * points for the DWC_otg driver. This module will be dynamically installed
37 * after Linux is booted using the insmod command. When the module is
38 * installed, the dwc_otg_init function is called. When the module is
39 * removed (using rmmod), the dwc_otg_cleanup function is called.
40 *
41 * This module also defines a data structure for the dwc_otg_driver, which is
42 * used in conjunction with the standard ARM lm_device structure. These
43 * structures allow the OTG driver to comply with the standard Linux driver
44 * model in which devices and drivers are registered with a bus driver. This
45 * has the benefit that Linux can expose attributes of the driver and device
46 * in its special sysfs file system. Users can then read or write files in
47 * this file system to perform diagnostics on the driver components or the
48 * device.
49 */
50
51#include <linux/kernel.h>
52#include <linux/module.h>
53#include <linux/moduleparam.h>
54#include <linux/init.h>
55#include <linux/gpio.h>
56
57#include <linux/device.h>
58#include <linux/platform_device.h>
59
60#include <linux/errno.h>
61#include <linux/types.h>
62#include <linux/stat.h> /* permission constants */
63#include <linux/irq.h>
64#include <asm/io.h>
65
66#include "dwc_otg_plat.h"
67#include "dwc_otg_attr.h"
68#include "dwc_otg_driver.h"
69#include "dwc_otg_cil.h"
70#include "dwc_otg_cil_ifx.h"
71
72// #include "dwc_otg_pcd.h" // device
73#include "dwc_otg_hcd.h" // host
74
75#include "dwc_otg_ifx.h" // for Infineon platform specific.
76
77#define DWC_DRIVER_VERSION "2.60a 22-NOV-2006"
78#define DWC_DRIVER_DESC "HS OTG USB Controller driver"
79
80const char dwc_driver_name[] = "dwc_otg";
81
82static unsigned long dwc_iomem_base = IFX_USB_IOMEM_BASE;
83int dwc_irq = LTQ_USB_INT;
84//int dwc_irq = 54;
85//int dwc_irq = IFXMIPS_USB_OC_INT;
86
87extern int ifx_usb_hc_init(unsigned long base_addr, int irq);
88extern void ifx_usb_hc_remove(void);
89
90/*-------------------------------------------------------------------------*/
91/* Encapsulate the module parameter settings */
92
93static dwc_otg_core_params_t dwc_otg_module_params = {
94        .opt = -1,
95        .otg_cap = -1,
96        .dma_enable = -1,
97    .dma_burst_size = -1,
98    .speed = -1,
99    .host_support_fs_ls_low_power = -1,
100    .host_ls_low_power_phy_clk = -1,
101    .enable_dynamic_fifo = -1,
102    .data_fifo_size = -1,
103    .dev_rx_fifo_size = -1,
104    .dev_nperio_tx_fifo_size = -1,
105    .dev_perio_tx_fifo_size = /* dev_perio_tx_fifo_size_1 */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 15 */
106    .host_rx_fifo_size = -1,
107    .host_nperio_tx_fifo_size = -1,
108    .host_perio_tx_fifo_size = -1,
109    .max_transfer_size = -1,
110    .max_packet_count = -1,
111    .host_channels = -1,
112    .dev_endpoints = -1,
113    .phy_type = -1,
114        .phy_utmi_width = -1,
115        .phy_ulpi_ddr = -1,
116        .phy_ulpi_ext_vbus = -1,
117    .i2c_enable = -1,
118    .ulpi_fs_ls = -1,
119    .ts_dline = -1,
120    .en_multiple_tx_fifo = -1,
121    .dev_tx_fifo_size = { /* dev_tx_fifo_size */
122     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
123    }, /* 15 */
124    .thr_ctl = -1,
125    .tx_thr_length = -1,
126    .rx_thr_length = -1,
127};
128
129/**
130 * This function shows the Driver Version.
131 */
132static ssize_t version_show(struct device_driver *dev, char *buf)
133{
134        return snprintf(buf, sizeof(DWC_DRIVER_VERSION)+2,"%s\n",
135                        DWC_DRIVER_VERSION);
136}
137static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
138
139/**
140 * Global Debug Level Mask.
141 */
142uint32_t g_dbg_lvl = 0xff; /* OFF */
143
144/**
145 * This function shows the driver Debug Level.
146 */
147static ssize_t dbg_level_show(struct device_driver *_drv, char *_buf)
148{
149        return sprintf(_buf, "0x%0x\n", g_dbg_lvl);
150}
151/**
152 * This function stores the driver Debug Level.
153 */
154static ssize_t dbg_level_store(struct device_driver *_drv, const char *_buf,
155                               size_t _count)
156{
157    g_dbg_lvl = simple_strtoul(_buf, NULL, 16);
158        return _count;
159}
160static DRIVER_ATTR(debuglevel, S_IRUGO|S_IWUSR, dbg_level_show, dbg_level_store);
161
162/**
163 * This function is called during module intialization to verify that
164 * the module parameters are in a valid state.
165 */
166static int check_parameters(dwc_otg_core_if_t *core_if)
167{
168    int i;
169    int retval = 0;
170
171/* Checks if the parameter is outside of its valid range of values */
172#define DWC_OTG_PARAM_TEST(_param_,_low_,_high_) \
173    ((dwc_otg_module_params._param_ < (_low_)) || \
174         (dwc_otg_module_params._param_ > (_high_)))
175
176/* If the parameter has been set by the user, check that the parameter value is
177 * within the value range of values. If not, report a module error. */
178#define DWC_OTG_PARAM_ERR(_param_,_low_,_high_,_string_) \
179        do { \
180        if (dwc_otg_module_params._param_ != -1) { \
181            if (DWC_OTG_PARAM_TEST(_param_,(_low_),(_high_))) { \
182                DWC_ERROR("`%d' invalid for parameter `%s'\n", \
183                      dwc_otg_module_params._param_, _string_); \
184                dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \
185                retval ++; \
186            } \
187        } \
188    } while (0)
189
190    DWC_OTG_PARAM_ERR(opt,0,1,"opt");
191    DWC_OTG_PARAM_ERR(otg_cap,0,2,"otg_cap");
192        DWC_OTG_PARAM_ERR(dma_enable,0,1,"dma_enable");
193    DWC_OTG_PARAM_ERR(speed,0,1,"speed");
194    DWC_OTG_PARAM_ERR(host_support_fs_ls_low_power,0,1,"host_support_fs_ls_low_power");
195    DWC_OTG_PARAM_ERR(host_ls_low_power_phy_clk,0,1,"host_ls_low_power_phy_clk");
196    DWC_OTG_PARAM_ERR(enable_dynamic_fifo,0,1,"enable_dynamic_fifo");
197    DWC_OTG_PARAM_ERR(data_fifo_size,32,32768,"data_fifo_size");
198    DWC_OTG_PARAM_ERR(dev_rx_fifo_size,16,32768,"dev_rx_fifo_size");
199    DWC_OTG_PARAM_ERR(dev_nperio_tx_fifo_size,16,32768,"dev_nperio_tx_fifo_size");
200    DWC_OTG_PARAM_ERR(host_rx_fifo_size,16,32768,"host_rx_fifo_size");
201    DWC_OTG_PARAM_ERR(host_nperio_tx_fifo_size,16,32768,"host_nperio_tx_fifo_size");
202    DWC_OTG_PARAM_ERR(host_perio_tx_fifo_size,16,32768,"host_perio_tx_fifo_size");
203    DWC_OTG_PARAM_ERR(max_transfer_size,2047,524288,"max_transfer_size");
204    DWC_OTG_PARAM_ERR(max_packet_count,15,511,"max_packet_count");
205    DWC_OTG_PARAM_ERR(host_channels,1,16,"host_channels");
206    DWC_OTG_PARAM_ERR(dev_endpoints,1,15,"dev_endpoints");
207    DWC_OTG_PARAM_ERR(phy_type,0,2,"phy_type");
208        DWC_OTG_PARAM_ERR(phy_ulpi_ddr,0,1,"phy_ulpi_ddr");
209        DWC_OTG_PARAM_ERR(phy_ulpi_ext_vbus,0,1,"phy_ulpi_ext_vbus");
210    DWC_OTG_PARAM_ERR(i2c_enable,0,1,"i2c_enable");
211    DWC_OTG_PARAM_ERR(ulpi_fs_ls,0,1,"ulpi_fs_ls");
212    DWC_OTG_PARAM_ERR(ts_dline,0,1,"ts_dline");
213
214    if (dwc_otg_module_params.dma_burst_size != -1) {
215        if (DWC_OTG_PARAM_TEST(dma_burst_size,1,1) &&
216            DWC_OTG_PARAM_TEST(dma_burst_size,4,4) &&
217            DWC_OTG_PARAM_TEST(dma_burst_size,8,8) &&
218            DWC_OTG_PARAM_TEST(dma_burst_size,16,16) &&
219            DWC_OTG_PARAM_TEST(dma_burst_size,32,32) &&
220            DWC_OTG_PARAM_TEST(dma_burst_size,64,64) &&
221            DWC_OTG_PARAM_TEST(dma_burst_size,128,128) &&
222            DWC_OTG_PARAM_TEST(dma_burst_size,256,256))
223        {
224            DWC_ERROR("`%d' invalid for parameter `dma_burst_size'\n",
225                  dwc_otg_module_params.dma_burst_size);
226            dwc_otg_module_params.dma_burst_size = 32;
227            retval ++;
228        }
229    }
230
231    if (dwc_otg_module_params.phy_utmi_width != -1) {
232        if (DWC_OTG_PARAM_TEST(phy_utmi_width,8,8) &&
233            DWC_OTG_PARAM_TEST(phy_utmi_width,16,16))
234        {
235            DWC_ERROR("`%d' invalid for parameter `phy_utmi_width'\n",
236                  dwc_otg_module_params.phy_utmi_width);
237            //dwc_otg_module_params.phy_utmi_width = 16;
238            dwc_otg_module_params.phy_utmi_width = 8;
239            retval ++;
240        }
241    }
242
243    for (i=0; i<15; i++) {
244        /** @todo should be like above */
245        //DWC_OTG_PARAM_ERR(dev_perio_tx_fifo_size[i],4,768,"dev_perio_tx_fifo_size");
246        if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
247            if (DWC_OTG_PARAM_TEST(dev_perio_tx_fifo_size[i],4,768)) {
248                DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
249                      dwc_otg_module_params.dev_perio_tx_fifo_size[i], "dev_perio_tx_fifo_size", i);
250                dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
251                retval ++;
252            }
253        }
254    }
255
256    DWC_OTG_PARAM_ERR(en_multiple_tx_fifo, 0, 1, "en_multiple_tx_fifo");
257    for (i = 0; i < 15; i++) {
258        /** @todo should be like above */
259            //DWC_OTG_PARAM_ERR(dev_tx_fifo_size[i],4,768,"dev_tx_fifo_size");
260            if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
261            if (DWC_OTG_PARAM_TEST(dev_tx_fifo_size[i], 4, 768)) {
262                DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
263                    dwc_otg_module_params.dev_tx_fifo_size[i],
264                     "dev_tx_fifo_size", i);
265                dwc_otg_module_params.dev_tx_fifo_size[i] =
266                    dwc_param_dev_tx_fifo_size_default;
267                retval++;
268            }
269        }
270    }
271    DWC_OTG_PARAM_ERR(thr_ctl, 0, 7, "thr_ctl");
272    DWC_OTG_PARAM_ERR(tx_thr_length, 8, 128, "tx_thr_length");
273    DWC_OTG_PARAM_ERR(rx_thr_length, 8, 128, "rx_thr_length");
274
275    /* At this point, all module parameters that have been set by the user
276     * are valid, and those that have not are left unset. Now set their
277     * default values and/or check the parameters against the hardware
278     * configurations of the OTG core. */
279
280
281
282/* This sets the parameter to the default value if it has not been set by the
283 * user */
284#define DWC_OTG_PARAM_SET_DEFAULT(_param_) \
285    ({ \
286        int changed = 1; \
287        if (dwc_otg_module_params._param_ == -1) { \
288            changed = 0; \
289            dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \
290        } \
291        changed; \
292    })
293
294/* This checks the macro agains the hardware configuration to see if it is
295 * valid. It is possible that the default value could be invalid. In this
296 * case, it will report a module error if the user touched the parameter.
297 * Otherwise it will adjust the value without any error. */
298#define DWC_OTG_PARAM_CHECK_VALID(_param_,_str_,_is_valid_,_set_valid_) \
299    ({ \
300            int changed = DWC_OTG_PARAM_SET_DEFAULT(_param_); \
301        int error = 0; \
302        if (!(_is_valid_)) { \
303            if (changed) { \
304                DWC_ERROR("`%d' invalid for parameter `%s'. Check HW configuration.\n", dwc_otg_module_params._param_,_str_); \
305                error = 1; \
306            } \
307            dwc_otg_module_params._param_ = (_set_valid_); \
308        } \
309        error; \
310    })
311
312    /* OTG Cap */
313    retval += DWC_OTG_PARAM_CHECK_VALID(otg_cap,"otg_cap",
314                  ({
315              int valid;
316              valid = 1;
317              switch (dwc_otg_module_params.otg_cap) {
318              case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
319                  if (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) valid = 0;
320                  break;
321              case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
322                  if ((core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) &&
323                      (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) &&
324                      (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) &&
325                      (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST))
326                  {
327                      valid = 0;
328                  }
329                  break;
330              case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
331                  /* always valid */
332                  break;
333              }
334              valid;
335          }),
336                  (((core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ||
337            (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) ||
338            (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
339            (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
340           DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
341           DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE));
342    
343    retval += DWC_OTG_PARAM_CHECK_VALID(dma_enable,"dma_enable",
344                        ((dwc_otg_module_params.dma_enable == 1) && (core_if->hwcfg2.b.architecture == 0)) ? 0 : 1,
345                        0);
346
347    retval += DWC_OTG_PARAM_CHECK_VALID(opt,"opt",
348                        1,
349                        0);
350
351    DWC_OTG_PARAM_SET_DEFAULT(dma_burst_size);
352
353    retval += DWC_OTG_PARAM_CHECK_VALID(host_support_fs_ls_low_power,
354                        "host_support_fs_ls_low_power",
355                        1, 0);
356
357    retval += DWC_OTG_PARAM_CHECK_VALID(enable_dynamic_fifo,
358                  "enable_dynamic_fifo",
359                  ((dwc_otg_module_params.enable_dynamic_fifo == 0) ||
360                   (core_if->hwcfg2.b.dynamic_fifo == 1)), 0);
361
362
363    retval += DWC_OTG_PARAM_CHECK_VALID(data_fifo_size,
364                  "data_fifo_size",
365                  (dwc_otg_module_params.data_fifo_size <= core_if->hwcfg3.b.dfifo_depth),
366                  core_if->hwcfg3.b.dfifo_depth);
367
368    retval += DWC_OTG_PARAM_CHECK_VALID(dev_rx_fifo_size,
369                  "dev_rx_fifo_size",
370                  (dwc_otg_module_params.dev_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
371                  dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
372
373    retval += DWC_OTG_PARAM_CHECK_VALID(dev_nperio_tx_fifo_size,
374                  "dev_nperio_tx_fifo_size",
375                  (dwc_otg_module_params.dev_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
376                  (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
377
378    retval += DWC_OTG_PARAM_CHECK_VALID(host_rx_fifo_size,
379                        "host_rx_fifo_size",
380                        (dwc_otg_module_params.host_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
381                        dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
382
383
384    retval += DWC_OTG_PARAM_CHECK_VALID(host_nperio_tx_fifo_size,
385                  "host_nperio_tx_fifo_size",
386                  (dwc_otg_module_params.host_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
387                  (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
388
389    retval += DWC_OTG_PARAM_CHECK_VALID(host_perio_tx_fifo_size,
390                        "host_perio_tx_fifo_size",
391                        (dwc_otg_module_params.host_perio_tx_fifo_size <= ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))),
392                        ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16)));
393
394    retval += DWC_OTG_PARAM_CHECK_VALID(max_transfer_size,
395                  "max_transfer_size",
396                  (dwc_otg_module_params.max_transfer_size < (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))),
397                  ((1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1));
398
399    retval += DWC_OTG_PARAM_CHECK_VALID(max_packet_count,
400                  "max_packet_count",
401                  (dwc_otg_module_params.max_packet_count < (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))),
402                  ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1));
403
404    retval += DWC_OTG_PARAM_CHECK_VALID(host_channels,
405                  "host_channels",
406                  (dwc_otg_module_params.host_channels <= (core_if->hwcfg2.b.num_host_chan + 1)),
407                  (core_if->hwcfg2.b.num_host_chan + 1));
408
409    retval += DWC_OTG_PARAM_CHECK_VALID(dev_endpoints,
410                  "dev_endpoints",
411                  (dwc_otg_module_params.dev_endpoints <= (core_if->hwcfg2.b.num_dev_ep)),
412                  core_if->hwcfg2.b.num_dev_ep);
413
414/*
415 * Define the following to disable the FS PHY Hardware checking. This is for
416 * internal testing only.
417 *
418 * #define NO_FS_PHY_HW_CHECKS
419 */
420
421#ifdef NO_FS_PHY_HW_CHECKS
422    retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
423                        "phy_type", 1, 0);
424#else
425    retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
426                        "phy_type",
427                        ({
428                            int valid = 0;
429                            if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_UTMI) &&
430                            ((core_if->hwcfg2.b.hs_phy_type == 1) ||
431                             (core_if->hwcfg2.b.hs_phy_type == 3)))
432                            {
433                                valid = 1;
434                            }
435                            else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_ULPI) &&
436                                 ((core_if->hwcfg2.b.hs_phy_type == 2) ||
437                                  (core_if->hwcfg2.b.hs_phy_type == 3)))
438                            {
439                                valid = 1;
440                            }
441                            else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) &&
442                                 (core_if->hwcfg2.b.fs_phy_type == 1))
443                            {
444                                valid = 1;
445                            }
446                            valid;
447                        }),
448                        ({
449                            int set = DWC_PHY_TYPE_PARAM_FS;
450                            if (core_if->hwcfg2.b.hs_phy_type) {
451                                if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
452                                (core_if->hwcfg2.b.hs_phy_type == 1)) {
453                                    set = DWC_PHY_TYPE_PARAM_UTMI;
454                                }
455                                else {
456                                    set = DWC_PHY_TYPE_PARAM_ULPI;
457                                }
458                            }
459                            set;
460                        }));
461#endif
462
463    retval += DWC_OTG_PARAM_CHECK_VALID(speed,"speed",
464                        (dwc_otg_module_params.speed == 0) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1,
465                        dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
466
467    retval += DWC_OTG_PARAM_CHECK_VALID(host_ls_low_power_phy_clk,
468                        "host_ls_low_power_phy_clk",
469                        ((dwc_otg_module_params.host_ls_low_power_phy_clk == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1),
470                        ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ : DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ));
471
472        DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ddr);
473        DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ext_vbus);
474        DWC_OTG_PARAM_SET_DEFAULT(phy_utmi_width);
475        DWC_OTG_PARAM_SET_DEFAULT(ulpi_fs_ls);
476        DWC_OTG_PARAM_SET_DEFAULT(ts_dline);
477
478#ifdef NO_FS_PHY_HW_CHECKS
479    retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable,
480                        "i2c_enable", 1, 0);
481#else
482    retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable,
483                        "i2c_enable",
484                        (dwc_otg_module_params.i2c_enable == 1) && (core_if->hwcfg3.b.i2c == 0) ? 0 : 1,
485                        0);
486#endif
487
488    for (i=0; i<16; i++) {
489
490        int changed = 1;
491        int error = 0;
492
493        if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] == -1) {
494            changed = 0;
495            dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
496        }
497        if (!(dwc_otg_module_params.dev_perio_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) {
498            if (changed) {
499                DWC_ERROR("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params.dev_perio_tx_fifo_size[i],i);
500                error = 1;
501            }
502            dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
503        }
504        retval += error;
505    }
506
507    retval += DWC_OTG_PARAM_CHECK_VALID(en_multiple_tx_fifo,
508                "en_multiple_tx_fifo",
509                ((dwc_otg_module_params.en_multiple_tx_fifo == 1) &&
510                (core_if->hwcfg4.b.ded_fifo_en == 0)) ? 0 : 1, 0);
511
512    for (i = 0; i < 16; i++) {
513        int changed = 1;
514        int error = 0;
515        if (dwc_otg_module_params.dev_tx_fifo_size[i] == -1) {
516            changed = 0;
517            dwc_otg_module_params.dev_tx_fifo_size[i] =
518                dwc_param_dev_tx_fifo_size_default;
519        }
520        if (!(dwc_otg_module_params.dev_tx_fifo_size[i] <=
521             (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) {
522            if (changed) {
523                DWC_ERROR("%d' invalid for parameter `dev_perio_fifo_size_%d'."
524                    "Check HW configuration.\n",dwc_otg_module_params.dev_tx_fifo_size[i],i);
525                error = 1;
526            }
527            dwc_otg_module_params.dev_tx_fifo_size[i] =
528                dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
529        }
530        retval += error;
531    }
532    DWC_OTG_PARAM_SET_DEFAULT(thr_ctl);
533    DWC_OTG_PARAM_SET_DEFAULT(tx_thr_length);
534    DWC_OTG_PARAM_SET_DEFAULT(rx_thr_length);
535    return retval;
536} // check_parameters
537
538
539/**
540 * This function is the top level interrupt handler for the Common
541 * (Device and host modes) interrupts.
542 */
543static irqreturn_t dwc_otg_common_irq(int _irq, void *_dev)
544{
545    dwc_otg_device_t *otg_dev = _dev;
546    int32_t retval = IRQ_NONE;
547
548    retval = dwc_otg_handle_common_intr( otg_dev->core_if );
549
550    mask_and_ack_ifx_irq (_irq);
551    
552    return IRQ_RETVAL(retval);
553}
554
555
556/**
557 * This function is called when a DWC_OTG device is unregistered with the
558 * dwc_otg_driver. This happens, for example, when the rmmod command is
559 * executed. The device may or may not be electrically present. If it is
560 * present, the driver stops device processing. Any resources used on behalf
561 * of this device are freed.
562 *
563 * @return
564 */
565static int
566dwc_otg_driver_remove(struct platform_device *_dev)
567{
568    //dwc_otg_device_t *otg_dev = dev_get_drvdata(&_dev->dev);
569    dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev);
570
571    DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
572
573    if (otg_dev == NULL) {
574        /* Memory allocation for the dwc_otg_device failed. */
575        return 0;
576    }
577
578    /*
579    * Free the IRQ
580    */
581    if (otg_dev->common_irq_installed) {
582        free_irq( otg_dev->irq, otg_dev );
583    }
584
585#ifndef DWC_DEVICE_ONLY
586    if (otg_dev->hcd != NULL) {
587        dwc_otg_hcd_remove(&_dev->dev);
588    }
589#endif
590    printk("after removehcd\n");
591
592// Note: Integrate HOST and DEVICE(Gadget) is not planned yet.
593#ifndef DWC_HOST_ONLY
594    if (otg_dev->pcd != NULL) {
595        dwc_otg_pcd_remove(otg_dev);
596    }
597#endif
598    if (otg_dev->core_if != NULL) {
599        dwc_otg_cil_remove( otg_dev->core_if );
600    }
601    printk("after removecil\n");
602
603    /*
604     * Remove the device attributes
605     */
606    dwc_otg_attr_remove(&_dev->dev);
607    printk("after removeattr\n");
608
609    /*
610     * Return the memory.
611     */
612    if (otg_dev->base != NULL) {
613        iounmap(otg_dev->base);
614    }
615    if (otg_dev->phys_addr != 0) {
616        release_mem_region(otg_dev->phys_addr, otg_dev->base_len);
617    }
618    kfree(otg_dev);
619        
620    /*
621     * Clear the drvdata pointer.
622     */
623    //dev_set_drvdata(&_dev->dev, 0);
624    platform_set_drvdata(_dev, 0);
625    return 0;
626}
627
628/**
629 * This function is called when an DWC_OTG device is bound to a
630 * dwc_otg_driver. It creates the driver components required to
631 * control the device (CIL, HCD, and PCD) and it initializes the
632 * device. The driver components are stored in a dwc_otg_device
633 * structure. A reference to the dwc_otg_device is saved in the
634 * lm_device. This allows the driver to access the dwc_otg_device
635 * structure on subsequent calls to driver methods for this device.
636 *
637 * @return
638 */
639static int __devinit
640dwc_otg_driver_probe(struct platform_device *_dev)
641{
642    int retval = 0;
643    dwc_otg_device_t *dwc_otg_device;
644    int pin = (int)_dev->dev.platform_data;
645    int32_t snpsid;
646    struct resource *res;
647    gusbcfg_data_t usbcfg = {.d32 = 0};
648
649    // GPIOs
650    if(pin >= 0)
651    {
652        gpio_request(pin, "usb_power");
653        gpio_direction_output(pin, 1);
654        gpio_set_value(pin, 1);
655        gpio_export(pin, 0);
656    }
657    dev_dbg(&_dev->dev, "dwc_otg_driver_probe (%p)\n", _dev);
658
659    dwc_otg_device = kmalloc(sizeof(dwc_otg_device_t), GFP_KERNEL);
660    if (dwc_otg_device == 0) {
661        dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
662        retval = -ENOMEM;
663        goto fail;
664    }
665    memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
666    dwc_otg_device->reg_offset = 0xFFFFFFFF;
667
668    /*
669     * Retrieve the memory and IRQ resources.
670     */
671    dwc_otg_device->irq = platform_get_irq(_dev, 0);
672    if (dwc_otg_device->irq == 0) {
673        dev_err(&_dev->dev, "no device irq\n");
674        retval = -ENODEV;
675        goto fail;
676    }
677    dev_dbg(&_dev->dev, "OTG - device irq: %d\n", dwc_otg_device->irq);
678    res = platform_get_resource(_dev, IORESOURCE_MEM, 0);
679    if (res == NULL) {
680        dev_err(&_dev->dev, "no CSR address\n");
681        retval = -ENODEV;
682        goto fail;
683    }
684    dev_dbg(&_dev->dev, "OTG - ioresource_mem start0x%08x: end:0x%08x\n",
685        (unsigned)res->start, (unsigned)res->end);
686    dwc_otg_device->phys_addr = res->start;
687    dwc_otg_device->base_len = res->end - res->start + 1;
688    if (request_mem_region(dwc_otg_device->phys_addr, dwc_otg_device->base_len,
689        dwc_driver_name) == NULL) {
690        dev_err(&_dev->dev, "request_mem_region failed\n");
691        retval = -EBUSY;
692        goto fail;
693    }
694
695    /*
696     * Map the DWC_otg Core memory into virtual address space.
697     */
698    dwc_otg_device->base = ioremap_nocache(dwc_otg_device->phys_addr, dwc_otg_device->base_len);
699    if (dwc_otg_device->base == NULL) {
700        dev_err(&_dev->dev, "ioremap() failed\n");
701        retval = -ENOMEM;
702        goto fail;
703    }
704    dev_dbg(&_dev->dev, "mapped base=0x%08x\n", (unsigned)dwc_otg_device->base);
705
706    /*
707     * Attempt to ensure this device is really a DWC_otg Controller.
708     * Read and verify the SNPSID register contents. The value should be
709     * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX".
710     */
711    snpsid = dwc_read_reg32((uint32_t *)((uint8_t *)dwc_otg_device->base + 0x40));
712    if ((snpsid & 0xFFFFF000) != 0x4F542000) {
713        dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n", snpsid);
714        retval = -EINVAL;
715        goto fail;
716    }
717
718    /*
719     * Initialize driver data to point to the global DWC_otg
720     * Device structure.
721     */
722    platform_set_drvdata(_dev, dwc_otg_device);
723    dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
724    dwc_otg_device->core_if = dwc_otg_cil_init( dwc_otg_device->base, &dwc_otg_module_params);
725    if (dwc_otg_device->core_if == 0) {
726        dev_err(&_dev->dev, "CIL initialization failed!\n");
727        retval = -ENOMEM;
728        goto fail;
729    }
730    
731    /*
732     * Validate parameter values.
733     */
734    if (check_parameters(dwc_otg_device->core_if) != 0) {
735        retval = -EINVAL;
736        goto fail;
737    }
738
739    /* Added for PLB DMA phys virt mapping */
740    //dwc_otg_device->core_if->phys_addr = dwc_otg_device->phys_addr;
741    /*
742     * Create Device Attributes in sysfs
743     */
744    dwc_otg_attr_create (&_dev->dev);
745
746    /*
747     * Disable the global interrupt until all the interrupt
748     * handlers are installed.
749     */
750    dwc_otg_disable_global_interrupts( dwc_otg_device->core_if );
751    /*
752     * Install the interrupt handler for the common interrupts before
753     * enabling common interrupts in core_init below.
754     */
755    DWC_DEBUGPL( DBG_CIL, "registering (common) handler for irq%d\n", dwc_otg_device->irq);
756
757    retval = request_irq((unsigned int)dwc_otg_device->irq, dwc_otg_common_irq,
758        //SA_INTERRUPT|SA_SHIRQ, "dwc_otg", (void *)dwc_otg_device );
759        IRQF_SHARED, "dwc_otg", (void *)dwc_otg_device );
760        //IRQF_DISABLED, "dwc_otg", (void *)dwc_otg_device );
761    if (retval != 0) {
762        DWC_ERROR("request of irq%d failed retval: %d\n", dwc_otg_device->irq, retval);
763        retval = -EBUSY;
764        goto fail;
765    } else {
766        dwc_otg_device->common_irq_installed = 1;
767    }
768
769    /*
770     * Initialize the DWC_otg core.
771     */
772    dwc_otg_core_init( dwc_otg_device->core_if );
773
774
775#ifndef DWC_HOST_ONLY // otg device mode. (gadget.)
776    /*
777     * Initialize the PCD
778     */
779    retval = dwc_otg_pcd_init(dwc_otg_device);
780    if (retval != 0) {
781        DWC_ERROR("dwc_otg_pcd_init failed\n");
782        dwc_otg_device->pcd = NULL;
783        goto fail;
784    }
785#endif // DWC_HOST_ONLY
786
787#ifndef DWC_DEVICE_ONLY // otg host mode. (HCD)
788    /*
789     * Initialize the HCD
790     */
791#if 1 /*fscz*/
792    /* force_host_mode */
793    usbcfg.d32 = dwc_read_reg32(&dwc_otg_device->core_if->core_global_regs ->gusbcfg);
794    usbcfg.b.force_host_mode = 1;
795    dwc_write_reg32(&dwc_otg_device->core_if->core_global_regs ->gusbcfg, usbcfg.d32);
796#endif
797    retval = dwc_otg_hcd_init(&_dev->dev, dwc_otg_device);
798    if (retval != 0) {
799        DWC_ERROR("dwc_otg_hcd_init failed\n");
800        dwc_otg_device->hcd = NULL;
801        goto fail;
802    }
803#endif // DWC_DEVICE_ONLY
804
805    /*
806     * Enable the global interrupt after all the interrupt
807     * handlers are installed.
808     */
809    dwc_otg_enable_global_interrupts( dwc_otg_device->core_if );
810#if 0 /*fscz*/
811    usbcfg.d32 = dwc_read_reg32(&dwc_otg_device->core_if->core_global_regs ->gusbcfg);
812    usbcfg.b.force_host_mode = 0;
813    dwc_write_reg32(&dwc_otg_device->core_if->core_global_regs ->gusbcfg, usbcfg.d32);
814#endif
815
816
817    return 0;
818
819fail:
820    dwc_otg_driver_remove(_dev);
821    return retval;
822}
823
824/**
825 * This structure defines the methods to be called by a bus driver
826 * during the lifecycle of a device on that bus. Both drivers and
827 * devices are registered with a bus driver. The bus driver matches
828 * devices to drivers based on information in the device and driver
829 * structures.
830 *
831 * The probe function is called when the bus driver matches a device
832 * to this driver. The remove function is called when a device is
833 * unregistered with the bus driver.
834 */
835struct platform_driver dwc_otg_driver = {
836    .probe = dwc_otg_driver_probe,
837    .remove = dwc_otg_driver_remove,
838// .suspend = dwc_otg_driver_suspend,
839// .resume = dwc_otg_driver_resume,
840    .driver = {
841        .name = dwc_driver_name,
842        .owner = THIS_MODULE,
843    },
844};
845EXPORT_SYMBOL(dwc_otg_driver);
846
847/**
848 * This function is called when the dwc_otg_driver is installed with the
849 * insmod command. It registers the dwc_otg_driver structure with the
850 * appropriate bus driver. This will cause the dwc_otg_driver_probe function
851 * to be called. In addition, the bus driver will automatically expose
852 * attributes defined for the device and driver in the special sysfs file
853 * system.
854 *
855 * @return
856 */
857static int __init dwc_otg_init(void)
858{
859    int retval = 0;
860
861    printk(KERN_INFO "%s: version %s\n", dwc_driver_name, DWC_DRIVER_VERSION);
862
863    if (ltq_is_ase())
864        dwc_irq = LTQ_USB_ASE_INT;
865
866    // ifxmips setup
867    retval = ifx_usb_hc_init(dwc_iomem_base, dwc_irq);
868    if (retval < 0)
869    {
870        printk(KERN_ERR "%s retval=%d\n", __func__, retval);
871        return retval;
872    }
873    dwc_otg_power_on(); // ifx only!!
874
875
876    retval = platform_driver_register(&dwc_otg_driver);
877
878    if (retval < 0) {
879        printk(KERN_ERR "%s retval=%d\n", __func__, retval);
880        goto error1;
881    }
882
883    retval = driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
884    if (retval < 0)
885    {
886        printk(KERN_ERR "%s retval=%d\n", __func__, retval);
887        goto error2;
888    }
889    retval = driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
890    if (retval < 0)
891    {
892        printk(KERN_ERR "%s retval=%d\n", __func__, retval);
893        goto error3;
894    }
895    return retval;
896
897
898error3:
899    driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
900error2:
901    driver_unregister(&dwc_otg_driver.driver);
902error1:
903    ifx_usb_hc_remove();
904    return retval;
905}
906module_init(dwc_otg_init);
907
908/**
909 * This function is called when the driver is removed from the kernel
910 * with the rmmod command. The driver unregisters itself with its bus
911 * driver.
912 *
913 */
914static void __exit dwc_otg_cleanup(void)
915{
916    printk(KERN_DEBUG "dwc_otg_cleanup()\n");
917
918    driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
919    driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
920
921    platform_driver_unregister(&dwc_otg_driver);
922    ifx_usb_hc_remove();
923
924    printk(KERN_INFO "%s module removed\n", dwc_driver_name);
925}
926module_exit(dwc_otg_cleanup);
927
928MODULE_DESCRIPTION(DWC_DRIVER_DESC);
929MODULE_AUTHOR("Synopsys Inc.");
930MODULE_LICENSE("GPL");
931
932module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
933MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
934module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
935MODULE_PARM_DESC(opt, "OPT Mode");
936module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
937MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
938module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int, 0444);
939MODULE_PARM_DESC(dma_burst_size, "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
940module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
941MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
942module_param_named(host_support_fs_ls_low_power, dwc_otg_module_params.host_support_fs_ls_low_power, int, 0444);
943MODULE_PARM_DESC(host_support_fs_ls_low_power, "Support Low Power w/FS or LS 0=Support 1=Don't Support");
944module_param_named(host_ls_low_power_phy_clk, dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
945MODULE_PARM_DESC(host_ls_low_power_phy_clk, "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
946module_param_named(enable_dynamic_fifo, dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
947MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
948module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int, 0444);
949MODULE_PARM_DESC(data_fifo_size, "Total number of words in the data FIFO memory 32-32768");
950module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, int, 0444);
951MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
952module_param_named(dev_nperio_tx_fifo_size, dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
953MODULE_PARM_DESC(dev_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
954module_param_named(dev_perio_tx_fifo_size_1, dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
955MODULE_PARM_DESC(dev_perio_tx_fifo_size_1, "Number of words in the periodic Tx FIFO 4-768");
956module_param_named(dev_perio_tx_fifo_size_2, dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
957MODULE_PARM_DESC(dev_perio_tx_fifo_size_2, "Number of words in the periodic Tx FIFO 4-768");
958module_param_named(dev_perio_tx_fifo_size_3, dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
959MODULE_PARM_DESC(dev_perio_tx_fifo_size_3, "Number of words in the periodic Tx FIFO 4-768");
960module_param_named(dev_perio_tx_fifo_size_4, dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
961MODULE_PARM_DESC(dev_perio_tx_fifo_size_4, "Number of words in the periodic Tx FIFO 4-768");
962module_param_named(dev_perio_tx_fifo_size_5, dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
963MODULE_PARM_DESC(dev_perio_tx_fifo_size_5, "Number of words in the periodic Tx FIFO 4-768");
964module_param_named(dev_perio_tx_fifo_size_6, dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
965MODULE_PARM_DESC(dev_perio_tx_fifo_size_6, "Number of words in the periodic Tx FIFO 4-768");
966module_param_named(dev_perio_tx_fifo_size_7, dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
967MODULE_PARM_DESC(dev_perio_tx_fifo_size_7, "Number of words in the periodic Tx FIFO 4-768");
968module_param_named(dev_perio_tx_fifo_size_8, dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
969MODULE_PARM_DESC(dev_perio_tx_fifo_size_8, "Number of words in the periodic Tx FIFO 4-768");
970module_param_named(dev_perio_tx_fifo_size_9, dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
971MODULE_PARM_DESC(dev_perio_tx_fifo_size_9, "Number of words in the periodic Tx FIFO 4-768");
972module_param_named(dev_perio_tx_fifo_size_10, dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
973MODULE_PARM_DESC(dev_perio_tx_fifo_size_10, "Number of words in the periodic Tx FIFO 4-768");
974module_param_named(dev_perio_tx_fifo_size_11, dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
975MODULE_PARM_DESC(dev_perio_tx_fifo_size_11, "Number of words in the periodic Tx FIFO 4-768");
976module_param_named(dev_perio_tx_fifo_size_12, dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
977MODULE_PARM_DESC(dev_perio_tx_fifo_size_12, "Number of words in the periodic Tx FIFO 4-768");
978module_param_named(dev_perio_tx_fifo_size_13, dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
979MODULE_PARM_DESC(dev_perio_tx_fifo_size_13, "Number of words in the periodic Tx FIFO 4-768");
980module_param_named(dev_perio_tx_fifo_size_14, dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
981MODULE_PARM_DESC(dev_perio_tx_fifo_size_14, "Number of words in the periodic Tx FIFO 4-768");
982module_param_named(dev_perio_tx_fifo_size_15, dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
983MODULE_PARM_DESC(dev_perio_tx_fifo_size_15, "Number of words in the periodic Tx FIFO 4-768");
984module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size, int, 0444);
985MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
986module_param_named(host_nperio_tx_fifo_size, dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
987MODULE_PARM_DESC(host_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
988module_param_named(host_perio_tx_fifo_size, dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
989MODULE_PARM_DESC(host_perio_tx_fifo_size, "Number of words in the host periodic Tx FIFO 16-32768");
990module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size, int, 0444);
991/** @todo Set the max to 512K, modify checks */
992MODULE_PARM_DESC(max_transfer_size, "The maximum transfer size supported in bytes 2047-65535");
993module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count, int, 0444);
994MODULE_PARM_DESC(max_packet_count, "The maximum number of packets in a transfer 15-511");
995module_param_named(host_channels, dwc_otg_module_params.host_channels, int, 0444);
996MODULE_PARM_DESC(host_channels, "The number of host channel registers to use 1-16");
997module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int, 0444);
998MODULE_PARM_DESC(dev_endpoints, "The number of endpoints in addition to EP0 available for device mode 1-15");
999module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
1000MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
1001module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int, 0444);
1002MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
1003module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
1004MODULE_PARM_DESC(phy_ulpi_ddr, "ULPI at double or single data rate 0=Single 1=Double");
1005module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus, int, 0444);
1006MODULE_PARM_DESC(phy_ulpi_ext_vbus, "ULPI PHY using internal or external vbus 0=Internal");
1007module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
1008MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
1009module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
1010MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
1011module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
1012MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
1013module_param_named(debug, g_dbg_lvl, int, 0444);
1014MODULE_PARM_DESC(debug, "0");
1015module_param_named(en_multiple_tx_fifo,
1016             dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
1017MODULE_PARM_DESC(en_multiple_tx_fifo,
1018          "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
1019module_param_named(dev_tx_fifo_size_1,
1020            dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
1021MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
1022module_param_named(dev_tx_fifo_size_2,
1023            dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
1024MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
1025module_param_named(dev_tx_fifo_size_3,
1026            dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
1027MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
1028module_param_named(dev_tx_fifo_size_4,
1029            dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
1030MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
1031module_param_named(dev_tx_fifo_size_5,
1032            dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
1033MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
1034module_param_named(dev_tx_fifo_size_6,
1035            dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
1036MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
1037module_param_named(dev_tx_fifo_size_7,
1038            dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
1039MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
1040module_param_named(dev_tx_fifo_size_8,
1041            dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
1042MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
1043module_param_named(dev_tx_fifo_size_9,
1044            dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
1045MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
1046module_param_named(dev_tx_fifo_size_10,
1047            dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
1048MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
1049module_param_named(dev_tx_fifo_size_11,
1050            dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
1051MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
1052module_param_named(dev_tx_fifo_size_12,
1053            dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
1054MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
1055module_param_named(dev_tx_fifo_size_13,
1056            dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
1057MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
1058module_param_named(dev_tx_fifo_size_14,
1059            dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
1060MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
1061module_param_named(dev_tx_fifo_size_15,
1062            dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
1063MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
1064module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
1065MODULE_PARM_DESC(thr_ctl, "Thresholding enable flag bit"
1066        "0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
1067module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int, 0444);
1068MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
1069module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int, 0444);
1070MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
1071module_param_named (iomem_base, dwc_iomem_base, ulong, 0444);
1072MODULE_PARM_DESC (dwc_iomem_base, "The base address of the DWC_OTG register.");
1073module_param_named (irq, dwc_irq, int, 0444);
1074MODULE_PARM_DESC (dwc_irq, "The interrupt number");
1075
1076/** @page "Module Parameters"
1077 *
1078 * The following parameters may be specified when starting the module.
1079 * These parameters define how the DWC_otg controller should be
1080 * configured. Parameter values are passed to the CIL initialization
1081 * function dwc_otg_cil_init
1082 *
1083 * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
1084 *
1085 
1086 <table>
1087 <tr><td>Parameter Name</td><td>Meaning</td></tr>
1088 
1089 <tr>
1090 <td>otg_cap</td>
1091 <td>Specifies the OTG capabilities. The driver will automatically detect the
1092 value for this parameter if none is specified.
1093 - 0: HNP and SRP capable (default, if available)
1094 - 1: SRP Only capable
1095 - 2: No HNP/SRP capable
1096 </td></tr>
1097 
1098 <tr>
1099 <td>dma_enable</td>
1100 <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
1101 The driver will automatically detect the value for this parameter if none is
1102 specified.
1103 - 0: Slave
1104 - 1: DMA (default, if available)
1105 </td></tr>
1106 
1107 <tr>
1108 <td>dma_burst_size</td>
1109 <td>The DMA Burst size (applicable only for External DMA Mode).
1110 - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
1111 </td></tr>
1112 
1113 <tr>
1114 <td>speed</td>
1115 <td>Specifies the maximum speed of operation in host and device mode. The
1116 actual speed depends on the speed of the attached device and the value of
1117 phy_type.
1118 - 0: High Speed (default)
1119 - 1: Full Speed
1120 </td></tr>
1121 
1122 <tr>
1123 <td>host_support_fs_ls_low_power</td>
1124 <td>Specifies whether low power mode is supported when attached to a Full
1125 Speed or Low Speed device in host mode.
1126 - 0: Don't support low power mode (default)
1127 - 1: Support low power mode
1128 </td></tr>
1129 
1130 <tr>
1131 <td>host_ls_low_power_phy_clk</td>
1132 <td>Specifies the PHY clock rate in low power mode when connected to a Low
1133 Speed device in host mode. This parameter is applicable only if
1134 HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
1135 - 0: 48 MHz (default)
1136 - 1: 6 MHz
1137 </td></tr>
1138 
1139 <tr>
1140 <td>enable_dynamic_fifo</td>
1141 <td> Specifies whether FIFOs may be resized by the driver software.
1142 - 0: Use cC FIFO size parameters
1143 - 1: Allow dynamic FIFO sizing (default)
1144 </td></tr>
1145 
1146 <tr>
1147 <td>data_fifo_size</td>
1148 <td>Total number of 4-byte words in the data FIFO memory. This memory
1149 includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
1150 - Values: 32 to 32768 (default 8192)
1151
1152 Note: The total FIFO memory depth in the FPGA configuration is 8192.
1153 </td></tr>
1154 
1155 <tr>
1156 <td>dev_rx_fifo_size</td>
1157 <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
1158 FIFO sizing is enabled.
1159 - Values: 16 to 32768 (default 1064)
1160 </td></tr>
1161 
1162 <tr>
1163 <td>dev_nperio_tx_fifo_size</td>
1164 <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
1165 dynamic FIFO sizing is enabled.
1166 - Values: 16 to 32768 (default 1024)
1167 </td></tr>
1168 
1169 <tr>
1170 <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
1171 <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
1172 when dynamic FIFO sizing is enabled.
1173 - Values: 4 to 768 (default 256)
1174 </td></tr>
1175 
1176 <tr>
1177 <td>host_rx_fifo_size</td>
1178 <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
1179 sizing is enabled.
1180 - Values: 16 to 32768 (default 1024)
1181 </td></tr>
1182 
1183 <tr>
1184 <td>host_nperio_tx_fifo_size</td>
1185 <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
1186 dynamic FIFO sizing is enabled in the core.
1187 - Values: 16 to 32768 (default 1024)
1188 </td></tr>
1189 
1190 <tr>
1191 <td>host_perio_tx_fifo_size</td>
1192 <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
1193 sizing is enabled.
1194 - Values: 16 to 32768 (default 1024)
1195 </td></tr>
1196 
1197 <tr>
1198 <td>max_transfer_size</td>
1199 <td>The maximum transfer size supported in bytes.
1200 - Values: 2047 to 65,535 (default 65,535)
1201 </td></tr>
1202 
1203 <tr>
1204 <td>max_packet_count</td>
1205 <td>The maximum number of packets in a transfer.
1206 - Values: 15 to 511 (default 511)
1207 </td></tr>
1208 
1209 <tr>
1210 <td>host_channels</td>
1211 <td>The number of host channel registers to use.
1212 - Values: 1 to 16 (default 12)
1213
1214 Note: The FPGA configuration supports a maximum of 12 host channels.
1215 </td></tr>
1216 
1217 <tr>
1218 <td>dev_endpoints</td>
1219 <td>The number of endpoints in addition to EP0 available for device mode
1220 operations.
1221 - Values: 1 to 15 (default 6 IN and OUT)
1222
1223 Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
1224 addition to EP0.
1225 </td></tr>
1226 
1227 <tr>
1228 <td>phy_type</td>
1229 <td>Specifies the type of PHY interface to use. By default, the driver will
1230 automatically detect the phy_type.
1231 - 0: Full Speed
1232 - 1: UTMI+ (default, if available)
1233 - 2: ULPI
1234 </td></tr>
1235 
1236 <tr>
1237 <td>phy_utmi_width</td>
1238 <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
1239 phy_type of UTMI+. Also, this parameter is applicable only if the
1240 OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
1241 core has been configured to work at either data path width.
1242 - Values: 8 or 16 bits (default 16)
1243 </td></tr>
1244 
1245 <tr>
1246 <td>phy_ulpi_ddr</td>
1247 <td>Specifies whether the ULPI operates at double or single data rate. This
1248 parameter is only applicable if phy_type is ULPI.
1249 - 0: single data rate ULPI interface with 8 bit wide data bus (default)
1250 - 1: double data rate ULPI interface with 4 bit wide data bus
1251 </td></tr>
1252
1253 <tr>
1254 <td>i2c_enable</td>
1255 <td>Specifies whether to use the I2C interface for full speed PHY. This
1256 parameter is only applicable if PHY_TYPE is FS.
1257 - 0: Disabled (default)
1258 - 1: Enabled
1259 </td></tr>
1260
1261 <tr>
1262 <td>otg_en_multiple_tx_fifo</td>
1263 <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
1264 The driver will automatically detect the value for this parameter if none is
1265 specified.
1266 - 0: Disabled
1267 - 1: Enabled (default, if available)
1268 </td></tr>
1269
1270 <tr>
1271 <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
1272 <td>Number of 4-byte words in each of the Tx FIFOs in device mode
1273 when dynamic FIFO sizing is enabled.
1274 - Values: 4 to 768 (default 256)
1275 </td></tr>
1276
1277*/
1278

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