Root/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_regs.h

1/* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_regs.h $
3 * $Revision: 1.1.1.1 $
4 * $Date: 2009-04-17 06:15:34 $
5 * $Change: 631780 $
6 *
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
10 *
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
20 *
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
31 * DAMAGE.
32 * ========================================================================== */
33
34#ifndef __DWC_OTG_REGS_H__
35#define __DWC_OTG_REGS_H__
36
37/**
38 * @file
39 *
40 * This file contains the data structures for accessing the DWC_otg core registers.
41 *
42 * The application interfaces with the HS OTG core by reading from and
43 * writing to the Control and Status Register (CSR) space through the
44 * AHB Slave interface. These registers are 32 bits wide, and the
45 * addresses are 32-bit-block aligned.
46 * CSRs are classified as follows:
47 * - Core Global Registers
48 * - Device Mode Registers
49 * - Device Global Registers
50 * - Device Endpoint Specific Registers
51 * - Host Mode Registers
52 * - Host Global Registers
53 * - Host Port CSRs
54 * - Host Channel Specific Registers
55 *
56 * Only the Core Global registers can be accessed in both Device and
57 * Host modes. When the HS OTG core is operating in one mode, either
58 * Device or Host, the application must not access registers from the
59 * other mode. When the core switches from one mode to another, the
60 * registers in the new mode of operation must be reprogrammed as they
61 * would be after a power-on reset.
62 */
63
64/****************************************************************************/
65/** DWC_otg Core registers .
66 * The dwc_otg_core_global_regs structure defines the size
67 * and relative field offsets for the Core Global registers.
68 */
69typedef struct dwc_otg_core_global_regs
70{
71        /** OTG Control and Status Register. <i>Offset: 000h</i> */
72        volatile uint32_t gotgctl;
73        /** OTG Interrupt Register. <i>Offset: 004h</i> */
74        volatile uint32_t gotgint;
75        /**Core AHB Configuration Register. <i>Offset: 008h</i> */
76        volatile uint32_t gahbcfg;
77#define DWC_GLBINTRMASK 0x0001
78#define DWC_DMAENABLE 0x0020
79#define DWC_NPTXEMPTYLVL_EMPTY 0x0080
80#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000
81#define DWC_PTXEMPTYLVL_EMPTY 0x0100
82#define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000
83
84
85        /**Core USB Configuration Register. <i>Offset: 00Ch</i> */
86        volatile uint32_t gusbcfg;
87        /**Core Reset Register. <i>Offset: 010h</i> */
88        volatile uint32_t grstctl;
89        /**Core Interrupt Register. <i>Offset: 014h</i> */
90        volatile uint32_t gintsts;
91        /**Core Interrupt Mask Register. <i>Offset: 018h</i> */
92        volatile uint32_t gintmsk;
93        /**Receive Status Queue Read Register (Read Only). <i>Offset: 01Ch</i> */
94        volatile uint32_t grxstsr;
95        /**Receive Status Queue Read & POP Register (Read Only). <i>Offset: 020h</i>*/
96        volatile uint32_t grxstsp;
97        /**Receive FIFO Size Register. <i>Offset: 024h</i> */
98        volatile uint32_t grxfsiz;
99        /**Non Periodic Transmit FIFO Size Register. <i>Offset: 028h</i> */
100        volatile uint32_t gnptxfsiz;
101        /**Non Periodic Transmit FIFO/Queue Status Register (Read
102         * Only). <i>Offset: 02Ch</i> */
103        volatile uint32_t gnptxsts;
104        /**I2C Access Register. <i>Offset: 030h</i> */
105        volatile uint32_t gi2cctl;
106        /**PHY Vendor Control Register. <i>Offset: 034h</i> */
107        volatile uint32_t gpvndctl;
108        /**General Purpose Input/Output Register. <i>Offset: 038h</i> */
109        volatile uint32_t ggpio;
110        /**User ID Register. <i>Offset: 03Ch</i> */
111        volatile uint32_t guid;
112        /**Synopsys ID Register (Read Only). <i>Offset: 040h</i> */
113        volatile uint32_t gsnpsid;
114        /**User HW Config1 Register (Read Only). <i>Offset: 044h</i> */
115        volatile uint32_t ghwcfg1;
116        /**User HW Config2 Register (Read Only). <i>Offset: 048h</i> */
117        volatile uint32_t ghwcfg2;
118#define DWC_SLAVE_ONLY_ARCH 0
119#define DWC_EXT_DMA_ARCH 1
120#define DWC_INT_DMA_ARCH 2
121
122#define DWC_MODE_HNP_SRP_CAPABLE 0
123#define DWC_MODE_SRP_ONLY_CAPABLE 1
124#define DWC_MODE_NO_HNP_SRP_CAPABLE 2
125#define DWC_MODE_SRP_CAPABLE_DEVICE 3
126#define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4
127#define DWC_MODE_SRP_CAPABLE_HOST 5
128#define DWC_MODE_NO_SRP_CAPABLE_HOST 6
129
130        /**User HW Config3 Register (Read Only). <i>Offset: 04Ch</i> */
131        volatile uint32_t ghwcfg3;
132        /**User HW Config4 Register (Read Only). <i>Offset: 050h</i>*/
133        volatile uint32_t ghwcfg4;
134        /** Reserved <i>Offset: 054h-0FFh</i> */
135        uint32_t reserved[43];
136        /** Host Periodic Transmit FIFO Size Register. <i>Offset: 100h</i> */
137        volatile uint32_t hptxfsiz;
138    /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled,
139        otherwise Device Transmit FIFO#n Register.
140         * <i>Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15).</i> */
141        //volatile uint32_t dptxfsiz[15];
142    volatile uint32_t dptxfsiz_dieptxf[15];
143} dwc_otg_core_global_regs_t;
144
145/**
146 * This union represents the bit fields of the Core OTG Control
147 * and Status Register (GOTGCTL). Set the bits using the bit
148 * fields then write the <i>d32</i> value to the register.
149 */
150typedef union gotgctl_data
151{
152        /** raw register data */
153        uint32_t d32;
154        /** register bits */
155        struct
156        {
157        unsigned reserved31_21 : 11;
158        unsigned currmod : 1;
159        unsigned bsesvld : 1;
160        unsigned asesvld : 1;
161        unsigned reserved17 : 1;
162        unsigned conidsts : 1;
163        unsigned reserved15_12 : 4;
164        unsigned devhnpen : 1;
165        unsigned hstsethnpen : 1;
166        unsigned hnpreq : 1;
167        unsigned hstnegscs : 1;
168        unsigned reserved7_2 : 6;
169        unsigned sesreq : 1;
170        unsigned sesreqscs : 1;
171        } b;
172} gotgctl_data_t;
173
174/**
175 * This union represents the bit fields of the Core OTG Interrupt Register
176 * (GOTGINT). Set/clear the bits using the bit fields then write the <i>d32</i>
177 * value to the register.
178 */
179typedef union gotgint_data
180{
181        /** raw register data */
182        uint32_t d32;
183        /** register bits */
184        struct
185        {
186        /** Current Mode */
187        unsigned reserved31_20 : 12;
188        /** Debounce Done */
189        unsigned debdone : 1;
190        /** A-Device Timeout Change */
191        unsigned adevtoutchng : 1;
192        /** Host Negotiation Detected */
193        unsigned hstnegdet : 1;
194        unsigned reserver16_10 : 7;
195        /** Host Negotiation Success Status Change */
196        unsigned hstnegsucstschng : 1;
197        /** Session Request Success Status Change */
198        unsigned sesreqsucstschng : 1;
199        unsigned reserved3_7 : 5;
200        /** Session End Detected */
201        unsigned sesenddet : 1;
202        /** Current Mode */
203        unsigned reserved1_0 : 2;
204        } b;
205} gotgint_data_t;
206
207
208/**
209 * This union represents the bit fields of the Core AHB Configuration
210 * Register (GAHBCFG). Set/clear the bits using the bit fields then
211 * write the <i>d32</i> value to the register.
212 */
213typedef union gahbcfg_data
214{
215        /** raw register data */
216        uint32_t d32;
217        /** register bits */
218        struct
219        {
220#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1
221#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
222                unsigned reserved9_31 : 23;
223                unsigned ptxfemplvl : 1;
224                unsigned nptxfemplvl_txfemplvl : 1;
225#define DWC_GAHBCFG_DMAENABLE 1
226                unsigned reserved : 1;
227                unsigned dmaenable : 1;
228#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0
229#define DWC_GAHBCFG_INT_DMA_BURST_INCR 1
230#define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3
231#define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5
232#define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7
233                unsigned hburstlen : 4;
234                unsigned glblintrmsk : 1;
235#define DWC_GAHBCFG_GLBINT_ENABLE 1
236
237        } b;
238} gahbcfg_data_t;
239
240/**
241 * This union represents the bit fields of the Core USB Configuration
242 * Register (GUSBCFG). Set the bits using the bit fields then write
243 * the <i>d32</i> value to the register.
244 */
245typedef union gusbcfg_data
246{
247        /** raw register data */
248        uint32_t d32;
249        /** register bits */
250        struct
251        {
252    unsigned corrupt_tx_packet: 1; /*fscz*/
253        unsigned force_device_mode: 1;
254        unsigned force_host_mode: 1;
255        unsigned reserved23_28 : 6;
256        unsigned term_sel_dl_pulse : 1;
257                unsigned ulpi_int_vbus_indicator : 1;
258                unsigned ulpi_ext_vbus_drv : 1;
259        unsigned ulpi_clk_sus_m : 1;
260        unsigned ulpi_auto_res : 1;
261        unsigned ulpi_fsls : 1;
262                unsigned otgutmifssel : 1;
263                unsigned phylpwrclksel : 1;
264                unsigned nptxfrwnden : 1;
265                unsigned usbtrdtim : 4;
266                unsigned hnpcap : 1;
267                unsigned srpcap : 1;
268                unsigned ddrsel : 1;
269                unsigned physel : 1;
270                unsigned fsintf : 1;
271                unsigned ulpi_utmi_sel : 1;
272                unsigned phyif : 1;
273                unsigned toutcal : 3;
274        } b;
275} gusbcfg_data_t;
276
277/**
278 * This union represents the bit fields of the Core Reset Register
279 * (GRSTCTL). Set/clear the bits using the bit fields then write the
280 * <i>d32</i> value to the register.
281 */
282typedef union grstctl_data
283{
284        /** raw register data */
285        uint32_t d32;
286        /** register bits */
287        struct
288        {
289                /** AHB Master Idle. Indicates the AHB Master State
290                 * Machine is in IDLE condition. */
291                unsigned ahbidle : 1;
292                /** DMA Request Signal. Indicated DMA request is in
293                 * probress. Used for debug purpose. */
294                unsigned dmareq : 1;
295                /** Reserved */
296            unsigned reserved29_11 : 19;
297                /** TxFIFO Number (TxFNum) (Device and Host).
298                 *
299                 * This is the FIFO number which needs to be flushed,
300                 * using the TxFIFO Flush bit. This field should not
301                 * be changed until the TxFIFO Flush bit is cleared by
302                 * the core.
303                 * - 0x0 : Non Periodic TxFIFO Flush
304                 * - 0x1 : Periodic TxFIFO #1 Flush in device mode
305                 * or Periodic TxFIFO in host mode
306                 * - 0x2 : Periodic TxFIFO #2 Flush in device mode.
307                 * - ...
308                 * - 0xF : Periodic TxFIFO #15 Flush in device mode
309                 * - 0x10: Flush all the Transmit NonPeriodic and
310                 * Transmit Periodic FIFOs in the core
311                 */
312                unsigned txfnum : 5;
313                /** TxFIFO Flush (TxFFlsh) (Device and Host).
314                 *
315                 * This bit is used to selectively flush a single or
316                 * all transmit FIFOs. The application must first
317                 * ensure that the core is not in the middle of a
318                 * transaction. <p>The application should write into
319                 * this bit, only after making sure that neither the
320                 * DMA engine is writing into the TxFIFO nor the MAC
321                 * is reading the data out of the FIFO. <p>The
322                 * application should wait until the core clears this
323                 * bit, before performing any operations. This bit
324                 * will takes 8 clocks (slowest of PHY or AHB clock)
325                 * to clear.
326                 */
327                unsigned txfflsh : 1;
328                /** RxFIFO Flush (RxFFlsh) (Device and Host)
329                 *
330                 * The application can flush the entire Receive FIFO
331                 * using this bit. <p>The application must first
332                 * ensure that the core is not in the middle of a
333                 * transaction. <p>The application should write into
334                 * this bit, only after making sure that neither the
335                 * DMA engine is reading from the RxFIFO nor the MAC
336                 * is writing the data in to the FIFO. <p>The
337                 * application should wait until the bit is cleared
338                 * before performing any other operations. This bit
339                 * will takes 8 clocks (slowest of PHY or AHB clock)
340                 * to clear.
341                 */
342                unsigned rxfflsh : 1;
343                /** In Token Sequence Learning Queue Flush
344                 * (INTknQFlsh) (Device Only)
345                 */
346                unsigned intknqflsh : 1;
347                /** Host Frame Counter Reset (Host Only)<br>
348                 *
349                 * The application can reset the (micro)frame number
350                 * counter inside the core, using this bit. When the
351                 * (micro)frame counter is reset, the subsequent SOF
352                 * sent out by the core, will have a (micro)frame
353                 * number of 0.
354                 */
355                unsigned hstfrm : 1;
356                /** Hclk Soft Reset
357         *
358         * The application uses this bit to reset the control logic in
359         * the AHB clock domain. Only AHB clock domain pipelines are
360         * reset.
361         */
362                unsigned hsftrst : 1;
363                /** Core Soft Reset (CSftRst) (Device and Host)
364                 *
365                 * The application can flush the control logic in the
366                 * entire core using this bit. This bit resets the
367                 * pipelines in the AHB Clock domain as well as the
368                 * PHY Clock domain.
369                 *
370                 * The state machines are reset to an IDLE state, the
371                 * control bits in the CSRs are cleared, all the
372                 * transmit FIFOs and the receive FIFO are flushed.
373                 *
374                 * The status mask bits that control the generation of
375                 * the interrupt, are cleared, to clear the
376                 * interrupt. The interrupt status bits are not
377                 * cleared, so the application can get the status of
378                 * any events that occurred in the core after it has
379                 * set this bit.
380                 *
381                 * Any transactions on the AHB are terminated as soon
382                 * as possible following the protocol. Any
383                 * transactions on the USB are terminated immediately.
384                 *
385                 * The configuration settings in the CSRs are
386                 * unchanged, so the software doesn't have to
387                 * reprogram these registers (Device
388                 * Configuration/Host Configuration/Core System
389                 * Configuration/Core PHY Configuration).
390                 *
391                 * The application can write to this bit, any time it
392                 * wants to reset the core. This is a self clearing
393                 * bit and the core clears this bit after all the
394                 * necessary logic is reset in the core, which may
395                 * take several clocks, depending on the current state
396                 * of the core.
397                 */
398                unsigned csftrst : 1;
399        } b;
400} grstctl_t;
401
402
403/**
404 * This union represents the bit fields of the Core Interrupt Mask
405 * Register (GINTMSK). Set/clear the bits using the bit fields then
406 * write the <i>d32</i> value to the register.
407 */
408typedef union gintmsk_data
409{
410        /** raw register data */
411        uint32_t d32;
412        /** register bits */
413        struct
414        {
415                unsigned wkupintr : 1;
416                unsigned sessreqintr : 1;
417                unsigned disconnect : 1;
418                unsigned conidstschng : 1;
419                unsigned reserved27 : 1;
420                unsigned ptxfempty : 1;
421                unsigned hcintr : 1;
422                unsigned portintr : 1;
423                unsigned reserved22_23 : 2;
424                unsigned incomplisoout : 1;
425                unsigned incomplisoin : 1;
426                unsigned outepintr : 1;
427                unsigned inepintr : 1;
428                unsigned epmismatch : 1;
429                unsigned reserved16 : 1;
430                unsigned eopframe : 1;
431                unsigned isooutdrop : 1;
432                unsigned enumdone : 1;
433                unsigned usbreset : 1;
434                unsigned usbsuspend : 1;
435                unsigned erlysuspend : 1;
436                unsigned i2cintr : 1;
437                unsigned reserved8 : 1;
438                unsigned goutnakeff : 1;
439                unsigned ginnakeff : 1;
440                unsigned nptxfempty : 1;
441                unsigned rxstsqlvl : 1;
442                unsigned sofintr : 1;
443                unsigned otgintr : 1;
444                unsigned modemismatch : 1;
445                unsigned reserved0 : 1;
446        } b;
447} gintmsk_data_t;
448/**
449 * This union represents the bit fields of the Core Interrupt Register
450 * (GINTSTS). Set/clear the bits using the bit fields then write the
451 * <i>d32</i> value to the register.
452 */
453typedef union gintsts_data
454{
455        /** raw register data */
456        uint32_t d32;
457#define DWC_SOF_INTR_MASK 0x0008
458        /** register bits */
459        struct
460        {
461#define DWC_HOST_MODE 1
462                unsigned wkupintr : 1;
463                unsigned sessreqintr : 1;
464                unsigned disconnect : 1;
465                unsigned conidstschng : 1;
466                unsigned reserved27 : 1;
467                unsigned ptxfempty : 1;
468                unsigned hcintr : 1;
469                unsigned portintr : 1;
470                unsigned reserved22_23 : 2;
471                unsigned incomplisoout : 1;
472                unsigned incomplisoin : 1;
473                unsigned outepintr : 1;
474                unsigned inepint: 1;
475                unsigned epmismatch : 1;
476                unsigned intokenrx : 1;
477                unsigned eopframe : 1;
478                unsigned isooutdrop : 1;
479                unsigned enumdone : 1;
480                unsigned usbreset : 1;
481                unsigned usbsuspend : 1;
482                unsigned erlysuspend : 1;
483                unsigned i2cintr : 1;
484                unsigned reserved8 : 1;
485                unsigned goutnakeff : 1;
486                unsigned ginnakeff : 1;
487                unsigned nptxfempty : 1;
488                unsigned rxstsqlvl : 1;
489                unsigned sofintr : 1;
490                unsigned otgintr : 1;
491                unsigned modemismatch : 1;
492                unsigned curmode : 1;
493        } b;
494} gintsts_data_t;
495
496
497/**
498 * This union represents the bit fields in the Device Receive Status Read and
499 * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
500 * element then read out the bits using the <i>b</i>it elements.
501 */
502typedef union device_grxsts_data {
503        /** raw register data */
504        uint32_t d32;
505        /** register bits */
506    struct {
507      unsigned reserved : 7;
508      unsigned fn : 4;
509#define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet
510#define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete
511
512#define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK
513#define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete
514#define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet
515      unsigned pktsts : 4;
516      unsigned dpid : 2;
517      unsigned bcnt : 11;
518      unsigned epnum : 4;
519        } b;
520} device_grxsts_data_t;
521
522/**
523 * This union represents the bit fields in the Host Receive Status Read and
524 * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
525 * element then read out the bits using the <i>b</i>it elements.
526 */
527typedef union host_grxsts_data {
528        /** raw register data */
529        uint32_t d32;
530        /** register bits */
531    struct {
532      unsigned reserved31_21 : 11;
533#define DWC_GRXSTS_PKTSTS_IN 0x2
534#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3
535#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5
536#define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7
537      unsigned pktsts : 4;
538      unsigned dpid : 2;
539      unsigned bcnt : 11;
540      unsigned chnum : 4;
541        } b;
542} host_grxsts_data_t;
543
544/**
545 * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ,
546 * GNPTXFSIZ, DPTXFSIZn). Read the register into the <i>d32</i> element then
547 * read out the bits using the <i>b</i>it elements.
548 */
549typedef union fifosize_data {
550        /** raw register data */
551        uint32_t d32;
552        /** register bits */
553    struct {
554        unsigned depth : 16;
555        unsigned startaddr : 16;
556        } b;
557} fifosize_data_t;
558
559/**
560 * This union represents the bit fields in the Non-Periodic Transmit
561 * FIFO/Queue Status Register (GNPTXSTS). Read the register into the
562 * <i>d32</i> element then read out the bits using the <i>b</i>it
563 * elements.
564 */
565typedef union gnptxsts_data {
566        /** raw register data */
567        uint32_t d32;
568        /** register bits */
569    struct {
570                unsigned reserved : 1;
571                /** Top of the Non-Periodic Transmit Request Queue
572                 * - bits 30:27 - Channel/EP Number
573                 * - bits 26:25 - Token Type
574                 * - bit 24 - Terminate (Last entry for the selected
575                 * channel/EP)
576                 * - 2'b00 - IN/OUT
577                 * - 2'b01 - Zero Length OUT
578                 * - 2'b10 - PING/Complete Split
579                 * - 2'b11 - Channel Halt
580
581                 */
582                unsigned nptxqtop_chnep : 4;
583                unsigned nptxqtop_token : 2;
584                unsigned nptxqtop_terminate : 1;
585        unsigned nptxqspcavail : 8;
586        unsigned nptxfspcavail : 16;
587        } b;
588} gnptxsts_data_t;
589
590/**
591 * This union represents the bit fields in the Transmit
592 * FIFO Status Register (DTXFSTS). Read the register into the
593 * <i>d32</i> element then read out the bits using the <i>b</i>it
594 * elements.
595 */
596typedef union dtxfsts_data /* fscz */ //*
597{
598    /** raw register data */
599    uint32_t d32;
600    /** register bits */
601    struct {
602        unsigned reserved : 16;
603        unsigned txfspcavail : 16;
604    } b;
605} dtxfsts_data_t;
606
607/**
608 * This union represents the bit fields in the I2C Control Register
609 * (I2CCTL). Read the register into the <i>d32</i> element then read out the
610 * bits using the <i>b</i>it elements.
611 */
612typedef union gi2cctl_data {
613        /** raw register data */
614        uint32_t d32;
615        /** register bits */
616    struct {
617        unsigned bsydne : 1;
618        unsigned rw : 1;
619        unsigned reserved : 2;
620        unsigned i2cdevaddr : 2;
621        unsigned i2csuspctl : 1;
622        unsigned ack : 1;
623        unsigned i2cen : 1;
624        unsigned addr : 7;
625        unsigned regaddr : 8;
626        unsigned rwdata : 8;
627        } b;
628} gi2cctl_data_t;
629
630/**
631 * This union represents the bit fields in the User HW Config1
632 * Register. Read the register into the <i>d32</i> element then read
633 * out the bits using the <i>b</i>it elements.
634 */
635typedef union hwcfg1_data {
636        /** raw register data */
637        uint32_t d32;
638        /** register bits */
639        struct {
640                unsigned ep_dir15 : 2;
641                unsigned ep_dir14 : 2;
642                unsigned ep_dir13 : 2;
643                unsigned ep_dir12 : 2;
644                unsigned ep_dir11 : 2;
645                unsigned ep_dir10 : 2;
646                unsigned ep_dir9 : 2;
647                unsigned ep_dir8 : 2;
648                unsigned ep_dir7 : 2;
649                unsigned ep_dir6 : 2;
650                unsigned ep_dir5 : 2;
651                unsigned ep_dir4 : 2;
652                unsigned ep_dir3 : 2;
653                unsigned ep_dir2 : 2;
654                unsigned ep_dir1 : 2;
655                unsigned ep_dir0 : 2;
656        } b;
657} hwcfg1_data_t;
658
659/**
660 * This union represents the bit fields in the User HW Config2
661 * Register. Read the register into the <i>d32</i> element then read
662 * out the bits using the <i>b</i>it elements.
663 */
664typedef union hwcfg2_data
665{
666        /** raw register data */
667        uint32_t d32;
668        /** register bits */
669        struct {
670                /* GHWCFG2 */
671                unsigned reserved31 : 1;
672                unsigned dev_token_q_depth : 5;
673                unsigned host_perio_tx_q_depth : 2;
674                unsigned nonperio_tx_q_depth : 2;
675                unsigned rx_status_q_depth : 2;
676                unsigned dynamic_fifo : 1;
677                unsigned perio_ep_supported : 1;
678                unsigned num_host_chan : 4;
679                unsigned num_dev_ep : 4;
680                unsigned fs_phy_type : 2;
681#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
682#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1
683#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2
684#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
685                unsigned hs_phy_type : 2;
686                unsigned point2point : 1;
687                unsigned architecture : 2;
688#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0
689#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
690#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
691#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
692#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
693#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
694#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
695                unsigned op_mode : 3;
696        } b;
697} hwcfg2_data_t;
698
699/**
700 * This union represents the bit fields in the User HW Config3
701 * Register. Read the register into the <i>d32</i> element then read
702 * out the bits using the <i>b</i>it elements.
703 */
704typedef union hwcfg3_data
705{
706        /** raw register data */
707        uint32_t d32;
708        /** register bits */
709        struct {
710                /* GHWCFG3 */
711                unsigned dfifo_depth : 16;
712                unsigned reserved15_13 : 3;
713                unsigned ahb_phy_clock_synch : 1;
714                unsigned synch_reset_type : 1;
715                unsigned optional_features : 1;
716                unsigned vendor_ctrl_if : 1;
717                unsigned i2c : 1;
718                unsigned otg_func : 1;
719                unsigned packet_size_cntr_width : 3;
720                unsigned xfer_size_cntr_width : 4;
721        } b;
722} hwcfg3_data_t;
723
724/**
725 * This union represents the bit fields in the User HW Config4
726 * Register. Read the register into the <i>d32</i> element then read
727 * out the bits using the <i>b</i>it elements.
728 */
729typedef union hwcfg4_data
730{
731        /** raw register data */
732        uint32_t d32;
733        /** register bits */
734        struct {
735unsigned reserved31_30 : 2; /* fscz */
736        unsigned num_in_eps : 4;
737        unsigned ded_fifo_en : 1;
738
739                unsigned session_end_filt_en : 1;
740                unsigned b_valid_filt_en : 1;
741                unsigned a_valid_filt_en : 1;
742                unsigned vbus_valid_filt_en : 1;
743                unsigned iddig_filt_en : 1;
744                unsigned num_dev_mode_ctrl_ep : 4;
745                unsigned utmi_phy_data_width : 2;
746                unsigned min_ahb_freq : 9;
747                unsigned power_optimiz : 1;
748                unsigned num_dev_perio_in_ep : 4;
749        } b;
750} hwcfg4_data_t;
751
752////////////////////////////////////////////
753// Device Registers
754/**
755 * Device Global Registers. <i>Offsets 800h-BFFh</i>
756 *
757 * The following structures define the size and relative field offsets
758 * for the Device Mode Registers.
759 *
760 * <i>These registers are visible only in Device mode and must not be
761 * accessed in Host mode, as the results are unknown.</i>
762 */
763typedef struct dwc_otg_dev_global_regs
764{
765        /** Device Configuration Register. <i>Offset 800h</i> */
766        volatile uint32_t dcfg;
767        /** Device Control Register. <i>Offset: 804h</i> */
768        volatile uint32_t dctl;
769        /** Device Status Register (Read Only). <i>Offset: 808h</i> */
770        volatile uint32_t dsts;
771        /** Reserved. <i>Offset: 80Ch</i> */
772        uint32_t unused;
773        /** Device IN Endpoint Common Interrupt Mask
774         * Register. <i>Offset: 810h</i> */
775        volatile uint32_t diepmsk;
776        /** Device OUT Endpoint Common Interrupt Mask
777         * Register. <i>Offset: 814h</i> */
778        volatile uint32_t doepmsk;
779        /** Device All Endpoints Interrupt Register. <i>Offset: 818h</i> */
780        volatile uint32_t daint;
781        /** Device All Endpoints Interrupt Mask Register. <i>Offset:
782         * 81Ch</i> */
783        volatile uint32_t daintmsk;
784        /** Device IN Token Queue Read Register-1 (Read Only).
785         * <i>Offset: 820h</i> */
786        volatile uint32_t dtknqr1;
787        /** Device IN Token Queue Read Register-2 (Read Only).
788         * <i>Offset: 824h</i> */
789        volatile uint32_t dtknqr2;
790        /** Device VBUS discharge Register. <i>Offset: 828h</i> */
791        volatile uint32_t dvbusdis;
792        /** Device VBUS Pulse Register. <i>Offset: 82Ch</i> */
793        volatile uint32_t dvbuspulse;
794        /** Device IN Token Queue Read Register-3 (Read Only).
795         * Device Thresholding control register (Read/Write)
796     * <i>Offset: 830h</i> */
797        volatile uint32_t dtknqr3_dthrctl;
798        /** Device IN Token Queue Read Register-4 (Read Only). /
799     * Device IN EPs empty Inr. Mask Register (Read/Write)
800         * <i>Offset: 834h</i> */
801        volatile uint32_t dtknqr4_fifoemptymsk;
802} dwc_otg_device_global_regs_t;
803
804/**
805 * This union represents the bit fields in the Device Configuration
806 * Register. Read the register into the <i>d32</i> member then
807 * set/clear the bits using the <i>b</i>it elements. Write the
808 * <i>d32</i> member to the dcfg register.
809 */
810typedef union dcfg_data
811{
812        /** raw register data */
813        uint32_t d32;
814        /** register bits */
815        struct {
816                unsigned reserved31_23 : 9;
817                /** In Endpoint Mis-match count */
818                unsigned epmscnt : 5;
819                unsigned reserved13_17 : 5;
820                /** Periodic Frame Interval */
821#define DWC_DCFG_FRAME_INTERVAL_80 0
822#define DWC_DCFG_FRAME_INTERVAL_85 1
823#define DWC_DCFG_FRAME_INTERVAL_90 2
824#define DWC_DCFG_FRAME_INTERVAL_95 3
825                unsigned perfrint : 2;
826                /** Device Addresses */
827                unsigned devaddr : 7;
828                unsigned reserved3 : 1;
829                /** Non Zero Length Status OUT Handshake */
830#define DWC_DCFG_SEND_STALL 1
831                unsigned nzstsouthshk : 1;
832                /** Device Speed */
833                unsigned devspd : 2;
834        } b;
835} dcfg_data_t;
836
837/**
838 * This union represents the bit fields in the Device Control
839 * Register. Read the register into the <i>d32</i> member then
840 * set/clear the bits using the <i>b</i>it elements.
841 */
842typedef union dctl_data
843{
844    /** raw register data */
845    uint32_t d32;
846    /** register bits */
847    struct {
848        unsigned reserved : 20;
849        /** Power-On Programming Done */
850        unsigned pwronprgdone : 1;
851        /** Clear Global OUT NAK */
852        unsigned cgoutnak : 1;
853        /** Set Global OUT NAK */
854        unsigned sgoutnak : 1;
855        /** Clear Global Non-Periodic IN NAK */
856        unsigned cgnpinnak : 1;
857        /** Set Global Non-Periodic IN NAK */
858        unsigned sgnpinnak : 1;
859        /** Test Control */
860        unsigned tstctl : 3;
861        /** Global OUT NAK Status */
862        unsigned goutnaksts : 1;
863        /** Global Non-Periodic IN NAK Status */
864        unsigned gnpinnaksts : 1;
865        /** Soft Disconnect */
866        unsigned sftdiscon : 1;
867        /** Remote Wakeup */
868        unsigned rmtwkupsig : 1;
869    } b;
870} dctl_data_t;
871
872/**
873 * This union represents the bit fields in the Device Status
874 * Register. Read the register into the <i>d32</i> member then
875 * set/clear the bits using the <i>b</i>it elements.
876 */
877typedef union dsts_data
878{
879    /** raw register data */
880    uint32_t d32;
881    /** register bits */
882    struct {
883        unsigned reserved22_31 : 10;
884        /** Frame or Microframe Number of the received SOF */
885        unsigned soffn : 14;
886        unsigned reserved4_7: 4;
887        /** Erratic Error */
888        unsigned errticerr : 1;
889        /** Enumerated Speed */
890#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
891#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
892#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2
893#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3
894        unsigned enumspd : 2;
895        /** Suspend Status */
896        unsigned suspsts : 1;
897        } b;
898} dsts_data_t;
899
900
901/**
902 * This union represents the bit fields in the Device IN EP Interrupt
903 * Register and the Device IN EP Common Mask Register.
904 *
905 * - Read the register into the <i>d32</i> member then set/clear the
906 * bits using the <i>b</i>it elements.
907 */
908typedef union diepint_data
909{
910    /** raw register data */
911    uint32_t d32;
912    /** register bits */
913    struct {
914        unsigned reserved07_31 : 23;
915        unsigned txfifoundrn : 1;
916        /** IN Endpoint HAK Effective mask */
917        unsigned emptyintr : 1;
918        /** IN Endpoint NAK Effective mask */
919        unsigned inepnakeff : 1;
920        /** IN Token Received with EP mismatch mask */
921        unsigned intknepmis : 1;
922        /** IN Token received with TxF Empty mask */
923        unsigned intktxfemp : 1;
924        /** TimeOUT Handshake mask (non-ISOC EPs) */
925        unsigned timeout : 1;
926        /** AHB Error mask */
927        unsigned ahberr : 1;
928        /** Endpoint disable mask */
929        unsigned epdisabled : 1;
930        /** Transfer complete mask */
931        unsigned xfercompl : 1;
932        } b;
933} diepint_data_t;
934/**
935 * This union represents the bit fields in the Device IN EP Common
936 * Interrupt Mask Register.
937 */
938typedef union diepint_data diepmsk_data_t;
939
940/**
941 * This union represents the bit fields in the Device OUT EP Interrupt
942 * Registerand Device OUT EP Common Interrupt Mask Register.
943 *
944 * - Read the register into the <i>d32</i> member then set/clear the
945 * bits using the <i>b</i>it elements.
946 */
947typedef union doepint_data
948{
949    /** raw register data */
950    uint32_t d32;
951    /** register bits */
952    struct {
953        unsigned reserved04_31 : 27;
954        /** OUT Token Received when Endpoint Disabled */
955        unsigned outtknepdis : 1;
956        /** Setup Phase Done (contorl EPs) */
957        unsigned setup : 1;
958        /** AHB Error */
959        unsigned ahberr : 1;
960        /** Endpoint disable */
961        unsigned epdisabled : 1;
962        /** Transfer complete */
963        unsigned xfercompl : 1;
964        } b;
965} doepint_data_t;
966/**
967 * This union represents the bit fields in the Device OUT EP Common
968 * Interrupt Mask Register.
969 */
970typedef union doepint_data doepmsk_data_t;
971
972
973/**
974 * This union represents the bit fields in the Device All EP Interrupt
975 * and Mask Registers.
976 * - Read the register into the <i>d32</i> member then set/clear the
977 * bits using the <i>b</i>it elements.
978 */
979typedef union daint_data
980{
981    /** raw register data */
982    uint32_t d32;
983    /** register bits */
984    struct {
985        /** OUT Endpoint bits */
986        unsigned out : 16;
987        /** IN Endpoint bits */
988        unsigned in : 16;
989        } ep;
990    struct {
991        /** OUT Endpoint bits */
992        unsigned outep15 : 1;
993        unsigned outep14 : 1;
994        unsigned outep13 : 1;
995        unsigned outep12 : 1;
996        unsigned outep11 : 1;
997        unsigned outep10 : 1;
998        unsigned outep9 : 1;
999        unsigned outep8 : 1;
1000        unsigned outep7 : 1;
1001        unsigned outep6 : 1;
1002        unsigned outep5 : 1;
1003        unsigned outep4 : 1;
1004        unsigned outep3 : 1;
1005        unsigned outep2 : 1;
1006        unsigned outep1 : 1;
1007        unsigned outep0 : 1;
1008        /** IN Endpoint bits */
1009        unsigned inep15 : 1;
1010        unsigned inep14 : 1;
1011        unsigned inep13 : 1;
1012        unsigned inep12 : 1;
1013        unsigned inep11 : 1;
1014        unsigned inep10 : 1;
1015        unsigned inep9 : 1;
1016        unsigned inep8 : 1;
1017        unsigned inep7 : 1;
1018        unsigned inep6 : 1;
1019        unsigned inep5 : 1;
1020        unsigned inep4 : 1;
1021        unsigned inep3 : 1;
1022        unsigned inep2 : 1;
1023        unsigned inep1 : 1;
1024        unsigned inep0 : 1;
1025        } b;
1026} daint_data_t;
1027
1028/**
1029 * This union represents the bit fields in the Device IN Token Queue
1030 * Read Registers.
1031 * - Read the register into the <i>d32</i> member.
1032 * - READ-ONLY Register
1033 */
1034typedef union dtknq1_data
1035{
1036        /** raw register data */
1037        uint32_t d32;
1038        /** register bits */
1039        struct {
1040                /** EP Numbers of IN Tokens 0 ... 4 */
1041                unsigned epnums0_5 : 24;
1042                /** write pointer has wrapped. */
1043                unsigned wrap_bit : 1;
1044                /** Reserved */
1045                unsigned reserved05_06 : 2;
1046                /** In Token Queue Write Pointer */
1047                unsigned intknwptr : 5;
1048        }b;
1049} dtknq1_data_t;
1050
1051/**
1052 * This union represents Threshold control Register
1053 * - Read and write the register into the <i>d32</i> member.
1054 * - READ-WRITABLE Register
1055 */
1056typedef union dthrctl_data //* /*fscz */
1057{
1058    /** raw register data */
1059    uint32_t d32;
1060    /** register bits */
1061    struct {
1062        /** Reserved */
1063        unsigned reserved26_31 : 6;
1064        /** Rx Thr. Length */
1065        unsigned rx_thr_len : 9;
1066        /** Rx Thr. Enable */
1067        unsigned rx_thr_en : 1;
1068        /** Reserved */
1069        unsigned reserved11_15 : 5;
1070        /** Tx Thr. Length */
1071        unsigned tx_thr_len : 9;
1072        /** ISO Tx Thr. Enable */
1073        unsigned iso_thr_en : 1;
1074        /** non ISO Tx Thr. Enable */
1075        unsigned non_iso_thr_en : 1;
1076
1077    }b;
1078} dthrctl_data_t;
1079
1080/**
1081 * Device Logical IN Endpoint-Specific Registers. <i>Offsets
1082 * 900h-AFCh</i>
1083 *
1084 * There will be one set of endpoint registers per logical endpoint
1085 * implemented.
1086 *
1087 * <i>These registers are visible only in Device mode and must not be
1088 * accessed in Host mode, as the results are unknown.</i>
1089 */
1090typedef struct dwc_otg_dev_in_ep_regs
1091{
1092        /** Device IN Endpoint Control Register. <i>Offset:900h +
1093         * (ep_num * 20h) + 00h</i> */
1094        volatile uint32_t diepctl;
1095        /** Reserved. <i>Offset:900h + (ep_num * 20h) + 04h</i> */
1096        uint32_t reserved04;
1097        /** Device IN Endpoint Interrupt Register. <i>Offset:900h +
1098         * (ep_num * 20h) + 08h</i> */
1099        volatile uint32_t diepint;
1100        /** Reserved. <i>Offset:900h + (ep_num * 20h) + 0Ch</i> */
1101        uint32_t reserved0C;
1102        /** Device IN Endpoint Transfer Size
1103         * Register. <i>Offset:900h + (ep_num * 20h) + 10h</i> */
1104        volatile uint32_t dieptsiz;
1105        /** Device IN Endpoint DMA Address Register. <i>Offset:900h +
1106         * (ep_num * 20h) + 14h</i> */
1107        volatile uint32_t diepdma;
1108        /** Reserved. <i>Offset:900h + (ep_num * 20h) + 18h - 900h +
1109         * (ep_num * 20h) + 1Ch</i>*/
1110        volatile uint32_t dtxfsts;
1111        /** Reserved. <i>Offset:900h + (ep_num * 20h) + 1Ch - 900h +
1112         * (ep_num * 20h) + 1Ch</i>*/
1113        uint32_t reserved18;
1114} dwc_otg_dev_in_ep_regs_t;
1115
1116/**
1117 * Device Logical OUT Endpoint-Specific Registers. <i>Offsets:
1118 * B00h-CFCh</i>
1119 *
1120 * There will be one set of endpoint registers per logical endpoint
1121 * implemented.
1122 *
1123 * <i>These registers are visible only in Device mode and must not be
1124 * accessed in Host mode, as the results are unknown.</i>
1125 */
1126typedef struct dwc_otg_dev_out_ep_regs
1127{
1128        /** Device OUT Endpoint Control Register. <i>Offset:B00h +
1129         * (ep_num * 20h) + 00h</i> */
1130        volatile uint32_t doepctl;
1131        /** Device OUT Endpoint Frame number Register. <i>Offset:
1132         * B00h + (ep_num * 20h) + 04h</i> */
1133        volatile uint32_t doepfn;
1134        /** Device OUT Endpoint Interrupt Register. <i>Offset:B00h +
1135         * (ep_num * 20h) + 08h</i> */
1136        volatile uint32_t doepint;
1137        /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 0Ch</i> */
1138        uint32_t reserved0C;
1139        /** Device OUT Endpoint Transfer Size Register. <i>Offset:
1140         * B00h + (ep_num * 20h) + 10h</i> */
1141        volatile uint32_t doeptsiz;
1142        /** Device OUT Endpoint DMA Address Register. <i>Offset:B00h
1143         * + (ep_num * 20h) + 14h</i> */
1144        volatile uint32_t doepdma;
1145        /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 18h - B00h +
1146         * (ep_num * 20h) + 1Ch</i> */
1147        uint32_t unused[2];
1148} dwc_otg_dev_out_ep_regs_t;
1149
1150/**
1151 * This union represents the bit fields in the Device EP Control
1152 * Register. Read the register into the <i>d32</i> member then
1153 * set/clear the bits using the <i>b</i>it elements.
1154 */
1155typedef union depctl_data
1156{
1157        /** raw register data */
1158        uint32_t d32;
1159        /** register bits */
1160        struct {
1161        /** Endpoint Enable */
1162        unsigned epena : 1;
1163        /** Endpoint Disable */
1164        unsigned epdis : 1;
1165                /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
1166                 * Writing to this field sets the Endpoint DPID (DPID)
1167                 * field in this register to DATA1 Set Odd
1168                 * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
1169                 * Writing to this field sets the Even/Odd
1170                 * (micro)frame (EO_FrNum) field to odd (micro) frame.
1171                 */
1172                unsigned setd1pid : 1;
1173                /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
1174                 * Writing to this field sets the Endpoint DPID (DPID)
1175                 * field in this register to DATA0. Set Even
1176                 * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
1177                 * Writing to this field sets the Even/Odd
1178                 * (micro)frame (EO_FrNum) field to even (micro)
1179                 * frame.
1180                 */
1181                unsigned setd0pid : 1;
1182        /** Set NAK */
1183        unsigned snak : 1;
1184        /** Clear NAK */
1185        unsigned cnak : 1;
1186        /** Tx Fifo Number
1187         * IN EPn/IN EP0
1188         * OUT EPn/OUT EP0 - reserved */
1189        unsigned txfnum : 4;
1190        /** Stall Handshake */
1191        unsigned stall : 1;
1192        /** Snoop Mode
1193         * OUT EPn/OUT EP0
1194         * IN EPn/IN EP0 - reserved */
1195        unsigned snp : 1;
1196        /** Endpoint Type
1197         * 2'b00: Control
1198         * 2'b01: Isochronous
1199         * 2'b10: Bulk
1200         * 2'b11: Interrupt */
1201        unsigned eptype : 2;
1202        /** NAK Status */
1203        unsigned naksts : 1;
1204        /** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
1205                 * This field contains the PID of the packet going to
1206                 * be received or transmitted on this endpoint. The
1207                 * application should program the PID of the first
1208                 * packet going to be received or transmitted on this
1209                 * endpoint , after the endpoint is
1210                 * activated. Application use the SetD1PID and
1211                 * SetD0PID fields of this register to program either
1212                 * D0 or D1 PID.
1213                 *
1214                 * The encoding for this field is
1215                 * - 0: D0
1216                 * - 1: D1
1217                 */
1218        unsigned dpid : 1;
1219        /** USB Active Endpoint */
1220        unsigned usbactep : 1;
1221        /** Next Endpoint
1222         * IN EPn/IN EP0
1223         * OUT EPn/OUT EP0 - reserved */
1224        unsigned nextep : 4;
1225        /** Maximum Packet Size
1226         * IN/OUT EPn
1227         * IN/OUT EP0 - 2 bits
1228         * 2'b00: 64 Bytes
1229         * 2'b01: 32
1230         * 2'b10: 16
1231         * 2'b11: 8 */
1232#define DWC_DEP0CTL_MPS_64 0
1233#define DWC_DEP0CTL_MPS_32 1
1234#define DWC_DEP0CTL_MPS_16 2
1235#define DWC_DEP0CTL_MPS_8 3
1236        unsigned mps : 11;
1237        } b;
1238} depctl_data_t;
1239
1240/**
1241 * This union represents the bit fields in the Device EP Transfer
1242 * Size Register. Read the register into the <i>d32</i> member then
1243 * set/clear the bits using the <i>b</i>it elements.
1244 */
1245typedef union deptsiz_data
1246{
1247        /** raw register data */
1248        uint32_t d32;
1249        /** register bits */
1250        struct {
1251        unsigned reserved : 1;
1252        /** Multi Count - Periodic IN endpoints */
1253        unsigned mc : 2;
1254        /** Packet Count */
1255        unsigned pktcnt : 10;
1256        /** Transfer size */
1257        unsigned xfersize : 19;
1258        } b;
1259} deptsiz_data_t;
1260
1261/**
1262 * This union represents the bit fields in the Device EP 0 Transfer
1263 * Size Register. Read the register into the <i>d32</i> member then
1264 * set/clear the bits using the <i>b</i>it elements.
1265 */
1266typedef union deptsiz0_data
1267{
1268        /** raw register data */
1269        uint32_t d32;
1270        /** register bits */
1271        struct {
1272                unsigned reserved31 : 1;
1273                /**Setup Packet Count (DOEPTSIZ0 Only) */
1274                unsigned supcnt : 2;
1275                /** Reserved */
1276        unsigned reserved28_20 : 9;
1277        /** Packet Count */
1278        unsigned pktcnt : 1;
1279                /** Reserved */
1280        unsigned reserved18_7 : 12;
1281        /** Transfer size */
1282        unsigned xfersize : 7;
1283        } b;
1284} deptsiz0_data_t;
1285
1286
1287/** Maximum number of Periodic FIFOs */
1288#define MAX_PERIO_FIFOS 15
1289/** Maximum number of TX FIFOs */
1290#define MAX_TX_FIFOS 15
1291/** Maximum number of Endpoints/HostChannels */
1292#define MAX_EPS_CHANNELS 16
1293//#define MAX_EPS_CHANNELS 4
1294
1295/**
1296 * The dwc_otg_dev_if structure contains information needed to manage
1297 * the DWC_otg controller acting in device mode. It represents the
1298 * programming view of the device-specific aspects of the controller.
1299 */
1300typedef struct dwc_otg_dev_if {
1301        /** Pointer to device Global registers.
1302         * Device Global Registers starting at offset 800h
1303         */
1304        dwc_otg_device_global_regs_t *dev_global_regs;
1305#define DWC_DEV_GLOBAL_REG_OFFSET 0x800
1306
1307        /**
1308         * Device Logical IN Endpoint-Specific Registers 900h-AFCh
1309         */
1310        dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS];
1311#define DWC_DEV_IN_EP_REG_OFFSET 0x900
1312#define DWC_EP_REG_OFFSET 0x20
1313
1314        /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */
1315        dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS];
1316#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00
1317
1318        /* Device configuration information*/
1319        uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */
1320        //uint8_t num_eps; /**< Number of EPs range: 0-16 (includes EP0) */
1321        //uint8_t num_perio_eps; /**< # of Periodic EP range: 0-15 */
1322    /*fscz */
1323    uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */
1324    uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/
1325
1326        /** Size of periodic FIFOs (Bytes) */
1327        uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS];
1328
1329    /** Size of Tx FIFOs (Bytes) */
1330    uint16_t tx_fifo_size[MAX_TX_FIFOS];
1331
1332    /** Thresholding enable flags and length varaiables **/
1333    uint16_t rx_thr_en;
1334    uint16_t iso_tx_thr_en;
1335    uint16_t non_iso_tx_thr_en;
1336
1337    uint16_t rx_thr_length;
1338    uint16_t tx_thr_length;
1339} dwc_otg_dev_if_t;
1340
1341/**
1342 * This union represents the bit fields in the Power and Clock Gating Control
1343 * Register. Read the register into the <i>d32</i> member then set/clear the
1344 * bits using the <i>b</i>it elements.
1345 */
1346typedef union pcgcctl_data
1347{
1348    /** raw register data */
1349    uint32_t d32;
1350
1351    /** register bits */
1352    struct {
1353        unsigned reserved31_05 : 27;
1354        /** PHY Suspended */
1355        unsigned physuspended : 1;
1356        /** Reset Power Down Modules */
1357        unsigned rstpdwnmodule : 1;
1358        /** Power Clamp */
1359        unsigned pwrclmp : 1;
1360        /** Gate Hclk */
1361        unsigned gatehclk : 1;
1362        /** Stop Pclk */
1363        unsigned stoppclk : 1;
1364    } b;
1365} pcgcctl_data_t;
1366
1367/////////////////////////////////////////////////
1368// Host Mode Register Structures
1369//
1370/**
1371 * The Host Global Registers structure defines the size and relative
1372 * field offsets for the Host Mode Global Registers. Host Global
1373 * Registers offsets 400h-7FFh.
1374*/
1375typedef struct dwc_otg_host_global_regs
1376{
1377        /** Host Configuration Register. <i>Offset: 400h</i> */
1378        volatile uint32_t hcfg;
1379        /** Host Frame Interval Register. <i>Offset: 404h</i> */
1380        volatile uint32_t hfir;
1381        /** Host Frame Number / Frame Remaining Register. <i>Offset: 408h</i> */
1382        volatile uint32_t hfnum;
1383        /** Reserved. <i>Offset: 40Ch</i> */
1384        uint32_t reserved40C;
1385        /** Host Periodic Transmit FIFO/ Queue Status Register. <i>Offset: 410h</i> */
1386        volatile uint32_t hptxsts;
1387        /** Host All Channels Interrupt Register. <i>Offset: 414h</i> */
1388        volatile uint32_t haint;
1389        /** Host All Channels Interrupt Mask Register. <i>Offset: 418h</i> */
1390        volatile uint32_t haintmsk;
1391} dwc_otg_host_global_regs_t;
1392
1393/**
1394 * This union represents the bit fields in the Host Configuration Register.
1395 * Read the register into the <i>d32</i> member then set/clear the bits using
1396 * the <i>b</i>it elements. Write the <i>d32</i> member to the hcfg register.
1397 */
1398typedef union hcfg_data
1399{
1400        /** raw register data */
1401        uint32_t d32;
1402
1403        /** register bits */
1404        struct {
1405                /** Reserved */
1406        //unsigned reserved31_03 : 29;
1407        /** FS/LS Only Support */
1408        unsigned fslssupp : 1;
1409        /** FS/LS Phy Clock Select */
1410#define DWC_HCFG_30_60_MHZ 0
1411#define DWC_HCFG_48_MHZ 1
1412#define DWC_HCFG_6_MHZ 2
1413        unsigned fslspclksel : 2;
1414        } b;
1415} hcfg_data_t;
1416
1417/**
1418 * This union represents the bit fields in the Host Frame Remaing/Number
1419 * Register.
1420 */
1421typedef union hfir_data
1422{
1423        /** raw register data */
1424        uint32_t d32;
1425
1426        /** register bits */
1427        struct {
1428        unsigned reserved : 16;
1429        unsigned frint : 16;
1430        } b;
1431} hfir_data_t;
1432
1433/**
1434 * This union represents the bit fields in the Host Frame Remaing/Number
1435 * Register.
1436 */
1437typedef union hfnum_data
1438{
1439        /** raw register data */
1440        uint32_t d32;
1441
1442        /** register bits */
1443        struct {
1444        unsigned frrem : 16;
1445#define DWC_HFNUM_MAX_FRNUM 0x3FFF
1446        unsigned frnum : 16;
1447        } b;
1448} hfnum_data_t;
1449
1450typedef union hptxsts_data
1451{
1452    /** raw register data */
1453    uint32_t d32;
1454
1455    /** register bits */
1456    struct {
1457        /** Top of the Periodic Transmit Request Queue
1458         * - bit 24 - Terminate (last entry for the selected channel)
1459         * - bits 26:25 - Token Type
1460         * - 2'b00 - Zero length
1461         * - 2'b01 - Ping
1462         * - 2'b10 - Disable
1463         * - bits 30:27 - Channel Number
1464         * - bit 31 - Odd/even microframe
1465         */
1466        unsigned ptxqtop_odd : 1;
1467        unsigned ptxqtop_chnum : 4;
1468        unsigned ptxqtop_token : 2;
1469        unsigned ptxqtop_terminate : 1;
1470        unsigned ptxqspcavail : 8;
1471        unsigned ptxfspcavail : 16;
1472    } b;
1473} hptxsts_data_t;
1474
1475/**
1476 * This union represents the bit fields in the Host Port Control and Status
1477 * Register. Read the register into the <i>d32</i> member then set/clear the
1478 * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
1479 * hprt0 register.
1480 */
1481typedef union hprt0_data
1482{
1483        /** raw register data */
1484        uint32_t d32;
1485        /** register bits */
1486        struct {
1487        unsigned reserved19_31 : 13;
1488#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0
1489#define DWC_HPRT0_PRTSPD_FULL_SPEED 1
1490#define DWC_HPRT0_PRTSPD_LOW_SPEED 2
1491        unsigned prtspd : 2;
1492        unsigned prttstctl : 4;
1493        unsigned prtpwr : 1;
1494        unsigned prtlnsts : 2;
1495        unsigned reserved9 : 1;
1496        unsigned prtrst : 1;
1497        unsigned prtsusp : 1;
1498        unsigned prtres : 1;
1499        unsigned prtovrcurrchng : 1;
1500        unsigned prtovrcurract : 1;
1501        unsigned prtenchng : 1;
1502        unsigned prtena : 1;
1503        unsigned prtconndet : 1;
1504        unsigned prtconnsts : 1;
1505        } b;
1506} hprt0_data_t;
1507
1508/**
1509 * This union represents the bit fields in the Host All Interrupt
1510 * Register.
1511 */
1512typedef union haint_data
1513{
1514        /** raw register data */
1515        uint32_t d32;
1516        /** register bits */
1517        struct {
1518        unsigned reserved : 16;
1519        unsigned ch15 : 1;
1520        unsigned ch14 : 1;
1521        unsigned ch13 : 1;
1522        unsigned ch12 : 1;
1523        unsigned ch11 : 1;
1524        unsigned ch10 : 1;
1525        unsigned ch9 : 1;
1526        unsigned ch8 : 1;
1527        unsigned ch7 : 1;
1528        unsigned ch6 : 1;
1529        unsigned ch5 : 1;
1530        unsigned ch4 : 1;
1531        unsigned ch3 : 1;
1532        unsigned ch2 : 1;
1533        unsigned ch1 : 1;
1534        unsigned ch0 : 1;
1535    } b;
1536        struct {
1537        unsigned reserved : 16;
1538        unsigned chint : 16;
1539    } b2;
1540} haint_data_t;
1541
1542/**
1543 * This union represents the bit fields in the Host All Interrupt
1544 * Register.
1545 */
1546typedef union haintmsk_data
1547{
1548        /** raw register data */
1549        uint32_t d32;
1550        /** register bits */
1551        struct {
1552        unsigned reserved : 16;
1553        unsigned ch15 : 1;
1554        unsigned ch14 : 1;
1555        unsigned ch13 : 1;
1556        unsigned ch12 : 1;
1557        unsigned ch11 : 1;
1558        unsigned ch10 : 1;
1559        unsigned ch9 : 1;
1560        unsigned ch8 : 1;
1561        unsigned ch7 : 1;
1562        unsigned ch6 : 1;
1563        unsigned ch5 : 1;
1564        unsigned ch4 : 1;
1565        unsigned ch3 : 1;
1566        unsigned ch2 : 1;
1567        unsigned ch1 : 1;
1568        unsigned ch0 : 1;
1569    } b;
1570        struct {
1571        unsigned reserved : 16;
1572        unsigned chint : 16;
1573    } b2;
1574} haintmsk_data_t;
1575
1576/**
1577 * Host Channel Specific Registers. <i>500h-5FCh</i>
1578 */
1579typedef struct dwc_otg_hc_regs
1580{
1581        /** Host Channel 0 Characteristic Register. <i>Offset: 500h + (chan_num * 20h) + 00h</i> */
1582        volatile uint32_t hcchar;
1583        /** Host Channel 0 Split Control Register. <i>Offset: 500h + (chan_num * 20h) + 04h</i> */
1584        volatile uint32_t hcsplt;
1585        /** Host Channel 0 Interrupt Register. <i>Offset: 500h + (chan_num * 20h) + 08h</i> */
1586        volatile uint32_t hcint;
1587        /** Host Channel 0 Interrupt Mask Register. <i>Offset: 500h + (chan_num * 20h) + 0Ch</i> */
1588        volatile uint32_t hcintmsk;
1589        /** Host Channel 0 Transfer Size Register. <i>Offset: 500h + (chan_num * 20h) + 10h</i> */
1590        volatile uint32_t hctsiz;
1591        /** Host Channel 0 DMA Address Register. <i>Offset: 500h + (chan_num * 20h) + 14h</i> */
1592        volatile uint32_t hcdma;
1593        /** Reserved. <i>Offset: 500h + (chan_num * 20h) + 18h - 500h + (chan_num * 20h) + 1Ch</i> */
1594        uint32_t reserved[2];
1595} dwc_otg_hc_regs_t;
1596
1597/**
1598 * This union represents the bit fields in the Host Channel Characteristics
1599 * Register. Read the register into the <i>d32</i> member then set/clear the
1600 * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
1601 * hcchar register.
1602 */
1603typedef union hcchar_data
1604{
1605        /** raw register data */
1606        uint32_t d32;
1607
1608        /** register bits */
1609        struct {
1610        /** Channel enable */
1611        unsigned chen : 1;
1612        /** Channel disable */
1613        unsigned chdis : 1;
1614        /**
1615         * Frame to transmit periodic transaction.
1616         * 0: even, 1: odd
1617         */
1618        unsigned oddfrm : 1;
1619        /** Device address */
1620        unsigned devaddr : 7;
1621        /** Packets per frame for periodic transfers. 0 is reserved. */
1622        unsigned multicnt : 2;
1623        /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */
1624        unsigned eptype : 2;
1625        /** 0: Full/high speed device, 1: Low speed device */
1626        unsigned lspddev : 1;
1627        unsigned reserved : 1;
1628        /** 0: OUT, 1: IN */
1629        unsigned epdir : 1;
1630        /** Endpoint number */
1631        unsigned epnum : 4;
1632        /** Maximum packet size in bytes */
1633        unsigned mps : 11;
1634        } b;
1635} hcchar_data_t;
1636
1637typedef union hcsplt_data
1638{
1639        /** raw register data */
1640        uint32_t d32;
1641
1642        /** register bits */
1643        struct {
1644        /** Split Enble */
1645        unsigned spltena : 1;
1646        /** Reserved */
1647        unsigned reserved : 14;
1648        /** Do Complete Split */
1649        unsigned compsplt : 1;
1650        /** Transaction Position */
1651#define DWC_HCSPLIT_XACTPOS_MID 0
1652#define DWC_HCSPLIT_XACTPOS_END 1
1653#define DWC_HCSPLIT_XACTPOS_BEGIN 2
1654#define DWC_HCSPLIT_XACTPOS_ALL 3
1655        unsigned xactpos : 2;
1656        /** Hub Address */
1657        unsigned hubaddr : 7;
1658        /** Port Address */
1659        unsigned prtaddr : 7;
1660    } b;
1661} hcsplt_data_t;
1662
1663
1664/**
1665 * This union represents the bit fields in the Host All Interrupt
1666 * Register.
1667 */
1668typedef union hcint_data
1669{
1670        /** raw register data */
1671        uint32_t d32;
1672        /** register bits */
1673        struct {
1674        /** Reserved */
1675        unsigned reserved : 21;
1676        /** Data Toggle Error */
1677        unsigned datatglerr : 1;
1678        /** Frame Overrun */
1679        unsigned frmovrun : 1;
1680        /** Babble Error */
1681        unsigned bblerr : 1;
1682        /** Transaction Err */
1683        unsigned xacterr : 1;
1684        /** NYET Response Received */
1685        unsigned nyet : 1;
1686        /** ACK Response Received */
1687        unsigned ack : 1;
1688        /** NAK Response Received */
1689        unsigned nak : 1;
1690        /** STALL Response Received */
1691        unsigned stall : 1;
1692        /** AHB Error */
1693        unsigned ahberr : 1;
1694        /** Channel Halted */
1695        unsigned chhltd : 1;
1696        /** Transfer Complete */
1697        unsigned xfercomp : 1;
1698    } b;
1699} hcint_data_t;
1700
1701/**
1702 * This union represents the bit fields in the Host Channel Transfer Size
1703 * Register. Read the register into the <i>d32</i> member then set/clear the
1704 * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
1705 * hcchar register.
1706 */
1707typedef union hctsiz_data
1708{
1709        /** raw register data */
1710        uint32_t d32;
1711
1712        /** register bits */
1713        struct {
1714        /** Do PING protocol when 1 */
1715        unsigned dopng : 1;
1716        /**
1717         * Packet ID for next data packet
1718         * 0: DATA0
1719         * 1: DATA2
1720         * 2: DATA1
1721         * 3: MDATA (non-Control), SETUP (Control)
1722         */
1723#define DWC_HCTSIZ_DATA0 0
1724#define DWC_HCTSIZ_DATA1 2
1725#define DWC_HCTSIZ_DATA2 1
1726#define DWC_HCTSIZ_MDATA 3
1727#define DWC_HCTSIZ_SETUP 3
1728        unsigned pid : 2;
1729        /** Data packets to transfer */
1730        unsigned pktcnt : 10;
1731        /** Total transfer size in bytes */
1732        unsigned xfersize : 19;
1733        } b;
1734} hctsiz_data_t;
1735
1736/**
1737 * This union represents the bit fields in the Host Channel Interrupt Mask
1738 * Register. Read the register into the <i>d32</i> member then set/clear the
1739 * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
1740 * hcintmsk register.
1741 */
1742typedef union hcintmsk_data
1743{
1744        /** raw register data */
1745        uint32_t d32;
1746
1747        /** register bits */
1748        struct {
1749        unsigned reserved : 21;
1750        unsigned datatglerr : 1;
1751        unsigned frmovrun : 1;
1752        unsigned bblerr : 1;
1753        unsigned xacterr : 1;
1754        unsigned nyet : 1;
1755        unsigned ack : 1;
1756        unsigned nak : 1;
1757        unsigned stall : 1;
1758        unsigned ahberr : 1;
1759        unsigned chhltd : 1;
1760        unsigned xfercompl : 1;
1761        } b;
1762} hcintmsk_data_t;
1763
1764/** OTG Host Interface Structure.
1765 *
1766 * The OTG Host Interface Structure structure contains information
1767 * needed to manage the DWC_otg controller acting in host mode. It
1768 * represents the programming view of the host-specific aspects of the
1769 * controller.
1770 */
1771typedef struct dwc_otg_host_if {
1772        /** Host Global Registers starting at offset 400h.*/
1773        dwc_otg_host_global_regs_t *host_global_regs;
1774#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400
1775
1776        /** Host Port 0 Control and Status Register */
1777        volatile uint32_t *hprt0;
1778#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440
1779        
1780
1781        /** Host Channel Specific Registers at offsets 500h-5FCh. */
1782        dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS];
1783#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500
1784#define DWC_OTG_CHAN_REGS_OFFSET 0x20
1785
1786
1787        /* Host configuration information */
1788        /** Number of Host Channels (range: 1-16) */
1789        uint8_t num_host_channels;
1790        /** Periodic EPs supported (0: no, 1: yes) */
1791        uint8_t perio_eps_supported;
1792        /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */
1793        uint16_t perio_tx_fifo_size;
1794  
1795} dwc_otg_host_if_t;
1796
1797#endif
1798

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