| 1 | /***************************************************************************** |
| 2 | ** FILE NAME : ifxusb_cif.c |
| 3 | ** PROJECT : IFX USB sub-system V3 |
| 4 | ** MODULES : IFX USB sub-system Host and Device driver |
| 5 | ** SRC VERSION : 1.0 |
| 6 | ** DATE : 1/Jan/2009 |
| 7 | ** AUTHOR : Chen, Howard |
| 8 | ** DESCRIPTION : The Core Interface provides basic services for accessing and |
| 9 | ** managing the IFX USB hardware. These services are used by both the |
| 10 | ** Host Controller Driver and the Peripheral Controller Driver. |
| 11 | *****************************************************************************/ |
| 12 | |
| 13 | /*! |
| 14 | \file ifxusb_cif.c |
| 15 | \ingroup IFXUSB_DRIVER_V3 |
| 16 | \brief This file contains the interface to the IFX USB Core. |
| 17 | */ |
| 18 | |
| 19 | #include <linux/clk.h> |
| 20 | #include <linux/version.h> |
| 21 | #include "ifxusb_version.h" |
| 22 | |
| 23 | #include <asm/byteorder.h> |
| 24 | #include <asm/unaligned.h> |
| 25 | |
| 26 | |
| 27 | #include <linux/jiffies.h> |
| 28 | #include <linux/platform_device.h> |
| 29 | #include <linux/kernel.h> |
| 30 | #include <linux/ioport.h> |
| 31 | |
| 32 | #if defined(__UEIP__) |
| 33 | // #include <asm/ifx/ifx_pmu.h> |
| 34 | // #include <ifx_pmu.h> |
| 35 | #endif |
| 36 | |
| 37 | |
| 38 | #include "ifxusb_plat.h" |
| 39 | #include "ifxusb_regs.h" |
| 40 | #include "ifxusb_cif.h" |
| 41 | |
| 42 | |
| 43 | #ifdef __IS_DEVICE__ |
| 44 | #include "ifxpcd.h" |
| 45 | #endif |
| 46 | |
| 47 | #ifdef __IS_HOST__ |
| 48 | #include "ifxhcd.h" |
| 49 | #endif |
| 50 | |
| 51 | #include <linux/mm.h> |
| 52 | |
| 53 | #include <linux/gfp.h> |
| 54 | |
| 55 | #if defined(__UEIP__) |
| 56 | // #include <asm/ifx/ifx_board.h> |
| 57 | //#include <ifx_board.h> |
| 58 | #endif |
| 59 | |
| 60 | //#include <asm/ifx/ifx_gpio.h> |
| 61 | //#include <ifx_gpio.h> |
| 62 | #if defined(__UEIP__) |
| 63 | // #include <asm/ifx/ifx_led.h> |
| 64 | //#include <ifx_led.h> |
| 65 | #endif |
| 66 | |
| 67 | |
| 68 | |
| 69 | #if defined(__UEIP__) |
| 70 | #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) |
| 71 | #ifndef USB_CTRL_PMU_SETUP |
| 72 | #define USB_CTRL_PMU_SETUP(__x) USB0_CTRL_PMU_SETUP(__x) |
| 73 | #endif |
| 74 | #ifndef USB_PHY_PMU_SETUP |
| 75 | #define USB_PHY_PMU_SETUP(__x) USB0_PHY_PMU_SETUP(__x) |
| 76 | #endif |
| 77 | #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) |
| 78 | #endif // defined(__UEIP__) |
| 79 | |
| 80 | /*! |
| 81 | \brief This function is called to allocate buffer of specified size. |
| 82 | The allocated buffer is mapped into DMA accessable address. |
| 83 | \param size Size in BYTE to be allocated |
| 84 | \param clear 0: don't do clear after buffer allocated, other: do clear to zero |
| 85 | \return 0/NULL: Fail; uncached pointer of allocated buffer |
| 86 | */ |
| 87 | void *ifxusb_alloc_buf(size_t size, int clear) |
| 88 | { |
| 89 | uint32_t *cached,*uncached; |
| 90 | uint32_t totalsize,page; |
| 91 | |
| 92 | if(!size) |
| 93 | return 0; |
| 94 | |
| 95 | size=(size+3)&0xFFFFFFFC; |
| 96 | totalsize=size + 12; |
| 97 | page=get_order(totalsize); |
| 98 | |
| 99 | cached = (void *) __get_free_pages(( GFP_ATOMIC | GFP_DMA), page); |
| 100 | |
| 101 | if(!cached) |
| 102 | { |
| 103 | IFX_PRINT("%s Allocation Failed size:%d\n",__func__,size); |
| 104 | return NULL; |
| 105 | } |
| 106 | |
| 107 | uncached = (uint32_t *)(KSEG1ADDR(cached)); |
| 108 | if(clear) |
| 109 | memset(uncached, 0, totalsize); |
| 110 | |
| 111 | *(uncached+0)=totalsize; |
| 112 | *(uncached+1)=page; |
| 113 | *(uncached+2)=(uint32_t)cached; |
| 114 | return (void *)(uncached+3); |
| 115 | } |
| 116 | |
| 117 | |
| 118 | /*! |
| 119 | \brief This function is called to free allocated buffer. |
| 120 | \param vaddr the uncached pointer of the buffer |
| 121 | */ |
| 122 | void ifxusb_free_buf(void *vaddr) |
| 123 | { |
| 124 | uint32_t totalsize,page; |
| 125 | uint32_t *cached,*uncached; |
| 126 | |
| 127 | if(vaddr != NULL) |
| 128 | { |
| 129 | uncached=vaddr; |
| 130 | uncached-=3; |
| 131 | totalsize=*(uncached+0); |
| 132 | page=*(uncached+1); |
| 133 | cached=(uint32_t *)(*(uncached+2)); |
| 134 | if(totalsize && page==get_order(totalsize) && cached==(uint32_t *)(KSEG0ADDR(uncached))) |
| 135 | { |
| 136 | free_pages((unsigned long)cached, page); |
| 137 | return; |
| 138 | } |
| 139 | // the memory is not allocated by ifxusb_alloc_buf. Allowed but must be careful. |
| 140 | return; |
| 141 | } |
| 142 | } |
| 143 | |
| 144 | |
| 145 | |
| 146 | /*! |
| 147 | \brief This function is called to initialize the IFXUSB CSR data |
| 148 | structures. The register addresses in the device and host |
| 149 | structures are initialized from the base address supplied by the |
| 150 | caller. The calling function must make the OS calls to get the |
| 151 | base address of the IFXUSB controller registers. |
| 152 | |
| 153 | \param _core_if Pointer of core_if structure |
| 154 | \param _irq irq number |
| 155 | \param _reg_base_addr Base address of IFXUSB core registers |
| 156 | \param _fifo_base_addr Fifo base address |
| 157 | \param _fifo_dbg_addr Fifo debug address |
| 158 | \return 0: success; |
| 159 | */ |
| 160 | int ifxusb_core_if_init(ifxusb_core_if_t *_core_if, |
| 161 | int _irq, |
| 162 | uint32_t _reg_base_addr, |
| 163 | uint32_t _fifo_base_addr, |
| 164 | uint32_t _fifo_dbg_addr) |
| 165 | { |
| 166 | int retval = 0; |
| 167 | uint32_t *reg_base =NULL; |
| 168 | uint32_t *fifo_base =NULL; |
| 169 | uint32_t *fifo_dbg =NULL; |
| 170 | |
| 171 | int i; |
| 172 | |
| 173 | IFX_DEBUGPL(DBG_CILV, "%s(%p,%d,0x%08X,0x%08X,0x%08X)\n", __func__, |
| 174 | _core_if, |
| 175 | _irq, |
| 176 | _reg_base_addr, |
| 177 | _fifo_base_addr, |
| 178 | _fifo_dbg_addr); |
| 179 | |
| 180 | if( _core_if == NULL) |
| 181 | { |
| 182 | IFX_ERROR("%s() invalid _core_if\n", __func__); |
| 183 | retval = -ENOMEM; |
| 184 | goto fail; |
| 185 | } |
| 186 | |
| 187 | //memset(_core_if, 0, sizeof(ifxusb_core_if_t)); |
| 188 | |
| 189 | _core_if->irq=_irq; |
| 190 | |
| 191 | reg_base =ioremap_nocache(_reg_base_addr , IFXUSB_IOMEM_SIZE ); |
| 192 | fifo_base =ioremap_nocache(_fifo_base_addr, IFXUSB_FIFOMEM_SIZE); |
| 193 | fifo_dbg =ioremap_nocache(_fifo_dbg_addr , IFXUSB_FIFODBG_SIZE); |
| 194 | if( reg_base == NULL || fifo_base == NULL || fifo_dbg == NULL) |
| 195 | { |
| 196 | IFX_ERROR("%s() usb ioremap() failed\n", __func__); |
| 197 | retval = -ENOMEM; |
| 198 | goto fail; |
| 199 | } |
| 200 | |
| 201 | _core_if->core_global_regs = (ifxusb_core_global_regs_t *)reg_base; |
| 202 | |
| 203 | /* |
| 204 | * Attempt to ensure this device is really a IFXUSB Controller. |
| 205 | * Read and verify the SNPSID register contents. The value should be |
| 206 | * 0x45F42XXX |
| 207 | */ |
| 208 | { |
| 209 | int32_t snpsid; |
| 210 | snpsid = ifxusb_rreg(&_core_if->core_global_regs->gsnpsid); |
| 211 | if ((snpsid & 0xFFFFF000) != 0x4F542000) |
| 212 | { |
| 213 | IFX_ERROR("%s() snpsid error(0x%08x) failed\n", __func__,snpsid); |
| 214 | retval = -EINVAL; |
| 215 | goto fail; |
| 216 | } |
| 217 | _core_if->snpsid=snpsid; |
| 218 | } |
| 219 | |
| 220 | #ifdef __IS_HOST__ |
| 221 | _core_if->host_global_regs = (ifxusb_host_global_regs_t *) |
| 222 | ((uint32_t)reg_base + IFXUSB_HOST_GLOBAL_REG_OFFSET); |
| 223 | _core_if->hprt0 = (uint32_t*)((uint32_t)reg_base + IFXUSB_HOST_PORT_REGS_OFFSET); |
| 224 | |
| 225 | for (i=0; i<MAX_EPS_CHANNELS; i++) |
| 226 | { |
| 227 | _core_if->hc_regs[i] = (ifxusb_hc_regs_t *) |
| 228 | ((uint32_t)reg_base + IFXUSB_HOST_CHAN_REGS_OFFSET + |
| 229 | (i * IFXUSB_CHAN_REGS_OFFSET)); |
| 230 | IFX_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n", |
| 231 | i, &_core_if->hc_regs[i]->hcchar); |
| 232 | } |
| 233 | #endif //__IS_HOST__ |
| 234 | |
| 235 | #ifdef __IS_DEVICE__ |
| 236 | _core_if->dev_global_regs = |
| 237 | (ifxusb_device_global_regs_t *)((uint32_t)reg_base + IFXUSB_DEV_GLOBAL_REG_OFFSET); |
| 238 | |
| 239 | for (i=0; i<MAX_EPS_CHANNELS; i++) |
| 240 | { |
| 241 | _core_if->in_ep_regs[i] = (ifxusb_dev_in_ep_regs_t *) |
| 242 | ((uint32_t)reg_base + IFXUSB_DEV_IN_EP_REG_OFFSET + |
| 243 | (i * IFXUSB_EP_REG_OFFSET)); |
| 244 | _core_if->out_ep_regs[i] = (ifxusb_dev_out_ep_regs_t *) |
| 245 | ((uint32_t)reg_base + IFXUSB_DEV_OUT_EP_REG_OFFSET + |
| 246 | (i * IFXUSB_EP_REG_OFFSET)); |
| 247 | IFX_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p/%p %p/0x%08X/0x%08X\n", |
| 248 | i, &_core_if->in_ep_regs[i]->diepctl, _core_if->in_ep_regs[i], |
| 249 | reg_base,IFXUSB_DEV_IN_EP_REG_OFFSET,(i * IFXUSB_EP_REG_OFFSET) |
| 250 | ); |
| 251 | IFX_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p/%p %p/0x%08X/0x%08X\n", |
| 252 | i, &_core_if->out_ep_regs[i]->doepctl, _core_if->out_ep_regs[i], |
| 253 | reg_base,IFXUSB_DEV_OUT_EP_REG_OFFSET,(i * IFXUSB_EP_REG_OFFSET) |
| 254 | ); |
| 255 | } |
| 256 | #endif //__IS_DEVICE__ |
| 257 | |
| 258 | /* Setting the FIFO and other Address. */ |
| 259 | for (i=0; i<MAX_EPS_CHANNELS; i++) |
| 260 | { |
| 261 | _core_if->data_fifo[i] = fifo_base + (i * IFXUSB_DATA_FIFO_SIZE); |
| 262 | IFX_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08x\n", |
| 263 | i, (unsigned)_core_if->data_fifo[i]); |
| 264 | } |
| 265 | |
| 266 | _core_if->data_fifo_dbg = fifo_dbg; |
| 267 | _core_if->pcgcctl = (uint32_t*)(((uint32_t)reg_base) + IFXUSB_PCGCCTL_OFFSET); |
| 268 | |
| 269 | /* |
| 270 | * Store the contents of the hardware configuration registers here for |
| 271 | * easy access later. |
| 272 | */ |
| 273 | _core_if->hwcfg1.d32 = ifxusb_rreg(&_core_if->core_global_regs->ghwcfg1); |
| 274 | _core_if->hwcfg2.d32 = ifxusb_rreg(&_core_if->core_global_regs->ghwcfg2); |
| 275 | _core_if->hwcfg3.d32 = ifxusb_rreg(&_core_if->core_global_regs->ghwcfg3); |
| 276 | _core_if->hwcfg4.d32 = ifxusb_rreg(&_core_if->core_global_regs->ghwcfg4); |
| 277 | |
| 278 | IFX_DEBUGPL(DBG_CILV,"hwcfg1=%08x\n",_core_if->hwcfg1.d32); |
| 279 | IFX_DEBUGPL(DBG_CILV,"hwcfg2=%08x\n",_core_if->hwcfg2.d32); |
| 280 | IFX_DEBUGPL(DBG_CILV,"hwcfg3=%08x\n",_core_if->hwcfg3.d32); |
| 281 | IFX_DEBUGPL(DBG_CILV,"hwcfg4=%08x\n",_core_if->hwcfg4.d32); |
| 282 | |
| 283 | |
| 284 | #ifdef __DED_FIFO__ |
| 285 | IFX_PRINT("Waiting for PHY Clock Lock!\n"); |
| 286 | while(!( ifxusb_rreg(&_core_if->core_global_regs->grxfsiz) & (1<<9))) |
| 287 | { |
| 288 | } |
| 289 | IFX_PRINT("PHY Clock Locked!\n"); |
| 290 | //ifxusb_clean_spram(_core_if,128*1024/4); |
| 291 | #endif |
| 292 | |
| 293 | /* Create new workqueue and init works */ |
| 294 | #if 0 |
| 295 | _core_if->wq_usb = create_singlethread_workqueue(_core_if->core_name); |
| 296 | |
| 297 | if(_core_if->wq_usb == 0) |
| 298 | { |
| 299 | IFX_DEBUGPL(DBG_CIL, "Creation of wq_usb failed\n"); |
| 300 | retval = -EINVAL; |
| 301 | goto fail; |
| 302 | } |
| 303 | |
| 304 | #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) |
| 305 | INIT_WORK(&core_if->w_conn_id, w_conn_id_status_change, core_if); |
| 306 | INIT_WORK(&core_if->w_wkp, w_wakeup_detected, core_if); |
| 307 | #else |
| 308 | INIT_WORK(&core_if->w_conn_id, w_conn_id_status_change); |
| 309 | INIT_DELAYED_WORK(&core_if->w_wkp, w_wakeup_detected); |
| 310 | #endif |
| 311 | #endif |
| 312 | return 0; |
| 313 | |
| 314 | fail: |
| 315 | if( reg_base != NULL) iounmap(reg_base ); |
| 316 | if( fifo_base != NULL) iounmap(fifo_base); |
| 317 | if( fifo_dbg != NULL) iounmap(fifo_dbg ); |
| 318 | return retval; |
| 319 | } |
| 320 | |
| 321 | /*! |
| 322 | \brief This function free the mapped address in the IFXUSB CSR data structures. |
| 323 | \param _core_if Pointer of core_if structure |
| 324 | */ |
| 325 | void ifxusb_core_if_remove(ifxusb_core_if_t *_core_if) |
| 326 | { |
| 327 | /* Disable all interrupts */ |
| 328 | if( _core_if->core_global_regs != NULL) |
| 329 | { |
| 330 | ifxusb_mreg( &_core_if->core_global_regs->gahbcfg, 1, 0); |
| 331 | ifxusb_wreg( &_core_if->core_global_regs->gintmsk, 0); |
| 332 | } |
| 333 | |
| 334 | if( _core_if->core_global_regs != NULL) iounmap(_core_if->core_global_regs ); |
| 335 | if( _core_if->data_fifo[0] != NULL) iounmap(_core_if->data_fifo[0] ); |
| 336 | if( _core_if->data_fifo_dbg != NULL) iounmap(_core_if->data_fifo_dbg ); |
| 337 | |
| 338 | #if 0 |
| 339 | if (_core_if->wq_usb) |
| 340 | destroy_workqueue(_core_if->wq_usb); |
| 341 | #endif |
| 342 | memset(_core_if, 0, sizeof(ifxusb_core_if_t)); |
| 343 | } |
| 344 | |
| 345 | |
| 346 | |
| 347 | |
| 348 | /*! |
| 349 | \brief This function enbles the controller's Global Interrupt in the AHB Config register. |
| 350 | \param _core_if Pointer of core_if structure |
| 351 | */ |
| 352 | void ifxusb_enable_global_interrupts( ifxusb_core_if_t *_core_if ) |
| 353 | { |
| 354 | gahbcfg_data_t ahbcfg ={ .d32 = 0}; |
| 355 | ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ |
| 356 | ifxusb_mreg(&_core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32); |
| 357 | } |
| 358 | |
| 359 | /*! |
| 360 | \brief This function disables the controller's Global Interrupt in the AHB Config register. |
| 361 | \param _core_if Pointer of core_if structure |
| 362 | */ |
| 363 | void ifxusb_disable_global_interrupts( ifxusb_core_if_t *_core_if ) |
| 364 | { |
| 365 | gahbcfg_data_t ahbcfg ={ .d32 = 0}; |
| 366 | ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ |
| 367 | ifxusb_mreg(&_core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0); |
| 368 | } |
| 369 | |
| 370 | |
| 371 | |
| 372 | |
| 373 | /*! |
| 374 | \brief Flush Tx and Rx FIFO. |
| 375 | \param _core_if Pointer of core_if structure |
| 376 | */ |
| 377 | void ifxusb_flush_both_fifo( ifxusb_core_if_t *_core_if ) |
| 378 | { |
| 379 | ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs; |
| 380 | volatile grstctl_t greset ={ .d32 = 0}; |
| 381 | int count = 0; |
| 382 | |
| 383 | IFX_DEBUGPL((DBG_CIL|DBG_PCDV), "%s\n", __func__); |
| 384 | greset.b.rxfflsh = 1; |
| 385 | greset.b.txfflsh = 1; |
| 386 | greset.b.txfnum = 0x10; |
| 387 | greset.b.intknqflsh=1; |
| 388 | greset.b.hstfrm=1; |
| 389 | ifxusb_wreg( &global_regs->grstctl, greset.d32 ); |
| 390 | |
| 391 | do |
| 392 | { |
| 393 | greset.d32 = ifxusb_rreg( &global_regs->grstctl); |
| 394 | if (++count > 10000) |
| 395 | { |
| 396 | IFX_WARN("%s() HANG! GRSTCTL=%0x\n", __func__, greset.d32); |
| 397 | break; |
| 398 | } |
| 399 | } while (greset.b.rxfflsh == 1 || greset.b.txfflsh == 1); |
| 400 | /* Wait for 3 PHY Clocks*/ |
| 401 | UDELAY(1); |
| 402 | } |
| 403 | |
| 404 | /*! |
| 405 | \brief Flush a Tx FIFO. |
| 406 | \param _core_if Pointer of core_if structure |
| 407 | \param _num Tx FIFO to flush. ( 0x10 for ALL TX FIFO ) |
| 408 | */ |
| 409 | void ifxusb_flush_tx_fifo( ifxusb_core_if_t *_core_if, const int _num ) |
| 410 | { |
| 411 | ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs; |
| 412 | volatile grstctl_t greset ={ .d32 = 0}; |
| 413 | int count = 0; |
| 414 | |
| 415 | IFX_DEBUGPL((DBG_CIL|DBG_PCDV), "Flush Tx FIFO %d\n", _num); |
| 416 | |
| 417 | greset.b.intknqflsh=1; |
| 418 | greset.b.txfflsh = 1; |
| 419 | greset.b.txfnum = _num; |
| 420 | ifxusb_wreg( &global_regs->grstctl, greset.d32 ); |
| 421 | |
| 422 | do |
| 423 | { |
| 424 | greset.d32 = ifxusb_rreg( &global_regs->grstctl); |
| 425 | if (++count > 10000&&(_num==0 ||_num==0x10)) |
| 426 | { |
| 427 | IFX_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n", |
| 428 | __func__, greset.d32, |
| 429 | ifxusb_rreg( &global_regs->gnptxsts)); |
| 430 | break; |
| 431 | } |
| 432 | } while (greset.b.txfflsh == 1); |
| 433 | /* Wait for 3 PHY Clocks*/ |
| 434 | UDELAY(1); |
| 435 | } |
| 436 | |
| 437 | |
| 438 | /*! |
| 439 | \brief Flush Rx FIFO. |
| 440 | \param _core_if Pointer of core_if structure |
| 441 | */ |
| 442 | void ifxusb_flush_rx_fifo( ifxusb_core_if_t *_core_if ) |
| 443 | { |
| 444 | ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs; |
| 445 | volatile grstctl_t greset ={ .d32 = 0}; |
| 446 | int count = 0; |
| 447 | |
| 448 | IFX_DEBUGPL((DBG_CIL|DBG_PCDV), "%s\n", __func__); |
| 449 | greset.b.rxfflsh = 1; |
| 450 | ifxusb_wreg( &global_regs->grstctl, greset.d32 ); |
| 451 | |
| 452 | do |
| 453 | { |
| 454 | greset.d32 = ifxusb_rreg( &global_regs->grstctl); |
| 455 | if (++count > 10000) |
| 456 | { |
| 457 | IFX_WARN("%s() HANG! GRSTCTL=%0x\n", __func__, greset.d32); |
| 458 | break; |
| 459 | } |
| 460 | } while (greset.b.rxfflsh == 1); |
| 461 | /* Wait for 3 PHY Clocks*/ |
| 462 | UDELAY(1); |
| 463 | } |
| 464 | |
| 465 | |
| 466 | #define SOFT_RESET_DELAY 100 |
| 467 | |
| 468 | /*! |
| 469 | \brief Do a soft reset of the core. Be careful with this because it |
| 470 | resets all the internal state machines of the core. |
| 471 | \param _core_if Pointer of core_if structure |
| 472 | */ |
| 473 | int ifxusb_core_soft_reset(ifxusb_core_if_t *_core_if) |
| 474 | { |
| 475 | ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs; |
| 476 | volatile grstctl_t greset ={ .d32 = 0}; |
| 477 | int count = 0; |
| 478 | |
| 479 | IFX_DEBUGPL(DBG_CILV, "%s\n", __func__); |
| 480 | /* Wait for AHB master IDLE state. */ |
| 481 | do |
| 482 | { |
| 483 | UDELAY(10); |
| 484 | greset.d32 = ifxusb_rreg( &global_regs->grstctl); |
| 485 | if (++count > 100000) |
| 486 | { |
| 487 | IFX_WARN("%s() HANG! AHB Idle GRSTCTL=%0x %x\n", __func__, |
| 488 | greset.d32, greset.b.ahbidle); |
| 489 | break; |
| 490 | } |
| 491 | } while (greset.b.ahbidle == 0); |
| 492 | |
| 493 | UDELAY(1); |
| 494 | |
| 495 | /* Core Soft Reset */ |
| 496 | count = 0; |
| 497 | greset.b.csftrst = 1; |
| 498 | ifxusb_wreg( &global_regs->grstctl, greset.d32 ); |
| 499 | |
| 500 | #ifdef SOFT_RESET_DELAY |
| 501 | MDELAY(SOFT_RESET_DELAY); |
| 502 | #endif |
| 503 | |
| 504 | do |
| 505 | { |
| 506 | UDELAY(10); |
| 507 | greset.d32 = ifxusb_rreg( &global_regs->grstctl); |
| 508 | if (++count > 100000) |
| 509 | { |
| 510 | IFX_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n", __func__, greset.d32); |
| 511 | return -1; |
| 512 | } |
| 513 | } while (greset.b.csftrst == 1); |
| 514 | |
| 515 | #ifdef SOFT_RESET_DELAY |
| 516 | MDELAY(SOFT_RESET_DELAY); |
| 517 | #endif |
| 518 | |
| 519 | |
| 520 | #if defined(__IS_VR9__) |
| 521 | if(_core_if->core_no==0) |
| 522 | { |
| 523 | set_bit (4, VR9_RCU_USBRESET2); |
| 524 | MDELAY(50); |
| 525 | clear_bit (4, VR9_RCU_USBRESET2); |
| 526 | } |
| 527 | else |
| 528 | { |
| 529 | set_bit (5, VR9_RCU_USBRESET2); |
| 530 | MDELAY(50); |
| 531 | clear_bit (5, VR9_RCU_USBRESET2); |
| 532 | } |
| 533 | MDELAY(50); |
| 534 | #endif //defined(__IS_VR9__) |
| 535 | |
| 536 | IFX_PRINT("USB core #%d soft-reset\n",_core_if->core_no); |
| 537 | |
| 538 | return 0; |
| 539 | } |
| 540 | |
| 541 | /*! |
| 542 | \brief Turn on the USB Core Power |
| 543 | \param _core_if Pointer of core_if structure |
| 544 | */ |
| 545 | void ifxusb_power_on (ifxusb_core_if_t *_core_if) |
| 546 | { |
| 547 | struct clk *clk0 = clk_get_sys("usb0", NULL); |
| 548 | struct clk *clk1 = clk_get_sys("usb1", NULL); |
| 549 | // set clock gating |
| 550 | IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); |
| 551 | #if defined(__UEIP__) |
| 552 | |
| 553 | #if defined(__IS_TWINPASS) || defined(__IS_DANUBE__) |
| 554 | set_bit (4, (volatile unsigned long *)DANUBE_CGU_IFCCR); |
| 555 | set_bit (5, (volatile unsigned long *)DANUBE_CGU_IFCCR); |
| 556 | #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 557 | #if defined(__IS_AMAZON_SE__) |
| 558 | // clear_bit (4, (volatile unsigned long *)AMAZON_SE_CGU_IFCCR); |
| 559 | clear_bit (5, (volatile unsigned long *)AMAZON_SE_CGU_IFCCR); |
| 560 | #endif //defined(__IS_AMAZON_SE__) |
| 561 | #if defined(__IS_AR9__) |
| 562 | set_bit (0, (volatile unsigned long *)AR9_CGU_IFCCR); |
| 563 | set_bit (1, (volatile unsigned long *)AR9_CGU_IFCCR); |
| 564 | #endif //defined(__IS_AR9__) |
| 565 | #if defined(__IS_VR9__) |
| 566 | // set_bit (0, (volatile unsigned long *)VR9_CGU_IFCCR); |
| 567 | // set_bit (1, (volatile unsigned long *)VR9_CGU_IFCCR); |
| 568 | #endif //defined(__IS_VR9__) |
| 569 | |
| 570 | MDELAY(50); |
| 571 | |
| 572 | // set power |
| 573 | #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) |
| 574 | USB_CTRL_PMU_SETUP(IFX_PMU_ENABLE); |
| 575 | //#if defined(__IS_TWINPASS__) |
| 576 | // ifxusb_enable_afe_oc(); |
| 577 | //#endif |
| 578 | #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) |
| 579 | #if defined(__IS_AR9__) || defined(__IS_VR9__) |
| 580 | if(_core_if->core_no==0) |
| 581 | clk_enable(clk0); |
| 582 | // USB0_CTRL_PMU_SETUP(IFX_PMU_ENABLE); |
| 583 | else |
| 584 | clk_enable(clk1); |
| 585 | // USB1_CTRL_PMU_SETUP(IFX_PMU_ENABLE); |
| 586 | #endif //defined(__IS_AR9__) || defined(__IS_VR9__) |
| 587 | |
| 588 | if(_core_if->core_global_regs) |
| 589 | { |
| 590 | // PHY configurations. |
| 591 | #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 592 | ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); |
| 593 | #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 594 | #if defined(__IS_AMAZON_SE__) |
| 595 | ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); |
| 596 | #endif //defined(__IS_AMAZON_SE__) |
| 597 | #if defined(__IS_AR9__) |
| 598 | ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); |
| 599 | #endif //defined(__IS_AR9__) |
| 600 | #if defined(__IS_VR9__) |
| 601 | //ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); |
| 602 | #endif //defined(__IS_VR9__) |
| 603 | } |
| 604 | #else //defined(__UEIP__) |
| 605 | #if defined(__IS_TWINPASS) || defined(__IS_DANUBE__) |
| 606 | set_bit (4, (volatile unsigned long *)DANUBE_CGU_IFCCR); |
| 607 | set_bit (5, (volatile unsigned long *)DANUBE_CGU_IFCCR); |
| 608 | #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 609 | #if defined(__IS_AMAZON_SE__) |
| 610 | // clear_bit (4, (volatile unsigned long *)AMAZON_SE_CGU_IFCCR); |
| 611 | clear_bit (5, (volatile unsigned long *)AMAZON_SE_CGU_IFCCR); |
| 612 | #endif //defined(__IS_AMAZON_SE__) |
| 613 | #if defined(__IS_AR9__) |
| 614 | set_bit (0, (volatile unsigned long *)AMAZON_S_CGU_IFCCR); |
| 615 | set_bit (1, (volatile unsigned long *)AMAZON_S_CGU_IFCCR); |
| 616 | #endif //defined(__IS_AR9__) |
| 617 | |
| 618 | MDELAY(50); |
| 619 | |
| 620 | // set power |
| 621 | #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 622 | clear_bit (6, (volatile unsigned long *)DANUBE_PMU_PWDCR);//USB |
| 623 | clear_bit (9, (volatile unsigned long *)DANUBE_PMU_PWDCR);//DSL |
| 624 | clear_bit (15, (volatile unsigned long *)DANUBE_PMU_PWDCR);//AHB |
| 625 | #if defined(__IS_TWINPASS__) |
| 626 | ifxusb_enable_afe_oc(); |
| 627 | #endif |
| 628 | #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 629 | #if defined(__IS_AMAZON_SE__) |
| 630 | clear_bit (6, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR); |
| 631 | clear_bit (9, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR); |
| 632 | clear_bit (15, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR); |
| 633 | #endif //defined(__IS_AMAZON_SE__) |
| 634 | #if defined(__IS_AR9__) |
| 635 | if(_core_if->core_no==0) |
| 636 | clear_bit (6, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//USB |
| 637 | else |
| 638 | clear_bit (27, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//USB |
| 639 | clear_bit (9, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//DSL |
| 640 | clear_bit (15, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//AHB |
| 641 | #endif //defined(__IS_AR9__) |
| 642 | |
| 643 | if(_core_if->core_global_regs) |
| 644 | { |
| 645 | // PHY configurations. |
| 646 | #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 647 | ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); |
| 648 | #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 649 | #if defined(__IS_AMAZON_SE__) |
| 650 | ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); |
| 651 | #endif //defined(__IS_AMAZON_SE__) |
| 652 | #if defined(__IS_AR9__) |
| 653 | ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); |
| 654 | #endif //defined(__IS_AR9__) |
| 655 | } |
| 656 | |
| 657 | #endif //defined(__UEIP__) |
| 658 | } |
| 659 | |
| 660 | /*! |
| 661 | \brief Turn off the USB Core Power |
| 662 | \param _core_if Pointer of core_if structure |
| 663 | */ |
| 664 | void ifxusb_power_off (ifxusb_core_if_t *_core_if) |
| 665 | { |
| 666 | struct clk *clk0 = clk_get_sys("usb0", NULL); |
| 667 | struct clk *clk1 = clk_get_sys("usb1", NULL); |
| 668 | ifxusb_phy_power_off (_core_if); |
| 669 | |
| 670 | // set power |
| 671 | #if defined(__UEIP__) |
| 672 | #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) |
| 673 | USB_CTRL_PMU_SETUP(IFX_PMU_DISABLE); |
| 674 | #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) |
| 675 | #if defined(__IS_AR9__) || defined(__IS_VR9__) |
| 676 | if(_core_if->core_no==0) |
| 677 | clk_disable(clk0); |
| 678 | //USB0_CTRL_PMU_SETUP(IFX_PMU_DISABLE); |
| 679 | else |
| 680 | clk_disable(clk1); |
| 681 | //USB1_CTRL_PMU_SETUP(IFX_PMU_DISABLE); |
| 682 | #endif //defined(__IS_AR9__) || defined(__IS_VR9__) |
| 683 | #else //defined(__UEIP__) |
| 684 | #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 685 | set_bit (6, (volatile unsigned long *)DANUBE_PMU_PWDCR);//USB |
| 686 | #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 687 | #if defined(__IS_AMAZON_SE__) |
| 688 | set_bit (6, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR);//USB |
| 689 | #endif //defined(__IS_AMAZON_SE__) |
| 690 | #if defined(__IS_AR9__) |
| 691 | if(_core_if->core_no==0) |
| 692 | set_bit (6, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//USB |
| 693 | else |
| 694 | set_bit (27, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//USB |
| 695 | #endif //defined(__IS_AR9__) |
| 696 | #endif //defined(__UEIP__) |
| 697 | } |
| 698 | |
| 699 | /*! |
| 700 | \brief Turn on the USB PHY Power |
| 701 | \param _core_if Pointer of core_if structure |
| 702 | */ |
| 703 | void ifxusb_phy_power_on (ifxusb_core_if_t *_core_if) |
| 704 | { |
| 705 | struct clk *clk0 = clk_get_sys("usb0", NULL); |
| 706 | struct clk *clk1 = clk_get_sys("usb1", NULL); |
| 707 | #if defined(__UEIP__) |
| 708 | if(_core_if->core_global_regs) |
| 709 | { |
| 710 | #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 711 | ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); |
| 712 | #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 713 | #if defined(__IS_AMAZON_SE__) |
| 714 | ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); |
| 715 | #endif //defined(__IS_AMAZON_SE__) |
| 716 | #if defined(__IS_AR9__) |
| 717 | ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); |
| 718 | #endif //defined(__IS_AR9__) |
| 719 | #if defined(__IS_VR9_S__) |
| 720 | if(_core_if->core_no==0) |
| 721 | set_bit (0, VR9_RCU_USB_ANA_CFG1A); |
| 722 | else |
| 723 | set_bit (0, VR9_RCU_USB_ANA_CFG1B); |
| 724 | #endif //defined(__IS_VR9__) |
| 725 | } |
| 726 | |
| 727 | #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) |
| 728 | USB_PHY_PMU_SETUP(IFX_PMU_ENABLE); |
| 729 | #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) |
| 730 | #if defined(__IS_AR9__) || defined(__IS_VR9__) |
| 731 | if(_core_if->core_no==0) |
| 732 | clk_enable(clk0); |
| 733 | //USB0_PHY_PMU_SETUP(IFX_PMU_ENABLE); |
| 734 | else |
| 735 | clk_enable(clk1); |
| 736 | //USB1_PHY_PMU_SETUP(IFX_PMU_ENABLE); |
| 737 | #endif //defined(__IS_AR9__) || defined(__IS_VR9__) |
| 738 | |
| 739 | // PHY configurations. |
| 740 | if(_core_if->core_global_regs) |
| 741 | { |
| 742 | #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 743 | ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); |
| 744 | #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 745 | #if defined(__IS_AMAZON_SE__) |
| 746 | ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); |
| 747 | #endif //defined(__IS_AMAZON_SE__) |
| 748 | #if defined(__IS_AR9__) |
| 749 | ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); |
| 750 | #endif //defined(__IS_AR9__) |
| 751 | #if defined(__IS_VR9_S__) |
| 752 | if(_core_if->core_no==0) |
| 753 | set_bit (0, VR9_RCU_USB_ANA_CFG1A); |
| 754 | else |
| 755 | set_bit (0, VR9_RCU_USB_ANA_CFG1B); |
| 756 | #endif //defined(__IS_VR9__) |
| 757 | } |
| 758 | #else //defined(__UEIP__) |
| 759 | // PHY configurations. |
| 760 | if(_core_if->core_global_regs) |
| 761 | { |
| 762 | #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 763 | ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); |
| 764 | #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 765 | #if defined(__IS_AMAZON_SE__) |
| 766 | ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); |
| 767 | #endif //defined(__IS_AMAZON_SE__) |
| 768 | #if defined(__IS_AR9__) |
| 769 | ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); |
| 770 | #endif //defined(__IS_AR9__) |
| 771 | } |
| 772 | |
| 773 | #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 774 | clear_bit (0, (volatile unsigned long *)DANUBE_PMU_PWDCR);//PHY |
| 775 | #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 776 | #if defined(__IS_AMAZON_SE__) |
| 777 | clear_bit (0, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR); |
| 778 | #endif //defined(__IS_AMAZON_SE__) |
| 779 | #if defined(__IS_AR9__) |
| 780 | if(_core_if->core_no==0) |
| 781 | clear_bit (0, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//PHY |
| 782 | else |
| 783 | clear_bit (26, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//PHY |
| 784 | #endif //defined(__IS_AR9__) |
| 785 | |
| 786 | // PHY configurations. |
| 787 | if(_core_if->core_global_regs) |
| 788 | { |
| 789 | #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 790 | ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); |
| 791 | #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 792 | #if defined(__IS_AMAZON_SE__) |
| 793 | ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); |
| 794 | #endif //defined(__IS_AMAZON_SE__) |
| 795 | #if defined(__IS_AR9__) |
| 796 | ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); |
| 797 | #endif //defined(__IS_AR9__) |
| 798 | } |
| 799 | #endif //defined(__UEIP__) |
| 800 | } |
| 801 | |
| 802 | |
| 803 | /*! |
| 804 | \brief Turn off the USB PHY Power |
| 805 | \param _core_if Pointer of core_if structure |
| 806 | */ |
| 807 | void ifxusb_phy_power_off (ifxusb_core_if_t *_core_if) |
| 808 | { |
| 809 | struct clk *clk0 = clk_get_sys("usb0", NULL); |
| 810 | struct clk *clk1 = clk_get_sys("usb1", NULL); |
| 811 | #if defined(__UEIP__) |
| 812 | #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) |
| 813 | USB_PHY_PMU_SETUP(IFX_PMU_DISABLE); |
| 814 | #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) |
| 815 | #if defined(__IS_AR9__) || defined(__IS_VR9__) |
| 816 | if(_core_if->core_no==0) |
| 817 | clk_disable(clk0); |
| 818 | //USB0_PHY_PMU_SETUP(IFX_PMU_DISABLE); |
| 819 | else |
| 820 | clk_disable(clk1); |
| 821 | //USB1_PHY_PMU_SETUP(IFX_PMU_DISABLE); |
| 822 | #endif // defined(__IS_AR9__) || defined(__IS_VR9__) |
| 823 | #else //defined(__UEIP__) |
| 824 | #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 825 | set_bit (0, (volatile unsigned long *)DANUBE_PMU_PWDCR);//PHY |
| 826 | #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 827 | #if defined(__IS_AMAZON_SE__) |
| 828 | set_bit (0, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR);//PHY |
| 829 | #endif //defined(__IS_AMAZON_SE__) |
| 830 | #if defined(__IS_AR9__) |
| 831 | if(_core_if->core_no==0) |
| 832 | set_bit (0, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//PHY |
| 833 | else |
| 834 | set_bit (26, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//PHY |
| 835 | #endif //defined(__IS_AR9__) |
| 836 | #endif //defined(__UEIP__) |
| 837 | } |
| 838 | |
| 839 | |
| 840 | /*! |
| 841 | \brief Reset on the USB Core RCU |
| 842 | \param _core_if Pointer of core_if structure |
| 843 | */ |
| 844 | #if defined(__IS_VR9__) |
| 845 | int already_hard_reset=0; |
| 846 | #endif |
| 847 | void ifxusb_hard_reset(ifxusb_core_if_t *_core_if) |
| 848 | { |
| 849 | #if defined(__UEIP__) |
| 850 | #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 851 | #if defined (__IS_HOST__) |
| 852 | clear_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG); |
| 853 | #elif defined (__IS_DEVICE__) |
| 854 | set_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG); |
| 855 | #endif |
| 856 | #endif //defined(__IS_AMAZON_SE__) |
| 857 | |
| 858 | #if defined(__IS_AMAZON_SE__) |
| 859 | #if defined (__IS_HOST__) |
| 860 | clear_bit (AMAZON_SE_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG); |
| 861 | #elif defined (__IS_DEVICE__) |
| 862 | set_bit (AMAZON_SE_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG); |
| 863 | #endif |
| 864 | #endif //defined(__IS_AMAZON_SE__) |
| 865 | |
| 866 | #if defined(__IS_AR9__) |
| 867 | if(_core_if->core_no==0) |
| 868 | { |
| 869 | #if defined (__IS_HOST__) |
| 870 | clear_bit (AR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR9_RCU_USB1CFG); |
| 871 | #elif defined (__IS_DEVICE__) |
| 872 | set_bit (AR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR9_RCU_USB1CFG); |
| 873 | #endif |
| 874 | } |
| 875 | else |
| 876 | { |
| 877 | #if defined (__IS_HOST__) |
| 878 | clear_bit (AR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR9_RCU_USB2CFG); |
| 879 | #elif defined (__IS_DEVICE__) |
| 880 | set_bit (AR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR9_RCU_USB2CFG); |
| 881 | #endif |
| 882 | } |
| 883 | #endif //defined(__IS_AR9__) |
| 884 | |
| 885 | #if defined(__IS_VR9__) |
| 886 | if(_core_if->core_no==0) |
| 887 | { |
| 888 | #if defined (__IS_HOST__) |
| 889 | clear_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB1CFG); |
| 890 | #elif defined (__IS_DEVICE__) |
| 891 | set_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB1CFG); |
| 892 | #endif |
| 893 | } |
| 894 | else |
| 895 | { |
| 896 | #if defined (__IS_HOST__) |
| 897 | clear_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB2CFG); |
| 898 | #elif defined (__IS_DEVICE__) |
| 899 | set_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB2CFG); |
| 900 | #endif |
| 901 | } |
| 902 | #endif //defined(__IS_VR9__) |
| 903 | |
| 904 | |
| 905 | // set the HC's byte-order to big-endian |
| 906 | #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 907 | set_bit (DANUBE_USBCFG_HOST_END_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG); |
| 908 | clear_bit (DANUBE_USBCFG_SLV_END_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG); |
| 909 | #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 910 | #if defined(__IS_AMAZON_SE__) |
| 911 | set_bit (AMAZON_SE_USBCFG_HOST_END_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG); |
| 912 | clear_bit (AMAZON_SE_USBCFG_SLV_END_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG); |
| 913 | #endif //defined(__IS_AMAZON_SE__) |
| 914 | #if defined(__IS_AR9__) |
| 915 | if(_core_if->core_no==0) |
| 916 | { |
| 917 | set_bit (AR9_USBCFG_HOST_END_BIT, (volatile unsigned long *)AR9_RCU_USB1CFG); |
| 918 | clear_bit (AR9_USBCFG_SLV_END_BIT, (volatile unsigned long *)AR9_RCU_USB1CFG); |
| 919 | } |
| 920 | else |
| 921 | { |
| 922 | set_bit (AR9_USBCFG_HOST_END_BIT, (volatile unsigned long *)AR9_RCU_USB2CFG); |
| 923 | clear_bit (AR9_USBCFG_SLV_END_BIT, (volatile unsigned long *)AR9_RCU_USB2CFG); |
| 924 | } |
| 925 | #endif //defined(__IS_AR9__) |
| 926 | #if defined(__IS_VR9__) |
| 927 | if(_core_if->core_no==0) |
| 928 | { |
| 929 | set_bit (VR9_USBCFG_HOST_END_BIT, (volatile unsigned long *)VR9_RCU_USB1CFG); |
| 930 | clear_bit (VR9_USBCFG_SLV_END_BIT, (volatile unsigned long *)VR9_RCU_USB1CFG); |
| 931 | } |
| 932 | else |
| 933 | { |
| 934 | set_bit (VR9_USBCFG_HOST_END_BIT, (volatile unsigned long *)VR9_RCU_USB2CFG); |
| 935 | clear_bit (VR9_USBCFG_SLV_END_BIT, (volatile unsigned long *)VR9_RCU_USB2CFG); |
| 936 | } |
| 937 | #endif //defined(__IS_VR9__) |
| 938 | |
| 939 | #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 940 | set_bit (4, DANUBE_RCU_RESET); |
| 941 | MDELAY(500); |
| 942 | clear_bit (4, DANUBE_RCU_RESET); |
| 943 | #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 944 | |
| 945 | #if defined(__IS_AMAZON_SE__) |
| 946 | set_bit (4, AMAZON_SE_RCU_RESET); |
| 947 | MDELAY(500); |
| 948 | clear_bit (4, AMAZON_SE_RCU_RESET); |
| 949 | MDELAY(500); |
| 950 | #endif //defined(__IS_AMAZON_SE__) |
| 951 | |
| 952 | #if defined(__IS_AR9__) |
| 953 | if(_core_if->core_no==0) |
| 954 | { |
| 955 | set_bit (4, AR9_RCU_USBRESET); |
| 956 | MDELAY(500); |
| 957 | clear_bit (4, AR9_RCU_USBRESET); |
| 958 | } |
| 959 | else |
| 960 | { |
| 961 | set_bit (28, AR9_RCU_USBRESET); |
| 962 | MDELAY(500); |
| 963 | clear_bit (28, AR9_RCU_USBRESET); |
| 964 | } |
| 965 | MDELAY(500); |
| 966 | #endif //defined(__IS_AR9__) |
| 967 | #if defined(__IS_VR9__) |
| 968 | if(!already_hard_reset) |
| 969 | { |
| 970 | set_bit (4, VR9_RCU_USBRESET); |
| 971 | MDELAY(500); |
| 972 | clear_bit (4, VR9_RCU_USBRESET); |
| 973 | MDELAY(500); |
| 974 | already_hard_reset=1; |
| 975 | } |
| 976 | #endif //defined(__IS_VR9__) |
| 977 | |
| 978 | #if defined(__IS_TWINPASS__) |
| 979 | ifxusb_enable_afe_oc(); |
| 980 | #endif |
| 981 | |
| 982 | if(_core_if->core_global_regs) |
| 983 | { |
| 984 | // PHY configurations. |
| 985 | #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 986 | ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); |
| 987 | #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 988 | #if defined(__IS_AMAZON_SE__) |
| 989 | ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); |
| 990 | #endif //defined(__IS_AMAZON_SE__) |
| 991 | #if defined(__IS_AR9__) |
| 992 | ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); |
| 993 | #endif //defined(__IS_AR9__) |
| 994 | #if defined(__IS_VR9__) |
| 995 | // ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); |
| 996 | #endif //defined(__IS_VR9__) |
| 997 | } |
| 998 | #else //defined(__UEIP__) |
| 999 | #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 1000 | #if defined (__IS_HOST__) |
| 1001 | clear_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG); |
| 1002 | #elif defined (__IS_DEVICE__) |
| 1003 | set_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG); |
| 1004 | #endif |
| 1005 | #endif //defined(__IS_AMAZON_SE__) |
| 1006 | |
| 1007 | #if defined(__IS_AMAZON_SE__) |
| 1008 | #if defined (__IS_HOST__) |
| 1009 | clear_bit (AMAZON_SE_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG); |
| 1010 | #elif defined (__IS_DEVICE__) |
| 1011 | set_bit (AMAZON_SE_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG); |
| 1012 | #endif |
| 1013 | #endif //defined(__IS_AMAZON_SE__) |
| 1014 | |
| 1015 | #if defined(__IS_AR9__) |
| 1016 | if(_core_if->core_no==0) |
| 1017 | { |
| 1018 | #if defined (__IS_HOST__) |
| 1019 | clear_bit (AMAZON_S_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB1CFG); |
| 1020 | #elif defined (__IS_DEVICE__) |
| 1021 | set_bit (AMAZON_S_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB1CFG); |
| 1022 | #endif |
| 1023 | } |
| 1024 | else |
| 1025 | { |
| 1026 | #if defined (__IS_HOST__) |
| 1027 | clear_bit (AMAZON_S_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB2CFG); |
| 1028 | #elif defined (__IS_DEVICE__) |
| 1029 | set_bit (AMAZON_S_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB2CFG); |
| 1030 | #endif |
| 1031 | } |
| 1032 | #endif //defined(__IS_AR9__) |
| 1033 | |
| 1034 | // set the HC's byte-order to big-endian |
| 1035 | #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 1036 | set_bit (DANUBE_USBCFG_HOST_END_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG); |
| 1037 | clear_bit (DANUBE_USBCFG_SLV_END_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG); |
| 1038 | #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 1039 | #if defined(__IS_AMAZON_SE__) |
| 1040 | set_bit (AMAZON_SE_USBCFG_HOST_END_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG); |
| 1041 | clear_bit (AMAZON_SE_USBCFG_SLV_END_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG); |
| 1042 | #endif //defined(__IS_AMAZON_SE__) |
| 1043 | #if defined(__IS_AR9__) |
| 1044 | if(_core_if->core_no==0) |
| 1045 | { |
| 1046 | set_bit (AMAZON_S_USBCFG_HOST_END_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB1CFG); |
| 1047 | clear_bit (AMAZON_S_USBCFG_SLV_END_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB1CFG); |
| 1048 | } |
| 1049 | else |
| 1050 | { |
| 1051 | set_bit (AMAZON_S_USBCFG_HOST_END_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB2CFG); |
| 1052 | clear_bit (AMAZON_S_USBCFG_SLV_END_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB2CFG); |
| 1053 | } |
| 1054 | #endif //defined(__IS_AR9__) |
| 1055 | |
| 1056 | #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 1057 | set_bit (4, DANUBE_RCU_RESET); |
| 1058 | #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 1059 | #if defined(__IS_AMAZON_SE__) |
| 1060 | set_bit (4, AMAZON_SE_RCU_RESET); |
| 1061 | #endif //defined(__IS_AMAZON_SE__) |
| 1062 | #if defined(__IS_AR9__) |
| 1063 | if(_core_if->core_no==0) |
| 1064 | { |
| 1065 | set_bit (4, AMAZON_S_RCU_USBRESET); |
| 1066 | } |
| 1067 | else |
| 1068 | { |
| 1069 | set_bit (28, AMAZON_S_RCU_USBRESET); |
| 1070 | } |
| 1071 | #endif //defined(__IS_AR9__) |
| 1072 | |
| 1073 | MDELAY(500); |
| 1074 | |
| 1075 | #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 1076 | clear_bit (4, DANUBE_RCU_RESET); |
| 1077 | #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 1078 | #if defined(__IS_AMAZON_SE__) |
| 1079 | clear_bit (4, AMAZON_SE_RCU_RESET); |
| 1080 | #endif //defined(__IS_AMAZON_SE__) |
| 1081 | #if defined(__IS_AR9__) |
| 1082 | if(_core_if->core_no==0) |
| 1083 | { |
| 1084 | clear_bit (4, AMAZON_S_RCU_USBRESET); |
| 1085 | } |
| 1086 | else |
| 1087 | { |
| 1088 | clear_bit (28, AMAZON_S_RCU_USBRESET); |
| 1089 | } |
| 1090 | #endif //defined(__IS_AR9__) |
| 1091 | |
| 1092 | MDELAY(500); |
| 1093 | |
| 1094 | #if defined(__IS_TWINPASS__) |
| 1095 | ifxusb_enable_afe_oc(); |
| 1096 | #endif |
| 1097 | |
| 1098 | if(_core_if->core_global_regs) |
| 1099 | { |
| 1100 | // PHY configurations. |
| 1101 | #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 1102 | ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); |
| 1103 | #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 1104 | #if defined(__IS_AMAZON_SE__) |
| 1105 | ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); |
| 1106 | #endif //defined(__IS_AMAZON_SE__) |
| 1107 | #if defined(__IS_AR9__) |
| 1108 | ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); |
| 1109 | #endif //defined(__IS_AR9__) |
| 1110 | } |
| 1111 | #endif //defined(__UEIP__) |
| 1112 | } |
| 1113 | |
| 1114 | #if defined(__GADGET_LED__) || defined(__HOST_LED__) |
| 1115 | #if defined(__UEIP__) |
| 1116 | static void *g_usb_led_trigger = NULL; |
| 1117 | #endif |
| 1118 | |
| 1119 | void ifxusb_led_init(ifxusb_core_if_t *_core_if) |
| 1120 | { |
| 1121 | #if defined(__UEIP__) |
| 1122 | if ( !g_usb_led_trigger ) |
| 1123 | { |
| 1124 | ifx_led_trigger_register("usb_link", &g_usb_led_trigger); |
| 1125 | if ( g_usb_led_trigger != NULL ) |
| 1126 | { |
| 1127 | struct ifx_led_trigger_attrib attrib = {0}; |
| 1128 | attrib.delay_on = 250; |
| 1129 | attrib.delay_off = 250; |
| 1130 | attrib.timeout = 2000; |
| 1131 | attrib.def_value = 1; |
| 1132 | attrib.flags = IFX_LED_TRIGGER_ATTRIB_DELAY_ON | IFX_LED_TRIGGER_ATTRIB_DELAY_OFF | IFX_LED_TRIGGER_ATTRIB_TIMEOUT | IFX_LED_TRIGGER_ATTRIB_DEF_VALUE; |
| 1133 | IFX_DEBUGP("Reg USB LED!!\n"); |
| 1134 | ifx_led_trigger_set_attrib(g_usb_led_trigger, &attrib); |
| 1135 | } |
| 1136 | } |
| 1137 | #endif //defined(__UEIP__) |
| 1138 | } |
| 1139 | |
| 1140 | void ifxusb_led_free(ifxusb_core_if_t *_core_if) |
| 1141 | { |
| 1142 | #if defined(__UEIP__) |
| 1143 | if ( g_usb_led_trigger ) |
| 1144 | { |
| 1145 | ifx_led_trigger_deregister(g_usb_led_trigger); |
| 1146 | g_usb_led_trigger = NULL; |
| 1147 | } |
| 1148 | #endif //defined(__UEIP__) |
| 1149 | } |
| 1150 | |
| 1151 | /*! |
| 1152 | \brief Turn off the USB 5V VBus Power |
| 1153 | \param _core_if Pointer of core_if structure |
| 1154 | */ |
| 1155 | void ifxusb_led(ifxusb_core_if_t *_core_if) |
| 1156 | { |
| 1157 | #if defined(__UEIP__) |
| 1158 | if(g_usb_led_trigger) |
| 1159 | ifx_led_trigger_activate(g_usb_led_trigger); |
| 1160 | #else |
| 1161 | #endif //defined(__UEIP__) |
| 1162 | } |
| 1163 | #endif // defined(__GADGET_LED__) || defined(__HOST_LED__) |
| 1164 | |
| 1165 | |
| 1166 | |
| 1167 | #if defined(__IS_HOST__) && defined(__DO_OC_INT__) && defined(__DO_OC_INT_ENABLE__) |
| 1168 | /*! |
| 1169 | \brief Turn on the OC Int |
| 1170 | */ |
| 1171 | void ifxusb_oc_int_on() |
| 1172 | { |
| 1173 | #if defined(__UEIP__) |
| 1174 | #else |
| 1175 | #if defined(__IS_TWINPASS__) |
| 1176 | irq_enable(DANUBE_USB_OC_INT); |
| 1177 | #endif |
| 1178 | #endif //defined(__UEIP__) |
| 1179 | } |
| 1180 | /*! |
| 1181 | \brief Turn off the OC Int |
| 1182 | */ |
| 1183 | void ifxusb_oc_int_off() |
| 1184 | { |
| 1185 | #if defined(__UEIP__) |
| 1186 | #else |
| 1187 | #if defined(__IS_TWINPASS__) |
| 1188 | irq_disable(DANUBE_USB_OC_INT); |
| 1189 | #endif |
| 1190 | #endif //defined(__UEIP__) |
| 1191 | } |
| 1192 | #endif //defined(__IS_HOST__) && defined(__DO_OC_INT__) && defined(__DO_OC_INT_ENABLE__) |
| 1193 | |
| 1194 | /* internal routines for debugging */ |
| 1195 | void ifxusb_dump_msg(const u8 *buf, unsigned int length) |
| 1196 | { |
| 1197 | #ifdef __DEBUG__ |
| 1198 | unsigned int start, num, i; |
| 1199 | char line[52], *p; |
| 1200 | |
| 1201 | if (length >= 512) |
| 1202 | return; |
| 1203 | start = 0; |
| 1204 | while (length > 0) |
| 1205 | { |
| 1206 | num = min(length, 16u); |
| 1207 | p = line; |
| 1208 | for (i = 0; i < num; ++i) |
| 1209 | { |
| 1210 | if (i == 8) |
| 1211 | *p++ = ' '; |
| 1212 | sprintf(p, " %02x", buf[i]); |
| 1213 | p += 3; |
| 1214 | } |
| 1215 | *p = 0; |
| 1216 | IFX_PRINT( "%6x: %s\n", start, line); |
| 1217 | buf += num; |
| 1218 | start += num; |
| 1219 | length -= num; |
| 1220 | } |
| 1221 | #endif |
| 1222 | } |
| 1223 | |
| 1224 | /* This functions reads the SPRAM and prints its content */ |
| 1225 | void ifxusb_dump_spram(ifxusb_core_if_t *_core_if) |
| 1226 | { |
| 1227 | #ifdef __ENABLE_DUMP__ |
| 1228 | volatile uint8_t *addr, *start_addr, *end_addr; |
| 1229 | uint32_t size; |
| 1230 | IFX_PRINT("SPRAM Data:\n"); |
| 1231 | start_addr = (void*)_core_if->core_global_regs; |
| 1232 | IFX_PRINT("Base Address: 0x%8X\n", (uint32_t)start_addr); |
| 1233 | |
| 1234 | start_addr = (void*)_core_if->data_fifo_dbg; |
| 1235 | IFX_PRINT("Starting Address: 0x%8X\n", (uint32_t)start_addr); |
| 1236 | |
| 1237 | size=_core_if->hwcfg3.b.dfifo_depth; |
| 1238 | size<<=2; |
| 1239 | size+=0x200; |
| 1240 | size&=0x0003FFFC; |
| 1241 | |
| 1242 | end_addr = (void*)_core_if->data_fifo_dbg; |
| 1243 | end_addr += size; |
| 1244 | |
| 1245 | for(addr = start_addr; addr < end_addr; addr+=16) |
| 1246 | { |
| 1247 | IFX_PRINT("0x%8X:\t%02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", (uint32_t)addr, |
| 1248 | addr[ 0], addr[ 1], addr[ 2], addr[ 3], |
| 1249 | addr[ 4], addr[ 5], addr[ 6], addr[ 7], |
| 1250 | addr[ 8], addr[ 9], addr[10], addr[11], |
| 1251 | addr[12], addr[13], addr[14], addr[15] |
| 1252 | ); |
| 1253 | } |
| 1254 | return; |
| 1255 | #endif //__ENABLE_DUMP__ |
| 1256 | } |
| 1257 | |
| 1258 | |
| 1259 | |
| 1260 | |
| 1261 | /* This function reads the core global registers and prints them */ |
| 1262 | void ifxusb_dump_registers(ifxusb_core_if_t *_core_if) |
| 1263 | { |
| 1264 | #ifdef __ENABLE_DUMP__ |
| 1265 | int i; |
| 1266 | volatile uint32_t *addr; |
| 1267 | #ifdef __IS_DEVICE__ |
| 1268 | volatile uint32_t *addri,*addro; |
| 1269 | #endif |
| 1270 | |
| 1271 | IFX_PRINT("Core Global Registers\n"); |
| 1272 | addr=&_core_if->core_global_regs->gotgctl; |
| 1273 | IFX_PRINT("GOTGCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1274 | addr=&_core_if->core_global_regs->gotgint; |
| 1275 | IFX_PRINT("GOTGINT @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1276 | addr=&_core_if->core_global_regs->gahbcfg; |
| 1277 | IFX_PRINT("GAHBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1278 | addr=&_core_if->core_global_regs->gusbcfg; |
| 1279 | IFX_PRINT("GUSBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1280 | addr=&_core_if->core_global_regs->grstctl; |
| 1281 | IFX_PRINT("GRSTCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1282 | addr=&_core_if->core_global_regs->gintsts; |
| 1283 | IFX_PRINT("GINTSTS @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1284 | addr=&_core_if->core_global_regs->gintmsk; |
| 1285 | IFX_PRINT("GINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1286 | addr=&_core_if->core_global_regs->gi2cctl; |
| 1287 | IFX_PRINT("GI2CCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1288 | addr=&_core_if->core_global_regs->gpvndctl; |
| 1289 | IFX_PRINT("GPVNDCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1290 | addr=&_core_if->core_global_regs->ggpio; |
| 1291 | IFX_PRINT("GGPIO @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1292 | addr=&_core_if->core_global_regs->guid; |
| 1293 | IFX_PRINT("GUID @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1294 | addr=&_core_if->core_global_regs->gsnpsid; |
| 1295 | IFX_PRINT("GSNPSID @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1296 | addr=&_core_if->core_global_regs->ghwcfg1; |
| 1297 | IFX_PRINT("GHWCFG1 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1298 | addr=&_core_if->core_global_regs->ghwcfg2; |
| 1299 | IFX_PRINT("GHWCFG2 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1300 | addr=&_core_if->core_global_regs->ghwcfg3; |
| 1301 | IFX_PRINT("GHWCFG3 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1302 | addr=&_core_if->core_global_regs->ghwcfg4; |
| 1303 | IFX_PRINT("GHWCFG4 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1304 | |
| 1305 | addr=_core_if->pcgcctl; |
| 1306 | IFX_PRINT("PCGCCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1307 | |
| 1308 | addr=&_core_if->core_global_regs->grxfsiz; |
| 1309 | IFX_PRINT("GRXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1310 | |
| 1311 | #ifdef __IS_HOST__ |
| 1312 | addr=&_core_if->core_global_regs->gnptxfsiz; |
| 1313 | IFX_PRINT("GNPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1314 | addr=&_core_if->core_global_regs->hptxfsiz; |
| 1315 | IFX_PRINT("HPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1316 | #endif //__IS_HOST__ |
| 1317 | |
| 1318 | #ifdef __IS_DEVICE__ |
| 1319 | #ifdef __DED_FIFO__ |
| 1320 | addr=&_core_if->core_global_regs->gnptxfsiz; |
| 1321 | IFX_PRINT("GNPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1322 | for (i=0; i<= _core_if->hwcfg4.b.num_in_eps; i++) |
| 1323 | { |
| 1324 | addr=&_core_if->core_global_regs->dptxfsiz_dieptxf[i]; |
| 1325 | IFX_PRINT("DPTXFSIZ[%d] @0x%08X : 0x%08X\n",i,(uint32_t)addr,ifxusb_rreg(addr)); |
| 1326 | } |
| 1327 | #else |
| 1328 | addr=&_core_if->core_global_regs->gnptxfsiz; |
| 1329 | IFX_PRINT("TXFSIZ[00] @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1330 | for (i=0; i< _core_if->hwcfg4.b.num_dev_perio_in_ep; i++) |
| 1331 | { |
| 1332 | addr=&_core_if->core_global_regs->dptxfsiz_dieptxf[i]; |
| 1333 | IFX_PRINT("TXFSIZ[%02d] @0x%08X : 0x%08X\n",i+1,(uint32_t)addr,ifxusb_rreg(addr)); |
| 1334 | } |
| 1335 | #endif |
| 1336 | #endif //__IS_DEVICE__ |
| 1337 | |
| 1338 | #ifdef __IS_HOST__ |
| 1339 | IFX_PRINT("Host Global Registers\n"); |
| 1340 | addr=&_core_if->host_global_regs->hcfg; |
| 1341 | IFX_PRINT("HCFG @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1342 | addr=&_core_if->host_global_regs->hfir; |
| 1343 | IFX_PRINT("HFIR @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1344 | addr=&_core_if->host_global_regs->hfnum; |
| 1345 | IFX_PRINT("HFNUM @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1346 | addr=&_core_if->host_global_regs->hptxsts; |
| 1347 | IFX_PRINT("HPTXSTS @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1348 | addr=&_core_if->host_global_regs->haint; |
| 1349 | IFX_PRINT("HAINT @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1350 | addr=&_core_if->host_global_regs->haintmsk; |
| 1351 | IFX_PRINT("HAINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1352 | addr= _core_if->hprt0; |
| 1353 | IFX_PRINT("HPRT0 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1354 | |
| 1355 | for (i=0; i<MAX_EPS_CHANNELS; i++) |
| 1356 | { |
| 1357 | IFX_PRINT("Host Channel %d Specific Registers\n", i); |
| 1358 | addr=&_core_if->hc_regs[i]->hcchar; |
| 1359 | IFX_PRINT("HCCHAR @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1360 | addr=&_core_if->hc_regs[i]->hcsplt; |
| 1361 | IFX_PRINT("HCSPLT @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1362 | addr=&_core_if->hc_regs[i]->hcint; |
| 1363 | IFX_PRINT("HCINT @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1364 | addr=&_core_if->hc_regs[i]->hcintmsk; |
| 1365 | IFX_PRINT("HCINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1366 | addr=&_core_if->hc_regs[i]->hctsiz; |
| 1367 | IFX_PRINT("HCTSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1368 | addr=&_core_if->hc_regs[i]->hcdma; |
| 1369 | IFX_PRINT("HCDMA @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1370 | } |
| 1371 | #endif //__IS_HOST__ |
| 1372 | |
| 1373 | #ifdef __IS_DEVICE__ |
| 1374 | IFX_PRINT("Device Global Registers\n"); |
| 1375 | addr=&_core_if->dev_global_regs->dcfg; |
| 1376 | IFX_PRINT("DCFG @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1377 | addr=&_core_if->dev_global_regs->dctl; |
| 1378 | IFX_PRINT("DCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1379 | addr=&_core_if->dev_global_regs->dsts; |
| 1380 | IFX_PRINT("DSTS @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1381 | addr=&_core_if->dev_global_regs->diepmsk; |
| 1382 | IFX_PRINT("DIEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1383 | addr=&_core_if->dev_global_regs->doepmsk; |
| 1384 | IFX_PRINT("DOEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1385 | addr=&_core_if->dev_global_regs->daintmsk; |
| 1386 | IFX_PRINT("DAINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1387 | addr=&_core_if->dev_global_regs->daint; |
| 1388 | IFX_PRINT("DAINT @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1389 | addr=&_core_if->dev_global_regs->dvbusdis; |
| 1390 | IFX_PRINT("DVBUSID @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1391 | addr=&_core_if->dev_global_regs->dvbuspulse; |
| 1392 | IFX_PRINT("DVBUSPULSE @0x%08X : 0x%08X\n", (uint32_t)addr,ifxusb_rreg(addr)); |
| 1393 | |
| 1394 | addr=&_core_if->dev_global_regs->dtknqr1; |
| 1395 | IFX_PRINT("DTKNQR1 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); |
| 1396 | if (_core_if->hwcfg2.b.dev_token_q_depth > 6) { |
| 1397 | addr=&_core_if->dev_global_regs->dtknqr2; |
| 1398 | IFX_PRINT("DTKNQR2 @0x%08X : 0x%08X\n", (uint32_t)addr,ifxusb_rreg(addr)); |
| 1399 | } |
| 1400 | |
| 1401 | if (_core_if->hwcfg2.b.dev_token_q_depth > 14) |
| 1402 | { |
| 1403 | addr=&_core_if->dev_global_regs->dtknqr3_dthrctl; |
| 1404 | IFX_PRINT("DTKNQR3_DTHRCTL @0x%08X : 0x%08X\n", (uint32_t)addr, ifxusb_rreg(addr)); |
| 1405 | } |
| 1406 | |
| 1407 | if (_core_if->hwcfg2.b.dev_token_q_depth > 22) |
| 1408 | { |
| 1409 | addr=&_core_if->dev_global_regs->dtknqr4_fifoemptymsk; |
| 1410 | IFX_PRINT("DTKNQR4 @0x%08X : 0x%08X\n", (uint32_t)addr, ifxusb_rreg(addr)); |
| 1411 | } |
| 1412 | |
| 1413 | //for (i=0; i<= MAX_EPS_CHANNELS; i++) |
| 1414 | //for (i=0; i<= 10; i++) |
| 1415 | for (i=0; i<= 3; i++) |
| 1416 | { |
| 1417 | IFX_PRINT("Device EP %d Registers\n", i); |
| 1418 | addri=&_core_if->in_ep_regs[i]->diepctl;addro=&_core_if->out_ep_regs[i]->doepctl; |
| 1419 | IFX_PRINT("DEPCTL I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro)); |
| 1420 | addro=&_core_if->out_ep_regs[i]->doepfn; |
| 1421 | IFX_PRINT("DEPFN I: O: 0x%08X\n",ifxusb_rreg(addro)); |
| 1422 | addri=&_core_if->in_ep_regs[i]->diepint;addro=&_core_if->out_ep_regs[i]->doepint; |
| 1423 | IFX_PRINT("DEPINT I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro)); |
| 1424 | addri=&_core_if->in_ep_regs[i]->dieptsiz;addro=&_core_if->out_ep_regs[i]->doeptsiz; |
| 1425 | IFX_PRINT("DETSIZ I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro)); |
| 1426 | addri=&_core_if->in_ep_regs[i]->diepdma;addro=&_core_if->out_ep_regs[i]->doepdma; |
| 1427 | IFX_PRINT("DEPDMA I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro)); |
| 1428 | addri=&_core_if->in_ep_regs[i]->dtxfsts; |
| 1429 | IFX_PRINT("DTXFSTS I: 0x%08X\n",ifxusb_rreg(addri) ); |
| 1430 | addri=&_core_if->in_ep_regs[i]->diepdmab;addro=&_core_if->out_ep_regs[i]->doepdmab; |
| 1431 | IFX_PRINT("DEPDMAB I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro)); |
| 1432 | } |
| 1433 | #endif //__IS_DEVICE__ |
| 1434 | #endif //__ENABLE_DUMP__ |
| 1435 | } |
| 1436 | |
| 1437 | void ifxusb_clean_spram(ifxusb_core_if_t *_core_if,uint32_t dwords) |
| 1438 | { |
| 1439 | volatile uint32_t *addr1,*addr2, *start_addr, *end_addr; |
| 1440 | |
| 1441 | if(!dwords) |
| 1442 | return; |
| 1443 | |
| 1444 | start_addr = (uint32_t *)_core_if->data_fifo_dbg; |
| 1445 | |
| 1446 | end_addr = (uint32_t *)_core_if->data_fifo_dbg; |
| 1447 | end_addr += dwords; |
| 1448 | |
| 1449 | IFX_PRINT("Clearning SPRAM: 0x%8X-0x%8X\n", (uint32_t)start_addr,(uint32_t)end_addr); |
| 1450 | for(addr1 = start_addr; addr1 < end_addr; addr1+=4) |
| 1451 | { |
| 1452 | for(addr2 = addr1; addr2 < addr1+4; addr2++) |
| 1453 | *addr2=0x00000000; |
| 1454 | } |
| 1455 | IFX_PRINT("Clearning SPRAM: 0x%8X-0x%8X Done\n", (uint32_t)start_addr,(uint32_t)end_addr); |
| 1456 | return; |
| 1457 | } |
| 1458 | |
| 1459 | |
