| 1 | /***************************************************************************** |
| 2 | ** FILE NAME : ifxusb_plat.h |
| 3 | ** PROJECT : IFX USB sub-system V3 |
| 4 | ** MODULES : IFX USB sub-system Host and Device driver |
| 5 | ** SRC VERSION : 1.0 |
| 6 | ** DATE : 1/Jan/2009 |
| 7 | ** AUTHOR : Chen, Howard |
| 8 | ** DESCRIPTION : This file contains the Platform Specific constants, interfaces |
| 9 | ** (functions and macros). |
| 10 | ** FUNCTIONS : |
| 11 | ** COMPILER : gcc |
| 12 | ** REFERENCE : IFX hardware ref handbook for each plateforms |
| 13 | ** COPYRIGHT : |
| 14 | ** Version Control Section ** |
| 15 | ** $Author$ |
| 16 | ** $Date$ |
| 17 | ** $Revisions$ |
| 18 | ** $Log$ Revision history |
| 19 | *****************************************************************************/ |
| 20 | |
| 21 | |
| 22 | /*! |
| 23 | \defgroup IFXUSB_PLATEFORM_DEFINITION Platform Specific constants, interfaces (functions and macros). |
| 24 | \ingroup IFXUSB_DRIVER_V3 |
| 25 | \brief Maintain plateform specific definitions and macros in this file. |
| 26 | Each plateform has its own definition zone. |
| 27 | */ |
| 28 | |
| 29 | /*! |
| 30 | \defgroup IFXUSB_PLATEFORM_MEM_ADDR Definition of memory address and size and default parameters |
| 31 | \ingroup IFXUSB_PLATEFORM_DEFINITION |
| 32 | */ |
| 33 | |
| 34 | /*! |
| 35 | \defgroup IFXUSB_DBG_ROUTINE Routines for debug message |
| 36 | \ingroup IFXUSB_PLATEFORM_DEFINITION |
| 37 | */ |
| 38 | |
| 39 | |
| 40 | /*! \file ifxusb_plat.h |
| 41 | \ingroup IFXUSB_DRIVER_V3 |
| 42 | \brief This file contains the Platform Specific constants, interfaces (functions and macros). |
| 43 | */ |
| 44 | |
| 45 | #if !defined(__IFXUSB_PLAT_H__) |
| 46 | #define __IFXUSB_PLAT_H__ |
| 47 | |
| 48 | |
| 49 | #include <linux/types.h> |
| 50 | #include <linux/slab.h> |
| 51 | #include <linux/list.h> |
| 52 | #include <linux/delay.h> |
| 53 | #include <asm/io.h> |
| 54 | |
| 55 | |
| 56 | #define IFXUSB_IOMEM_SIZE 0x00001000 |
| 57 | #define IFXUSB_FIFOMEM_SIZE 0x00010000 |
| 58 | #define IFXUSB_FIFODBG_SIZE 0x00020000 |
| 59 | |
| 60 | |
| 61 | |
| 62 | /*! |
| 63 | \addtogroup IFXUSB_PLATEFORM_MEM_ADDR |
| 64 | */ |
| 65 | /*@{*/ |
| 66 | #if defined(__UEIP__) |
| 67 | #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 68 | // #define IFXUSB_IRQ 54 |
| 69 | #define IFXUSB_IOMEM_BASE 0x1e101000 |
| 70 | #define IFXUSB_FIFOMEM_BASE 0x1e120000 |
| 71 | #define IFXUSB_FIFODBG_BASE 0x1e140000 |
| 72 | // #define IFXUSB_OC_IRQ 151 |
| 73 | |
| 74 | #ifndef DANUBE_RCU_BASE_ADDR |
| 75 | #define DANUBE_RCU_BASE_ADDR (0xBF203000) |
| 76 | #endif |
| 77 | |
| 78 | #ifndef DANUBE_CGU |
| 79 | #define DANUBE_CGU (0xBF103000) |
| 80 | #endif |
| 81 | #ifndef DANUBE_CGU_IFCCR |
| 82 | #define DANUBE_CGU_IFCCR ((volatile unsigned long *)(DANUBE_CGU+ 0x0018)) |
| 83 | #endif |
| 84 | #ifndef DANUBE_PMU |
| 85 | #define DANUBE_PMU (KSEG1+0x1F102000) |
| 86 | #endif |
| 87 | #ifndef DANUBE_PMU_PWDCR |
| 88 | #define DANUBE_PMU_PWDCR ((volatile unsigned long *)(DANUBE_PMU+0x001C)) |
| 89 | #endif |
| 90 | |
| 91 | #ifndef DANUBE_GPIO_P0_OUT |
| 92 | #define DANUBE_GPIO_P0_OUT (0xBF103000+0x10) |
| 93 | #define DANUBE_GPIO_P0_DIR (0xBF103000+0x18) |
| 94 | #define DANUBE_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) |
| 95 | #define DANUBE_GPIO_P0_ALTSEL1 (0xBF103000+0x20) |
| 96 | #define DANUBE_GPIO_P0_OD (0xBF103000+0x24) |
| 97 | #define DANUBE_GPIO_P0_PUDSEL (0xBF103000+0x2C) |
| 98 | #define DANUBE_GPIO_P0_PUDEN (0xBF103000+0x30) |
| 99 | #define DANUBE_GPIO_P1_OUT (0xBF103000+0x40) |
| 100 | #define DANUBE_GPIO_P1_DIR (0xBF103000+0x48) |
| 101 | #define DANUBE_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) |
| 102 | #define DANUBE_GPIO_P1_ALTSEL1 (0xBF103000+0x50) |
| 103 | #define DANUBE_GPIO_P1_OD (0xBF103000+0x54) |
| 104 | #define DANUBE_GPIO_P1_PUDSEL (0xBF103000+0x5C) |
| 105 | #define DANUBE_GPIO_P1_PUDEN (0xBF103000+0x60) |
| 106 | #endif |
| 107 | |
| 108 | #define DANUBE_RCU_USBCFG ((volatile unsigned long *)(DANUBE_RCU_BASE_ADDR + 0x18)) |
| 109 | #define DANUBE_RCU_RESET ((volatile unsigned long *)(DANUBE_RCU_BASE_ADDR + 0x10)) |
| 110 | #define DANUBE_USBCFG_HDSEL_BIT 11 // 0:host, 1:device |
| 111 | #define DANUBE_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end |
| 112 | #define DANUBE_USBCFG_SLV_END_BIT 9 // 0:little_end, 1:big_end |
| 113 | |
| 114 | #define default_param_dma_burst_size 4 |
| 115 | |
| 116 | #define default_param_speed IFXUSB_PARAM_SPEED_HIGH |
| 117 | |
| 118 | #define default_param_max_transfer_size -1 //(Max, hwcfg) |
| 119 | #define default_param_max_packet_count -1 //(Max, hwcfg) |
| 120 | #define default_param_phy_utmi_width 16 |
| 121 | |
| 122 | #define default_param_turn_around_time_hs 4 |
| 123 | #define default_param_turn_around_time_fs 4 |
| 124 | #define default_param_timeout_cal_hs -1 //(NoChange) |
| 125 | #define default_param_timeout_cal_fs -1 //(NoChange) |
| 126 | |
| 127 | #define default_param_data_fifo_size -1 //(Max, hwcfg) |
| 128 | |
| 129 | #ifdef __IS_HOST__ |
| 130 | #define default_param_host_channels -1 //(Max, hwcfg) |
| 131 | #define default_param_rx_fifo_size 640 |
| 132 | #define default_param_nperio_tx_fifo_size 640 |
| 133 | #define default_param_perio_tx_fifo_size 768 |
| 134 | #endif //__IS_HOST__ |
| 135 | |
| 136 | #ifdef __IS_DEVICE__ |
| 137 | #ifdef __DED_INTR__ |
| 138 | #define default_param_rx_fifo_size 1024 |
| 139 | #define default_param_nperio_tx_fifo_size 1016 |
| 140 | #define default_param_perio_tx_fifo_size_01 8 |
| 141 | #else |
| 142 | #define default_param_rx_fifo_size 1024 |
| 143 | #define default_param_nperio_tx_fifo_size 1024 |
| 144 | #define default_param_perio_tx_fifo_size_01 0 |
| 145 | #endif |
| 146 | #define default_param_perio_tx_fifo_size_02 0 |
| 147 | #define default_param_perio_tx_fifo_size_03 0 |
| 148 | #define default_param_perio_tx_fifo_size_04 0 |
| 149 | #define default_param_perio_tx_fifo_size_05 0 |
| 150 | #define default_param_perio_tx_fifo_size_06 0 |
| 151 | #define default_param_perio_tx_fifo_size_07 0 |
| 152 | #define default_param_perio_tx_fifo_size_08 0 |
| 153 | #define default_param_perio_tx_fifo_size_09 0 |
| 154 | #define default_param_perio_tx_fifo_size_10 0 |
| 155 | #define default_param_perio_tx_fifo_size_11 0 |
| 156 | #define default_param_perio_tx_fifo_size_12 0 |
| 157 | #define default_param_perio_tx_fifo_size_13 0 |
| 158 | #define default_param_perio_tx_fifo_size_14 0 |
| 159 | #define default_param_perio_tx_fifo_size_15 0 |
| 160 | #endif //__IS_DEVICE__ |
| 161 | |
| 162 | #elif defined(__IS_AMAZON_SE__) |
| 163 | //#include <asm/amazon_se/amazon_se.h> |
| 164 | //#include <asm/amazon_se/irq.h> |
| 165 | |
| 166 | // #define IFXUSB_IRQ 31 |
| 167 | #define IFXUSB_IOMEM_BASE 0x1e101000 |
| 168 | #define IFXUSB_FIFOMEM_BASE 0x1e120000 |
| 169 | #define IFXUSB_FIFODBG_BASE 0x1e140000 |
| 170 | // #define IFXUSB_OC_IRQ 20 |
| 171 | |
| 172 | #ifndef AMAZON_SE_RCU_BASE_ADDR |
| 173 | #define AMAZON_SE_RCU_BASE_ADDR (0xBF203000) |
| 174 | #endif |
| 175 | #define AMAZON_SE_RCU_USBCFG ((volatile unsigned long *)(AMAZON_SE_RCU_BASE_ADDR + 0x18)) |
| 176 | #define AMAZON_SE_RCU_RESET ((volatile unsigned long *)(AMAZON_SE_RCU_BASE_ADDR + 0x10)) |
| 177 | #define AMAZON_SE_USBCFG_HDSEL_BIT 11 // 0:host, 1:device |
| 178 | #define AMAZON_SE_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end |
| 179 | #define AMAZON_SE_USBCFG_SLV_END_BIT 9 // 0:little_end, 1:big_end |
| 180 | |
| 181 | #ifndef AMAZON_SE_GPIO_P0_OUT |
| 182 | #define AMAZON_SE_GPIO_P0_OUT (0xBF103000+0x10) |
| 183 | #define AMAZON_SE_GPIO_P0_DIR (0xBF103000+0x18) |
| 184 | #define AMAZON_SE_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) |
| 185 | #define AMAZON_SE_GPIO_P0_ALTSEL1 (0xBF103000+0x20) |
| 186 | #define AMAZON_SE_GPIO_P0_OD (0xBF103000+0x24) |
| 187 | #define AMAZON_SE_GPIO_P0_PUDSEL (0xBF103000+0x2C) |
| 188 | #define AMAZON_SE_GPIO_P0_PUDEN (0xBF103000+0x30) |
| 189 | #define AMAZON_SE_GPIO_P1_OUT (0xBF103000+0x40) |
| 190 | #define AMAZON_SE_GPIO_P1_DIR (0xBF103000+0x48) |
| 191 | #define AMAZON_SE_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) |
| 192 | #define AMAZON_SE_GPIO_P1_ALTSEL1 (0xBF103000+0x50) |
| 193 | #define AMAZON_SE_GPIO_P1_OD (0xBF103000+0x54) |
| 194 | #define AMAZON_SE_GPIO_P1_PUDSEL (0xBF103000+0x5C) |
| 195 | #define AMAZON_SE_GPIO_P1_PUDEN (0xBF103000+0x60) |
| 196 | #endif |
| 197 | |
| 198 | #ifndef AMAZON_SE_CGU |
| 199 | #define AMAZON_SE_CGU (0xBF103000) |
| 200 | #endif |
| 201 | #ifndef AMAZON_SE_CGU_IFCCR |
| 202 | #define AMAZON_SE_CGU_IFCCR ((volatile unsigned long *)(AMAZON_SE_CGU+ 0x0018)) |
| 203 | #endif |
| 204 | #ifndef AMAZON_SE_PMU |
| 205 | #define AMAZON_SE_PMU (KSEG1+0x1F102000) |
| 206 | #endif |
| 207 | #ifndef AMAZON_SE_PMU_PWDCR |
| 208 | #define AMAZON_SE_PMU_PWDCR ((volatile unsigned long *)(AMAZON_SE_PMU+0x001C)) |
| 209 | #endif |
| 210 | |
| 211 | #define default_param_dma_burst_size 4 |
| 212 | |
| 213 | #define default_param_speed IFXUSB_PARAM_SPEED_HIGH |
| 214 | |
| 215 | #define default_param_max_transfer_size -1 //(Max, hwcfg) |
| 216 | #define default_param_max_packet_count -1 //(Max, hwcfg) |
| 217 | #define default_param_phy_utmi_width 16 |
| 218 | |
| 219 | #define default_param_turn_around_time_hs 4 //(NoChange) |
| 220 | #define default_param_turn_around_time_fs 4 //(NoChange) |
| 221 | #define default_param_timeout_cal_hs -1 //(NoChange) |
| 222 | #define default_param_timeout_cal_fs -1 //(NoChange) |
| 223 | |
| 224 | #define default_param_data_fifo_size -1 //(Max, hwcfg) |
| 225 | |
| 226 | #ifdef __IS_HOST__ |
| 227 | #define default_param_host_channels -1 //(Max, hwcfg) |
| 228 | #define default_param_rx_fifo_size 240 |
| 229 | #define default_param_nperio_tx_fifo_size 240 |
| 230 | #define default_param_perio_tx_fifo_size 32 |
| 231 | #endif //__IS_HOST__ |
| 232 | #ifdef __IS_DEVICE__ |
| 233 | #ifdef __DED_INTR__ |
| 234 | #define default_param_rx_fifo_size 256 |
| 235 | #define default_param_nperio_tx_fifo_size 248 |
| 236 | #define default_param_perio_tx_fifo_size_01 8 |
| 237 | #else |
| 238 | #define default_param_rx_fifo_size 256 |
| 239 | #define default_param_nperio_tx_fifo_size 256 |
| 240 | #define default_param_perio_tx_fifo_size_01 0 |
| 241 | #endif |
| 242 | #define default_param_perio_tx_fifo_size_02 0 |
| 243 | #define default_param_perio_tx_fifo_size_03 0 |
| 244 | #define default_param_perio_tx_fifo_size_04 0 |
| 245 | #define default_param_perio_tx_fifo_size_05 0 |
| 246 | #define default_param_perio_tx_fifo_size_06 0 |
| 247 | #define default_param_perio_tx_fifo_size_07 0 |
| 248 | #define default_param_perio_tx_fifo_size_08 0 |
| 249 | #define default_param_perio_tx_fifo_size_09 0 |
| 250 | #define default_param_perio_tx_fifo_size_10 0 |
| 251 | #define default_param_perio_tx_fifo_size_11 0 |
| 252 | #define default_param_perio_tx_fifo_size_12 0 |
| 253 | #define default_param_perio_tx_fifo_size_13 0 |
| 254 | #define default_param_perio_tx_fifo_size_14 0 |
| 255 | #define default_param_perio_tx_fifo_size_15 0 |
| 256 | #endif //__IS_DEVICE__ |
| 257 | |
| 258 | #elif defined(__IS_AR9__) |
| 259 | // #define IFXUSB1_IRQ 54 |
| 260 | #define IFXUSB1_IOMEM_BASE 0x1E101000 |
| 261 | #define IFXUSB1_FIFOMEM_BASE 0x1E120000 |
| 262 | #define IFXUSB1_FIFODBG_BASE 0x1E140000 |
| 263 | |
| 264 | // #define IFXUSB2_IRQ 83 |
| 265 | #define IFXUSB2_IOMEM_BASE 0x1E106000 |
| 266 | #define IFXUSB2_FIFOMEM_BASE 0x1E1E0000 |
| 267 | #define IFXUSB2_FIFODBG_BASE 0x1E1C0000 |
| 268 | |
| 269 | // #define IFXUSB_OC_IRQ 60 |
| 270 | |
| 271 | #ifndef AR9_RCU_BASE_ADDR |
| 272 | #define AR9_RCU_BASE_ADDR (0xBF203000) |
| 273 | #endif |
| 274 | |
| 275 | #ifndef AR9_CGU |
| 276 | #define AR9_CGU (0xBF103000) |
| 277 | #endif |
| 278 | #ifndef AR9_CGU_IFCCR |
| 279 | #define AR9_CGU_IFCCR ((volatile unsigned long *)(AR9_CGU+ 0x0018)) |
| 280 | #endif |
| 281 | |
| 282 | #ifndef AR9_PMU |
| 283 | #define AR9_PMU (KSEG1+0x1F102000) |
| 284 | #endif |
| 285 | #ifndef AR9_PMU_PWDCR |
| 286 | #define AR9_PMU_PWDCR ((volatile unsigned long *)(AR9_PMU+0x001C)) |
| 287 | #endif |
| 288 | |
| 289 | #ifndef AR9_GPIO_P0_OUT |
| 290 | #define AR9_GPIO_P0_OUT (0xBF103000+0x10) |
| 291 | #define AR9_GPIO_P0_DIR (0xBF103000+0x18) |
| 292 | #define AR9_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) |
| 293 | #define AR9_GPIO_P0_ALTSEL1 (0xBF103000+0x20) |
| 294 | #define AR9_GPIO_P0_OD (0xBF103000+0x24) |
| 295 | #define AR9_GPIO_P0_PUDSEL (0xBF103000+0x2C) |
| 296 | #define AR9_GPIO_P0_PUDEN (0xBF103000+0x30) |
| 297 | #define AR9_GPIO_P1_OUT (0xBF103000+0x40) |
| 298 | #define AR9_GPIO_P1_DIR (0xBF103000+0x48) |
| 299 | #define AR9_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) |
| 300 | #define AR9_GPIO_P1_ALTSEL1 (0xBF103000+0x50) |
| 301 | #define AR9_GPIO_P1_OD (0xBF103000+0x54) |
| 302 | #define AR9_GPIO_P1_PUDSEL (0xBF103000+0x5C) |
| 303 | #define AR9_GPIO_P1_PUDEN (0xBF103000+0x60) |
| 304 | #endif |
| 305 | |
| 306 | #define AR9_RCU_USB1CFG ((volatile unsigned long *)(AR9_RCU_BASE_ADDR + 0x18)) |
| 307 | #define AR9_RCU_USB2CFG ((volatile unsigned long *)(AR9_RCU_BASE_ADDR + 0x34)) |
| 308 | #define AR9_RCU_USBRESET ((volatile unsigned long *)(AR9_RCU_BASE_ADDR + 0x10)) |
| 309 | #define AR9_USBCFG_ARB 7 // |
| 310 | #define AR9_USBCFG_HDSEL_BIT 11 // 0:host, 1:device |
| 311 | #define AR9_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end |
| 312 | #define AR9_USBCFG_SLV_END_BIT 17 // 0:little_end, 1:big_end |
| 313 | |
| 314 | #define default_param_dma_burst_size 4 |
| 315 | |
| 316 | #define default_param_speed IFXUSB_PARAM_SPEED_HIGH |
| 317 | |
| 318 | #define default_param_max_transfer_size -1 //(Max, hwcfg) |
| 319 | #define default_param_max_packet_count -1 //(Max, hwcfg) |
| 320 | #define default_param_phy_utmi_width 16 |
| 321 | |
| 322 | #define default_param_turn_around_time_hs 4 //(NoChange) |
| 323 | #define default_param_turn_around_time_fs 4 //(NoChange) |
| 324 | #define default_param_timeout_cal_hs -1 //(NoChange) |
| 325 | #define default_param_timeout_cal_fs -1 //(NoChange) |
| 326 | |
| 327 | #define default_param_data_fifo_size -1 //(Max, hwcfg) |
| 328 | |
| 329 | #ifdef __IS_HOST__ |
| 330 | #define default_param_host_channels -1 //(Max, hwcfg) |
| 331 | #define default_param_rx_fifo_size 240 |
| 332 | #define default_param_nperio_tx_fifo_size 240 |
| 333 | #define default_param_perio_tx_fifo_size 32 |
| 334 | #endif //__IS_HOST__ |
| 335 | #ifdef __IS_DEVICE__ |
| 336 | #ifdef __DED_INTR__ |
| 337 | #define default_param_rx_fifo_size 256 |
| 338 | // #define default_param_nperio_tx_fifo_size 248 |
| 339 | // #define default_param_perio_tx_fifo_size_01 8 |
| 340 | #define default_param_nperio_tx_fifo_size 252 |
| 341 | #define default_param_perio_tx_fifo_size_01 4 |
| 342 | #else |
| 343 | #define default_param_rx_fifo_size 256 |
| 344 | #define default_param_nperio_tx_fifo_size 256 |
| 345 | #define default_param_perio_tx_fifo_size_01 0 |
| 346 | #endif |
| 347 | #define default_param_perio_tx_fifo_size_02 0 |
| 348 | #define default_param_perio_tx_fifo_size_03 0 |
| 349 | #define default_param_perio_tx_fifo_size_04 0 |
| 350 | #define default_param_perio_tx_fifo_size_05 0 |
| 351 | #define default_param_perio_tx_fifo_size_06 0 |
| 352 | #define default_param_perio_tx_fifo_size_07 0 |
| 353 | #define default_param_perio_tx_fifo_size_08 0 |
| 354 | #define default_param_perio_tx_fifo_size_09 0 |
| 355 | #define default_param_perio_tx_fifo_size_10 0 |
| 356 | #define default_param_perio_tx_fifo_size_11 0 |
| 357 | #define default_param_perio_tx_fifo_size_12 0 |
| 358 | #define default_param_perio_tx_fifo_size_13 0 |
| 359 | #define default_param_perio_tx_fifo_size_14 0 |
| 360 | #define default_param_perio_tx_fifo_size_15 0 |
| 361 | #endif //__IS_DEVICE__ |
| 362 | |
| 363 | #elif defined(__IS_VR9__) |
| 364 | // #define IFXUSB1_IRQ 54 |
| 365 | #define IFXUSB1_IOMEM_BASE 0x1E101000 |
| 366 | #define IFXUSB1_FIFOMEM_BASE 0x1E120000 |
| 367 | #define IFXUSB1_FIFODBG_BASE 0x1E140000 |
| 368 | |
| 369 | // #define IFXUSB2_IRQ 83 |
| 370 | #define IFXUSB2_IOMEM_BASE 0x1E106000 |
| 371 | #define IFXUSB2_FIFOMEM_BASE 0x1E1E0000 |
| 372 | #define IFXUSB2_FIFODBG_BASE 0x1E1C0000 |
| 373 | // #define IFXUSB_OC_IRQ 60 |
| 374 | |
| 375 | #ifndef VR9_RCU_BASE_ADDR |
| 376 | #define VR9_RCU_BASE_ADDR (0xBF203000) |
| 377 | #endif |
| 378 | |
| 379 | #ifndef VR9_CGU |
| 380 | #define VR9_CGU (0xBF103000) |
| 381 | #endif |
| 382 | #ifndef VR9_CGU_IFCCR |
| 383 | #define VR9_CGU_IFCCR ((volatile unsigned long *)(VR9_CGU+ 0x0018)) |
| 384 | #endif |
| 385 | |
| 386 | #ifndef VR9_PMU |
| 387 | #define VR9_PMU (KSEG1+0x1F102000) |
| 388 | #endif |
| 389 | #ifndef VR9_PMU_PWDCR |
| 390 | #define VR9_PMU_PWDCR ((volatile unsigned long *)(VR9_PMU+0x001C)) |
| 391 | #endif |
| 392 | |
| 393 | #ifndef VR9_GPIO_P0_OUT |
| 394 | #define VR9_GPIO_P0_OUT (0xBF103000+0x10) |
| 395 | #define VR9_GPIO_P0_DIR (0xBF103000+0x18) |
| 396 | #define VR9_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) |
| 397 | #define VR9_GPIO_P0_ALTSEL1 (0xBF103000+0x20) |
| 398 | #define VR9_GPIO_P0_OD (0xBF103000+0x24) |
| 399 | #define VR9_GPIO_P0_PUDSEL (0xBF103000+0x2C) |
| 400 | #define VR9_GPIO_P0_PUDEN (0xBF103000+0x30) |
| 401 | #define VR9_GPIO_P1_OUT (0xBF103000+0x40) |
| 402 | #define VR9_GPIO_P1_DIR (0xBF103000+0x48) |
| 403 | #define VR9_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) |
| 404 | #define VR9_GPIO_P1_ALTSEL1 (0xBF103000+0x50) |
| 405 | #define VR9_GPIO_P1_OD (0xBF103000+0x54) |
| 406 | #define VR9_GPIO_P1_PUDSEL (0xBF103000+0x5C) |
| 407 | #define VR9_GPIO_P1_PUDEN (0xBF103000+0x60) |
| 408 | #endif |
| 409 | |
| 410 | #define VR9_RCU_USB1CFG ((volatile unsigned long *)(VR9_RCU_BASE_ADDR + 0x18)) |
| 411 | #define VR9_RCU_USB2CFG ((volatile unsigned long *)(VR9_RCU_BASE_ADDR + 0x34)) |
| 412 | #define VR9_RCU_USB_ANA_CFG1A ((volatile unsigned long *)(AR9_RCU_BASE_ADDR + 0x38)) |
| 413 | #define VR9_RCU_USB_ANA_CFG1B ((volatile unsigned long *)(AR9_RCU_BASE_ADDR + 0x3C)) |
| 414 | #define VR9_RCU_USBRESET ((volatile unsigned long *)(VR9_RCU_BASE_ADDR + 0x10)) |
| 415 | #define VR9_RCU_USBRESET2 ((volatile unsigned long *)(VR9_RCU_BASE_ADDR + 0x48)) |
| 416 | #define VR9_USBCFG_ARB 7 // |
| 417 | #define VR9_USBCFG_HDSEL_BIT 11 // 0:host, 1:device |
| 418 | #define VR9_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end |
| 419 | #define VR9_USBCFG_SLV_END_BIT 9 // 0:little_end, 1:big_end |
| 420 | |
| 421 | /*== AVM/BC 20101220 Workaround VR9 DMA burst size == |
| 422 | * Using 2 Devices in diferent ports cause a general USB Host Error. |
| 423 | * Workaround found in UGW4.3 |
| 424 | */ |
| 425 | // #define default_param_dma_burst_size 4 //(ALL) |
| 426 | //WA for AHB |
| 427 | #define default_param_dma_burst_size 0 //(ALL) |
| 428 | |
| 429 | #define default_param_speed IFXUSB_PARAM_SPEED_HIGH |
| 430 | |
| 431 | #define default_param_max_transfer_size -1 //(Max, hwcfg) |
| 432 | #define default_param_max_packet_count -1 //(Max, hwcfg) |
| 433 | #define default_param_phy_utmi_width 16 |
| 434 | |
| 435 | #define default_param_turn_around_time_hs 6 //(NoChange) snpsid >= 0x4f54260a |
| 436 | #define default_param_turn_around_time_fs 6 //(NoChange) snpsid >= 0x4f54260a |
| 437 | #define default_param_timeout_cal_hs -1 //(NoChange) |
| 438 | #define default_param_timeout_cal_fs -1 //(NoChange) |
| 439 | |
| 440 | #define default_param_data_fifo_size -1 //(Max, hwcfg) |
| 441 | |
| 442 | #ifdef __IS_HOST__ |
| 443 | #define default_param_host_channels -1 //(Max, hwcfg) |
| 444 | #define default_param_rx_fifo_size 240 |
| 445 | #define default_param_nperio_tx_fifo_size 240 |
| 446 | #define default_param_perio_tx_fifo_size 32 |
| 447 | #endif //__IS_HOST__ |
| 448 | #ifdef __IS_DEVICE__ |
| 449 | #if 0 |
| 450 | #define default_param_rx_fifo_size 256 |
| 451 | #define default_param_tx_fifo_size_00 -1 |
| 452 | #define default_param_tx_fifo_size_01 -1 |
| 453 | #define default_param_tx_fifo_size_02 -1 |
| 454 | #else |
| 455 | #define default_param_rx_fifo_size 256 |
| 456 | #define default_param_tx_fifo_size_00 32 |
| 457 | #define default_param_tx_fifo_size_01 200 |
| 458 | #define default_param_tx_fifo_size_02 8 |
| 459 | #endif |
| 460 | #define default_param_tx_fifo_size_03 -1 |
| 461 | #define default_param_tx_fifo_size_04 -1 |
| 462 | #define default_param_tx_fifo_size_05 -1 |
| 463 | #define default_param_tx_fifo_size_06 -1 |
| 464 | #define default_param_tx_fifo_size_07 -1 |
| 465 | #define default_param_tx_fifo_size_08 -1 |
| 466 | #define default_param_tx_fifo_size_09 -1 |
| 467 | #define default_param_tx_fifo_size_10 -1 |
| 468 | #define default_param_tx_fifo_size_11 -1 |
| 469 | #define default_param_tx_fifo_size_12 -1 |
| 470 | #define default_param_tx_fifo_size_13 -1 |
| 471 | #define default_param_tx_fifo_size_14 -1 |
| 472 | #define default_param_tx_fifo_size_15 -1 |
| 473 | #define default_param_dma_unalgned_tx -1 |
| 474 | #define default_param_dma_unalgned_rx -1 |
| 475 | #define default_param_thr_ctl -1 |
| 476 | #define default_param_tx_thr_length -1 |
| 477 | #define default_param_rx_thr_length -1 |
| 478 | #endif //__IS_DEVICE__ |
| 479 | #else // __IS_VR9__ |
| 480 | #error "Please choose one platform!!" |
| 481 | #endif // __IS_VR9__ |
| 482 | |
| 483 | #else //UEIP |
| 484 | #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) |
| 485 | // #define IFXUSB_IRQ 54 |
| 486 | #define IFXUSB_IOMEM_BASE 0x1e101000 |
| 487 | #define IFXUSB_FIFOMEM_BASE 0x1e120000 |
| 488 | #define IFXUSB_FIFODBG_BASE 0x1e140000 |
| 489 | // #define IFXUSB_OC_IRQ 151 |
| 490 | |
| 491 | |
| 492 | #ifndef DANUBE_RCU_BASE_ADDR |
| 493 | #define DANUBE_RCU_BASE_ADDR (0xBF203000) |
| 494 | #endif |
| 495 | |
| 496 | #ifndef DANUBE_CGU |
| 497 | #define DANUBE_CGU (0xBF103000) |
| 498 | #endif |
| 499 | #ifndef DANUBE_CGU_IFCCR |
| 500 | #define DANUBE_CGU_IFCCR ((volatile unsigned long *)(DANUBE_CGU+ 0x0018)) |
| 501 | #endif |
| 502 | #ifndef DANUBE_PMU |
| 503 | #define DANUBE_PMU (KSEG1+0x1F102000) |
| 504 | #endif |
| 505 | #ifndef DANUBE_PMU_PWDCR |
| 506 | #define DANUBE_PMU_PWDCR ((volatile unsigned long *)(DANUBE_PMU+0x001C)) |
| 507 | #endif |
| 508 | |
| 509 | #ifndef DANUBE_GPIO_P0_OUT |
| 510 | #define DANUBE_GPIO_P0_OUT (0xBF103000+0x10) |
| 511 | #define DANUBE_GPIO_P0_DIR (0xBF103000+0x18) |
| 512 | #define DANUBE_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) |
| 513 | #define DANUBE_GPIO_P0_ALTSEL1 (0xBF103000+0x20) |
| 514 | #define DANUBE_GPIO_P0_OD (0xBF103000+0x24) |
| 515 | #define DANUBE_GPIO_P0_PUDSEL (0xBF103000+0x2C) |
| 516 | #define DANUBE_GPIO_P0_PUDEN (0xBF103000+0x30) |
| 517 | #define DANUBE_GPIO_P1_OUT (0xBF103000+0x40) |
| 518 | #define DANUBE_GPIO_P1_DIR (0xBF103000+0x48) |
| 519 | #define DANUBE_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) |
| 520 | #define DANUBE_GPIO_P1_ALTSEL1 (0xBF103000+0x50) |
| 521 | #define DANUBE_GPIO_P1_OD (0xBF103000+0x54) |
| 522 | #define DANUBE_GPIO_P1_PUDSEL (0xBF103000+0x5C) |
| 523 | #define DANUBE_GPIO_P1_PUDEN (0xBF103000+0x60) |
| 524 | #endif |
| 525 | |
| 526 | |
| 527 | #define DANUBE_RCU_USBCFG ((volatile unsigned long *)(DANUBE_RCU_BASE_ADDR + 0x18)) |
| 528 | #define DANUBE_RCU_RESET ((volatile unsigned long *)(DANUBE_RCU_BASE_ADDR + 0x10)) |
| 529 | #define DANUBE_USBCFG_HDSEL_BIT 11 // 0:host, 1:device |
| 530 | #define DANUBE_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end |
| 531 | #define DANUBE_USBCFG_SLV_END_BIT 9 // 0:little_end, 1:big_end |
| 532 | |
| 533 | #define default_param_dma_burst_size 4 |
| 534 | |
| 535 | #define default_param_speed IFXUSB_PARAM_SPEED_HIGH |
| 536 | |
| 537 | #define default_param_max_transfer_size -1 //(Max, hwcfg) |
| 538 | #define default_param_max_packet_count -1 //(Max, hwcfg) |
| 539 | #define default_param_phy_utmi_width 16 |
| 540 | |
| 541 | #define default_param_turn_around_time_hs 4 //(NoChange) |
| 542 | #define default_param_turn_around_time_fs 4 //(NoChange) |
| 543 | #define default_param_timeout_cal_hs -1 //(NoChange) |
| 544 | #define default_param_timeout_cal_fs -1 //(NoChange) |
| 545 | |
| 546 | #define default_param_data_fifo_size -1 //(Max, hwcfg) |
| 547 | #ifdef __IS_HOST__ |
| 548 | #define default_param_host_channels -1 //(Max, hwcfg) |
| 549 | #define default_param_rx_fifo_size 640 |
| 550 | #define default_param_nperio_tx_fifo_size 640 |
| 551 | #define default_param_perio_tx_fifo_size 768 |
| 552 | #endif //__IS_HOST__ |
| 553 | |
| 554 | #ifdef __IS_DEVICE__ |
| 555 | #ifdef __DED_INTR__ |
| 556 | #define default_param_rx_fifo_size 1024 |
| 557 | #define default_param_nperio_tx_fifo_size 1016 |
| 558 | #define default_param_perio_tx_fifo_size_01 8 |
| 559 | #else |
| 560 | #define default_param_rx_fifo_size 1024 |
| 561 | #define default_param_nperio_tx_fifo_size 1024 |
| 562 | #define default_param_perio_tx_fifo_size_01 0 |
| 563 | #endif |
| 564 | #define default_param_perio_tx_fifo_size_02 0 |
| 565 | #define default_param_perio_tx_fifo_size_03 0 |
| 566 | #define default_param_perio_tx_fifo_size_04 0 |
| 567 | #define default_param_perio_tx_fifo_size_05 0 |
| 568 | #define default_param_perio_tx_fifo_size_06 0 |
| 569 | #define default_param_perio_tx_fifo_size_07 0 |
| 570 | #define default_param_perio_tx_fifo_size_08 0 |
| 571 | #define default_param_perio_tx_fifo_size_09 0 |
| 572 | #define default_param_perio_tx_fifo_size_10 0 |
| 573 | #define default_param_perio_tx_fifo_size_11 0 |
| 574 | #define default_param_perio_tx_fifo_size_12 0 |
| 575 | #define default_param_perio_tx_fifo_size_13 0 |
| 576 | #define default_param_perio_tx_fifo_size_14 0 |
| 577 | #define default_param_perio_tx_fifo_size_15 0 |
| 578 | #endif //__IS_DEVICE__ |
| 579 | |
| 580 | #elif defined(__IS_AMAZON_SE__) |
| 581 | #include <asm/amazon_se/amazon_se.h> |
| 582 | //#include <asm/amazon_se/irq.h> |
| 583 | |
| 584 | // #define IFXUSB_IRQ 31 |
| 585 | #define IFXUSB_IOMEM_BASE 0x1e101000 |
| 586 | #define IFXUSB_FIFOMEM_BASE 0x1e120000 |
| 587 | #define IFXUSB_FIFODBG_BASE 0x1e140000 |
| 588 | // #define IFXUSB_OC_IRQ 20 |
| 589 | |
| 590 | #define AMAZON_SE_RCU_USBCFG ((volatile unsigned long *)(AMAZON_SE_RCU_BASE_ADDR + 0x18)) |
| 591 | #define AMAZON_SE_RCU_RESET ((volatile unsigned long *)(AMAZON_SE_RCU_BASE_ADDR + 0x10)) |
| 592 | #define AMAZON_SE_USBCFG_HDSEL_BIT 11 // 0:host, 1:device |
| 593 | #define AMAZON_SE_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end |
| 594 | #define AMAZON_SE_USBCFG_SLV_END_BIT 9 // 0:little_end, 1:big_end |
| 595 | |
| 596 | #ifndef AMAZON_SE_GPIO_P0_OUT |
| 597 | #define AMAZON_SE_GPIO_P0_OUT (0xBF103000+0x10) |
| 598 | #define AMAZON_SE_GPIO_P0_DIR (0xBF103000+0x18) |
| 599 | #define AMAZON_SE_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) |
| 600 | #define AMAZON_SE_GPIO_P0_ALTSEL1 (0xBF103000+0x20) |
| 601 | #define AMAZON_SE_GPIO_P0_OD (0xBF103000+0x24) |
| 602 | #define AMAZON_SE_GPIO_P0_PUDSEL (0xBF103000+0x2C) |
| 603 | #define AMAZON_SE_GPIO_P0_PUDEN (0xBF103000+0x30) |
| 604 | #define AMAZON_SE_GPIO_P1_OUT (0xBF103000+0x40) |
| 605 | #define AMAZON_SE_GPIO_P1_DIR (0xBF103000+0x48) |
| 606 | #define AMAZON_SE_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) |
| 607 | #define AMAZON_SE_GPIO_P1_ALTSEL1 (0xBF103000+0x50) |
| 608 | #define AMAZON_SE_GPIO_P1_OD (0xBF103000+0x54) |
| 609 | #define AMAZON_SE_GPIO_P1_PUDSEL (0xBF103000+0x5C) |
| 610 | #define AMAZON_SE_GPIO_P1_PUDEN (0xBF103000+0x60) |
| 611 | #endif |
| 612 | |
| 613 | |
| 614 | #ifndef AMAZON_SE_CGU |
| 615 | #define AMAZON_SE_CGU (0xBF103000) |
| 616 | #endif |
| 617 | #ifndef AMAZON_SE_CGU_IFCCR |
| 618 | #define AMAZON_SE_CGU_IFCCR ((volatile unsigned long *)(AMAZON_SE_CGU+ 0x0018)) |
| 619 | #endif |
| 620 | #ifndef AMAZON_SE_PMU |
| 621 | #define AMAZON_SE_PMU (KSEG1+0x1F102000) |
| 622 | #endif |
| 623 | #ifndef AMAZON_SE_PMU_PWDCR |
| 624 | #define AMAZON_SE_PMU_PWDCR ((volatile unsigned long *)(AMAZON_SE_PMU+0x001C)) |
| 625 | #endif |
| 626 | |
| 627 | #define default_param_dma_burst_size 4 |
| 628 | |
| 629 | #define default_param_speed IFXUSB_PARAM_SPEED_HIGH |
| 630 | |
| 631 | #define default_param_max_transfer_size -1 //(Max, hwcfg) |
| 632 | #define default_param_max_packet_count -1 //(Max, hwcfg) |
| 633 | #define default_param_phy_utmi_width 16 |
| 634 | |
| 635 | #define default_param_turn_around_time_hs 4 //(NoChange) |
| 636 | #define default_param_turn_around_time_fs 4 //(NoChange) |
| 637 | #define default_param_timeout_cal_hs -1 //(NoChange) |
| 638 | #define default_param_timeout_cal_fs -1 //(NoChange) |
| 639 | |
| 640 | #define default_param_data_fifo_size -1 //(Max, hwcfg) |
| 641 | |
| 642 | #ifdef __IS_HOST__ |
| 643 | #define default_param_host_channels -1 //(Max, hwcfg) |
| 644 | #define default_param_rx_fifo_size 240 |
| 645 | #define default_param_nperio_tx_fifo_size 240 |
| 646 | #define default_param_perio_tx_fifo_size 32 |
| 647 | #endif //__IS_HOST__ |
| 648 | #ifdef __IS_DEVICE__ |
| 649 | #ifdef __DED_INTR__ |
| 650 | #define default_param_rx_fifo_size 256 |
| 651 | #define default_param_nperio_tx_fifo_size 248 |
| 652 | #define default_param_perio_tx_fifo_size_01 8 |
| 653 | #else |
| 654 | #define default_param_rx_fifo_size 256 |
| 655 | #define default_param_nperio_tx_fifo_size 256 |
| 656 | #define default_param_perio_tx_fifo_size_01 0 |
| 657 | #endif |
| 658 | #define default_param_perio_tx_fifo_size_02 0 |
| 659 | #define default_param_perio_tx_fifo_size_03 0 |
| 660 | #define default_param_perio_tx_fifo_size_04 0 |
| 661 | #define default_param_perio_tx_fifo_size_05 0 |
| 662 | #define default_param_perio_tx_fifo_size_06 0 |
| 663 | #define default_param_perio_tx_fifo_size_07 0 |
| 664 | #define default_param_perio_tx_fifo_size_08 0 |
| 665 | #define default_param_perio_tx_fifo_size_09 0 |
| 666 | #define default_param_perio_tx_fifo_size_10 0 |
| 667 | #define default_param_perio_tx_fifo_size_11 0 |
| 668 | #define default_param_perio_tx_fifo_size_12 0 |
| 669 | #define default_param_perio_tx_fifo_size_13 0 |
| 670 | #define default_param_perio_tx_fifo_size_14 0 |
| 671 | #define default_param_perio_tx_fifo_size_15 0 |
| 672 | #endif //__IS_DEVICE__ |
| 673 | |
| 674 | #elif defined(__IS_AR9__) |
| 675 | // #define IFXUSB1_IRQ 54 |
| 676 | #define IFXUSB1_IOMEM_BASE 0x1E101000 |
| 677 | #define IFXUSB1_FIFOMEM_BASE 0x1E120000 |
| 678 | #define IFXUSB1_FIFODBG_BASE 0x1E140000 |
| 679 | |
| 680 | // #define IFXUSB2_IRQ 83 |
| 681 | #define IFXUSB2_IOMEM_BASE 0x1E106000 |
| 682 | #define IFXUSB2_FIFOMEM_BASE 0x1E1E0000 |
| 683 | #define IFXUSB2_FIFODBG_BASE 0x1E1C0000 |
| 684 | |
| 685 | // #define IFXUSB_OC_IRQ 60 |
| 686 | |
| 687 | #ifndef AMAZON_S_RCU_BASE_ADDR |
| 688 | #define AMAZON_S_RCU_BASE_ADDR (0xBF203000) |
| 689 | #endif |
| 690 | |
| 691 | #ifndef AMAZON_S_CGU |
| 692 | #define AMAZON_S_CGU (0xBF103000) |
| 693 | #endif |
| 694 | #ifndef AMAZON_S_CGU_IFCCR |
| 695 | #define AMAZON_S_CGU_IFCCR ((volatile unsigned long *)(AMAZON_S_CGU+ 0x0018)) |
| 696 | #endif |
| 697 | |
| 698 | #ifndef AMAZON_S_PMU |
| 699 | #define AMAZON_S_PMU (KSEG1+0x1F102000) |
| 700 | #endif |
| 701 | #ifndef AMAZON_S_PMU_PWDCR |
| 702 | #define AMAZON_S_PMU_PWDCR ((volatile unsigned long *)(AMAZON_S_PMU+0x001C)) |
| 703 | #endif |
| 704 | |
| 705 | #ifndef AMAZON_S_GPIO_P0_OUT |
| 706 | #define AMAZON_S_GPIO_P0_OUT (0xBF103000+0x10) |
| 707 | #define AMAZON_S_GPIO_P0_DIR (0xBF103000+0x18) |
| 708 | #define AMAZON_S_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) |
| 709 | #define AMAZON_S_GPIO_P0_ALTSEL1 (0xBF103000+0x20) |
| 710 | #define AMAZON_S_GPIO_P0_OD (0xBF103000+0x24) |
| 711 | #define AMAZON_S_GPIO_P0_PUDSEL (0xBF103000+0x2C) |
| 712 | #define AMAZON_S_GPIO_P0_PUDEN (0xBF103000+0x30) |
| 713 | #define AMAZON_S_GPIO_P1_OUT (0xBF103000+0x40) |
| 714 | #define AMAZON_S_GPIO_P1_DIR (0xBF103000+0x48) |
| 715 | #define AMAZON_S_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) |
| 716 | #define AMAZON_S_GPIO_P1_ALTSEL1 (0xBF103000+0x50) |
| 717 | #define AMAZON_S_GPIO_P1_OD (0xBF103000+0x54) |
| 718 | #define AMAZON_S_GPIO_P1_PUDSEL (0xBF103000+0x5C) |
| 719 | #define AMAZON_S_GPIO_P1_PUDEN (0xBF103000+0x60) |
| 720 | #endif |
| 721 | |
| 722 | #define AMAZON_S_RCU_USB1CFG ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x18)) |
| 723 | #define AMAZON_S_RCU_USB2CFG ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x34)) |
| 724 | #define AMAZON_S_RCU_USBRESET ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x10)) |
| 725 | #define AMAZON_S_USBCFG_ARB 7 // |
| 726 | #define AMAZON_S_USBCFG_HDSEL_BIT 11 // 0:host, 1:device |
| 727 | #define AMAZON_S_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end |
| 728 | #define AMAZON_S_USBCFG_SLV_END_BIT 17 // 0:little_end, 1:big_end |
| 729 | |
| 730 | #define default_param_dma_burst_size 4 |
| 731 | |
| 732 | #define default_param_speed IFXUSB_PARAM_SPEED_HIGH |
| 733 | |
| 734 | #define default_param_max_transfer_size -1 //(Max, hwcfg) |
| 735 | #define default_param_max_packet_count -1 //(Max, hwcfg) |
| 736 | #define default_param_phy_utmi_width 16 |
| 737 | |
| 738 | #define default_param_turn_around_time_hs 4 //(NoChange) |
| 739 | #define default_param_turn_around_time_fs 4 //(NoChange) |
| 740 | #define default_param_timeout_cal_hs -1 //(NoChange) |
| 741 | #define default_param_timeout_cal_fs -1 //(NoChange) |
| 742 | |
| 743 | #define default_param_data_fifo_size -1 //(Max, hwcfg) |
| 744 | |
| 745 | #ifdef __IS_HOST__ |
| 746 | #define default_param_host_channels -1 //(Max, hwcfg) |
| 747 | #define default_param_rx_fifo_size 240 |
| 748 | #define default_param_nperio_tx_fifo_size 240 |
| 749 | #define default_param_perio_tx_fifo_size 32 |
| 750 | #endif //__IS_HOST__ |
| 751 | #ifdef __IS_DEVICE__ |
| 752 | #ifdef __DED_INTR__ |
| 753 | #define default_param_rx_fifo_size 256 |
| 754 | #define default_param_nperio_tx_fifo_size 248 |
| 755 | #define default_param_perio_tx_fifo_size_01 8 |
| 756 | #else |
| 757 | #define default_param_rx_fifo_size 256 |
| 758 | #define default_param_nperio_tx_fifo_size 256 |
| 759 | #define default_param_perio_tx_fifo_size_01 0 |
| 760 | #endif |
| 761 | #define default_param_perio_tx_fifo_size_02 0 |
| 762 | #define default_param_perio_tx_fifo_size_03 0 |
| 763 | #define default_param_perio_tx_fifo_size_04 0 |
| 764 | #define default_param_perio_tx_fifo_size_05 0 |
| 765 | #define default_param_perio_tx_fifo_size_06 0 |
| 766 | #define default_param_perio_tx_fifo_size_07 0 |
| 767 | #define default_param_perio_tx_fifo_size_08 0 |
| 768 | #define default_param_perio_tx_fifo_size_09 0 |
| 769 | #define default_param_perio_tx_fifo_size_10 0 |
| 770 | #define default_param_perio_tx_fifo_size_11 0 |
| 771 | #define default_param_perio_tx_fifo_size_12 0 |
| 772 | #define default_param_perio_tx_fifo_size_13 0 |
| 773 | #define default_param_perio_tx_fifo_size_14 0 |
| 774 | #define default_param_perio_tx_fifo_size_15 0 |
| 775 | #endif //__IS_DEVICE__ |
| 776 | |
| 777 | #elif defined(__IS_VR9__) |
| 778 | // #define IFXUSB1_IRQ 54 |
| 779 | #define IFXUSB1_IOMEM_BASE 0x1E101000 |
| 780 | #define IFXUSB1_FIFOMEM_BASE 0x1E120000 |
| 781 | #define IFXUSB1_FIFODBG_BASE 0x1E140000 |
| 782 | |
| 783 | // #define IFXUSB2_IRQ 83 |
| 784 | #define IFXUSB2_IOMEM_BASE 0x1E106000 |
| 785 | #define IFXUSB2_FIFOMEM_BASE 0x1E1E0000 |
| 786 | #define IFXUSB2_FIFODBG_BASE 0x1E1C0000 |
| 787 | // #define IFXUSB_OC_IRQ 60 |
| 788 | |
| 789 | #ifndef AMAZON_S_RCU_BASE_ADDR |
| 790 | #define AMAZON_S_RCU_BASE_ADDR (0xBF203000) |
| 791 | #endif |
| 792 | |
| 793 | #ifndef AMAZON_S_CGU |
| 794 | #define AMAZON_S_CGU (0xBF103000) |
| 795 | #endif |
| 796 | #ifndef AMAZON_S_CGU_IFCCR |
| 797 | #define AMAZON_S_CGU_IFCCR ((volatile unsigned long *)(AMAZON_S_CGU+ 0x0018)) |
| 798 | #endif |
| 799 | |
| 800 | #ifndef AMAZON_S_PMU |
| 801 | #define AMAZON_S_PMU (KSEG1+0x1F102000) |
| 802 | #endif |
| 803 | #ifndef AMAZON_S_PMU_PWDCR |
| 804 | #define AMAZON_S_PMU_PWDCR ((volatile unsigned long *)(AMAZON_S_PMU+0x001C)) |
| 805 | #endif |
| 806 | |
| 807 | #ifndef AMAZON_S_GPIO_P0_OUT |
| 808 | #define AMAZON_S_GPIO_P0_OUT (0xBF103000+0x10) |
| 809 | #define AMAZON_S_GPIO_P0_DIR (0xBF103000+0x18) |
| 810 | #define AMAZON_S_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) |
| 811 | #define AMAZON_S_GPIO_P0_ALTSEL1 (0xBF103000+0x20) |
| 812 | #define AMAZON_S_GPIO_P0_OD (0xBF103000+0x24) |
| 813 | #define AMAZON_S_GPIO_P0_PUDSEL (0xBF103000+0x2C) |
| 814 | #define AMAZON_S_GPIO_P0_PUDEN (0xBF103000+0x30) |
| 815 | #define AMAZON_S_GPIO_P1_OUT (0xBF103000+0x40) |
| 816 | #define AMAZON_S_GPIO_P1_DIR (0xBF103000+0x48) |
| 817 | #define AMAZON_S_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) |
| 818 | #define AMAZON_S_GPIO_P1_ALTSEL1 (0xBF103000+0x50) |
| 819 | #define AMAZON_S_GPIO_P1_OD (0xBF103000+0x54) |
| 820 | #define AMAZON_S_GPIO_P1_PUDSEL (0xBF103000+0x5C) |
| 821 | #define AMAZON_S_GPIO_P1_PUDEN (0xBF103000+0x60) |
| 822 | #endif |
| 823 | |
| 824 | #define AMAZON_S_RCU_USB1CFG ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x18)) |
| 825 | #define AMAZON_S_RCU_USB2CFG ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x34)) |
| 826 | #define AMAZON_S_RCU_USBRESET ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x10)) |
| 827 | #define AMAZON_S_USBCFG_ARB 7 // |
| 828 | #define AMAZON_S_USBCFG_HDSEL_BIT 11 // 0:host, 1:device |
| 829 | #define AMAZON_S_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end |
| 830 | #define AMAZON_S_USBCFG_SLV_END_BIT 17 // 0:little_end, 1:big_end |
| 831 | |
| 832 | #define default_param_dma_burst_size 4 //(ALL) |
| 833 | |
| 834 | #define default_param_speed IFXUSB_PARAM_SPEED_HIGH |
| 835 | |
| 836 | #define default_param_max_transfer_size -1 //(Max, hwcfg) |
| 837 | #define default_param_max_packet_count -1 //(Max, hwcfg) |
| 838 | #define default_param_phy_utmi_width 16 |
| 839 | |
| 840 | #define default_param_turn_around_time_hs 6 //(NoChange) snpsid >= 0x4f54260a |
| 841 | #define default_param_turn_around_time_fs 6 //(NoChange) snpsid >= 0x4f54260a |
| 842 | #define default_param_timeout_cal_hs -1 //(NoChange) |
| 843 | #define default_param_timeout_cal_fs -1 //(NoChange) |
| 844 | |
| 845 | #define default_param_data_fifo_size -1 //(Max, hwcfg) |
| 846 | |
| 847 | #ifdef __IS_HOST__ |
| 848 | #define default_param_host_channels -1 //(Max, hwcfg) |
| 849 | #define default_param_rx_fifo_size 240 |
| 850 | #define default_param_nperio_tx_fifo_size 240 |
| 851 | #define default_param_perio_tx_fifo_size 32 |
| 852 | #endif //__IS_HOST__ |
| 853 | #ifdef __IS_DEVICE__ |
| 854 | #define default_param_rx_fifo_size 256 |
| 855 | #define default_param_tx_fifo_size_00 -1 |
| 856 | #define default_param_tx_fifo_size_01 -1 |
| 857 | #define default_param_tx_fifo_size_02 -1 |
| 858 | #define default_param_tx_fifo_size_03 -1 |
| 859 | #define default_param_tx_fifo_size_04 -1 |
| 860 | #define default_param_tx_fifo_size_05 -1 |
| 861 | #define default_param_tx_fifo_size_06 -1 |
| 862 | #define default_param_tx_fifo_size_07 -1 |
| 863 | #define default_param_tx_fifo_size_08 -1 |
| 864 | #define default_param_tx_fifo_size_09 -1 |
| 865 | #define default_param_tx_fifo_size_10 -1 |
| 866 | #define default_param_tx_fifo_size_11 -1 |
| 867 | #define default_param_tx_fifo_size_12 -1 |
| 868 | #define default_param_tx_fifo_size_13 -1 |
| 869 | #define default_param_tx_fifo_size_14 -1 |
| 870 | #define default_param_tx_fifo_size_15 -1 |
| 871 | #define default_param_dma_unalgned_tx -1 |
| 872 | #define default_param_dma_unalgned_rx -1 |
| 873 | #define default_param_thr_ctl -1 |
| 874 | #define default_param_tx_thr_length -1 |
| 875 | #define default_param_rx_thr_length -1 |
| 876 | #endif //__IS_DEVICE__ |
| 877 | #else // __IS_VR9__ |
| 878 | #error "Please choose one platform!!" |
| 879 | #endif // __IS_VR9__ |
| 880 | #endif //UEIP |
| 881 | |
| 882 | /*@}*//*IFXUSB_PLATEFORM_MEM_ADDR*/ |
| 883 | |
| 884 | ///////////////////////////////////////////////////////////////////////// |
| 885 | |
| 886 | #ifdef __IS_HOST__ |
| 887 | #ifdef CONFIG_USB_HOST_IFX_FORCE_USB11 |
| 888 | #undef default_param_speed |
| 889 | #define default_param_speed IFXUSB_PARAM_SPEED_FULL |
| 890 | #endif |
| 891 | #endif |
| 892 | #ifdef __IS_DEVICE__ |
| 893 | #ifndef CONFIG_USB_GADGET_DUALSPEED |
| 894 | #undef default_param_speed |
| 895 | #define default_param_speed IFXUSB_PARAM_SPEED_FULL |
| 896 | #endif |
| 897 | #endif |
| 898 | |
| 899 | ///////////////////////////////////////////////////////////////////////// |
| 900 | |
| 901 | static __inline__ void UDELAY( const uint32_t _usecs ) |
| 902 | { |
| 903 | udelay( _usecs ); |
| 904 | } |
| 905 | |
| 906 | static __inline__ void MDELAY( const uint32_t _msecs ) |
| 907 | { |
| 908 | mdelay( _msecs ); |
| 909 | } |
| 910 | |
| 911 | static __inline__ void SPIN_LOCK( spinlock_t *_lock ) |
| 912 | { |
| 913 | spin_lock(_lock); |
| 914 | } |
| 915 | |
| 916 | static __inline__ void SPIN_UNLOCK( spinlock_t *_lock ) |
| 917 | { |
| 918 | spin_unlock(_lock); |
| 919 | } |
| 920 | |
| 921 | #define SPIN_LOCK_IRQSAVE( _l, _f ) \ |
| 922 | { \ |
| 923 | spin_lock_irqsave(_l,_f); \ |
| 924 | } |
| 925 | |
| 926 | #define SPIN_UNLOCK_IRQRESTORE( _l,_f ) \ |
| 927 | { \ |
| 928 | spin_unlock_irqrestore(_l,_f); \ |
| 929 | } |
| 930 | |
| 931 | ///////////////////////////////////////////////////////////////////////// |
| 932 | /*! |
| 933 | \addtogroup IFXUSB_DBG_ROUTINE |
| 934 | */ |
| 935 | /*@{*/ |
| 936 | #ifdef __IS_HOST__ |
| 937 | extern uint32_t h_dbg_lvl; |
| 938 | #endif |
| 939 | |
| 940 | #ifdef __IS_DEVICE__ |
| 941 | extern uint32_t d_dbg_lvl; |
| 942 | #endif |
| 943 | |
| 944 | /*! \brief When debug level has the DBG_CIL bit set, display CIL Debug messages. */ |
| 945 | #define DBG_CIL (0x2) |
| 946 | /*! \brief When debug level has the DBG_CILV bit set, display CIL Verbose debug messages */ |
| 947 | #define DBG_CILV (0x20) |
| 948 | /*! \brief When debug level has the DBG_PCD bit set, display PCD (Device) debug messages */ |
| 949 | #define DBG_PCD (0x4) |
| 950 | /*! \brief When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug messages */ |
| 951 | #define DBG_PCDV (0x40) |
| 952 | /*! \brief When debug level has the DBG_HCD bit set, display Host debug messages */ |
| 953 | #define DBG_HCD (0x8) |
| 954 | /*! \brief When debug level has the DBG_HCDV bit set, display Verbose Host debug messages */ |
| 955 | #define DBG_HCDV (0x80) |
| 956 | /*! \brief When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host mode. */ |
| 957 | #define DBG_HCD_URB (0x800) |
| 958 | /*! \brief When debug level has any bit set, display debug messages */ |
| 959 | #define DBG_ANY (0xFF) |
| 960 | /*! \brief All debug messages off */ |
| 961 | #define DBG_OFF 0 |
| 962 | |
| 963 | #define DBG_ENTRY (0x8000) |
| 964 | |
| 965 | #define IFXUSB "IFXUSB: " |
| 966 | |
| 967 | /*! |
| 968 | \fn inline uint32_t SET_DEBUG_LEVEL( const uint32_t _new ) |
| 969 | \brief Set the Debug Level variable. |
| 970 | \param _new 32-bit mask of debug level. |
| 971 | \return previous debug level |
| 972 | */ |
| 973 | static inline uint32_t SET_DEBUG_LEVEL( const uint32_t _new ) |
| 974 | { |
| 975 | #ifdef __IS_HOST__ |
| 976 | uint32_t old = h_dbg_lvl; |
| 977 | h_dbg_lvl = _new; |
| 978 | #endif |
| 979 | |
| 980 | #ifdef __IS_DEVICE__ |
| 981 | uint32_t old = d_dbg_lvl; |
| 982 | d_dbg_lvl = _new; |
| 983 | #endif |
| 984 | return old; |
| 985 | } |
| 986 | |
| 987 | #ifdef __DEBUG__ |
| 988 | #ifdef __IS_HOST__ |
| 989 | # define IFX_DEBUGPL(lvl, x...) do{ if ((lvl)&h_dbg_lvl)printk( KERN_DEBUG IFXUSB x ); }while(0) |
| 990 | # define CHK_DEBUG_LEVEL(level) ((level) & h_dbg_lvl) |
| 991 | #endif |
| 992 | |
| 993 | #ifdef __IS_DEVICE__ |
| 994 | # define IFX_DEBUGPL(lvl, x...) do{ if ((lvl)&d_dbg_lvl)printk( KERN_DEBUG IFXUSB x ); }while(0) |
| 995 | # define CHK_DEBUG_LEVEL(level) ((level) & d_dbg_lvl) |
| 996 | #endif |
| 997 | |
| 998 | # define IFX_DEBUGP(x...) IFX_DEBUGPL(DBG_ANY, x ) |
| 999 | #else |
| 1000 | # define IFX_DEBUGPL(lvl, x...) do{}while(0) |
| 1001 | # define IFX_DEBUGP(x...) |
| 1002 | # define CHK_DEBUG_LEVEL(level) (0) |
| 1003 | #endif //__DEBUG__ |
| 1004 | |
| 1005 | /* Print an Error message. */ |
| 1006 | #define IFX_ERROR(x...) printk( KERN_ERR IFXUSB x ) |
| 1007 | /* Print a Warning message. */ |
| 1008 | #define IFX_WARN(x...) printk( KERN_WARNING IFXUSB x ) |
| 1009 | /* Print a notice (normal but significant message). */ |
| 1010 | #define IFX_NOTICE(x...) printk( KERN_NOTICE IFXUSB x ) |
| 1011 | /* Basic message printing. */ |
| 1012 | #define IFX_PRINT(x...) printk( KERN_INFO IFXUSB x ) |
| 1013 | |
| 1014 | /*@}*//*IFXUSB_DBG_ROUTINE*/ |
| 1015 | |
| 1016 | |
| 1017 | #endif //__IFXUSB_PLAT_H__ |
| 1018 | |
| 1019 | |
