Root/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_regs.h

1/*****************************************************************************
2 ** FILE NAME : ifxusb_regs.h
3 ** PROJECT : IFX USB sub-system V3
4 ** MODULES : IFX USB sub-system Host and Device driver
5 ** SRC VERSION : 1.0
6 ** DATE : 1/Jan/2009
7 ** AUTHOR : Chen, Howard
8 ** DESCRIPTION : This file contains the data structures for accessing the IFXUSB core
9 ** registers.
10 ** The application interfaces with the USB core by reading from and
11 ** writing to the Control and Status Register (CSR) space through the
12 ** AHB Slave interface. These registers are 32 bits wide, and the
13 ** addresses are 32-bit-block aligned.
14 ** CSRs are classified as follows:
15 ** - Core Global Registers
16 ** - Device Mode Registers
17 ** - Device Global Registers
18 ** - Device Endpoint Specific Registers
19 ** - Host Mode Registers
20 ** - Host Global Registers
21 ** - Host Port CSRs
22 ** - Host Channel Specific Registers
23 **
24 ** Only the Core Global registers can be accessed in both Device and
25 ** Host modes. When the USB core is operating in one mode, either
26 ** Device or Host, the application must not access registers from the
27 ** other mode. When the core switches from one mode to another, the
28 ** registers in the new mode of operation must be reprogrammed as they
29 ** would be after a power-on reset.
30 ** FUNCTIONS :
31 ** COMPILER : gcc
32 ** REFERENCE : Synopsys DWC-OTG Driver 2.7
33 ** COPYRIGHT :
34 ** Version Control Section **
35 ** $Author$
36 ** $Date$
37 ** $Revisions$
38 ** $Log$ Revision history
39*****************************************************************************/
40
41
42
43/*!
44  \defgroup IFXUSB_CSR_DEFINITION Control and Status Register bit-map definition
45  \ingroup IFXUSB_DRIVER_V3
46   \brief Data structures for accessing the IFXUSB core registers.
47          The application interfaces with the USB core by reading from and
48          writing to the Control and Status Register (CSR) space through the
49          AHB Slave interface. These registers are 32 bits wide, and the
50          addresses are 32-bit-block aligned.
51          CSRs are classified as follows:
52           - Core Global Registers
53           - Device Mode Registers
54           - Device Global Registers
55           - Device Endpoint Specific Registers
56           - Host Mode Registers
57           - Host Global Registers
58           - Host Port CSRs
59           - Host Channel Specific Registers
60
61          Only the Core Global registers can be accessed in both Device andHost modes.
62          When the USB core is operating in one mode, either Device or Host, the
63          application must not access registers from the other mode. When the core
64          switches from one mode to another, the registers in the new mode of operation
65          must be reprogrammed as they would be after a power-on reset.
66 */
67
68/*!
69  \defgroup IFXUSB_CSR_DEVICE_GLOBAL_REG Device Mode Registers
70  \ingroup IFXUSB_CSR_DEFINITION
71  \brief Bit-mapped structure to access Device Mode Global Registers
72 */
73
74/*!
75  \defgroup IFXUSB_CSR_DEVICE_EP_REG Device Mode EP Registers
76  \ingroup IFXUSB_CSR_DEFINITION
77    \brief Bit-mapped structure to access Device Mode EP Registers
78     There will be one set of endpoint registers per logical endpoint
79     implemented.
80     These registers are visible only in Device mode and must not be
81     accessed in Host mode, as the results are unknown.
82 */
83
84/*!
85  \defgroup IFXUSB_CSR_DEVICE_DMA_DESC Device mode scatter dma descriptor strusture
86  \ingroup IFXUSB_CSR_DEFINITION
87  \brief Bit-mapped structure to DMA descriptor
88 */
89
90
91/*!
92  \defgroup IFXUSB_CSR_HOST_GLOBAL_REG Host Mode Registers
93  \ingroup IFXUSB_CSR_DEFINITION
94  \brief Bit-mapped structure to access Host Mode Global Registers
95 */
96
97/*!
98  \defgroup IFXUSB_CSR_HOST_HC_REG Host Mode HC Registers
99  \ingroup IFXUSB_CSR_DEFINITION
100    \brief Bit-mapped structure to access Host Mode Host Channel Registers
101     There will be one set of endpoint registers per host channel
102     implemented.
103     These registers are visible only in Host mode and must not be
104     accessed in Device mode, as the results are unknown.
105 */
106
107/*!
108  \defgroup IFXUSB_CSR_PWR_CLK_GATING_REG Power and Clock Gating Control Register
109  \ingroup IFXUSB_CSR_DEFINITION
110  \brief Bit-mapped structure to Power and Clock Gating Control Register
111 */
112
113
114
115
116
117
118
119
120/*!
121  \defgroup IFXUSB_CSR_CORE_GLOBAL_REG Core Global Registers
122  \ingroup IFXUSB_CSR_DEFINITION
123  \brief Bit-mapped structure to access Core Global Registers
124 */
125/*!
126  \defgroup IFXUSB_CSR_CORE_GLOBAL_REG Core Global Registers
127  \ingroup IFXUSB_CSR_DEFINITION
128  \brief Bit-mapped structure to access Core Global Registers
129 */
130
131
132
133
134
135
136
137
138
139/*!
140  \file ifxusb_regs.h
141  \ingroup IFXUSB_DRIVER_V3
142  \brief This file contains the data structures for accessing the IFXUSB core registers.
143 */
144
145
146#ifndef __IFXUSB_REGS_H__
147#define __IFXUSB_REGS_H__
148
149/****************************************************************************/
150
151#define MAX_PERIO_FIFOS 15 /** Maximum number of Periodic FIFOs */
152#define MAX_TX_FIFOS 15 /** Maximum number of Periodic FIFOs */
153#define MAX_EPS_CHANNELS 16 /** Maximum number of Endpoints/HostChannels */
154
155/****************************************************************************/
156
157/*!
158  \addtogroup IFXUSB_CSR_ACCESS_MACROS
159 */
160/*@{*/
161
162//#define RecordRegRW
163
164/*!
165   \fn static __inline__ uint32_t ifxusb_rreg( volatile uint32_t *_reg)
166   \brief Reads the content of a register.
167   \param _reg address of register to read.
168   \return contents of the register.
169 */
170static __inline__ uint32_t ifxusb_rreg( volatile uint32_t *_reg)
171{
172    #ifdef RecordRegRW
173        uint32_t r;
174        r=*(_reg);
175        return (r);
176    #else
177        return (*(_reg));
178    #endif
179};
180
181
182/*!
183   \fn static __inline__ void ifxusb_wreg( volatile uint32_t *_reg, const uint32_t _value)
184   \brief Writes a register with a 32 bit value.
185   \param _reg address of register to write.
186   \param _value value to write to _reg.
187 */
188static __inline__ void ifxusb_wreg( volatile uint32_t *_reg, const uint32_t _value)
189{
190    #ifdef RecordRegRW
191        printk(KERN_INFO "[W %p<-%08X]\n",_reg,_value);
192    #else
193        *(_reg)=_value;
194    #endif
195};
196
197/*!
198   \fn static __inline__ void ifxusb_mreg( volatile uint32_t *_reg, const uint32_t _clear_mask, const uint32_t _set_mask)
199   \brief Modifies bit values in a register. Using the
200          algorithm: (reg_contents & ~clear_mask) | set_mask.
201   \param _reg address of register to modify.
202   \param _clear_mask bit mask to be cleared.
203   \param _set_mask bit mask to be set.
204 */
205static __inline__ void ifxusb_mreg( volatile uint32_t *_reg, const uint32_t _clear_mask, const uint32_t _set_mask)
206{
207    uint32_t v;
208    #ifdef RecordRegRW
209        uint32_t r;
210        v= *(_reg);
211        r=v;
212        r&=(~_clear_mask);
213        r|= _set_mask;
214        *(_reg)=r ;
215        printk(KERN_INFO "[M %p->%08X+%08X/%08X<-%08X]\n",_reg,r,_clear_mask,_set_mask,r);
216    #else
217        v= *(_reg);
218        v&=(~_clear_mask);
219        v|= _set_mask;
220        *(_reg)=v ;
221    #endif
222};
223
224/*@}*//*IFXUSB_CSR_ACCESS_MACROS*/
225/****************************************************************************/
226
227/*!
228  \addtogroup IFXUSB_CSR_CORE_GLOBAL_REG
229 */
230/*@{*/
231
232/*!
233 \struct ifxusb_core_global_regs
234 \brief IFXUSB Core registers .
235         The ifxusb_core_global_regs structure defines the size
236         and relative field offsets for the Core Global registers.
237 */
238typedef struct ifxusb_core_global_regs
239{
240    volatile uint32_t gotgctl; /*!< 000h OTG Control and Status Register. */
241    volatile uint32_t gotgint; /*!< 004h OTG Interrupt Register. */
242    volatile uint32_t gahbcfg; /*!< 008h Core AHB Configuration Register. */
243    volatile uint32_t gusbcfg; /*!< 00Ch Core USB Configuration Register. */
244    volatile uint32_t grstctl; /*!< 010h Core Reset Register. */
245    volatile uint32_t gintsts; /*!< 014h Core Interrupt Register. */
246    volatile uint32_t gintmsk; /*!< 018h Core Interrupt Mask Register. */
247    volatile uint32_t grxstsr; /*!< 01Ch Receive Status Queue Read Register (Read Only). */
248    volatile uint32_t grxstsp; /*!< 020h Receive Status Queue Read & POP Register (Read Only). */
249    volatile uint32_t grxfsiz; /*!< 024h Receive FIFO Size Register. */
250    volatile uint32_t gnptxfsiz; /*!< 028h Non Periodic Transmit FIFO Size Register. */
251    volatile uint32_t gnptxsts; /*!< 02Ch Non Periodic Transmit FIFO/Queue Status Register (Read Only). */
252    volatile uint32_t gi2cctl; /*!< 030h I2C Access Register. */
253    volatile uint32_t gpvndctl; /*!< 034h PHY Vendor Control Register. */
254    volatile uint32_t ggpio; /*!< 038h General Purpose Input/Output Register. */
255    volatile uint32_t guid; /*!< 03Ch User ID Register. */
256    volatile uint32_t gsnpsid; /*!< 040h Synopsys ID Register (Read Only). */
257    volatile uint32_t ghwcfg1; /*!< 044h User HW Config1 Register (Read Only). */
258    volatile uint32_t ghwcfg2; /*!< 048h User HW Config2 Register (Read Only). */
259    volatile uint32_t ghwcfg3; /*!< 04Ch User HW Config3 Register (Read Only). */
260    volatile uint32_t ghwcfg4; /*!< 050h User HW Config4 Register (Read Only). */
261    volatile uint32_t reserved[43]; /*!< 054h Reserved 054h-0FFh */
262    volatile uint32_t hptxfsiz; /*!< 100h Host Periodic Transmit FIFO Size Register. */
263    volatile uint32_t dptxfsiz_dieptxf[15];/*!< 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15.
264                                               Device Periodic Transmit FIFO#n Register if dedicated
265                                               fifos are disabled, otherwise Device Transmit FIFO#n
266                                               Register.
267                                             */
268} ifxusb_core_global_regs_t;
269
270/*!
271 \brief Bits of the Core OTG Control and Status Register (GOTGCTL).
272 */
273typedef union gotgctl_data
274{
275    uint32_t d32;
276    struct{
277        unsigned reserved21_31 : 11;
278        unsigned currmod : 1 ; /*!< 20 */
279        unsigned bsesvld : 1 ; /*!< 19 */
280        unsigned asesvld : 1 ; /*!< 18 */
281        unsigned reserved17 : 1 ;
282        unsigned conidsts : 1 ; /*!< 16 */
283        unsigned reserved12_15 : 4 ;
284        unsigned devhnpen : 1 ; /*!< 11 */
285        unsigned hstsethnpen : 1 ; /*!< 10 */
286        unsigned hnpreq : 1 ; /*!< 09 */
287        unsigned hstnegscs : 1 ; /*!< 08 */
288        unsigned reserved2_7 : 6 ;
289        unsigned sesreq : 1 ; /*!< 01 */
290        unsigned sesreqscs : 1 ; /*!< 00 */
291    } b;
292} gotgctl_data_t;
293
294/*!
295 \brief Bit fields of the Core OTG Interrupt Register (GOTGINT).
296 */
297typedef union gotgint_data
298{
299    uint32_t d32;
300    struct
301    {
302        unsigned reserved31_20 : 12;
303        unsigned debdone : 1 ; /*!< 19 Debounce Done */
304        unsigned adevtoutchng : 1 ; /*!< 18 A-Device Timeout Change */
305        unsigned hstnegdet : 1 ; /*!< 17 Host Negotiation Detected */
306        unsigned reserver10_16 : 7 ;
307        unsigned hstnegsucstschng : 1 ; /*!< 09 Host Negotiation Success Status Change */
308        unsigned sesreqsucstschng : 1 ; /*!< 08 Session Request Success Status Change */
309        unsigned reserved3_7 : 5 ;
310        unsigned sesenddet : 1 ; /*!< 02 Session End Detected */
311        unsigned reserved0_1 : 2 ;
312    } b;
313} gotgint_data_t;
314
315/*!
316 \brief Bit fields of the Core AHB Configuration Register (GAHBCFG).
317 */
318typedef union gahbcfg_data
319{
320    uint32_t d32;
321    struct
322    {
323        unsigned reserved9_31 : 23;
324        unsigned ptxfemplvl : 1 ; /*!< 08 Periodic FIFO empty level trigger condition*/
325        unsigned nptxfemplvl : 1 ; /*!< 07 Non-Periodic FIFO empty level trigger condition*/
326            #define IFXUSB_GAHBCFG_TXFEMPTYLVL_EMPTY 1
327            #define IFXUSB_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
328        unsigned reserved : 1 ;
329        unsigned dmaenable : 1 ; /*!< 05 DMA enable*/
330            #define IFXUSB_GAHBCFG_DMAENABLE 1
331        unsigned hburstlen : 4 ; /*!< 01-04 DMA Burst-length*/
332            #define IFXUSB_GAHBCFG_INT_DMA_BURST_SINGLE 0
333            #define IFXUSB_GAHBCFG_INT_DMA_BURST_INCR 1
334            #define IFXUSB_GAHBCFG_INT_DMA_BURST_INCR4 3
335            #define IFXUSB_GAHBCFG_INT_DMA_BURST_INCR8 5
336            #define IFXUSB_GAHBCFG_INT_DMA_BURST_INCR16 7
337        unsigned glblintrmsk : 1 ; /*!< 00 USB Global Interrupt Enable */
338            #define IFXUSB_GAHBCFG_GLBINT_ENABLE 1
339    } b;
340} gahbcfg_data_t;
341
342/*!
343 \brief Bit fields of the Core USB Configuration Register (GUSBCFG).
344*/
345typedef union gusbcfg_data
346{
347    uint32_t d32;
348    struct
349    {
350        unsigned reserved31 : 1;
351        unsigned ForceDevMode : 1; /*!< 30 Force Device Mode */
352        unsigned ForceHstMode : 1; /*!< 29 Force Host Mode */
353        unsigned TxEndDelay : 1; /*!< 28 Tx End Delay */
354        unsigned reserved2723 : 5;
355        unsigned term_sel_dl_pulse : 1; /*!< 22 TermSel DLine Pulsing Selection */
356        unsigned reserved2117 : 5;
357        unsigned otgutmifssel : 1; /*!< 16 UTMIFS Select */
358        unsigned phylpwrclksel : 1; /*!< 15 PHY Low-Power Clock Select */
359        unsigned reserved14 : 1;
360        unsigned usbtrdtim : 4; /*!< 13-10 USB Turnaround Time */
361        unsigned hnpcap : 1; /*!< 09 HNP-Capable */
362        unsigned srpcap : 1; /*!< 08 SRP-Capable */
363        unsigned reserved07 : 1;
364        unsigned physel : 1; /*!< 06 USB 2.0 High-Speed PHY or
365                                                     USB 1.1 Full-Speed Serial
366                                                     Transceiver Select */
367        unsigned fsintf : 1; /*!< 05 Full-Speed Serial Interface Select */
368        unsigned ulpi_utmi_sel : 1; /*!< 04 ULPI or UTMI+ Select */
369        unsigned phyif : 1; /*!< 03 PHY Interface */
370        unsigned toutcal : 3; /*!< 00-02 HS/FS Timeout Calibration */
371    }b;
372} gusbcfg_data_t;
373
374/*!
375 \brief Bit fields of the Core Reset Register (GRSTCTL).
376 */
377typedef union grstctl_data
378{
379    uint32_t d32;
380    struct
381    {
382        unsigned ahbidle : 1; /*!< 31 AHB Master Idle. Indicates the AHB Master State
383                                             Machine is in IDLE condition. */
384        unsigned dmareq : 1; /*!< 30 DMA Request Signal. Indicated DMA request is in
385                                             probress. Used for debug purpose. */
386        unsigned reserved11_29 :19;
387        unsigned txfnum : 5; /*!< 10-06 TxFIFO Number (TxFNum) to be flushed.
388                                          0x00: Non Periodic TxFIFO Flush or TxFIFO 0
389                                          0x01-0x0F: Periodic TxFIFO Flush or TxFIFO n
390                                          0x10: Flush all TxFIFO
391                                       */
392        unsigned txfflsh : 1; /*!< 05 TxFIFO Flush */
393        unsigned rxfflsh : 1; /*!< 04 RxFIFO Flush */
394        unsigned intknqflsh : 1; /*!< 03 In Token Sequence Learning Queue Flush (Device Only) */
395        unsigned hstfrm : 1; /*!< 02 Host Frame Counter Reset (Host Only) */
396        unsigned hsftrst : 1; /*!< 01 Hclk Soft Reset */
397
398        unsigned csftrst : 1; /*!< 00 Core Soft Reset
399                                             The application can flush the control logic in the
400                                             entire core using this bit. This bit resets the
401                                             pipelines in the AHB Clock domain as well as the
402                                             PHY Clock domain.
403                                             The state machines are reset to an IDLE state, the
404                                             control bits in the CSRs are cleared, all the
405                                             transmit FIFOs and the receive FIFO are flushed.
406                                             The status mask bits that control the generation of
407                                             the interrupt, are cleared, to clear the
408                                             interrupt. The interrupt status bits are not
409                                             cleared, so the application can get the status of
410                                             any events that occurred in the core after it has
411                                             set this bit.
412                                             Any transactions on the AHB are terminated as soon
413                                             as possible following the protocol. Any
414                                             transactions on the USB are terminated immediately.
415                                             The configuration settings in the CSRs are
416                                             unchanged, so the software doesn't have to
417                                             reprogram these registers (Device
418                                             Configuration/Host Configuration/Core System
419                                             Configuration/Core PHY Configuration).
420                                             The application can write to this bit, any time it
421                                             wants to reset the core. This is a self clearing
422                                             bit and the core clears this bit after all the
423                                             necessary logic is reset in the core, which may
424                                             take several clocks, depending on the current state
425                                             of the core.
426                                       */
427    }b;
428} grstctl_t;
429
430/*!
431 \brief Bit fields of the Core Interrupt Mask Register (GINTMSK) and
432        Core Interrupt Register (GINTSTS).
433 */
434typedef union gint_data
435{
436    uint32_t d32;
437        #define IFXUSB_SOF_INTR_MASK 0x0008
438    struct
439    {
440        unsigned wkupintr : 1; /*!< 31 Resume/Remote Wakeup Detected Interrupt */
441        unsigned sessreqintr : 1; /*!< 30 Session Request/New Session Detected Interrupt */
442        unsigned disconnect : 1; /*!< 29 Disconnect Detected Interrupt */
443        unsigned conidstschng : 1; /*!< 28 Connector ID Status Change */
444        unsigned reserved27 : 1;
445        unsigned ptxfempty : 1; /*!< 26 Periodic TxFIFO Empty */
446        unsigned hcintr : 1; /*!< 25 Host Channels Interrupt */
447        unsigned portintr : 1; /*!< 24 Host Port Interrupt */
448        unsigned reserved23 : 1;
449        unsigned fetsuspmsk : 1; /*!< 22 Data Fetch Suspended */
450        unsigned incomplisoout : 1; /*!< 21 Incomplete IsochronousOUT/Period Transfer */
451        unsigned incomplisoin : 1; /*!< 20 Incomplete Isochronous IN Transfer */
452        unsigned outepintr : 1; /*!< 19 OUT Endpoints Interrupt */
453        unsigned inepintr : 1; /*!< 18 IN Endpoints Interrupt */
454        unsigned epmismatch : 1; /*!< 17 Endpoint Mismatch Interrupt */
455        unsigned reserved16 : 1;
456        unsigned eopframe : 1; /*!< 15 End of Periodic Frame Interrupt */
457        unsigned isooutdrop : 1; /*!< 14 Isochronous OUT Packet Dropped Interrupt */
458        unsigned enumdone : 1; /*!< 13 Enumeration Done */
459        unsigned usbreset : 1; /*!< 12 USB Reset */
460        unsigned usbsuspend : 1; /*!< 11 USB Suspend */
461        unsigned erlysuspend : 1; /*!< 10 Early Suspend */
462        unsigned i2cintr : 1; /*!< 09 I2C Interrupt */
463        unsigned reserved8 : 1;
464        unsigned goutnakeff : 1; /*!< 07 Global OUT NAK Effective */
465        unsigned ginnakeff : 1; /*!< 06 Global Non-periodic IN NAK Effective */
466        unsigned nptxfempty : 1; /*!< 05 Non-periodic TxFIFO Empty */
467        unsigned rxstsqlvl : 1; /*!< 04 Receive FIFO Non-Empty */
468        unsigned sofintr : 1; /*!< 03 Start of (u)Frame */
469        unsigned otgintr : 1; /*!< 02 OTG Interrupt */
470        unsigned modemismatch : 1; /*!< 01 Mode Mismatch Interrupt */
471        unsigned reserved0 : 1;
472    } b;
473} gint_data_t;
474
475/*!
476  \brief Bit fields in the Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP)
477 */
478typedef union grxsts_data
479{
480    uint32_t d32;
481    struct
482    {
483        unsigned reserved : 7;
484        unsigned fn : 4; /*!< 24-21 Frame Number */
485        unsigned pktsts : 4; /*!< 20-17 Packet Status */
486            #define IFXUSB_DSTS_DATA_UPDT 0x2 // OUT Data Packet
487            #define IFXUSB_DSTS_XFER_COMP 0x3 // OUT Data Transfer Complete
488            #define IFXUSB_DSTS_GOUT_NAK 0x1 // Global OUT NAK
489            #define IFXUSB_DSTS_SETUP_COMP 0x4 // Setup Phase Complete
490            #define IFXUSB_DSTS_SETUP_UPDT 0x6 // SETUP Packet
491        unsigned dpid : 2; /*!< 16-15 Data PID */
492        unsigned bcnt :11; /*!< 14-04 Byte Count */
493        unsigned epnum : 4; /*!< 03-00 Endpoint Number */
494    } db;
495    struct
496    {
497        unsigned reserved :11;
498        unsigned pktsts : 4; /*!< 20-17 Packet Status */
499            #define IFXUSB_HSTS_DATA_UPDT 0x2 // OUT Data Packet
500            #define IFXUSB_HSTS_XFER_COMP 0x3 // OUT Data Transfer Complete
501            #define IFXUSB_HSTS_DATA_TOGGLE_ERR 0x5 // DATA TOGGLE Error
502            #define IFXUSB_HSTS_CH_HALTED 0x7 // Channel Halted
503        unsigned dpid : 2; /*!< 16-15 Data PID */
504        unsigned bcnt :11; /*!< 14-04 Byte Count */
505        unsigned chnum : 4; /*!< 03-00 Channel Number */
506    } hb;
507} grxsts_data_t;
508
509/*!
510  \brief Bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn).
511 */
512typedef union fifosize_data
513{
514    uint32_t d32;
515    struct
516    {
517        unsigned depth : 16; /*!< 31-16 TxFIFO Depth (in DWord)*/
518        unsigned startaddr : 16; /*!< 15-00 RAM Starting address */
519    } b;
520} fifosize_data_t;
521
522/*!
523  \brief Bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS).
524 */
525
526typedef union gnptxsts_data
527{
528    uint32_t d32;
529    struct
530    {
531        unsigned reserved : 1;
532        unsigned nptxqtop_chnep : 4; /*!< 30-27 Channel/EP Number of top of the Non-Periodic
533                                             Transmit Request Queue
534                                          */
535        unsigned nptxqtop_token : 2; /*!< 26-25 Token Type top of the Non-Periodic
536                                             Transmit Request Queue
537                                              0 - IN/OUT
538                                              1 - Zero Length OUT
539                                              2 - PING/Complete Split
540                                              3 - Channel Halt
541                                          */
542        unsigned nptxqtop_terminate : 1; /*!< 24 Terminate (Last entry for the selected
543                                                   channel/EP)*/
544        unsigned nptxqspcavail : 8; /*!< 23-16 Transmit Request Queue Space Available */
545        unsigned nptxfspcavail :16; /*!< 15-00 TxFIFO Space Avail (in DWord)*/
546    }b;
547} gnptxsts_data_t;
548
549
550/*!
551  \brief Bit fields in the Transmit FIFO Status Register (DTXFSTS).
552 */
553typedef union dtxfsts_data
554{
555    uint32_t d32;
556    struct
557    {
558        unsigned reserved : 16;
559        unsigned txfspcavail : 16; /*!< 15-00 TxFIFO Space Avail (in DWord)*/
560    }b;
561} dtxfsts_data_t;
562
563
564/*!
565  \brief Bit fields in the I2C Control Register (I2CCTL).
566 */
567typedef union gi2cctl_data
568{
569    uint32_t d32;
570    struct
571    {
572        unsigned bsydne : 1; /*!< 31 I2C Busy/Done*/
573        unsigned rw : 1; /*!< 30 Read/Write Indicator */
574        unsigned reserved : 2;
575        unsigned i2cdevaddr : 2; /*!< 27-26 I2C Device Address */
576        unsigned i2csuspctl : 1; /*!< 25 I2C Suspend Control */
577        unsigned ack : 1; /*!< 24 I2C ACK */
578        unsigned i2cen : 1; /*!< 23 I2C Enable */
579        unsigned addr : 7; /*!< 22-16 I2C Address */
580        unsigned regaddr : 8; /*!< 15-08 I2C Register Addr */
581        unsigned rwdata : 8; /*!< I2C Read/Write Data */
582    } b;
583} gi2cctl_data_t;
584
585
586/*!
587  \brief Bit fields in the User HW Config1 Register.
588 */
589typedef union hwcfg1_data
590{
591    uint32_t d32;
592    struct
593    {
594        unsigned ep_dir15 : 2; /*!< Direction of each EP
595                                   0: BIDIR (IN and OUT) endpoint
596                                   1: IN endpoint
597                                   2: OUT endpoint
598                                   3: Reserved
599                                */
600        unsigned ep_dir14 : 2;
601        unsigned ep_dir13 : 2;
602        unsigned ep_dir12 : 2;
603        unsigned ep_dir11 : 2;
604        unsigned ep_dir10 : 2;
605        unsigned ep_dir09 : 2;
606        unsigned ep_dir08 : 2;
607        unsigned ep_dir07 : 2;
608        unsigned ep_dir06 : 2;
609        unsigned ep_dir05 : 2;
610        unsigned ep_dir04 : 2;
611        unsigned ep_dir03 : 2;
612        unsigned ep_dir02 : 2;
613        unsigned ep_dir01 : 2;
614        unsigned ep_dir00 : 2;
615    }b;
616} hwcfg1_data_t;
617
618/*!
619  \brief Bit fields in the User HW Config2 Register.
620 */
621typedef union hwcfg2_data
622{
623    uint32_t d32;
624    struct
625    {
626        unsigned reserved31 : 1;
627        unsigned dev_token_q_depth : 5; /*!< 30-26 Device Mode IN Token Sequence Learning Queue Depth */
628        unsigned host_perio_tx_q_depth : 2; /*!< 25-24 Host Mode Periodic Request Queue Depth */
629        unsigned nonperio_tx_q_depth : 2; /*!< 23-22 Non-periodic Request Queue Depth */
630        unsigned rx_status_q_depth : 2; /*!< 21-20 Multi Processor Interrupt Enabled */
631        unsigned dynamic_fifo : 1; /*!< 19 Dynamic FIFO Sizing Enabled */
632        unsigned perio_ep_supported : 1; /*!< 18 Periodic OUT Channels Supported in Host Mode */
633        unsigned num_host_chan : 4; /*!< 17-14 Number of Host Channels */
634        unsigned num_dev_ep : 4; /*!< 13-10 Number of Device Endpoints */
635        unsigned fs_phy_type : 2; /*!< 09-08 Full-Speed PHY Interface Type */
636            #define IFXUSB_HWCFG2_FS_PHY_TYPE_NOT_SUPPORTED 0
637            #define IFXUSB_HWCFG2_FS_PHY_TYPE_DEDICATE 1
638            #define IFXUSB_HWCFG2_FS_PHY_TYPE_UTMI 2
639            #define IFXUSB_HWCFG2_FS_PHY_TYPE_ULPI 3
640        unsigned hs_phy_type : 2; /*!< 07-06 High-Speed PHY Interface Type */
641            #define IFXUSB_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
642            #define IFXUSB_HWCFG2_HS_PHY_TYPE_UTMI 1
643            #define IFXUSB_HWCFG2_HS_PHY_TYPE_ULPI 2
644            #define IFXUSB_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
645        unsigned point2point : 1; /*!< 05 Point-to-Point */
646        unsigned architecture : 2; /*!< 04-03 Architecture */
647            #define IFXUSB_HWCFG2_ARCH_SLAVE_ONLY 0
648            #define IFXUSB_HWCFG2_ARCH_EXT_DMA 1
649            #define IFXUSB_HWCFG2_ARCH_INT_DMA 2
650        unsigned op_mode : 3; /*!< 02-00 Mode of Operation */
651            #define IFXUSB_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0
652            #define IFXUSB_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
653            #define IFXUSB_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
654            #define IFXUSB_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
655            #define IFXUSB_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
656            #define IFXUSB_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
657            #define IFXUSB_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
658    } b;
659} hwcfg2_data_t;
660
661/*!
662  \brief Bit fields in the User HW Config3 Register.
663 */
664typedef union hwcfg3_data
665{
666    uint32_t d32;
667    struct
668    {
669        unsigned dfifo_depth :16; /*!< 31-16 DFIFO Depth */
670        unsigned reserved15_12 : 4;
671        unsigned synch_reset_type : 1; /*!< 11 Reset Style for Clocked always Blocks in RTL */
672        unsigned optional_features : 1; /*!< 10 Optional Features Removed */
673        unsigned vendor_ctrl_if : 1; /*!< 09 Vendor Control Interface Support */
674        unsigned i2c : 1; /*!< 08 I2C Selection */
675        unsigned otg_func : 1; /*!< 07 OTG Function Enabled */
676        unsigned packet_size_cntr_width : 3; /*!< 06-04 Width of Packet Size Counters */
677        unsigned xfer_size_cntr_width : 4; /*!< 03-00 Width of Transfer Size Counters */
678    } b;
679} hwcfg3_data_t;
680
681/*!
682  \brief Bit fields in the User HW Config4
683 * Register. Read the register into the <i>d32</i> element then read
684 * out the bits using the <i>b</i>it elements.
685 */
686typedef union hwcfg4_data
687{
688    uint32_t d32;
689    struct
690    {
691        unsigned desc_dma_dyn : 1; /*!< 31 Scatter/Gather DMA */
692        unsigned desc_dma : 1; /*!< 30 Scatter/Gather DMA configuration */
693        unsigned num_in_eps : 4; /*!< 29-26 Number of Device Mode IN Endpoints Including Control Endpoints */
694        unsigned ded_fifo_en : 1; /*!< 25 Enable Dedicated Transmit FIFO for device IN Endpoints */
695        unsigned session_end_filt_en : 1; /*!< 24 session_end Filter Enabled */
696        unsigned b_valid_filt_en : 1; /*!< 23 b_valid Filter Enabled */
697        unsigned a_valid_filt_en : 1; /*!< 22 a_valid Filter Enabled */
698        unsigned vbus_valid_filt_en : 1; /*!< 21 vbus_valid Filter Enabled */
699        unsigned iddig_filt_en : 1; /*!< 20 iddig Filter Enable */
700        unsigned num_dev_mode_ctrl_ep : 4; /*!< 19-16 Number of Device Mode Control Endpoints in Addition to Endpoint 0 */
701        unsigned utmi_phy_data_width : 2; /*!< 15-14 UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width */
702        unsigned reserved13_06 : 8;
703        unsigned min_ahb_freq : 1; /*!< 05 Minimum AHB Frequency Less Than 60 MHz */
704        unsigned power_optimiz : 1; /*!< 04 Enable Power Optimization? */
705        unsigned num_dev_perio_in_ep : 4; /*!< 03-00 Number of Device Mode Periodic IN Endpoints */
706    } b;
707} hwcfg4_data_t;
708
709/*@}*//*IFXUSB_CSR_CORE_GLOBAL_REG*/
710
711/****************************************************************************/
712/*!
713  \addtogroup IFXUSB_CSR_DEVICE_GLOBAL_REG
714 */
715/*@{*/
716
717/*!
718 \struct ifxusb_dev_global_regs
719 \brief IFXUSB Device Mode Global registers. Offsets 800h-BFFh
720        The ifxusb_dev_global_regs structure defines the size
721        and relative field offsets for the Device Global registers.
722        These registers are visible only in Device mode and must not be
723        accessed in Host mode, as the results are unknown.
724 */
725typedef struct ifxusb_dev_global_regs
726{
727    volatile uint32_t dcfg; /*!< 800h Device Configuration Register. */
728    volatile uint32_t dctl; /*!< 804h Device Control Register. */
729    volatile uint32_t dsts; /*!< 808h Device Status Register (Read Only). */
730    uint32_t unused;
731    volatile uint32_t diepmsk; /*!< 810h Device IN Endpoint Common Interrupt Mask Register. */
732    volatile uint32_t doepmsk; /*!< 814h Device OUT Endpoint Common Interrupt Mask Register. */
733    volatile uint32_t daint; /*!< 818h Device All Endpoints Interrupt Register. */
734    volatile uint32_t daintmsk; /*!< 81Ch Device All Endpoints Interrupt Mask Register. */
735    volatile uint32_t dtknqr1; /*!< 820h Device IN Token Queue Read Register-1 (Read Only). */
736    volatile uint32_t dtknqr2; /*!< 824h Device IN Token Queue Read Register-2 (Read Only). */
737    volatile uint32_t dvbusdis; /*!< 828h Device VBUS discharge Register.*/
738    volatile uint32_t dvbuspulse; /*!< 82Ch Device VBUS Pulse Register. */
739    volatile uint32_t dtknqr3_dthrctl; /*!< 830h Device IN Token Queue Read Register-3 (Read Only).
740                                                     Device Thresholding control register (Read/Write)
741                                             */
742    volatile uint32_t dtknqr4_fifoemptymsk; /*!< 834h Device IN Token Queue Read Register-4 (Read Only).
743                                                      Device IN EPs empty Inr. Mask Register (Read/Write)
744                                             */
745} ifxusb_device_global_regs_t;
746
747/*!
748  \brief Bit fields in the Device Configuration Register.
749 */
750
751typedef union dcfg_data
752{
753    uint32_t d32;
754    struct
755    {
756        unsigned reserved31_26 : 6;
757        unsigned perschintvl : 2; /*!< 25-24 Periodic Scheduling Interval */
758        unsigned descdma : 1; /*!< 23 Enable Descriptor DMA in Device mode */
759        unsigned epmscnt : 5; /*!< 22-18 In Endpoint Mis-match count */
760        unsigned reserved13_17 : 5;
761        unsigned perfrint : 2; /*!< 12-11 Periodic Frame Interval */
762            #define IFXUSB_DCFG_FRAME_INTERVAL_80 0
763            #define IFXUSB_DCFG_FRAME_INTERVAL_85 1
764            #define IFXUSB_DCFG_FRAME_INTERVAL_90 2
765            #define IFXUSB_DCFG_FRAME_INTERVAL_95 3
766        unsigned devaddr : 7; /*!< 10-04 Device Addresses */
767        unsigned reserved3 : 1;
768        unsigned nzstsouthshk : 1; /*!< 02 Non Zero Length Status OUT Handshake */
769            #define IFXUSB_DCFG_SEND_STALL 1
770        unsigned devspd : 2; /*!< 01-00 Device Speed */
771    } b;
772} dcfg_data_t;
773
774/*!
775  \brief Bit fields in the Device Control Register.
776 */
777typedef union dctl_data
778{
779    uint32_t d32;
780    struct
781    {
782        unsigned reserved16_31 :16;
783        unsigned ifrmnum : 1; /*!< 15 Ignore Frame Number for ISOC EPs */
784        unsigned gmc : 2; /*!< 14-13 Global Multi Count */
785        unsigned gcontbna : 1; /*!< 12 Global Continue on BNA */
786        unsigned pwronprgdone : 1; /*!< 11 Power-On Programming Done */
787        unsigned cgoutnak : 1; /*!< 10 Clear Global OUT NAK */
788        unsigned sgoutnak : 1; /*!< 09 Set Global OUT NAK */
789        unsigned cgnpinnak : 1; /*!< 08 Clear Global Non-Periodic IN NAK */
790        unsigned sgnpinnak : 1; /*!< 07 Set Global Non-Periodic IN NAK */
791        unsigned tstctl : 3; /*!< 06-04 Test Control */
792        unsigned goutnaksts : 1; /*!< 03 Global OUT NAK Status */
793        unsigned gnpinnaksts : 1; /*!< 02 Global Non-Periodic IN NAK Status */
794        unsigned sftdiscon : 1; /*!< 01 Soft Disconnect */
795        unsigned rmtwkupsig : 1; /*!< 00 Remote Wakeup */
796    } b;
797} dctl_data_t;
798
799
800/*!
801  \brief Bit fields in the Device Status Register.
802 */
803typedef union dsts_data
804{
805    uint32_t d32;
806    struct
807    {
808        unsigned reserved22_31 :10;
809        unsigned soffn :14; /*!< 21-08 Frame or Microframe Number of the received SOF */
810        unsigned reserved4_7 : 4;
811        unsigned errticerr : 1; /*!< 03 Erratic Error */
812        unsigned enumspd : 2; /*!< 02-01 Enumerated Speed */
813            #define IFXUSB_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
814            #define IFXUSB_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
815            #define IFXUSB_DSTS_ENUMSPD_LS_PHY_6MHZ 2
816            #define IFXUSB_DSTS_ENUMSPD_FS_PHY_48MHZ 3
817        unsigned suspsts : 1; /*!< 00 Suspend Status */
818    } b;
819} dsts_data_t;
820
821/*!
822  \brief Bit fields in the Device IN EP Interrupt Register
823         and the Device IN EP Common Mask Register.
824 */
825typedef union diepint_data
826{
827    uint32_t d32;
828    struct
829    {
830        unsigned reserved14_31 :18;
831        unsigned nakmsk : 1; /*!< 13 NAK interrupt Mask */
832        unsigned reserved10_12 : 3;
833        unsigned bna : 1; /*!< 09 BNA Interrupt mask */
834        unsigned txfifoundrn : 1; /*!< 08 Fifo Underrun Mask */
835        unsigned emptyintr : 1; /*!< 07 IN Endpoint HAK Effective mask */
836        unsigned inepnakeff : 1; /*!< 06 IN Endpoint HAK Effective mask */
837        unsigned intknepmis : 1; /*!< 05 IN Token Received with EP mismatch mask */
838        unsigned intktxfemp : 1; /*!< 04 IN Token received with TxF Empty mask */
839        unsigned timeout : 1; /*!< 03 TimeOUT Handshake mask (non-ISOC EPs) */
840        unsigned ahberr : 1; /*!< 02 AHB Error mask */
841        unsigned epdisabled : 1; /*!< 01 Endpoint disable mask */
842        unsigned xfercompl : 1; /*!< 00 Transfer complete mask */
843    } b;
844} diepint_data_t;
845
846
847/*!
848  \brief Bit fields in the Device OUT EP Interrupt Register and
849         Device OUT EP Common Interrupt Mask Register.
850  */
851typedef union doepint_data
852{
853    uint32_t d32;
854    struct
855    {
856        unsigned reserved15_31 :17;
857        unsigned nyetmsk : 1; /*!< 14 NYET Interrupt */
858        unsigned nakmsk : 1; /*!< 13 NAK Interrupt */
859        unsigned bbleerrmsk : 1; /*!< 12 Babble Interrupt */
860        unsigned reserved10_11 : 2;
861        unsigned bna : 1; /*!< 09 BNA Interrupt */
862        unsigned outpkterr : 1; /*!< 08 OUT packet Error */
863        unsigned reserved07 : 1;
864        unsigned back2backsetup : 1; /*!< 06 Back-to-Back SETUP Packets Received */
865        unsigned stsphsercvd : 1; /*!< 05 */
866        unsigned outtknepdis : 1; /*!< 04 OUT Token Received when Endpoint Disabled */
867        unsigned setup : 1; /*!< 03 Setup Phase Done (contorl EPs) */
868        unsigned ahberr : 1; /*!< 02 AHB Error */
869        unsigned epdisabled : 1; /*!< 01 Endpoint disable */
870        unsigned xfercompl : 1; /*!< 00 Transfer complete */
871    } b;
872} doepint_data_t;
873
874
875/*!
876  \brief Bit fields in the Device All EP Interrupt Registers.
877 */
878typedef union daint_data
879{
880    uint32_t d32;
881    struct
882    {
883        unsigned out : 16; /*!< 31-16 OUT Endpoint bits */
884        unsigned in : 16; /*!< 15-00 IN Endpoint bits */
885    } eps;
886    struct
887    {
888        /** OUT Endpoint bits */
889        unsigned outep15 : 1;
890        unsigned outep14 : 1;
891        unsigned outep13 : 1;
892        unsigned outep12 : 1;
893        unsigned outep11 : 1;
894        unsigned outep10 : 1;
895        unsigned outep09 : 1;
896        unsigned outep08 : 1;
897        unsigned outep07 : 1;
898        unsigned outep06 : 1;
899        unsigned outep05 : 1;
900        unsigned outep04 : 1;
901        unsigned outep03 : 1;
902        unsigned outep02 : 1;
903        unsigned outep01 : 1;
904        unsigned outep00 : 1;
905        /** IN Endpoint bits */
906        unsigned inep15 : 1;
907        unsigned inep14 : 1;
908        unsigned inep13 : 1;
909        unsigned inep12 : 1;
910        unsigned inep11 : 1;
911        unsigned inep10 : 1;
912        unsigned inep09 : 1;
913        unsigned inep08 : 1;
914        unsigned inep07 : 1;
915        unsigned inep06 : 1;
916        unsigned inep05 : 1;
917        unsigned inep04 : 1;
918        unsigned inep03 : 1;
919        unsigned inep02 : 1;
920        unsigned inep01 : 1;
921        unsigned inep00 : 1;
922    } ep;
923} daint_data_t;
924
925
926/*!
927  \brief Bit fields in the Device IN Token Queue Read Registers.
928 */
929typedef union dtknq1_data
930{
931    uint32_t d32;
932    struct
933    {
934        unsigned epnums0_5 :24; /*!< 31-08 EP Numbers of IN Tokens 0 ... 4 */
935        unsigned wrap_bit : 1; /*!< 07 write pointer has wrapped */
936        unsigned reserved05_06 : 2;
937        unsigned intknwptr : 5; /*!< 04-00 In Token Queue Write Pointer */
938    }b;
939} dtknq1_data_t;
940
941
942/*!
943  \brief Bit fields in Threshold control Register
944 */
945typedef union dthrctl_data
946{
947    uint32_t d32;
948    struct
949    {
950        unsigned reserved26_31 : 6;
951        unsigned rx_thr_len : 9; /*!< 25-17 Rx Thr. Length */
952        unsigned rx_thr_en : 1; /*!< 16 Rx Thr. Enable */
953        unsigned reserved11_15 : 5;
954        unsigned tx_thr_len : 9; /*!< 10-02 Tx Thr. Length */
955        unsigned iso_thr_en : 1; /*!< 01 ISO Tx Thr. Enable */
956        unsigned non_iso_thr_en : 1; /*!< 00 non ISO Tx Thr. Enable */
957    } b;
958} dthrctl_data_t;
959
960/*@}*//*IFXUSB_CSR_DEVICE_GLOBAL_REG*/
961
962/****************************************************************************/
963
964/*!
965  \addtogroup IFXUSB_CSR_DEVICE_EP_REG
966 */
967/*@{*/
968
969/*!
970  \struct ifxusb_dev_in_ep_regs
971  \brief Device Logical IN Endpoint-Specific Registers.
972   There will be one set of endpoint registers per logical endpoint
973   implemented.
974   each EP's IN EP Register are offset at :
975           900h + * (ep_num * 20h)
976 */
977
978typedef struct ifxusb_dev_in_ep_regs
979{
980    volatile uint32_t diepctl; /*!< 00h: Endpoint Control Register */
981    uint32_t reserved04; /*!< 04h: */
982    volatile uint32_t diepint; /*!< 08h: Endpoint Interrupt Register */
983    uint32_t reserved0C; /*!< 0Ch: */
984    volatile uint32_t dieptsiz; /*!< 10h: Endpoint Transfer Size Register.*/
985    volatile uint32_t diepdma; /*!< 14h: Endpoint DMA Address Register. */
986    volatile uint32_t dtxfsts; /*!< 18h: Endpoint Transmit FIFO Status Register. */
987    volatile uint32_t diepdmab; /*!< 1Ch: Endpoint DMA Buffer Register. */
988} ifxusb_dev_in_ep_regs_t;
989
990/*!
991  \brief Device Logical OUT Endpoint-Specific Registers.
992   There will be one set of endpoint registers per logical endpoint
993   implemented.
994   each EP's OUT EP Register are offset at :
995           B00h + * (ep_num * 20h) + 00h
996 */
997typedef struct ifxusb_dev_out_ep_regs
998{
999    volatile uint32_t doepctl; /*!< 00h: Endpoint Control Register */
1000    volatile uint32_t doepfn; /*!< 04h: Endpoint Frame number Register */
1001    volatile uint32_t doepint; /*!< 08h: Endpoint Interrupt Register */
1002    uint32_t reserved0C; /*!< 0Ch: */
1003    volatile uint32_t doeptsiz; /*!< 10h: Endpoint Transfer Size Register.*/
1004    volatile uint32_t doepdma; /*!< 14h: Endpoint DMA Address Register. */
1005    uint32_t reserved18; /*!< 18h: */
1006    volatile uint32_t doepdmab; /*!< 1Ch: Endpoint DMA Buffer Register. */
1007} ifxusb_dev_out_ep_regs_t;
1008
1009
1010/*!
1011  \brief Bit fields in the Device EP Control
1012  Register.
1013 */
1014typedef union depctl_data
1015{
1016    uint32_t d32;
1017    struct
1018    {
1019        unsigned epena : 1; /*!< 31 Endpoint Enable */
1020        unsigned epdis : 1; /*!< 30 Endpoint Disable */
1021        unsigned setd1pid : 1; /*!< 29 Set DATA1 PID (INTR/Bulk IN and OUT endpoints) */
1022        unsigned setd0pid : 1; /*!< 28 Set DATA0 PID (INTR/Bulk IN and OUT endpoints) */
1023        unsigned snak : 1; /*!< 27 Set NAK */
1024        unsigned cnak : 1; /*!< 26 Clear NAK */
1025        unsigned txfnum : 4; /*!< 25-22 Tx Fifo Number */
1026        unsigned stall : 1; /*!< 21 Stall Handshake */
1027        unsigned snp : 1; /*!< 20 Snoop Mode */
1028        unsigned eptype : 2; /*!< 19-18 Endpoint Type
1029                                          0: Control
1030                                          1: Isochronous
1031                                          2: Bulk
1032                                          3: Interrupt
1033                                 */
1034        unsigned naksts : 1; /*!< 17 NAK Status */
1035        unsigned dpid : 1; /*!< 16 Endpoint DPID (INTR/Bulk IN and OUT endpoints) */
1036        unsigned usbactep : 1; /*!< 15 USB Active Endpoint */
1037        unsigned nextep : 4; /*!< 14-11 Next Endpoint */
1038        unsigned mps :11; /*!< 10-00 Maximum Packet Size */
1039            #define IFXUSB_DEP0CTL_MPS_64 0
1040            #define IFXUSB_DEP0CTL_MPS_32 1
1041            #define IFXUSB_DEP0CTL_MPS_16 2
1042            #define IFXUSB_DEP0CTL_MPS_8 3
1043    } b;
1044} depctl_data_t;
1045
1046
1047/*!
1048  \brief Bit fields in the Device EP Transfer Size Register. (EP0 and EPn)
1049 */
1050typedef union deptsiz_data
1051{
1052    uint32_t d32;
1053    struct
1054    {
1055        unsigned reserved31 : 1;
1056        unsigned supcnt : 2; /*!< 30-29 Setup Packet Count */
1057        unsigned reserved20_28 : 9;
1058        unsigned pktcnt : 1; /*!< 19 Packet Count */
1059        unsigned reserved7_18 :12;
1060        unsigned xfersize : 7; /*!< 06-00 Transfer size */
1061    }b0;
1062    struct
1063    {
1064        unsigned reserved : 1;
1065        unsigned mc : 2; /*!< 30-29 Multi Count */
1066        unsigned pktcnt :10; /*!< 28-19 Packet Count */
1067        unsigned xfersize :19; /*!< 18-00 Transfer size */
1068    } b;
1069} deptsiz_data_t;
1070
1071/*@}*//*IFXUSB_CSR_DEVICE_EP_REG*/
1072/****************************************************************************/
1073
1074/*!
1075  \addtogroup IFXUSB_CSR_DEVICE_DMA_DESC
1076 */
1077/*@{*/
1078/*!
1079  \struct desc_sts_data
1080  \brief Bit fields in the DMA Descriptor status quadlet.
1081 */
1082typedef union desc_sts_data
1083{
1084    struct
1085    {
1086        unsigned bs : 2; /*!< 31-30 Buffer Status */
1087            #define BS_HOST_READY 0x0
1088            #define BS_DMA_BUSY 0x1
1089            #define BS_DMA_DONE 0x2
1090            #define BS_HOST_BUSY 0x3
1091        unsigned sts : 2; /*!< 29-28 Receive/Trasmit Status */
1092            #define RTS_SUCCESS 0x0
1093            #define RTS_BUFFLUSH 0x1
1094            #define RTS_RESERVED 0x2
1095            #define RTS_BUFERR 0x3
1096        unsigned l : 1; /*!< 27 Last */
1097        unsigned sp : 1; /*!< 26 Short Packet */
1098        unsigned ioc : 1; /*!< 25 Interrupt On Complete */
1099        unsigned sr : 1; /*!< 24 Setup Packet received */
1100        unsigned mtrf : 1; /*!< 23 Multiple Transfer */
1101        unsigned reserved16_22 : 7;
1102        unsigned bytes :16; /*!< 15-00 Transfer size in bytes */
1103    } b;
1104    uint32_t d32; /*!< DMA Descriptor data buffer pointer */
1105} desc_sts_data_t;
1106
1107/*@}*//*IFXUSB_CSR_DEVICE_DMA_DESC*/
1108/****************************************************************************/
1109
1110/*!
1111  \addtogroup IFXUSB_CSR_HOST_GLOBAL_REG
1112 */
1113/*@{*/
1114/*!
1115 \struct ifxusb_host_global_regs
1116 \brief IFXUSB Host Mode Global registers. Offsets 400h-7FFh
1117        The ifxusb_host_global_regs structure defines the size
1118        and relative field offsets for the Host Global registers.
1119        These registers are visible only in Host mode and must not be
1120        accessed in Device mode, as the results are unknown.
1121 */
1122typedef struct ifxusb_host_global_regs
1123{
1124    volatile uint32_t hcfg; /*!< 400h Host Configuration Register. */
1125    volatile uint32_t hfir; /*!< 404h Host Frame Interval Register. */
1126    volatile uint32_t hfnum; /*!< 408h Host Frame Number / Frame Remaining Register. */
1127    uint32_t reserved40C;
1128    volatile uint32_t hptxsts; /*!< 410h Host Periodic Transmit FIFO/ Queue Status Register. */
1129    volatile uint32_t haint; /*!< 414h Host All Channels Interrupt Register. */
1130    volatile uint32_t haintmsk; /*!< 418h Host All Channels Interrupt Mask Register. */
1131} ifxusb_host_global_regs_t;
1132
1133/*!
1134  \brief Bit fields in the Host Configuration Register.
1135 */
1136typedef union hcfg_data
1137{
1138    uint32_t d32;
1139    struct
1140    {
1141        unsigned reserved31_03 :29;
1142        unsigned fslssupp : 1; /*!< 02 FS/LS Only Support */
1143        unsigned fslspclksel : 2; /*!< 01-00 FS/LS Phy Clock Select */
1144            #define IFXUSB_HCFG_30_60_MHZ 0
1145            #define IFXUSB_HCFG_48_MHZ 1
1146            #define IFXUSB_HCFG_6_MHZ 2
1147    } b;
1148} hcfg_data_t;
1149
1150/*!
1151  \brief Bit fields in the Host Frame Interval Register.
1152 */
1153typedef union hfir_data
1154{
1155    uint32_t d32;
1156    struct
1157    {
1158        unsigned reserved : 16;
1159        unsigned frint : 16; /*!< 15-00 Frame Interval */
1160    } b;
1161} hfir_data_t;
1162
1163/*!
1164 \brief Bit fields in the Host Frame Time Remaing/Number Register.
1165 */
1166typedef union hfnum_data
1167{
1168    uint32_t d32;
1169    struct
1170    {
1171        unsigned frrem : 16; /*!< 31-16 Frame Time Remaining */
1172        unsigned frnum : 16; /*!< 15-00 Frame Number*/
1173            #define IFXUSB_HFNUM_MAX_FRNUM 0x3FFF
1174    } b;
1175} hfnum_data_t;
1176
1177/*!
1178  \brief Bit fields in the Host Periodic Transmit FIFO/Queue Status Register
1179 */
1180typedef union hptxsts_data
1181{
1182    /** raw register data */
1183    uint32_t d32;
1184    struct
1185    {
1186        /** Top of the Periodic Transmit Request Queue
1187         * - bit 24 - Terminate (last entry for the selected channel)
1188         */
1189        unsigned ptxqtop_odd : 1; /*!< 31 Top of the Periodic Transmit Request
1190                                                  Queue Odd/even microframe*/
1191        unsigned ptxqtop_chnum : 4; /*!< 30-27 Top of the Periodic Transmit Request
1192                                                  Channel Number */
1193        unsigned ptxqtop_token : 2; /*!< 26-25 Top of the Periodic Transmit Request
1194                                                  Token Type
1195                                                  0 - Zero length
1196                                                  1 - Ping
1197                                                  2 - Disable
1198                                         */
1199        unsigned ptxqtop_terminate : 1; /*!< 24 Top of the Periodic Transmit Request
1200                                                  Terminate (last entry for the selected channel)*/
1201        unsigned ptxqspcavail : 8; /*!< 23-16 Periodic Transmit Request Queue Space Available */
1202        unsigned ptxfspcavail :16; /*!< 15-00 Periodic Transmit Data FIFO Space Available */
1203    } b;
1204} hptxsts_data_t;
1205
1206/*!
1207  \brief Bit fields in the Host Port Control and Status Register.
1208 */
1209typedef union hprt0_data
1210{
1211    uint32_t d32;
1212    struct
1213    {
1214        unsigned reserved19_31 :13;
1215        unsigned prtspd : 2; /*!< 18-17 Port Speed */
1216            #define IFXUSB_HPRT0_PRTSPD_HIGH_SPEED 0
1217            #define IFXUSB_HPRT0_PRTSPD_FULL_SPEED 1
1218            #define IFXUSB_HPRT0_PRTSPD_LOW_SPEED 2
1219        unsigned prttstctl : 4; /*!< 16-13 Port Test Control */
1220        unsigned prtpwr : 1; /*!< 12 Port Power */
1221        unsigned prtlnsts : 2; /*!< 11-10 Port Line Status */
1222        unsigned reserved9 : 1;
1223        unsigned prtrst : 1; /*!< 08 Port Reset */
1224        unsigned prtsusp : 1; /*!< 07 Port Suspend */
1225        unsigned prtres : 1; /*!< 06 Port Resume */
1226        unsigned prtovrcurrchng : 1; /*!< 05 Port Overcurrent Change */
1227        unsigned prtovrcurract : 1; /*!< 04 Port Overcurrent Active */
1228        unsigned prtenchng : 1; /*!< 03 Port Enable/Disable Change */
1229        unsigned prtena : 1; /*!< 02 Port Enable */
1230        unsigned prtconndet : 1; /*!< 01 Port Connect Detected */
1231        unsigned prtconnsts : 1; /*!< 00 Port Connect Status */
1232    }b;
1233} hprt0_data_t;
1234
1235/*!
1236  \brief Bit fields in the Host All Interrupt Register.
1237 */
1238typedef union haint_data
1239{
1240    uint32_t d32;
1241    struct
1242    {
1243        unsigned reserved : 16;
1244        unsigned ch15 : 1;
1245        unsigned ch14 : 1;
1246        unsigned ch13 : 1;
1247        unsigned ch12 : 1;
1248        unsigned ch11 : 1;
1249        unsigned ch10 : 1;
1250        unsigned ch09 : 1;
1251        unsigned ch08 : 1;
1252        unsigned ch07 : 1;
1253        unsigned ch06 : 1;
1254        unsigned ch05 : 1;
1255        unsigned ch04 : 1;
1256        unsigned ch03 : 1;
1257        unsigned ch02 : 1;
1258        unsigned ch01 : 1;
1259        unsigned ch00 : 1;
1260    } b;
1261    struct
1262    {
1263        unsigned reserved : 16;
1264        unsigned chint : 16;
1265    } b2;
1266} haint_data_t;
1267/*@}*//*IFXUSB_CSR_HOST_GLOBAL_REG*/
1268/****************************************************************************/
1269/*!
1270  \addtogroup IFXUSB_CSR_HOST_HC_REG
1271 */
1272/*@{*/
1273/*!
1274  \brief Host Channel Specific Registers
1275   There will be one set of hc registers per host channelimplemented.
1276   each HC's Register are offset at :
1277           500h + * (hc_num * 20h)
1278 */
1279typedef struct ifxusb_hc_regs
1280{
1281    volatile uint32_t hcchar; /*!< 00h Host Channel Characteristic Register.*/
1282    volatile uint32_t hcsplt; /*!< 04h Host Channel Split Control Register.*/
1283    volatile uint32_t hcint; /*!< 08h Host Channel Interrupt Register. */
1284    volatile uint32_t hcintmsk; /*!< 0Ch Host Channel Interrupt Mask Register. */
1285    volatile uint32_t hctsiz; /*!< 10h Host Channel Transfer Size Register. */
1286    volatile uint32_t hcdma; /*!< 14h Host Channel DMA Address Register. */
1287    uint32_t reserved[2]; /*!< 18h Reserved. */
1288} ifxusb_hc_regs_t;
1289
1290
1291/*!
1292  \brief Bit fields in the Host Channel Characteristics Register.
1293 */
1294typedef union hcchar_data
1295{
1296    uint32_t d32;
1297    struct
1298    {
1299        unsigned chen : 1; /*!< 31 Channel enable */
1300        unsigned chdis : 1; /*!< 30 Channel disable */
1301        unsigned oddfrm : 1; /*!< 29 Frame to transmit periodic transaction */
1302        unsigned devaddr : 7; /*!< 28-22 Device address */
1303        unsigned multicnt : 2; /*!< 21-20 Packets per frame for periodic transfers */
1304        unsigned eptype : 2; /*!< 19-18 0: Control, 1: Isoc, 2: Bulk, 3: Intr */
1305        unsigned lspddev : 1; /*!< 17 0: Full/high speed device, 1: Low speed device */
1306        unsigned reserved : 1;
1307        unsigned epdir : 1; /*!< 15 0: OUT, 1: IN */
1308        unsigned epnum : 4; /*!< 14-11 Endpoint number */
1309        unsigned mps :11; /*!< 10-00 Maximum packet size in bytes */
1310    } b;
1311} hcchar_data_t;
1312
1313/*!
1314  \brief Bit fields in the Host Channel Split Control Register
1315 */
1316typedef union hcsplt_data
1317{
1318    uint32_t d32;
1319    struct
1320    {
1321        unsigned spltena : 1; /*!< 31 Split Enble */
1322        unsigned reserved :14;
1323        unsigned compsplt : 1; /*!< 16 Do Complete Split */
1324        unsigned xactpos : 2; /*!< 15-14 Transaction Position */
1325            #define IFXUSB_HCSPLIT_XACTPOS_MID 0
1326            #define IFXUSB_HCSPLIT_XACTPOS_END 1
1327            #define IFXUSB_HCSPLIT_XACTPOS_BEGIN 2
1328            #define IFXUSB_HCSPLIT_XACTPOS_ALL 3
1329        unsigned hubaddr : 7; /*!< 13-07 Hub Address */
1330        unsigned prtaddr : 7; /*!< 06-00 Port Address */
1331    } b;
1332} hcsplt_data_t;
1333
1334/*!
1335  \brief Bit fields in the Host Interrupt Register.
1336 */
1337typedef union hcint_data
1338{
1339    uint32_t d32;
1340    struct
1341    {
1342        unsigned reserved :21;
1343        unsigned datatglerr : 1; /*!< 10 Data Toggle Error */
1344        unsigned frmovrun : 1; /*!< 09 Frame Overrun */
1345        unsigned bblerr : 1; /*!< 08 Babble Error */
1346        unsigned xacterr : 1; /*!< 07 Transaction Err */
1347        unsigned nyet : 1; /*!< 06 NYET Response Received */
1348        unsigned ack : 1; /*!< 05 ACK Response Received */
1349        unsigned nak : 1; /*!< 04 NAK Response Received */
1350        unsigned stall : 1; /*!< 03 STALL Response Received */
1351        unsigned ahberr : 1; /*!< 02 AHB Error */
1352        unsigned chhltd : 1; /*!< 01 Channel Halted */
1353        unsigned xfercomp : 1; /*!< 00 Channel Halted */
1354    }b;
1355} hcint_data_t;
1356
1357
1358/*!
1359 \brief Bit fields in the Host Channel Transfer Size
1360  Register.
1361 */
1362typedef union hctsiz_data
1363{
1364    uint32_t d32;
1365    struct
1366    {
1367        /** */
1368        unsigned dopng : 1; /*!< 31 Do PING protocol when 1 */
1369        /**
1370         * Packet ID for next data packet
1371         * 0: DATA0
1372         * 1: DATA2
1373         * 2: DATA1
1374         * 3: MDATA (non-Control), SETUP (Control)
1375         */
1376        unsigned pid : 2; /*!< 30-29 Packet ID for next data packet
1377                                          0: DATA0
1378                                          1: DATA2
1379                                          2: DATA1
1380                                          3: MDATA (non-Control), SETUP (Control)
1381                                 */
1382            #define IFXUSB_HCTSIZ_DATA0 0
1383            #define IFXUSB_HCTSIZ_DATA1 2
1384            #define IFXUSB_HCTSIZ_DATA2 1
1385            #define IFXUSB_HCTSIZ_MDATA 3
1386            #define IFXUSB_HCTSIZ_SETUP 3
1387        unsigned pktcnt :10; /*!< 28-19 Data packets to transfer */
1388        unsigned xfersize :19; /*!< 18-00 Total transfer size in bytes */
1389    }b;
1390} hctsiz_data_t;
1391
1392/*@}*//*IFXUSB_CSR_HOST_HC_REG*/
1393
1394/****************************************************************************/
1395
1396/*!
1397  \addtogroup IFXUSB_CSR_PWR_CLK_GATING_REG
1398 */
1399/*@{*/
1400/*!
1401  \brief Bit fields in the Power and Clock Gating Control Register
1402 */
1403typedef union pcgcctl_data
1404{
1405    uint32_t d32;
1406    struct
1407    {
1408        unsigned reserved : 27;
1409        unsigned physuspended : 1; /*!< 04 PHY Suspended */
1410        unsigned rstpdwnmodule : 1; /*!< 03 Reset Power Down Modules */
1411        unsigned pwrclmp : 1; /*!< 02 Power Clamp */
1412        unsigned gatehclk : 1; /*!< 01 Gate Hclk */
1413        unsigned stoppclk : 1; /*!< 00 Stop Pclk */
1414    } b;
1415} pcgcctl_data_t;
1416/*@}*//*IFXUSB_CSR_PWR_CLK_GATING_REG*/
1417
1418/****************************************************************************/
1419
1420#endif //__IFXUSB_REGS_H__
1421

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