Root/target/linux/lantiq/patches-3.3/0002-xway-support.patch

1From cf678877a86e03302686d0364c982d573daa6e2c Mon Sep 17 00:00:00 2001
2From: John Crispin <blogic@openwrt.org>
3Date: Fri, 3 Aug 2012 09:49:04 +0200
4Subject: [PATCH 02/25] xway support
5
6---
7 .../mips/include/asm/mach-lantiq/xway/lantiq_irq.h | 31 +--
8 .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 96 +++++++--
9 arch/mips/lantiq/xway/Kconfig | 21 ++
10 arch/mips/lantiq/xway/Makefile | 5 +-
11 arch/mips/lantiq/xway/clk-ase.c | 48 -----
12 arch/mips/lantiq/xway/clk-xway.c | 223 --------------------
13 arch/mips/lantiq/xway/devices.c | 72 ++++---
14 arch/mips/lantiq/xway/devices.h | 2 +
15 arch/mips/lantiq/xway/dma.c | 27 +--
16 arch/mips/lantiq/xway/ebu.c | 52 -----
17 arch/mips/lantiq/xway/gpio.c | 92 +++++++--
18 arch/mips/lantiq/xway/gpio_ebu.c | 3 +-
19 arch/mips/lantiq/xway/gpio_stp.c | 49 +++--
20 arch/mips/lantiq/xway/mach-easy50601.c | 15 +-
21 arch/mips/lantiq/xway/mach-easy50712.c | 17 +-
22 arch/mips/lantiq/xway/pmu.c | 69 ------
23 arch/mips/lantiq/xway/prom-ase.c | 39 ----
24 arch/mips/lantiq/xway/prom-xway.c | 54 -----
25 arch/mips/lantiq/xway/reset.c | 92 ++++++---
26 arch/mips/lantiq/xway/setup-ase.c | 19 --
27 arch/mips/lantiq/xway/setup-xway.c | 20 --
28 21 files changed, 349 insertions(+), 697 deletions(-)
29 delete mode 100644 arch/mips/lantiq/xway/clk-ase.c
30 delete mode 100644 arch/mips/lantiq/xway/clk-xway.c
31 delete mode 100644 arch/mips/lantiq/xway/ebu.c
32 delete mode 100644 arch/mips/lantiq/xway/pmu.c
33 delete mode 100644 arch/mips/lantiq/xway/prom-ase.c
34 delete mode 100644 arch/mips/lantiq/xway/prom-xway.c
35 delete mode 100644 arch/mips/lantiq/xway/setup-ase.c
36 delete mode 100644 arch/mips/lantiq/xway/setup-xway.c
37
38diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
39index b4465a8..4f69ff0 100644
40--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
41+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
42@@ -9,6 +9,8 @@
43 #ifndef _LANTIQ_XWAY_IRQ_H__
44 #define _LANTIQ_XWAY_IRQ_H__
45 
46+#define IM_NUM 5
47+
48 #define INT_NUM_IRQ0 8
49 #define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
50 #define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32)
51@@ -27,37 +29,26 @@
52 
53 #define LTQ_SSC_TIR (INT_NUM_IM0_IRL0 + 15)
54 #define LTQ_SSC_RIR (INT_NUM_IM0_IRL0 + 14)
55+#define LTQ_SSC_TIR_AR9 (INT_NUM_IM0_IRL0 + 14)
56+#define LTQ_SSC_RIR_AR9 (INT_NUM_IM0_IRL0 + 15)
57 #define LTQ_SSC_EIR (INT_NUM_IM0_IRL0 + 16)
58+#define LTQ_SSC_RIR_ASE (INT_NUM_IM0_IRL0 + 16)
59+#define LTQ_SSC_TIR_ASE (INT_NUM_IM0_IRL0 + 17)
60+#define LTQ_SSC_EIR_ASE (INT_NUM_IM0_IRL0 + 18)
61+#define LTQ_SSC_FIR_ASE (INT_NUM_IM0_IRL0 + 19)
62 
63 #define LTQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21)
64 #define LTQ_MEI_INT (INT_NUM_IM1_IRL0 + 23)
65 
66 #define LTQ_TIMER6_INT (INT_NUM_IM1_IRL0 + 23)
67 #define LTQ_USB_INT (INT_NUM_IM1_IRL0 + 22)
68+#define LTQ_USB_ASE_INT (INT_NUM_IM0_IRL0 + 31)
69 #define LTQ_USB_OC_INT (INT_NUM_IM4_IRL0 + 23)
70 
71 #define MIPS_CPU_TIMER_IRQ 7
72 
73-#define LTQ_DMA_CH0_INT (INT_NUM_IM2_IRL0)
74-#define LTQ_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1)
75-#define LTQ_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2)
76-#define LTQ_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3)
77-#define LTQ_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4)
78-#define LTQ_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5)
79-#define LTQ_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6)
80-#define LTQ_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7)
81-#define LTQ_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8)
82-#define LTQ_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9)
83-#define LTQ_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10)
84-#define LTQ_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11)
85-#define LTQ_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25)
86-#define LTQ_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26)
87-#define LTQ_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27)
88-#define LTQ_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28)
89-#define LTQ_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29)
90-#define LTQ_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30)
91-#define LTQ_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16)
92-#define LTQ_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21)
93+#define LTQ_DMA_ETOP ((ltq_is_ase()) ? \
94+ (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0))
95 
96 #define LTQ_PPE_MBOX_INT (INT_NUM_IM2_IRL0 + 24)
97 
98diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
99index 8a3c6be..1ec8f2a 100644
100--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
101+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
102@@ -17,23 +17,44 @@
103 #define SOC_ID_DANUBE1 0x129
104 #define SOC_ID_DANUBE2 0x12B
105 #define SOC_ID_TWINPASS 0x12D
106-#define SOC_ID_AMAZON_SE 0x152
107+#define SOC_ID_AMAZON_SE_1 0x152 /* 50601 */
108+#define SOC_ID_AMAZON_SE_2 0x153 /* 50600 */
109 #define SOC_ID_ARX188 0x16C
110-#define SOC_ID_ARX168 0x16D
111+#define SOC_ID_ARX168_1 0x16D
112+#define SOC_ID_ARX168_2 0x16E
113 #define SOC_ID_ARX182 0x16F
114+#define SOC_ID_GRX188 0x170
115+#define SOC_ID_GRX168 0x171
116+
117+#define SOC_ID_VRX288 0x1C0 /* v1.1 */
118+#define SOC_ID_VRX282 0x1C1 /* v1.1 */
119+#define SOC_ID_VRX268 0x1C2 /* v1.1 */
120+#define SOC_ID_GRX268 0x1C8 /* v1.1 */
121+#define SOC_ID_GRX288 0x1C9 /* v1.1 */
122+#define SOC_ID_VRX288_2 0x00B /* v1.2 */
123+#define SOC_ID_VRX268_2 0x00C /* v1.2 */
124+#define SOC_ID_GRX288_2 0x00D /* v1.2 */
125+#define SOC_ID_GRX282_2 0x00E /* v1.2 */
126 
127 /* SoC Types */
128 #define SOC_TYPE_DANUBE 0x01
129 #define SOC_TYPE_TWINPASS 0x02
130 #define SOC_TYPE_AR9 0x03
131-#define SOC_TYPE_VR9 0x04
132-#define SOC_TYPE_AMAZON_SE 0x05
133+#define SOC_TYPE_VR9_1 0x04 /* v1.1 */
134+#define SOC_TYPE_VR9_2 0x05 /* v1.2 */
135+#define SOC_TYPE_AMAZON_SE 0x06
136 
137 /* ASC0/1 - serial port */
138 #define LTQ_ASC0_BASE_ADDR 0x1E100400
139 #define LTQ_ASC1_BASE_ADDR 0x1E100C00
140 #define LTQ_ASC_SIZE 0x400
141 
142+/*
143+ * during early_printk no ioremap is possible
144+ * lets use KSEG1 instead
145+ */
146+#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
147+
148 /* RCU - reset control unit */
149 #define LTQ_RCU_BASE_ADDR 0x1F203000
150 #define LTQ_RCU_SIZE 0x1000
151@@ -61,6 +82,8 @@
152 #define LTQ_CGU_BASE_ADDR 0x1F103000
153 #define LTQ_CGU_SIZE 0x1000
154 
155+#define CGU_EPHY 0x10
156+
157 /* ICU - interrupt control unit */
158 #define LTQ_ICU_BASE_ADDR 0x1F880200
159 #define LTQ_ICU_SIZE 0x100
160@@ -73,18 +96,14 @@
161 #define LTQ_PMU_BASE_ADDR 0x1F102000
162 #define LTQ_PMU_SIZE 0x1000
163 
164-#define PMU_DMA 0x0020
165-#define PMU_USB 0x8041
166-#define PMU_LED 0x0800
167-#define PMU_GPT 0x1000
168-#define PMU_PPE 0x2000
169-#define PMU_FPI 0x4000
170-#define PMU_SWITCH 0x10000000
171-
172 /* ETOP - ethernet */
173 #define LTQ_ETOP_BASE_ADDR 0x1E180000
174 #define LTQ_ETOP_SIZE 0x40000
175 
176+/* GBIT - gigabit switch */
177+#define LTQ_GBIT_BASE_ADDR 0x1E108000
178+#define LTQ_GBIT_SIZE 0x4000
179+
180 /* DMA */
181 #define LTQ_DMA_BASE_ADDR 0x1E104100
182 #define LTQ_DMA_SIZE 0x800
183@@ -97,6 +116,8 @@
184 #define LTQ_WDT_BASE_ADDR 0x1F8803F0
185 #define LTQ_WDT_SIZE 0x10
186 
187+#define LTQ_RST_CAUSE_WDTRST 0x20
188+
189 /* STP - serial to parallel conversion unit */
190 #define LTQ_STP_BASE_ADDR 0x1E100BB0
191 #define LTQ_STP_SIZE 0x40
192@@ -105,7 +126,9 @@
193 #define LTQ_GPIO0_BASE_ADDR 0x1E100B10
194 #define LTQ_GPIO1_BASE_ADDR 0x1E100B40
195 #define LTQ_GPIO2_BASE_ADDR 0x1E100B70
196+#define LTQ_GPIO3_BASE_ADDR 0x1E100BA0
197 #define LTQ_GPIO_SIZE 0x30
198+#define LTQ_GPIO3_SIZE 0x10
199 
200 /* SSC */
201 #define LTQ_SSC_BASE_ADDR 0x1e100800
202@@ -121,20 +144,57 @@
203 #define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
204 #define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))
205 
206-/* request a non-gpio and set the PIO config */
207-extern int ltq_gpio_request(unsigned int pin, unsigned int alt0,
208- unsigned int alt1, unsigned int dir, const char *name);
209-extern void ltq_pmu_enable(unsigned int module);
210-extern void ltq_pmu_disable(unsigned int module);
211+/* BOOT_SEL - find what boot media we have */
212+#define BS_EXT_ROM 0x0
213+#define BS_FLASH 0x1
214+#define BS_MII0 0x2
215+#define BS_PCI 0x3
216+#define BS_UART1 0x4
217+#define BS_SPI 0x5
218+#define BS_NAND 0x6
219+#define BS_RMII0 0x7
220+
221+extern unsigned char ltq_boot_select(void);
222+
223+/* register access macros for EBU and CGU */
224+#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y))
225+#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x))
226+#define ltq_ebu_w32_mask(x, y, z) \
227+ ltq_w32_mask(x, y, ltq_ebu_membase + (z))
228+#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y))
229+#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x))
230+
231+extern __iomem void *ltq_ebu_membase;
232+extern __iomem void *ltq_cgu_membase;
233+
234+static inline int ltq_is_ase(void)
235+{
236+ return (ltq_get_soc_type() == SOC_TYPE_AMAZON_SE);
237+}
238 
239 static inline int ltq_is_ar9(void)
240 {
241     return (ltq_get_soc_type() == SOC_TYPE_AR9);
242 }
243 
244+static inline int ltq_is_vr9_1(void)
245+{
246+ return (ltq_get_soc_type() == SOC_TYPE_VR9_1);
247+}
248+
249+static inline int ltq_is_vr9_2(void)
250+{
251+ return (ltq_get_soc_type() == SOC_TYPE_VR9_2);
252+}
253+
254 static inline int ltq_is_vr9(void)
255 {
256- return (ltq_get_soc_type() == SOC_TYPE_VR9);
257+ return (ltq_is_vr9_1() || ltq_is_vr9_2());
258+}
259+
260+static inline int ltq_is_falcon(void)
261+{
262+ return 0;
263 }
264 
265 #endif /* CONFIG_SOC_TYPE_XWAY */
266diff --git a/arch/mips/lantiq/xway/Kconfig b/arch/mips/lantiq/xway/Kconfig
267index 2b857de..54a51ff 100644
268--- a/arch/mips/lantiq/xway/Kconfig
269+++ b/arch/mips/lantiq/xway/Kconfig
270@@ -8,6 +8,27 @@ config LANTIQ_MACH_EASY50712
271 
272 endmenu
273 
274+choice
275+ prompt "PCI"
276+ default PCI_LANTIQ_NONE
277+
278+config PCI_LANTIQ_NONE
279+ bool "None"
280+
281+config PCI_LANTIQ
282+ bool "PCI Support"
283+ depends on PCI
284+
285+config PCIE_LANTIQ
286+ bool "PCIE Support"
287+ select ARCH_SUPPORTS_MSI
288+
289+endchoice
290+
291+config PCIE_LANTIQ_MSI
292+ bool
293+ depends on PCIE_LANTIQ && PCI_MSI
294+ default y
295 endif
296 
297 if SOC_AMAZON_SE
298diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
299index c517f2e..c9baf91 100644
300--- a/arch/mips/lantiq/xway/Makefile
301+++ b/arch/mips/lantiq/xway/Makefile
302@@ -1,7 +1,4 @@
303-obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o
304-
305-obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o setup-xway.o
306-obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o setup-ase.o
307+obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o prom.o nand.o timer.o dev-ifxhcd.o
308 
309 obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
310 obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
311diff --git a/arch/mips/lantiq/xway/clk-ase.c b/arch/mips/lantiq/xway/clk-ase.c
312deleted file mode 100644
313index 6522583..0000000
314--- a/arch/mips/lantiq/xway/clk-ase.c
315+++ /dev/null
316@@ -1,48 +0,0 @@
317-/*
318- * This program is free software; you can redistribute it and/or modify it
319- * under the terms of the GNU General Public License version 2 as published
320- * by the Free Software Foundation.
321- *
322- * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
323- */
324-
325-#include <linux/io.h>
326-#include <linux/export.h>
327-#include <linux/init.h>
328-#include <linux/clk.h>
329-
330-#include <asm/time.h>
331-#include <asm/irq.h>
332-#include <asm/div64.h>
333-
334-#include <lantiq_soc.h>
335-
336-/* cgu registers */
337-#define LTQ_CGU_SYS 0x0010
338-
339-unsigned int ltq_get_io_region_clock(void)
340-{
341- return CLOCK_133M;
342-}
343-EXPORT_SYMBOL(ltq_get_io_region_clock);
344-
345-unsigned int ltq_get_fpi_bus_clock(int fpi)
346-{
347- return CLOCK_133M;
348-}
349-EXPORT_SYMBOL(ltq_get_fpi_bus_clock);
350-
351-unsigned int ltq_get_cpu_hz(void)
352-{
353- if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5))
354- return CLOCK_266M;
355- else
356- return CLOCK_133M;
357-}
358-EXPORT_SYMBOL(ltq_get_cpu_hz);
359-
360-unsigned int ltq_get_fpi_hz(void)
361-{
362- return CLOCK_133M;
363-}
364-EXPORT_SYMBOL(ltq_get_fpi_hz);
365diff --git a/arch/mips/lantiq/xway/clk-xway.c b/arch/mips/lantiq/xway/clk-xway.c
366deleted file mode 100644
367index 696b1a3..0000000
368--- a/arch/mips/lantiq/xway/clk-xway.c
369+++ /dev/null
370@@ -1,223 +0,0 @@
371-/*
372- * This program is free software; you can redistribute it and/or modify it
373- * under the terms of the GNU General Public License version 2 as published
374- * by the Free Software Foundation.
375- *
376- * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
377- */
378-
379-#include <linux/io.h>
380-#include <linux/export.h>
381-#include <linux/init.h>
382-#include <linux/clk.h>
383-
384-#include <asm/time.h>
385-#include <asm/irq.h>
386-#include <asm/div64.h>
387-
388-#include <lantiq_soc.h>
389-
390-static unsigned int ltq_ram_clocks[] = {
391- CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
392-#define DDR_HZ ltq_ram_clocks[ltq_cgu_r32(LTQ_CGU_SYS) & 0x3]
393-
394-#define BASIC_FREQUENCY_1 35328000
395-#define BASIC_FREQUENCY_2 36000000
396-#define BASIS_REQUENCY_USB 12000000
397-
398-#define GET_BITS(x, msb, lsb) \
399- (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
400-
401-#define LTQ_CGU_PLL0_CFG 0x0004
402-#define LTQ_CGU_PLL1_CFG 0x0008
403-#define LTQ_CGU_PLL2_CFG 0x000C
404-#define LTQ_CGU_SYS 0x0010
405-#define LTQ_CGU_UPDATE 0x0014
406-#define LTQ_CGU_IF_CLK 0x0018
407-#define LTQ_CGU_OSC_CON 0x001C
408-#define LTQ_CGU_SMD 0x0020
409-#define LTQ_CGU_CT1SR 0x0028
410-#define LTQ_CGU_CT2SR 0x002C
411-#define LTQ_CGU_PCMCR 0x0030
412-#define LTQ_CGU_PCI_CR 0x0034
413-#define LTQ_CGU_PD_PC 0x0038
414-#define LTQ_CGU_FMR 0x003C
415-
416-#define CGU_PLL0_PHASE_DIVIDER_ENABLE \
417- (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 31))
418-#define CGU_PLL0_BYPASS \
419- (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 30))
420-#define CGU_PLL0_CFG_DSMSEL \
421- (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 28))
422-#define CGU_PLL0_CFG_FRAC_EN \
423- (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 27))
424-#define CGU_PLL1_SRC \
425- (ltq_cgu_r32(LTQ_CGU_PLL1_CFG) & (1 << 31))
426-#define CGU_PLL2_PHASE_DIVIDER_ENABLE \
427- (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & (1 << 20))
428-#define CGU_SYS_FPI_SEL (1 << 6)
429-#define CGU_SYS_DDR_SEL 0x3
430-#define CGU_PLL0_SRC (1 << 29)
431-
432-#define CGU_PLL0_CFG_PLLK GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 26, 17)
433-#define CGU_PLL0_CFG_PLLN GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 12, 6)
434-#define CGU_PLL0_CFG_PLLM GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 5, 2)
435-#define CGU_PLL2_SRC GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 18, 17)
436-#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 16, 13)
437-
438-static unsigned int ltq_get_pll0_fdiv(void);
439-
440-static inline unsigned int get_input_clock(int pll)
441-{
442- switch (pll) {
443- case 0:
444- if (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & CGU_PLL0_SRC)
445- return BASIS_REQUENCY_USB;
446- else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
447- return BASIC_FREQUENCY_1;
448- else
449- return BASIC_FREQUENCY_2;
450- case 1:
451- if (CGU_PLL1_SRC)
452- return BASIS_REQUENCY_USB;
453- else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
454- return BASIC_FREQUENCY_1;
455- else
456- return BASIC_FREQUENCY_2;
457- case 2:
458- switch (CGU_PLL2_SRC) {
459- case 0:
460- return ltq_get_pll0_fdiv();
461- case 1:
462- return CGU_PLL2_PHASE_DIVIDER_ENABLE ?
463- BASIC_FREQUENCY_1 :
464- BASIC_FREQUENCY_2;
465- case 2:
466- return BASIS_REQUENCY_USB;
467- }
468- default:
469- return 0;
470- }
471-}
472-
473-static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den)
474-{
475- u64 res, clock = get_input_clock(pll);
476-
477- res = num * clock;
478- do_div(res, den);
479- return res;
480-}
481-
482-static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N,
483- unsigned int K)
484-{
485- unsigned int num = ((N + 1) << 10) + K;
486- unsigned int den = (M + 1) << 10;
487-
488- return cal_dsm(pll, num, den);
489-}
490-
491-static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N,
492- unsigned int K)
493-{
494- unsigned int num = ((N + 1) << 11) + K + 512;
495- unsigned int den = (M + 1) << 11;
496-
497- return cal_dsm(pll, num, den);
498-}
499-
500-static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N,
501- unsigned int K)
502-{
503- unsigned int num = K >= 512 ?
504- ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
505- unsigned int den = (M + 1) << 12;
506-
507- return cal_dsm(pll, num, den);
508-}
509-
510-static inline unsigned int dsm(int pll, unsigned int M, unsigned int N,
511- unsigned int K, unsigned int dsmsel, unsigned int phase_div_en)
512-{
513- if (!dsmsel)
514- return mash_dsm(pll, M, N, K);
515- else if (!phase_div_en)
516- return mash_dsm(pll, M, N, K);
517- else
518- return ssff_dsm_2(pll, M, N, K);
519-}
520-
521-static inline unsigned int ltq_get_pll0_fosc(void)
522-{
523- if (CGU_PLL0_BYPASS)
524- return get_input_clock(0);
525- else
526- return !CGU_PLL0_CFG_FRAC_EN
527- ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0,
528- CGU_PLL0_CFG_DSMSEL,
529- CGU_PLL0_PHASE_DIVIDER_ENABLE)
530- : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN,
531- CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL,
532- CGU_PLL0_PHASE_DIVIDER_ENABLE);
533-}
534-
535-static unsigned int ltq_get_pll0_fdiv(void)
536-{
537- unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
538-
539- return (ltq_get_pll0_fosc() + (div >> 1)) / div;
540-}
541-
542-unsigned int ltq_get_io_region_clock(void)
543-{
544- unsigned int ret = ltq_get_pll0_fosc();
545-
546- switch (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) {
547- default:
548- case 0:
549- return (ret + 1) / 2;
550- case 1:
551- return (ret * 2 + 2) / 5;
552- case 2:
553- return (ret + 1) / 3;
554- case 3:
555- return (ret + 2) / 4;
556- }
557-}
558-EXPORT_SYMBOL(ltq_get_io_region_clock);
559-
560-unsigned int ltq_get_fpi_bus_clock(int fpi)
561-{
562- unsigned int ret = ltq_get_io_region_clock();
563-
564- if ((fpi == 2) && (ltq_cgu_r32(LTQ_CGU_SYS) & CGU_SYS_FPI_SEL))
565- ret >>= 1;
566- return ret;
567-}
568-EXPORT_SYMBOL(ltq_get_fpi_bus_clock);
569-
570-unsigned int ltq_get_cpu_hz(void)
571-{
572- switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0xc) {
573- case 0:
574- return CLOCK_333M;
575- case 4:
576- return DDR_HZ;
577- case 8:
578- return DDR_HZ << 1;
579- default:
580- return DDR_HZ >> 1;
581- }
582-}
583-EXPORT_SYMBOL(ltq_get_cpu_hz);
584-
585-unsigned int ltq_get_fpi_hz(void)
586-{
587- unsigned int ddr_clock = DDR_HZ;
588-
589- if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40)
590- return ddr_clock >> 1;
591- return ddr_clock;
592-}
593-EXPORT_SYMBOL(ltq_get_fpi_hz);
594diff --git a/arch/mips/lantiq/xway/devices.c b/arch/mips/lantiq/xway/devices.c
595index d614aa7..5d4650d 100644
596--- a/arch/mips/lantiq/xway/devices.c
597+++ b/arch/mips/lantiq/xway/devices.c
598@@ -31,22 +31,10 @@
599 
600 /* gpio */
601 static struct resource ltq_gpio_resource[] = {
602- {
603- .name = "gpio0",
604- .start = LTQ_GPIO0_BASE_ADDR,
605- .end = LTQ_GPIO0_BASE_ADDR + LTQ_GPIO_SIZE - 1,
606- .flags = IORESOURCE_MEM,
607- }, {
608- .name = "gpio1",
609- .start = LTQ_GPIO1_BASE_ADDR,
610- .end = LTQ_GPIO1_BASE_ADDR + LTQ_GPIO_SIZE - 1,
611- .flags = IORESOURCE_MEM,
612- }, {
613- .name = "gpio2",
614- .start = LTQ_GPIO2_BASE_ADDR,
615- .end = LTQ_GPIO2_BASE_ADDR + LTQ_GPIO_SIZE - 1,
616- .flags = IORESOURCE_MEM,
617- }
618+ MEM_RES("gpio0", LTQ_GPIO0_BASE_ADDR, LTQ_GPIO_SIZE),
619+ MEM_RES("gpio1", LTQ_GPIO1_BASE_ADDR, LTQ_GPIO_SIZE),
620+ MEM_RES("gpio2", LTQ_GPIO2_BASE_ADDR, LTQ_GPIO_SIZE),
621+ MEM_RES("gpio3", LTQ_GPIO3_BASE_ADDR, LTQ_GPIO3_SIZE),
622 };
623 
624 void __init ltq_register_gpio(void)
625@@ -60,30 +48,23 @@ void __init ltq_register_gpio(void)
626     if (ltq_is_ar9() || ltq_is_vr9()) {
627         platform_device_register_simple("ltq_gpio", 2,
628             &ltq_gpio_resource[2], 1);
629+ platform_device_register_simple("ltq_gpio", 3,
630+ &ltq_gpio_resource[3], 1);
631     }
632 }
633 
634 /* serial to parallel conversion */
635-static struct resource ltq_stp_resource = {
636- .name = "stp",
637- .start = LTQ_STP_BASE_ADDR,
638- .end = LTQ_STP_BASE_ADDR + LTQ_STP_SIZE - 1,
639- .flags = IORESOURCE_MEM,
640-};
641+static struct resource ltq_stp_resource =
642+ MEM_RES("stp", LTQ_STP_BASE_ADDR, LTQ_STP_SIZE);
643 
644 void __init ltq_register_gpio_stp(void)
645 {
646- platform_device_register_simple("ltq_stp", 0, &ltq_stp_resource, 1);
647+ platform_device_register_simple("ltq_stp", -1, &ltq_stp_resource, 1);
648 }
649 
650 /* asc ports - amazon se has its own serial mapping */
651 static struct resource ltq_ase_asc_resources[] = {
652- {
653- .name = "asc0",
654- .start = LTQ_ASC1_BASE_ADDR,
655- .end = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1,
656- .flags = IORESOURCE_MEM,
657- },
658+ MEM_RES("asc0", LTQ_ASC1_BASE_ADDR, LTQ_ASC_SIZE),
659     IRQ_RES(tx, LTQ_ASC_ASE_TIR),
660     IRQ_RES(rx, LTQ_ASC_ASE_RIR),
661     IRQ_RES(err, LTQ_ASC_ASE_EIR),
662@@ -96,24 +77,45 @@ void __init ltq_register_ase_asc(void)
663 }
664 
665 /* ethernet */
666-static struct resource ltq_etop_resources = {
667- .name = "etop",
668- .start = LTQ_ETOP_BASE_ADDR,
669- .end = LTQ_ETOP_BASE_ADDR + LTQ_ETOP_SIZE - 1,
670- .flags = IORESOURCE_MEM,
671+static struct resource ltq_etop_resources[] = {
672+ MEM_RES("etop", LTQ_ETOP_BASE_ADDR, LTQ_ETOP_SIZE),
673+ MEM_RES("gbit", LTQ_GBIT_BASE_ADDR, LTQ_GBIT_SIZE),
674 };
675 
676 static struct platform_device ltq_etop = {
677     .name = "ltq_etop",
678- .resource = &ltq_etop_resources,
679+ .resource = ltq_etop_resources,
680     .num_resources = 1,
681+ .id = -1,
682 };
683 
684 void __init
685 ltq_register_etop(struct ltq_eth_data *eth)
686 {
687+ /* only register the gphy on socs that have one */
688+ if (ltq_is_ar9() | ltq_is_vr9())
689+ ltq_etop.num_resources = 2;
690     if (eth) {
691         ltq_etop.dev.platform_data = eth;
692         platform_device_register(&ltq_etop);
693     }
694 }
695+
696+/* ethernet */
697+static struct resource ltq_vrx200_resources[] = {
698+ MEM_RES("gbit", LTQ_GBIT_BASE_ADDR, LTQ_GBIT_SIZE),
699+};
700+
701+static struct platform_device ltq_vrx200 = {
702+ .name = "ltq_vrx200",
703+ .resource = ltq_vrx200_resources,
704+ .num_resources = 1,
705+ .id = -1,
706+};
707+
708+void __init
709+ltq_register_vrx200(struct ltq_eth_data *eth)
710+{
711+ ltq_vrx200.dev.platform_data = eth;
712+ platform_device_register(&ltq_vrx200);
713+}
714diff --git a/arch/mips/lantiq/xway/devices.h b/arch/mips/lantiq/xway/devices.h
715index e904934..08befd9 100644
716--- a/arch/mips/lantiq/xway/devices.h
717+++ b/arch/mips/lantiq/xway/devices.h
718@@ -16,5 +16,7 @@ extern void ltq_register_gpio(void);
719 extern void ltq_register_gpio_stp(void);
720 extern void ltq_register_ase_asc(void);
721 extern void ltq_register_etop(struct ltq_eth_data *eth);
722+extern void xway_register_nand(struct mtd_partition *parts, int count);
723+extern void ltq_register_vrx200(struct ltq_eth_data *eth);
724 
725 #endif
726diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c
727index b210e93..ce86529 100644
728--- a/arch/mips/lantiq/xway/dma.c
729+++ b/arch/mips/lantiq/xway/dma.c
730@@ -20,10 +20,13 @@
731 #include <linux/io.h>
732 #include <linux/dma-mapping.h>
733 #include <linux/export.h>
734+#include <linux/clk.h>
735 
736 #include <lantiq_soc.h>
737 #include <xway_dma.h>
738 
739+#include "../devices.h"
740+
741 #define LTQ_DMA_CTRL 0x10
742 #define LTQ_DMA_CPOLL 0x14
743 #define LTQ_DMA_CS 0x18
744@@ -55,12 +58,8 @@
745 #define ltq_dma_w32_mask(x, y, z) ltq_w32_mask(x, y, \
746                         ltq_dma_membase + (z))
747 
748-static struct resource ltq_dma_resource = {
749- .name = "dma",
750- .start = LTQ_DMA_BASE_ADDR,
751- .end = LTQ_DMA_BASE_ADDR + LTQ_DMA_SIZE - 1,
752- .flags = IORESOURCE_MEM,
753-};
754+static struct resource ltq_dma_resource =
755+ MEM_RES("dma", LTQ_DMA_BASE_ADDR, LTQ_DMA_SIZE);
756 
757 static void __iomem *ltq_dma_membase;
758 
759@@ -218,24 +217,18 @@ EXPORT_SYMBOL_GPL(ltq_dma_init_port);
760 int __init
761 ltq_dma_init(void)
762 {
763+ struct clk *clk;
764     int i;
765 
766- /* insert and request the memory region */
767- if (insert_resource(&iomem_resource, &ltq_dma_resource) < 0)
768- panic("Failed to insert dma memory");
769-
770- if (request_mem_region(ltq_dma_resource.start,
771- resource_size(&ltq_dma_resource), "dma") < 0)
772- panic("Failed to request dma memory");
773-
774     /* remap dma register range */
775- ltq_dma_membase = ioremap_nocache(ltq_dma_resource.start,
776- resource_size(&ltq_dma_resource));
777+ ltq_dma_membase = ltq_remap_resource(&ltq_dma_resource);
778     if (!ltq_dma_membase)
779         panic("Failed to remap dma memory");
780 
781     /* power up and reset the dma engine */
782- ltq_pmu_enable(PMU_DMA);
783+ clk = clk_get_sys("ltq_dma", NULL);
784+ WARN_ON(!clk);
785+ clk_enable(clk);
786     ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL);
787 
788     /* disable all interrupts */
789diff --git a/arch/mips/lantiq/xway/ebu.c b/arch/mips/lantiq/xway/ebu.c
790deleted file mode 100644
791index 862e3e8..0000000
792--- a/arch/mips/lantiq/xway/ebu.c
793+++ /dev/null
794@@ -1,52 +0,0 @@
795-/*
796- * This program is free software; you can redistribute it and/or modify it
797- * under the terms of the GNU General Public License version 2 as published
798- * by the Free Software Foundation.
799- *
800- * EBU - the external bus unit attaches PCI, NOR and NAND
801- *
802- * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
803- */
804-
805-#include <linux/kernel.h>
806-#include <linux/module.h>
807-#include <linux/ioport.h>
808-
809-#include <lantiq_soc.h>
810-
811-/* all access to the ebu must be locked */
812-DEFINE_SPINLOCK(ebu_lock);
813-EXPORT_SYMBOL_GPL(ebu_lock);
814-
815-static struct resource ltq_ebu_resource = {
816- .name = "ebu",
817- .start = LTQ_EBU_BASE_ADDR,
818- .end = LTQ_EBU_BASE_ADDR + LTQ_EBU_SIZE - 1,
819- .flags = IORESOURCE_MEM,
820-};
821-
822-/* remapped base addr of the clock unit and external bus unit */
823-void __iomem *ltq_ebu_membase;
824-
825-static int __init lantiq_ebu_init(void)
826-{
827- /* insert and request the memory region */
828- if (insert_resource(&iomem_resource, &ltq_ebu_resource) < 0)
829- panic("Failed to insert ebu memory");
830-
831- if (request_mem_region(ltq_ebu_resource.start,
832- resource_size(&ltq_ebu_resource), "ebu") < 0)
833- panic("Failed to request ebu memory");
834-
835- /* remap ebu register range */
836- ltq_ebu_membase = ioremap_nocache(ltq_ebu_resource.start,
837- resource_size(&ltq_ebu_resource));
838- if (!ltq_ebu_membase)
839- panic("Failed to remap ebu memory");
840-
841- /* make sure to unprotect the memory region where flash is located */
842- ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
843- return 0;
844-}
845-
846-postcore_initcall(lantiq_ebu_init);
847diff --git a/arch/mips/lantiq/xway/gpio.c b/arch/mips/lantiq/xway/gpio.c
848index d2fa98f..375329b 100644
849--- a/arch/mips/lantiq/xway/gpio.c
850+++ b/arch/mips/lantiq/xway/gpio.c
851@@ -21,9 +21,19 @@
852 #define LTQ_GPIO_ALTSEL0 0x0C
853 #define LTQ_GPIO_ALTSEL1 0x10
854 #define LTQ_GPIO_OD 0x14
855-
856+#define LTQ_GPIO_PUDSEL 0x1C
857+#define LTQ_GPIO_PUDEN 0x20
858+#define LTQ_GPIO3_OD 0x24
859+#define LTQ_GPIO3_ALTSEL1 0x24
860+#define LTQ_GPIO3_PUDSEL 0x28
861+#define LTQ_GPIO3_PUDEN 0x2C
862+
863+/* PORT3 only has 8 pins and its register layout
864+ is slightly different */
865 #define PINS_PER_PORT 16
866-#define MAX_PORTS 3
867+#define PINS_PORT3 8
868+#define MAX_PORTS 4
869+#define MAX_PIN 56
870 
871 #define ltq_gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p)))
872 #define ltq_gpio_setbit(m, r, p) ltq_w32_mask(0, (1 << p), m + r)
873@@ -48,14 +58,14 @@ int irq_to_gpio(unsigned int gpio)
874 }
875 EXPORT_SYMBOL(irq_to_gpio);
876 
877-int ltq_gpio_request(unsigned int pin, unsigned int alt0,
878- unsigned int alt1, unsigned int dir, const char *name)
879+int ltq_gpio_request(struct device *dev, unsigned int pin, unsigned int mux,
880+ unsigned int dir, const char *name)
881 {
882     int id = 0;
883 
884- if (pin >= (MAX_PORTS * PINS_PER_PORT))
885+ if (pin >= MAX_PIN)
886         return -EINVAL;
887- if (gpio_request(pin, name)) {
888+ if (devm_gpio_request(dev, pin, name)) {
889         pr_err("failed to setup lantiq gpio: %s\n", name);
890         return -EBUSY;
891     }
892@@ -67,18 +77,27 @@ int ltq_gpio_request(unsigned int pin, unsigned int alt0,
893         pin -= PINS_PER_PORT;
894         id++;
895     }
896- if (alt0)
897+ if (mux & 0x2)
898         ltq_gpio_setbit(ltq_gpio_port[id].membase,
899             LTQ_GPIO_ALTSEL0, pin);
900     else
901         ltq_gpio_clearbit(ltq_gpio_port[id].membase,
902             LTQ_GPIO_ALTSEL0, pin);
903- if (alt1)
904- ltq_gpio_setbit(ltq_gpio_port[id].membase,
905- LTQ_GPIO_ALTSEL1, pin);
906- else
907- ltq_gpio_clearbit(ltq_gpio_port[id].membase,
908- LTQ_GPIO_ALTSEL1, pin);
909+ if (id == 3) {
910+ if (mux & 0x1)
911+ ltq_gpio_setbit(ltq_gpio_port[1].membase,
912+ LTQ_GPIO3_ALTSEL1, pin);
913+ else
914+ ltq_gpio_clearbit(ltq_gpio_port[1].membase,
915+ LTQ_GPIO3_ALTSEL1, pin);
916+ } else {
917+ if (mux & 0x1)
918+ ltq_gpio_setbit(ltq_gpio_port[id].membase,
919+ LTQ_GPIO_ALTSEL1, pin);
920+ else
921+ ltq_gpio_clearbit(ltq_gpio_port[id].membase,
922+ LTQ_GPIO_ALTSEL1, pin);
923+ }
924     return 0;
925 }
926 EXPORT_SYMBOL(ltq_gpio_request);
927@@ -104,7 +123,18 @@ static int ltq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
928 {
929     struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
930 
931- ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
932+ if (chip->ngpio == PINS_PORT3) {
933+ ltq_gpio_clearbit(ltq_gpio_port[0].membase,
934+ LTQ_GPIO3_OD, offset);
935+ ltq_gpio_setbit(ltq_gpio_port[0].membase,
936+ LTQ_GPIO3_PUDSEL, offset);
937+ ltq_gpio_setbit(ltq_gpio_port[0].membase,
938+ LTQ_GPIO3_PUDEN, offset);
939+ } else {
940+ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
941+ ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset);
942+ ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset);
943+ }
944     ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset);
945 
946     return 0;
947@@ -115,7 +145,18 @@ static int ltq_gpio_direction_output(struct gpio_chip *chip,
948 {
949     struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
950 
951- ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
952+ if (chip->ngpio == PINS_PORT3) {
953+ ltq_gpio_setbit(ltq_gpio_port[0].membase,
954+ LTQ_GPIO3_OD, offset);
955+ ltq_gpio_clearbit(ltq_gpio_port[0].membase,
956+ LTQ_GPIO3_PUDSEL, offset);
957+ ltq_gpio_clearbit(ltq_gpio_port[0].membase,
958+ LTQ_GPIO3_PUDEN, offset);
959+ } else {
960+ ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
961+ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset);
962+ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset);
963+ }
964     ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset);
965     ltq_gpio_set(chip, offset, value);
966 
967@@ -127,7 +168,11 @@ static int ltq_gpio_req(struct gpio_chip *chip, unsigned offset)
968     struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
969 
970     ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL0, offset);
971- ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL1, offset);
972+ if (chip->ngpio == PINS_PORT3)
973+ ltq_gpio_clearbit(ltq_gpio_port[1].membase,
974+ LTQ_GPIO3_ALTSEL1, offset);
975+ else
976+ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL1, offset);
977     return 0;
978 }
979 
980@@ -140,6 +185,16 @@ static int ltq_gpio_probe(struct platform_device *pdev)
981             pdev->id);
982         return -EINVAL;
983     }
984+
985+ /* dirty hack - The registers of port3 are not mapped linearly.
986+ Port 3 may only load if Port 1/2 are mapped */
987+ if ((pdev->id == 3) && (!ltq_gpio_port[1].membase
988+ || !ltq_gpio_port[2].membase)) {
989+ dev_err(&pdev->dev,
990+ "ports 1/2 need to be loaded before port 3 works\n");
991+ return -ENOMEM;
992+ }
993+
994     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
995     if (!res) {
996         dev_err(&pdev->dev, "failed to get memory for gpio port %d\n",
997@@ -169,7 +224,10 @@ static int ltq_gpio_probe(struct platform_device *pdev)
998     ltq_gpio_port[pdev->id].chip.set = ltq_gpio_set;
999     ltq_gpio_port[pdev->id].chip.request = ltq_gpio_req;
1000     ltq_gpio_port[pdev->id].chip.base = PINS_PER_PORT * pdev->id;
1001- ltq_gpio_port[pdev->id].chip.ngpio = PINS_PER_PORT;
1002+ if (pdev->id == 3)
1003+ ltq_gpio_port[pdev->id].chip.ngpio = PINS_PORT3;
1004+ else
1005+ ltq_gpio_port[pdev->id].chip.ngpio = PINS_PER_PORT;
1006     platform_set_drvdata(pdev, &ltq_gpio_port[pdev->id]);
1007     return gpiochip_add(&ltq_gpio_port[pdev->id].chip);
1008 }
1009diff --git a/arch/mips/lantiq/xway/gpio_ebu.c b/arch/mips/lantiq/xway/gpio_ebu.c
1010index b91c7f1..bc5696b 100644
1011--- a/arch/mips/lantiq/xway/gpio_ebu.c
1012+++ b/arch/mips/lantiq/xway/gpio_ebu.c
1013@@ -61,9 +61,8 @@ static struct gpio_chip ltq_ebu_chip = {
1014     .label = "ltq_ebu",
1015     .direction_output = ltq_ebu_direction_output,
1016     .set = ltq_ebu_set,
1017- .base = 72,
1018+ .base = 100,
1019     .ngpio = 16,
1020- .can_sleep = 1,
1021     .owner = THIS_MODULE,
1022 };
1023 
1024diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c
1025index ff9991c..791beeb 100644
1026--- a/arch/mips/lantiq/xway/gpio_stp.c
1027+++ b/arch/mips/lantiq/xway/gpio_stp.c
1028@@ -15,6 +15,8 @@
1029 #include <linux/mutex.h>
1030 #include <linux/io.h>
1031 #include <linux/gpio.h>
1032+#include <linux/clk.h>
1033+#include <linux/err.h>
1034 
1035 #include <lantiq_soc.h>
1036 
1037@@ -25,6 +27,7 @@
1038 #define LTQ_STP_AR 0x10
1039 
1040 #define LTQ_STP_CON_SWU (1 << 31)
1041+#define LTQ_STP_SWU_MASK (1 << 31)
1042 #define LTQ_STP_2HZ 0
1043 #define LTQ_STP_4HZ (1 << 23)
1044 #define LTQ_STP_8HZ (2 << 23)
1045@@ -35,6 +38,8 @@
1046 #define LTQ_STP_ADSL_SRC (3 << 24)
1047 
1048 #define LTQ_STP_GROUP0 (1 << 0)
1049+#define LTQ_STP_GROUP1 (1 << 1)
1050+#define LTQ_STP_GROUP2 (1 << 2)
1051 
1052 #define LTQ_STP_RISING 0
1053 #define LTQ_STP_FALLING (1 << 26)
1054@@ -56,6 +61,12 @@ static void ltq_stp_set(struct gpio_chip *chip, unsigned offset, int value)
1055     else
1056         ltq_stp_shadow &= ~(1 << offset);
1057     ltq_stp_w32(ltq_stp_shadow, LTQ_STP_CPU0);
1058+ ltq_stp_w32_mask(LTQ_STP_SWU_MASK, LTQ_STP_CON_SWU, LTQ_STP_CON0);
1059+}
1060+
1061+static int ltq_stp_get(struct gpio_chip *chip, unsigned offset)
1062+{
1063+ return !!(ltq_stp_r32(LTQ_STP_CPU0) & (1<<offset));
1064 }
1065 
1066 static int ltq_stp_direction_output(struct gpio_chip *chip, unsigned offset,
1067@@ -70,18 +81,15 @@ static struct gpio_chip ltq_stp_chip = {
1068     .label = "ltq_stp",
1069     .direction_output = ltq_stp_direction_output,
1070     .set = ltq_stp_set,
1071- .base = 48,
1072+ .get = ltq_stp_get,
1073+ .base = 200,
1074     .ngpio = 24,
1075- .can_sleep = 1,
1076     .owner = THIS_MODULE,
1077 };
1078 
1079-static int ltq_stp_hw_init(void)
1080+static int ltq_stp_hw_init(struct device *dev)
1081 {
1082- /* the 3 pins used to control the external stp */
1083- ltq_gpio_request(4, 1, 0, 1, "stp-st");
1084- ltq_gpio_request(5, 1, 0, 1, "stp-d");
1085- ltq_gpio_request(6, 1, 0, 1, "stp-sh");
1086+ struct clk *clk;
1087 
1088     /* sane defaults */
1089     ltq_stp_w32(0, LTQ_STP_AR);
1090@@ -93,21 +101,18 @@ static int ltq_stp_hw_init(void)
1091     /* rising or falling edge */
1092     ltq_stp_w32_mask(LTQ_STP_EDGE_MASK, LTQ_STP_FALLING, LTQ_STP_CON0);
1093 
1094- /* per default stp 15-0 are set */
1095- ltq_stp_w32_mask(0, LTQ_STP_GROUP0, LTQ_STP_CON1);
1096-
1097- /* stp are update periodically by the FPI bus */
1098- ltq_stp_w32_mask(LTQ_STP_UPD_MASK, LTQ_STP_UPD_FPI, LTQ_STP_CON1);
1099-
1100- /* set stp update speed */
1101- ltq_stp_w32_mask(LTQ_STP_SPEED_MASK, LTQ_STP_8HZ, LTQ_STP_CON1);
1102+ /* enable all three led groups */
1103+ ltq_stp_w32_mask(0, LTQ_STP_GROUP0 | LTQ_STP_GROUP1 | LTQ_STP_GROUP2,
1104+ LTQ_STP_CON1);
1105 
1106     /* tell the hardware that pin (led) 0 and 1 are controlled
1107      * by the dsl arc
1108      */
1109     ltq_stp_w32_mask(0, LTQ_STP_ADSL_SRC, LTQ_STP_CON0);
1110 
1111- ltq_pmu_enable(PMU_LED);
1112+ clk = clk_get(dev, NULL);
1113+ WARN_ON(IS_ERR(clk));
1114+ clk_enable(clk);
1115     return 0;
1116 }
1117 
1118@@ -115,6 +120,7 @@ static int __devinit ltq_stp_probe(struct platform_device *pdev)
1119 {
1120     struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1121     int ret = 0;
1122+ int pin;
1123 
1124     if (!res)
1125         return -ENOENT;
1126@@ -130,9 +136,18 @@ static int __devinit ltq_stp_probe(struct platform_device *pdev)
1127         dev_err(&pdev->dev, "failed to remap STP memory\n");
1128         return -ENOMEM;
1129     }
1130+
1131+ /* the 3 pins used to control the external stp */
1132+ pin = ltq_is_ase() ? 1 : 4;
1133+ if (ltq_gpio_request(&pdev->dev, pin, 2, 1, "stp-st") ||
1134+ ltq_gpio_request(&pdev->dev, pin+1, 2, 1, "stp-d") ||
1135+ ltq_gpio_request(&pdev->dev, pin+2, 2, 1, "stp-sh")) {
1136+ dev_err(&pdev->dev, "failed to request needed gpios\n");
1137+ return -EBUSY;
1138+ }
1139     ret = gpiochip_add(&ltq_stp_chip);
1140     if (!ret)
1141- ret = ltq_stp_hw_init();
1142+ ret = ltq_stp_hw_init(&pdev->dev);
1143 
1144     return ret;
1145 }
1146diff --git a/arch/mips/lantiq/xway/mach-easy50601.c b/arch/mips/lantiq/xway/mach-easy50601.c
1147index d5aaf63..e76c29a 100644
1148--- a/arch/mips/lantiq/xway/mach-easy50601.c
1149+++ b/arch/mips/lantiq/xway/mach-easy50601.c
1150@@ -32,12 +32,7 @@ static struct mtd_partition easy50601_partitions[] = {
1151     {
1152         .name = "linux",
1153         .offset = 0x20000,
1154- .size = 0xE0000,
1155- },
1156- {
1157- .name = "rootfs",
1158- .offset = 0x100000,
1159- .size = 0x300000,
1160+ .size = 0x3d0000,
1161     },
1162 };
1163 
1164@@ -46,9 +41,15 @@ static struct physmap_flash_data easy50601_flash_data = {
1165     .parts = easy50601_partitions,
1166 };
1167 
1168-static void __init easy50601_init(void)
1169+static struct ltq_eth_data ltq_eth_data = {
1170+ .mii_mode = -1, /* use EPHY */
1171+};
1172+
1173+static void __init
1174+easy50601_init(void)
1175 {
1176     ltq_register_nor(&easy50601_flash_data);
1177+ ltq_register_etop(&ltq_eth_data);
1178 }
1179 
1180 MIPS_MACHINE(LTQ_MACH_EASY50601,
1181diff --git a/arch/mips/lantiq/xway/mach-easy50712.c b/arch/mips/lantiq/xway/mach-easy50712.c
1182index ea5027b..581aa76 100644
1183--- a/arch/mips/lantiq/xway/mach-easy50712.c
1184+++ b/arch/mips/lantiq/xway/mach-easy50712.c
1185@@ -34,12 +34,7 @@ static struct mtd_partition easy50712_partitions[] = {
1186     {
1187         .name = "linux",
1188         .offset = 0x20000,
1189- .size = 0xe0000,
1190- },
1191- {
1192- .name = "rootfs",
1193- .offset = 0x100000,
1194- .size = 0x300000,
1195+ .size = 0x3d0000,
1196     },
1197 };
1198 
1199@@ -60,15 +55,17 @@ static struct ltq_eth_data ltq_eth_data = {
1200     .mii_mode = PHY_INTERFACE_MODE_MII,
1201 };
1202 
1203-static void __init easy50712_init(void)
1204+static void __init
1205+easy50712_init(void)
1206 {
1207     ltq_register_gpio_stp();
1208     ltq_register_nor(&easy50712_flash_data);
1209     ltq_register_pci(&ltq_pci_data);
1210     ltq_register_etop(&ltq_eth_data);
1211+ ltq_register_tapi();
1212 }
1213 
1214 MIPS_MACHINE(LTQ_MACH_EASY50712,
1215- "EASY50712",
1216- "EASY50712 Eval Board",
1217- easy50712_init);
1218+ "EASY50712",
1219+ "EASY50712 Eval Board",
1220+ easy50712_init);
1221diff --git a/arch/mips/lantiq/xway/pmu.c b/arch/mips/lantiq/xway/pmu.c
1222deleted file mode 100644
1223index fe85361..0000000
1224--- a/arch/mips/lantiq/xway/pmu.c
1225+++ /dev/null
1226@@ -1,69 +0,0 @@
1227-/*
1228- * This program is free software; you can redistribute it and/or modify it
1229- * under the terms of the GNU General Public License version 2 as published
1230- * by the Free Software Foundation.
1231- *
1232- * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
1233- */
1234-
1235-#include <linux/kernel.h>
1236-#include <linux/module.h>
1237-#include <linux/ioport.h>
1238-
1239-#include <lantiq_soc.h>
1240-
1241-/* PMU - the power management unit allows us to turn part of the core
1242- * on and off
1243- */
1244-
1245-/* the enable / disable registers */
1246-#define LTQ_PMU_PWDCR 0x1C
1247-#define LTQ_PMU_PWDSR 0x20
1248-
1249-#define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y))
1250-#define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x))
1251-
1252-static struct resource ltq_pmu_resource = {
1253- .name = "pmu",
1254- .start = LTQ_PMU_BASE_ADDR,
1255- .end = LTQ_PMU_BASE_ADDR + LTQ_PMU_SIZE - 1,
1256- .flags = IORESOURCE_MEM,
1257-};
1258-
1259-static void __iomem *ltq_pmu_membase;
1260-
1261-void ltq_pmu_enable(unsigned int module)
1262-{
1263- int err = 1000000;
1264-
1265- ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR);
1266- do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module));
1267-
1268- if (!err)
1269- panic("activating PMU module failed!");
1270-}
1271-EXPORT_SYMBOL(ltq_pmu_enable);
1272-
1273-void ltq_pmu_disable(unsigned int module)
1274-{
1275- ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR);
1276-}
1277-EXPORT_SYMBOL(ltq_pmu_disable);
1278-
1279-int __init ltq_pmu_init(void)
1280-{
1281- if (insert_resource(&iomem_resource, &ltq_pmu_resource) < 0)
1282- panic("Failed to insert pmu memory");
1283-
1284- if (request_mem_region(ltq_pmu_resource.start,
1285- resource_size(&ltq_pmu_resource), "pmu") < 0)
1286- panic("Failed to request pmu memory");
1287-
1288- ltq_pmu_membase = ioremap_nocache(ltq_pmu_resource.start,
1289- resource_size(&ltq_pmu_resource));
1290- if (!ltq_pmu_membase)
1291- panic("Failed to remap pmu memory");
1292- return 0;
1293-}
1294-
1295-core_initcall(ltq_pmu_init);
1296diff --git a/arch/mips/lantiq/xway/prom-ase.c b/arch/mips/lantiq/xway/prom-ase.c
1297deleted file mode 100644
1298index ae4959a..0000000
1299--- a/arch/mips/lantiq/xway/prom-ase.c
1300+++ /dev/null
1301@@ -1,39 +0,0 @@
1302-/*
1303- * This program is free software; you can redistribute it and/or modify it
1304- * under the terms of the GNU General Public License version 2 as published
1305- * by the Free Software Foundation.
1306- *
1307- * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
1308- */
1309-
1310-#include <linux/export.h>
1311-#include <linux/clk.h>
1312-#include <asm/bootinfo.h>
1313-#include <asm/time.h>
1314-
1315-#include <lantiq_soc.h>
1316-
1317-#include "../prom.h"
1318-
1319-#define SOC_AMAZON_SE "Amazon_SE"
1320-
1321-#define PART_SHIFT 12
1322-#define PART_MASK 0x0FFFFFFF
1323-#define REV_SHIFT 28
1324-#define REV_MASK 0xF0000000
1325-
1326-void __init ltq_soc_detect(struct ltq_soc_info *i)
1327-{
1328- i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
1329- i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
1330- switch (i->partnum) {
1331- case SOC_ID_AMAZON_SE:
1332- i->name = SOC_AMAZON_SE;
1333- i->type = SOC_TYPE_AMAZON_SE;
1334- break;
1335-
1336- default:
1337- unreachable();
1338- break;
1339- }
1340-}
1341diff --git a/arch/mips/lantiq/xway/prom-xway.c b/arch/mips/lantiq/xway/prom-xway.c
1342deleted file mode 100644
1343index 2228133..0000000
1344--- a/arch/mips/lantiq/xway/prom-xway.c
1345+++ /dev/null
1346@@ -1,54 +0,0 @@
1347-/*
1348- * This program is free software; you can redistribute it and/or modify it
1349- * under the terms of the GNU General Public License version 2 as published
1350- * by the Free Software Foundation.
1351- *
1352- * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
1353- */
1354-
1355-#include <linux/export.h>
1356-#include <linux/clk.h>
1357-#include <asm/bootinfo.h>
1358-#include <asm/time.h>
1359-
1360-#include <lantiq_soc.h>
1361-
1362-#include "../prom.h"
1363-
1364-#define SOC_DANUBE "Danube"
1365-#define SOC_TWINPASS "Twinpass"
1366-#define SOC_AR9 "AR9"
1367-
1368-#define PART_SHIFT 12
1369-#define PART_MASK 0x0FFFFFFF
1370-#define REV_SHIFT 28
1371-#define REV_MASK 0xF0000000
1372-
1373-void __init ltq_soc_detect(struct ltq_soc_info *i)
1374-{
1375- i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
1376- i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
1377- switch (i->partnum) {
1378- case SOC_ID_DANUBE1:
1379- case SOC_ID_DANUBE2:
1380- i->name = SOC_DANUBE;
1381- i->type = SOC_TYPE_DANUBE;
1382- break;
1383-
1384- case SOC_ID_TWINPASS:
1385- i->name = SOC_TWINPASS;
1386- i->type = SOC_TYPE_DANUBE;
1387- break;
1388-
1389- case SOC_ID_ARX188:
1390- case SOC_ID_ARX168:
1391- case SOC_ID_ARX182:
1392- i->name = SOC_AR9;
1393- i->type = SOC_TYPE_AR9;
1394- break;
1395-
1396- default:
1397- unreachable();
1398- break;
1399- }
1400-}
1401diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
1402index 8b66bd8..970ca17 100644
1403--- a/arch/mips/lantiq/xway/reset.c
1404+++ b/arch/mips/lantiq/xway/reset.c
1405@@ -11,26 +11,62 @@
1406 #include <linux/ioport.h>
1407 #include <linux/pm.h>
1408 #include <linux/export.h>
1409+#include <linux/delay.h>
1410 #include <asm/reboot.h>
1411 
1412 #include <lantiq_soc.h>
1413 
1414+#include "../devices.h"
1415+
1416 #define ltq_rcu_w32(x, y) ltq_w32((x), ltq_rcu_membase + (y))
1417 #define ltq_rcu_r32(x) ltq_r32(ltq_rcu_membase + (x))
1418 
1419-/* register definitions */
1420-#define LTQ_RCU_RST 0x0010
1421-#define LTQ_RCU_RST_ALL 0x40000000
1422-
1423-#define LTQ_RCU_RST_STAT 0x0014
1424-#define LTQ_RCU_STAT_SHIFT 26
1425-
1426-static struct resource ltq_rcu_resource = {
1427- .name = "rcu",
1428- .start = LTQ_RCU_BASE_ADDR,
1429- .end = LTQ_RCU_BASE_ADDR + LTQ_RCU_SIZE - 1,
1430- .flags = IORESOURCE_MEM,
1431-};
1432+/* reset request register */
1433+#define RCU_RST_REQ 0x0010
1434+/* reset status register */
1435+#define RCU_RST_STAT 0x0014
1436+
1437+/* reset cause */
1438+#define RCU_STAT_SHIFT 26
1439+/* boot selection */
1440+#define RCU_BOOT_SEL_SHIFT 26
1441+#define RCU_BOOT_SEL_MASK 0x7
1442+
1443+/* Global SW Reset */
1444+#define RCU_RD_SRST BIT(30)
1445+/* Memory Controller */
1446+#define RCU_RD_MC BIT(14)
1447+/* PCI core */
1448+#define RCU_RD_PCI BIT(13)
1449+/* Voice DFE/AFE */
1450+#define RCU_RD_DFE_AFE BIT(12)
1451+/* DSL AFE */
1452+#define RCU_RD_DSL_AFE BIT(11)
1453+/* SDIO core */
1454+#define RCU_RD_SDIO BIT(10)
1455+/* DMA core */
1456+#define RCU_RD_DMA BIT(9)
1457+/* PPE core */
1458+#define RCU_RD_PPE BIT(8)
1459+/* ARC/DFE core */
1460+#define RCU_RD_ARC_DFE BIT(7)
1461+/* AHB bus */
1462+#define RCU_RD_AHB BIT(6)
1463+/* Ethernet MAC1 */
1464+#define RCU_RD_ENET_MAC1 BIT(5)
1465+/* USB and Phy core */
1466+#define RCU_RD_USB BIT(4)
1467+/* CPU1 subsystem */
1468+#define RCU_RD_CPU1 BIT(3)
1469+/* FPI bus */
1470+#define RCU_RD_FPI BIT(2)
1471+/* CPU0 subsystem */
1472+#define RCU_RD_CPU0 BIT(1)
1473+/* HW reset via HRST pin */
1474+#define RCU_RD_HRST BIT(0)
1475+
1476+static struct resource ltq_rcu_resource =
1477+ MEM_RES("rcu", LTQ_RCU_BASE_ADDR, LTQ_RCU_SIZE);
1478 
1479 /* remapped base addr of the reset control unit */
1480 static void __iomem *ltq_rcu_membase;
1481@@ -38,16 +74,29 @@ static void __iomem *ltq_rcu_membase;
1482 /* This function is used by the watchdog driver */
1483 int ltq_reset_cause(void)
1484 {
1485- u32 val = ltq_rcu_r32(LTQ_RCU_RST_STAT);
1486- return val >> LTQ_RCU_STAT_SHIFT;
1487+ u32 val = ltq_rcu_r32(RCU_RST_STAT);
1488+ return val >> RCU_STAT_SHIFT;
1489 }
1490 EXPORT_SYMBOL_GPL(ltq_reset_cause);
1491 
1492+unsigned char ltq_boot_select(void)
1493+{
1494+ u32 val = ltq_rcu_r32(RCU_RST_STAT);
1495+ return (val >> RCU_BOOT_SEL_SHIFT) & RCU_BOOT_SEL_MASK;
1496+}
1497+
1498+void ltq_reset_once(unsigned int module, ulong usec)
1499+{
1500+ ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | module, RCU_RST_REQ);
1501+ udelay(usec);
1502+ ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~module, RCU_RST_REQ);
1503+}
1504+
1505 static void ltq_machine_restart(char *command)
1506 {
1507     pr_notice("System restart\n");
1508     local_irq_disable();
1509- ltq_rcu_w32(ltq_rcu_r32(LTQ_RCU_RST) | LTQ_RCU_RST_ALL, LTQ_RCU_RST);
1510+ ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | RCU_RD_SRST, RCU_RST_REQ);
1511     unreachable();
1512 }
1513 
1514@@ -67,17 +116,8 @@ static void ltq_machine_power_off(void)
1515 
1516 static int __init mips_reboot_setup(void)
1517 {
1518- /* insert and request the memory region */
1519- if (insert_resource(&iomem_resource, &ltq_rcu_resource) < 0)
1520- panic("Failed to insert rcu memory");
1521-
1522- if (request_mem_region(ltq_rcu_resource.start,
1523- resource_size(&ltq_rcu_resource), "rcu") < 0)
1524- panic("Failed to request rcu memory");
1525-
1526     /* remap rcu register range */
1527- ltq_rcu_membase = ioremap_nocache(ltq_rcu_resource.start,
1528- resource_size(&ltq_rcu_resource));
1529+ ltq_rcu_membase = ltq_remap_resource(&ltq_rcu_resource);
1530     if (!ltq_rcu_membase)
1531         panic("Failed to remap rcu memory");
1532 
1533diff --git a/arch/mips/lantiq/xway/setup-ase.c b/arch/mips/lantiq/xway/setup-ase.c
1534deleted file mode 100644
1535index f6f3267..0000000
1536--- a/arch/mips/lantiq/xway/setup-ase.c
1537+++ /dev/null
1538@@ -1,19 +0,0 @@
1539-/*
1540- * This program is free software; you can redistribute it and/or modify it
1541- * under the terms of the GNU General Public License version 2 as published
1542- * by the Free Software Foundation.
1543- *
1544- * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
1545- */
1546-
1547-#include <lantiq_soc.h>
1548-
1549-#include "../prom.h"
1550-#include "devices.h"
1551-
1552-void __init ltq_soc_setup(void)
1553-{
1554- ltq_register_ase_asc();
1555- ltq_register_gpio();
1556- ltq_register_wdt();
1557-}
1558diff --git a/arch/mips/lantiq/xway/setup-xway.c b/arch/mips/lantiq/xway/setup-xway.c
1559deleted file mode 100644
1560index c292f64..0000000
1561--- a/arch/mips/lantiq/xway/setup-xway.c
1562+++ /dev/null
1563@@ -1,20 +0,0 @@
1564-/*
1565- * This program is free software; you can redistribute it and/or modify it
1566- * under the terms of the GNU General Public License version 2 as published
1567- * by the Free Software Foundation.
1568- *
1569- * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
1570- */
1571-
1572-#include <lantiq_soc.h>
1573-
1574-#include "../prom.h"
1575-#include "devices.h"
1576-
1577-void __init ltq_soc_setup(void)
1578-{
1579- ltq_register_asc(0);
1580- ltq_register_asc(1);
1581- ltq_register_gpio();
1582- ltq_register_wdt();
1583-}
1584--
15851.7.9.1
1586
1587

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