| 1 | From fcecdbe52ca3f17c798a080454d67df92d1e71f8 Mon Sep 17 00:00:00 2001 |
| 2 | From: John Crispin <blogic@openwrt.org> |
| 3 | Date: Fri, 3 Aug 2012 10:30:28 +0200 |
| 4 | Subject: [PATCH 25/25] svip cp1 |
| 5 | |
| 6 | --- |
| 7 | arch/mips/lantiq/devices.c | 10 ++++++++++ |
| 8 | arch/mips/lantiq/prom.c | 1 + |
| 9 | arch/mips/lantiq/setup.c | 15 +++++++++++++++ |
| 10 | 3 files changed, 26 insertions(+), 0 deletions(-) |
| 11 | |
| 12 | diff --git a/arch/mips/lantiq/devices.c b/arch/mips/lantiq/devices.c |
| 13 | index 2d7c46a..7128115 100644 |
| 14 | --- a/arch/mips/lantiq/devices.c |
| 15 | +++ b/arch/mips/lantiq/devices.c |
| 16 | @@ -102,19 +102,29 @@ void __init ltq_register_pci(struct ltq_pci_data *data) |
| 17 | } |
| 18 | #endif |
| 19 | |
| 20 | +#ifdef CONFIG_SOC_SVIP |
| 21 | +extern unsigned int *prom_cp1_base; |
| 22 | +#else |
| 23 | static unsigned int *cp1_base = 0; |
| 24 | +#endif |
| 25 | unsigned int* |
| 26 | ltq_get_cp1_base(void) |
| 27 | { |
| 28 | +#ifdef CONFIG_SOC_SVIP |
| 29 | + return prom_cp1_base; |
| 30 | +#else |
| 31 | return cp1_base; |
| 32 | +#endif |
| 33 | } |
| 34 | EXPORT_SYMBOL(ltq_get_cp1_base); |
| 35 | |
| 36 | void __init |
| 37 | ltq_register_tapi(void) |
| 38 | { |
| 39 | +#ifndef CONFIG_SOC_SVIP |
| 40 | #define CP1_SIZE (1 << 20) |
| 41 | dma_addr_t dma; |
| 42 | cp1_base = |
| 43 | (void*)CPHYSADDR(dma_alloc_coherent(NULL, CP1_SIZE, &dma, GFP_ATOMIC)); |
| 44 | +#endif |
| 45 | } |
| 46 | diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c |
| 47 | index 0fdef27..cab608b 100644 |
| 48 | --- a/arch/mips/lantiq/prom.c |
| 49 | +++ b/arch/mips/lantiq/prom.c |
| 50 | @@ -129,6 +129,7 @@ err_res: |
| 51 | } |
| 52 | EXPORT_SYMBOL(ltq_remap_resource); |
| 53 | |
| 54 | + |
| 55 | void __init prom_init(void) |
| 56 | { |
| 57 | ltq_soc_detect(&soc_info); |
| 58 | diff --git a/arch/mips/lantiq/setup.c b/arch/mips/lantiq/setup.c |
| 59 | index 114989d..9aa0310 100644 |
| 60 | --- a/arch/mips/lantiq/setup.c |
| 61 | +++ b/arch/mips/lantiq/setup.c |
| 62 | @@ -21,8 +21,15 @@ |
| 63 | /* set to 1 if the bootloader is BRN-BOOT instead of u-boot */ |
| 64 | unsigned long ltq_brn_boot = 0; |
| 65 | |
| 66 | +#ifdef CONFIG_SOC_SVIP |
| 67 | +unsigned int *prom_cp1_base; |
| 68 | +#endif |
| 69 | + |
| 70 | void __init plat_mem_setup(void) |
| 71 | { |
| 72 | +#ifdef CONFIG_SOC_SVIP |
| 73 | + int prom_cp1_size = 0x800000; |
| 74 | +#endif |
| 75 | /* assume 16M as default incase uboot fails to pass proper ramsize */ |
| 76 | unsigned long memsize = 16; |
| 77 | char **envp = (char **) KSEG1ADDR(fw_arg2); |
| 78 | @@ -54,6 +61,14 @@ void __init plat_mem_setup(void) |
| 79 | envp++; |
| 80 | } |
| 81 | memsize *= 1024 * 1024; |
| 82 | + |
| 83 | +#ifdef CONFIG_SOC_SVIP |
| 84 | + memsize -= prom_cp1_size; |
| 85 | + prom_cp1_base = (unsigned int *)KSEG1ADDR(memsize); |
| 86 | + |
| 87 | + printk("Using %ldMB Ram and reserving %dMB for cp1\n", |
| 88 | + memsize>>20, prom_cp1_size>>20); |
| 89 | +#endif |
| 90 | add_memory_region(0x00000000, memsize, BOOT_MEM_RAM); |
| 91 | } |
| 92 | |
| 93 | -- |
| 94 | 1.7.9.1 |
| 95 | |
| 96 | |
