| 1 | --- a/gcc/config/avr32/avr32.c |
| 2 | +++ b/gcc/config/avr32/avr32.c |
| 3 | @@ -6726,7 +6726,28 @@ avr32_reorg_optimization (void) |
| 4 | } |
| 5 | } |
| 6 | |
| 7 | - if (TARGET_MD_REORG_OPTIMIZATION && (optimize_size || (optimize > 0))) |
| 8 | + /* Disabled this optimization since it has a bug */ |
| 9 | + /* In the case where the data instruction the shifted insn gets folded |
| 10 | + * into is a branch destination, this breaks, i.e. |
| 11 | + * |
| 12 | + * add r8, r10, r8 << 2 |
| 13 | + * 1: |
| 14 | + * ld.w r11, r8[0] |
| 15 | + * ... |
| 16 | + * mov r8, sp |
| 17 | + * rjmp 1b |
| 18 | + * |
| 19 | + * gets folded to: |
| 20 | + * |
| 21 | + * 1: |
| 22 | + * ld.w r11, r10[r8 << 2] |
| 23 | + * ... |
| 24 | + * mov r8, sp |
| 25 | + * rjmp 1b |
| 26 | + * |
| 27 | + * which is clearly wrong.. |
| 28 | + */ |
| 29 | + if (0 && TARGET_MD_REORG_OPTIMIZATION && (optimize_size || (optimize > 0))) |
| 30 | { |
| 31 | |
| 32 | /* Scan through all insns looking for shifted add operations */ |
| 33 | |
