Date:2010-04-24 12:48:14 (10 years 4 months ago)
Author:Lars C.
Commit:0719a04733b321567934afbe52e58e9369af731e
Message:Add jz4740 mmc driver

Files: drivers/mmc/host/Kconfig (1 diff)
drivers/mmc/host/Makefile (1 diff)
drivers/mmc/host/jz_mmc.c (1 diff)
include/linux/mmc/jz4740_mmc.h (1 diff)

Change Details

drivers/mmc/host/Kconfig
8181
8282      If unsure, say Y.
8383
84config MMC_JZ
85    tristate "JZ SD/Multimedia Card Interface support"
86    depends on SOC_JZ4720 || SOC_JZ4740
87    help
88      This selects the Ingenic JZ4720/JZ4740 SD/Multimedia card Interface.
89      If you have abIngenic platform with a Multimedia Card slot,
90      say Y or M here.
91
92      If unsure, say N.
93
94      To compile this driver as a module, choose M here:
95      the module will be called ricoh_mmc.
96
97      If unsure, say Y.
98
8499config MMC_SDHCI_OF
85100    tristate "SDHCI support on OpenFirmware platforms"
86101    depends on MMC_SDHCI && PPC_OF
drivers/mmc/host/Makefile
66    EXTRA_CFLAGS += -DDEBUG
77endif
88
9obj-$(CONFIG_MMC_JZ) += jz_mmc.o
910obj-$(CONFIG_MMC_ARMMMCI) += mmci.o
1011obj-$(CONFIG_MMC_PXA) += pxamci.o
1112obj-$(CONFIG_MMC_IMX) += imxmmc.o
drivers/mmc/host/jz_mmc.c
1/*
2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ7420/JZ4740 GPIO SD/MMC controller driver
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/mmc/host.h>
17#include <linux/io.h>
18#include <linux/irq.h>
19#include <linux/interrupt.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/delay.h>
23#include <linux/scatterlist.h>
24#include <linux/clk.h>
25#include <linux/mmc/jz4740_mmc.h>
26
27#include <linux/gpio.h>
28#include <asm/mach-jz4740/gpio.h>
29#include <asm/cacheflush.h>
30#include <linux/dma-mapping.h>
31
32#define JZ_REG_MMC_STRPCL 0x00
33#define JZ_REG_MMC_STATUS 0x04
34#define JZ_REG_MMC_CLKRT 0x08
35#define JZ_REG_MMC_CMDAT 0x0C
36#define JZ_REG_MMC_RESTO 0x10
37#define JZ_REG_MMC_RDTO 0x14
38#define JZ_REG_MMC_BLKLEN 0x18
39#define JZ_REG_MMC_NOB 0x1C
40#define JZ_REG_MMC_SNOB 0x20
41#define JZ_REG_MMC_IMASK 0x24
42#define JZ_REG_MMC_IREG 0x28
43#define JZ_REG_MMC_CMD 0x2C
44#define JZ_REG_MMC_ARG 0x30
45#define JZ_REG_MMC_RESP_FIFO 0x34
46#define JZ_REG_MMC_RXFIFO 0x38
47#define JZ_REG_MMC_TXFIFO 0x3C
48
49#define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7)
50#define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6)
51#define JZ_MMC_STRPCL_START_READWAIT BIT(5)
52#define JZ_MMC_STRPCL_STOP_READWAIT BIT(4)
53#define JZ_MMC_STRPCL_RESET BIT(3)
54#define JZ_MMC_STRPCL_START_OP BIT(2)
55#define JZ_MMC_STRPCL_CLOCK_CONTROL (BIT(1) | BIT(0))
56#define JZ_MMC_STRPCL_CLOCK_STOP BIT(0)
57#define JZ_MMC_STRPCL_CLOCK_START BIT(1)
58
59
60#define JZ_MMC_STATUS_IS_RESETTING BIT(15)
61#define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14)
62#define JZ_MMC_STATUS_PRG_DONE BIT(13)
63#define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12)
64#define JZ_MMC_STATUS_END_CMD_RES BIT(11)
65#define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10)
66#define JZ_MMC_STATUS_IS_READWAIT BIT(9)
67#define JZ_MMC_STATUS_CLK_EN BIT(8)
68#define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7)
69#define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6)
70#define JZ_MMC_STATUS_CRC_RES_ERR BIT(5)
71#define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4)
72#define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3)
73#define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2)
74#define JZ_MMC_STATUS_TIMEOUT_RES BIT(1)
75#define JZ_MMC_STATUS_TIMEOUT_READ BIT(0)
76
77#define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0))
78#define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2))
79
80
81#define JZ_MMC_CMDAT_IO_ABORT BIT(11)
82#define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10)
83#define JZ_MMC_CMDAT_DMA_EN BIT(8)
84#define JZ_MMC_CMDAT_INIT BIT(7)
85#define JZ_MMC_CMDAT_BUSY BIT(6)
86#define JZ_MMC_CMDAT_STREAM BIT(5)
87#define JZ_MMC_CMDAT_WRITE BIT(4)
88#define JZ_MMC_CMDAT_DATA_EN BIT(3)
89#define JZ_MMC_CMDAT_RESPONSE_FORMAT (BIT(2) | BIT(1) | BIT(0))
90#define JZ_MMC_CMDAT_RSP_R1 1
91#define JZ_MMC_CMDAT_RSP_R2 2
92#define JZ_MMC_CMDAT_RSP_R3 3
93
94#define JZ_MMC_IRQ_SDIO BIT(7)
95#define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6)
96#define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5)
97#define JZ_MMC_IRQ_END_CMD_RES BIT(2)
98#define JZ_MMC_IRQ_PRG_DONE BIT(1)
99#define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0)
100
101
102#define JZ_MMC_CLK_RATE 24000000
103
104#define JZ4740_MMC_MAX_TIMEOUT 10000000
105
106struct jz4740_mmc_host {
107    struct mmc_host *mmc;
108    struct platform_device *pdev;
109    struct jz4740_mmc_platform_data *pdata;
110    struct clk *clk;
111
112    int irq;
113    int card_detect_irq;
114
115    struct resource *mem;
116    void __iomem *base;
117    struct mmc_request *req;
118    struct mmc_command *cmd;
119
120    int max_clock;
121    uint32_t cmdat;
122
123    uint16_t irq_mask;
124
125    spinlock_t lock;
126    struct timer_list clock_timer;
127    struct timer_list timeout_timer;
128    unsigned waiting:1;
129};
130
131static void jz4740_mmc_cmd_done(struct jz4740_mmc_host *host);
132
133static void jz4740_mmc_enable_irq(struct jz4740_mmc_host *host, unsigned int irq)
134{
135    unsigned long flags;
136    spin_lock_irqsave(&host->lock, flags);
137
138    host->irq_mask &= ~irq;
139    writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
140
141    spin_unlock_irqrestore(&host->lock, flags);
142}
143
144static void jz4740_mmc_disable_irq(struct jz4740_mmc_host *host, unsigned int irq)
145{
146    unsigned long flags;
147    spin_lock_irqsave(&host->lock, flags);
148
149    host->irq_mask |= irq;
150    writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
151
152    spin_unlock_irqrestore(&host->lock, flags);
153}
154
155static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host, bool start_transfer)
156{
157    uint16_t val = JZ_MMC_STRPCL_CLOCK_START;
158
159    if (start_transfer)
160        val |= JZ_MMC_STRPCL_START_OP;
161
162    writew(val, host->base + JZ_REG_MMC_STRPCL);
163}
164
165static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host)
166{
167    uint32_t status;
168
169    writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL);
170    do {
171        status = readl(host->base + JZ_REG_MMC_STATUS);
172    } while (status & JZ_MMC_STATUS_CLK_EN);
173
174}
175
176static void jz4740_mmc_reset(struct jz4740_mmc_host *host)
177{
178    uint32_t status;
179
180    writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL);
181    udelay(10);
182    do {
183        status = readl(host->base + JZ_REG_MMC_STATUS);
184    } while (status & JZ_MMC_STATUS_IS_RESETTING);
185}
186
187static void jz4740_mmc_request_done(struct jz4740_mmc_host *host)
188{
189    struct mmc_request *req;
190    unsigned long flags;
191
192    spin_lock_irqsave(&host->lock, flags);
193    req = host->req;
194    host->req = NULL;
195    host->waiting = 0;
196    spin_unlock_irqrestore(&host->lock, flags);
197
198    if (!unlikely(req))
199        return;
200
201    mmc_request_done(host->mmc, req);
202}
203
204static inline unsigned int jz4740_mmc_wait_irq(struct jz4740_mmc_host *host,
205    unsigned int irq)
206{
207    unsigned int timeout = JZ4740_MMC_MAX_TIMEOUT;
208    uint16_t status;
209
210    do {
211        status = readw(host->base + JZ_REG_MMC_IREG);
212    } while (!(status & irq) && --timeout);
213
214    return timeout;
215}
216
217static void jz4740_mmc_write_data(struct jz4740_mmc_host *host, struct mmc_data *data)
218{
219    struct scatterlist *sg;
220    uint32_t *sg_pointer;
221    int status;
222    unsigned int timeout;
223    size_t i, j;
224
225    for (sg = data->sg; sg; sg = sg_next(sg)) {
226        sg_pointer = sg_virt(sg);
227        i = sg->length / 4;
228        j = i >> 3;
229        i = i & 0x7;
230        while (j) {
231            timeout = jz4740_mmc_wait_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
232            if (unlikely(timeout == 0))
233                goto err_timeout;
234
235            writel(sg_pointer[0], host->base + JZ_REG_MMC_TXFIFO);
236            writel(sg_pointer[1], host->base + JZ_REG_MMC_TXFIFO);
237            writel(sg_pointer[2], host->base + JZ_REG_MMC_TXFIFO);
238            writel(sg_pointer[3], host->base + JZ_REG_MMC_TXFIFO);
239            writel(sg_pointer[4], host->base + JZ_REG_MMC_TXFIFO);
240            writel(sg_pointer[5], host->base + JZ_REG_MMC_TXFIFO);
241            writel(sg_pointer[6], host->base + JZ_REG_MMC_TXFIFO);
242            writel(sg_pointer[7], host->base + JZ_REG_MMC_TXFIFO);
243            sg_pointer += 8;
244            --j;
245        }
246        if (i) {
247            timeout = jz4740_mmc_wait_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
248            if (unlikely(timeout == 0))
249                goto err_timeout;
250
251            while (i) {
252                writel(*sg_pointer, host->base + JZ_REG_MMC_TXFIFO);
253                ++sg_pointer;
254                --i;
255            }
256        }
257        data->bytes_xfered += sg->length;
258    }
259
260    status = readl(host->base + JZ_REG_MMC_STATUS);
261    if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK)
262        goto err;
263
264    timeout = JZ4740_MMC_MAX_TIMEOUT;
265    do {
266        status = readl(host->base + JZ_REG_MMC_STATUS);
267    } while ((status & JZ_MMC_STATUS_DATA_TRAN_DONE) == 0 && --timeout);
268
269    if (unlikely(timeout == 0))
270        goto err_timeout;
271    writew(JZ_MMC_IRQ_DATA_TRAN_DONE, host->base + JZ_REG_MMC_IREG);
272
273    return;
274err_timeout:
275    host->req->cmd->error = -ETIMEDOUT;
276    data->error = -ETIMEDOUT;
277    return;
278err:
279    if(status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) {
280        host->req->cmd->error = -ETIMEDOUT;
281        data->error = -ETIMEDOUT;
282    } else {
283        host->req->cmd->error = -EILSEQ;
284        data->error = -EILSEQ;
285    }
286}
287
288static void jz4740_mmc_timeout(unsigned long data)
289{
290    struct jz4740_mmc_host *host = (struct jz4740_mmc_host*)data;
291    unsigned long flags;
292
293    spin_lock_irqsave(&host->lock, flags);
294    if (!host->waiting) {
295        spin_unlock_irqrestore(&host->lock, flags);
296        return;
297    }
298
299    host->waiting = 0;
300
301    spin_unlock_irqrestore(&host->lock, flags);
302
303    host->req->cmd->error = -ETIMEDOUT;
304    jz4740_mmc_request_done(host);
305}
306
307static void jz4740_mmc_read_data(struct jz4740_mmc_host *host,
308                struct mmc_data *data)
309{
310    struct scatterlist *sg;
311    uint32_t *sg_pointer;
312    uint32_t d;
313    uint16_t status = 0;
314    size_t i, j;
315    unsigned int timeout;
316
317    for (sg = data->sg; sg; sg = sg_next(sg)) {
318        sg_pointer = sg_virt(sg);
319        i = sg->length;
320        j = i >> 5;
321        i = i & 0x1f;
322        while (j) {
323            timeout = jz4740_mmc_wait_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
324            if (unlikely(timeout == 0))
325                goto err_timeout;
326
327            sg_pointer[0] = readl(host->base + JZ_REG_MMC_RXFIFO);
328            sg_pointer[1] = readl(host->base + JZ_REG_MMC_RXFIFO);
329            sg_pointer[2] = readl(host->base + JZ_REG_MMC_RXFIFO);
330            sg_pointer[3] = readl(host->base + JZ_REG_MMC_RXFIFO);
331            sg_pointer[4] = readl(host->base + JZ_REG_MMC_RXFIFO);
332            sg_pointer[5] = readl(host->base + JZ_REG_MMC_RXFIFO);
333            sg_pointer[6] = readl(host->base + JZ_REG_MMC_RXFIFO);
334            sg_pointer[7] = readl(host->base + JZ_REG_MMC_RXFIFO);
335
336            sg_pointer += 8;
337            --j;
338        }
339
340        while (i >= 4) {
341            timeout = jz4740_mmc_wait_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
342            if (unlikely(timeout == 0))
343                goto err_timeout;
344
345            *sg_pointer = readl(host->base + JZ_REG_MMC_RXFIFO);
346            ++sg_pointer;
347            i -= 4;
348        }
349        if (i > 0) {
350            d = readl(host->base + JZ_REG_MMC_RXFIFO);
351            memcpy(sg_pointer, &d, i);
352        }
353        data->bytes_xfered += sg->length;
354
355        flush_dcache_page(sg_page(sg));
356    }
357
358    status = readl(host->base + JZ_REG_MMC_STATUS);
359    if (status & JZ_MMC_STATUS_READ_ERROR_MASK)
360        goto err;
361
362    /* For whatever reason there is sometime one word more in the fifo then
363     * requested */
364    while ((status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) == 0 && --timeout) {
365        d = readl(host->base + JZ_REG_MMC_RXFIFO);
366        status = readl(host->base + JZ_REG_MMC_STATUS);
367    }
368    return;
369err_timeout:
370    host->req->cmd->error = -ETIMEDOUT;
371    data->error = -ETIMEDOUT;
372    return;
373err:
374    if (status & JZ_MMC_STATUS_TIMEOUT_READ) {
375        host->req->cmd->error = -ETIMEDOUT;
376        data->error = -ETIMEDOUT;
377    } else {
378        host->req->cmd->error = -EILSEQ;
379        data->error = -EILSEQ;
380    }
381}
382
383static irqreturn_t jz_mmc_irq_worker(int irq, void *devid)
384{
385    struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid;
386
387    if (host->cmd->error)
388        jz4740_mmc_request_done(host);
389    else
390        jz4740_mmc_cmd_done(host);
391
392    return IRQ_HANDLED;
393}
394
395static irqreturn_t jz_mmc_irq(int irq, void *devid)
396{
397    struct jz4740_mmc_host *host = devid;
398    uint16_t irq_reg, status, tmp;
399    unsigned long flags;
400    irqreturn_t ret = IRQ_HANDLED;
401
402    irq_reg = readw(host->base + JZ_REG_MMC_IREG);
403
404    tmp = irq_reg;
405    spin_lock_irqsave(&host->lock, flags);
406    irq_reg &= ~host->irq_mask;
407    spin_unlock_irqrestore(&host->lock, flags);
408
409    tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ |
410            JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE);
411
412    if (tmp != irq_reg) {
413        dev_warn(&host->pdev->dev, "Sparse irq: %x\n", tmp & ~irq_reg);
414        writew(tmp & ~irq_reg, host->base + JZ_REG_MMC_IREG);
415    }
416
417
418    if (irq_reg & JZ_MMC_IRQ_SDIO) {
419        writew(JZ_MMC_IRQ_SDIO, host->base + JZ_REG_MMC_IREG);
420        mmc_signal_sdio_irq(host->mmc);
421    }
422
423    if (!host->req || !host->cmd) {
424        goto handled;
425    }
426
427
428    spin_lock_irqsave(&host->lock, flags);
429    if (!host->waiting) {
430        spin_unlock_irqrestore(&host->lock, flags);
431        goto handled;
432    }
433
434    host->waiting = 0;
435    spin_unlock_irqrestore(&host->lock, flags);
436
437    del_timer(&host->timeout_timer);
438
439    status = readl(host->base + JZ_REG_MMC_STATUS);
440
441    if (status & JZ_MMC_STATUS_TIMEOUT_RES) {
442        host->cmd->error = -ETIMEDOUT;
443    } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) {
444        host->cmd->error = -EIO;
445    } else if(status & (JZ_MMC_STATUS_CRC_READ_ERROR |
446                        JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
447        host->cmd->data->error = -EIO;
448    } else if(status & (JZ_MMC_STATUS_CRC_READ_ERROR |
449                        JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
450        host->cmd->data->error = -EIO;
451    }
452
453    if (irq_reg & JZ_MMC_IRQ_END_CMD_RES) {
454        jz4740_mmc_disable_irq(host, JZ_MMC_IRQ_END_CMD_RES);
455        writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG);
456        ret = IRQ_WAKE_THREAD;
457    }
458
459    return ret;
460handled:
461
462    writew(0xff, host->base + JZ_REG_MMC_IREG);
463    return IRQ_HANDLED;
464}
465
466static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate) {
467    int div = 0;
468    int real_rate;
469
470    jz4740_mmc_clock_disable(host);
471    clk_set_rate(host->clk, JZ_MMC_CLK_RATE);
472
473    real_rate = clk_get_rate(host->clk);
474
475    while (real_rate > rate && div < 7) {
476        ++div;
477        real_rate >>= 1;
478    }
479
480    writew(div, host->base + JZ_REG_MMC_CLKRT);
481    return real_rate;
482}
483
484
485static void jz4740_mmc_read_response(struct jz4740_mmc_host *host, struct mmc_command *cmd)
486{
487    int i;
488    uint16_t tmp;
489    if (cmd->flags & MMC_RSP_136) {
490        tmp = readw(host->base + JZ_REG_MMC_RESP_FIFO);
491        for (i = 0; i < 4; ++i) {
492            cmd->resp[i] = tmp << 24;
493            cmd->resp[i] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) << 8;
494            tmp = readw(host->base + JZ_REG_MMC_RESP_FIFO);
495            cmd->resp[i] |= tmp >> 8;
496        }
497    } else {
498        cmd->resp[0] = readw(host->base + JZ_REG_MMC_RESP_FIFO) << 24;
499        cmd->resp[0] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) << 8;
500        cmd->resp[0] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) & 0xff;
501    }
502}
503
504static void jz4740_mmc_send_command(struct jz4740_mmc_host *host, struct mmc_command *cmd)
505{
506    uint32_t cmdat = host->cmdat;
507
508    host->cmdat &= ~JZ_MMC_CMDAT_INIT;
509    jz4740_mmc_clock_disable(host);
510
511    host->cmd = cmd;
512
513    if (cmd->flags & MMC_RSP_BUSY)
514        cmdat |= JZ_MMC_CMDAT_BUSY;
515
516    switch (mmc_resp_type(cmd)) {
517    case MMC_RSP_R1B:
518    case MMC_RSP_R1:
519        cmdat |= JZ_MMC_CMDAT_RSP_R1;
520        break;
521    case MMC_RSP_R2:
522        cmdat |= JZ_MMC_CMDAT_RSP_R2;
523        break;
524    case MMC_RSP_R3:
525        cmdat |= JZ_MMC_CMDAT_RSP_R3;
526        break;
527    default:
528        break;
529    }
530
531    if (cmd->data) {
532        cmdat |= JZ_MMC_CMDAT_DATA_EN;
533        if (cmd->data->flags & MMC_DATA_WRITE)
534            cmdat |= JZ_MMC_CMDAT_WRITE;
535        if (cmd->data->flags & MMC_DATA_STREAM)
536            cmdat |= JZ_MMC_CMDAT_STREAM;
537
538        writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN);
539        writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB);
540    }
541
542    writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD);
543    writel(cmd->arg, host->base + JZ_REG_MMC_ARG);
544    writel(cmdat, host->base + JZ_REG_MMC_CMDAT);
545
546    host->waiting = 1;
547    jz4740_mmc_clock_enable(host, 1);
548    mod_timer(&host->timeout_timer, jiffies + 5*HZ);
549}
550
551static void jz4740_mmc_cmd_done(struct jz4740_mmc_host *host)
552{
553    uint32_t status;
554    struct mmc_command *cmd = host->req->cmd;
555    struct mmc_request *req = host->req;
556    unsigned int timeout = JZ4740_MMC_MAX_TIMEOUT;
557
558    if (cmd->flags & MMC_RSP_PRESENT)
559        jz4740_mmc_read_response(host, cmd);
560
561    if (cmd->data) {
562        if (cmd->data->flags & MMC_DATA_READ)
563            jz4740_mmc_read_data(host, cmd->data);
564        else
565            jz4740_mmc_write_data(host, cmd->data);
566    }
567
568    if (req->stop) {
569        jz4740_mmc_send_command(host, req->stop);
570        do {
571            status = readw(host->base + JZ_REG_MMC_IREG);
572        } while ((status & JZ_MMC_IRQ_PRG_DONE) == 0 && --timeout);
573        writew(JZ_MMC_IRQ_PRG_DONE, host->base + JZ_REG_MMC_IREG);
574    }
575
576    if (unlikely(timeout == 0))
577        req->stop->error = -ETIMEDOUT;
578
579    jz4740_mmc_request_done(host);
580}
581
582static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
583{
584    struct jz4740_mmc_host *host = mmc_priv(mmc);
585
586    host->req = req;
587
588    writew(0xffff, host->base + JZ_REG_MMC_IREG);
589
590    writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG);
591    jz4740_mmc_enable_irq(host, JZ_MMC_IRQ_END_CMD_RES);
592    jz4740_mmc_send_command(host, req->cmd);
593}
594
595
596static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
597{
598    struct jz4740_mmc_host *host = mmc_priv(mmc);
599    if (ios->clock)
600        jz4740_mmc_set_clock_rate(host, ios->clock);
601
602    switch (ios->power_mode) {
603    case MMC_POWER_UP:
604        jz4740_mmc_reset(host);
605        if (gpio_is_valid(host->pdata->gpio_power))
606            gpio_set_value(host->pdata->gpio_power,
607                    !host->pdata->power_active_low);
608        host->cmdat |= JZ_MMC_CMDAT_INIT;
609        clk_enable(host->clk);
610        break;
611    case MMC_POWER_ON:
612        break;
613    default:
614        if (gpio_is_valid(host->pdata->gpio_power))
615            gpio_set_value(host->pdata->gpio_power,
616                    host->pdata->power_active_low);
617        clk_disable(host->clk);
618        break;
619    }
620
621    switch (ios->bus_width) {
622    case MMC_BUS_WIDTH_1:
623        host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
624        break;
625    case MMC_BUS_WIDTH_4:
626        host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
627        break;
628    default:
629        dev_err(&host->pdev->dev, "Invalid bus width: %d\n", ios->bus_width);
630    }
631}
632
633static int jz4740_mmc_get_ro(struct mmc_host *mmc)
634{
635    struct jz4740_mmc_host *host = mmc_priv(mmc);
636    if (!gpio_is_valid(host->pdata->gpio_read_only))
637        return -ENOSYS;
638
639    return gpio_get_value(host->pdata->gpio_read_only) ^
640        host->pdata->read_only_active_low;
641}
642
643static int jz4740_mmc_get_cd(struct mmc_host *mmc)
644{
645    struct jz4740_mmc_host *host = mmc_priv(mmc);
646    if (!gpio_is_valid(host->pdata->gpio_card_detect))
647        return -ENOSYS;
648
649    return gpio_get_value(host->pdata->gpio_card_detect) ^
650            host->pdata->card_detect_active_low;
651}
652
653static irqreturn_t jz4740_mmc_card_detect_irq(int irq, void *devid)
654{
655    struct jz4740_mmc_host *host = devid;
656
657    mmc_detect_change(host->mmc, HZ / 3);
658
659    return IRQ_HANDLED;
660}
661
662static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
663{
664    struct jz4740_mmc_host *host = mmc_priv(mmc);
665    if (enable)
666        jz4740_mmc_enable_irq(host, JZ_MMC_IRQ_SDIO);
667    else
668        jz4740_mmc_disable_irq(host, JZ_MMC_IRQ_SDIO);
669}
670
671static const struct mmc_host_ops jz4740_mmc_ops = {
672    .request = jz4740_mmc_request,
673    .set_ios = jz4740_mmc_set_ios,
674    .get_ro = jz4740_mmc_get_ro,
675    .get_cd = jz4740_mmc_get_cd,
676    .enable_sdio_irq = jz4740_mmc_enable_sdio_irq,
677};
678
679static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = {
680    JZ_GPIO_BULK_PIN(MSC_CMD),
681    JZ_GPIO_BULK_PIN(MSC_CLK),
682    JZ_GPIO_BULK_PIN(MSC_DATA0),
683    JZ_GPIO_BULK_PIN(MSC_DATA1),
684    JZ_GPIO_BULK_PIN(MSC_DATA2),
685    JZ_GPIO_BULK_PIN(MSC_DATA3),
686};
687
688static int __devinit jz4740_mmc_request_gpios(struct platform_device *pdev)
689{
690    int ret;
691    struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
692
693    if (!pdata)
694        return 0;
695
696    if (gpio_is_valid(pdata->gpio_card_detect)) {
697        ret = gpio_request(pdata->gpio_card_detect, "MMC detect change");
698        if (ret) {
699            dev_err(&pdev->dev, "Failed to request detect change gpio\n");
700            goto err;
701        }
702        gpio_direction_input(pdata->gpio_card_detect);
703    }
704
705    if (gpio_is_valid(pdata->gpio_read_only)) {
706        ret = gpio_request(pdata->gpio_read_only, "MMC read only");
707        if (ret) {
708            dev_err(&pdev->dev, "Failed to request read only gpio: %d\n", ret);
709            goto err_free_gpio_card_detect;
710        }
711        gpio_direction_input(pdata->gpio_read_only);
712    }
713
714    if (gpio_is_valid(pdata->gpio_power)) {
715        ret = gpio_request(pdata->gpio_power, "MMC power");
716        if (ret) {
717            dev_err(&pdev->dev, "Failed to request power gpio: %d\n", ret);
718            goto err_free_gpio_read_only;
719        }
720        gpio_direction_output(pdata->gpio_power, pdata->power_active_low);
721    }
722
723    return 0;
724
725err_free_gpio_read_only:
726    if (gpio_is_valid(pdata->gpio_read_only))
727        gpio_free(pdata->gpio_read_only);
728err_free_gpio_card_detect:
729    if (gpio_is_valid(pdata->gpio_card_detect))
730        gpio_free(pdata->gpio_card_detect);
731err:
732    return ret;
733}
734
735static void jz4740_mmc_free_gpios(struct platform_device *pdev)
736{
737    struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
738
739    if (!pdata)
740        return;
741
742    if (gpio_is_valid(pdata->gpio_power))
743        gpio_free(pdata->gpio_power);
744    if (gpio_is_valid(pdata->gpio_read_only))
745        gpio_free(pdata->gpio_read_only);
746    if (gpio_is_valid(pdata->gpio_card_detect))
747        gpio_free(pdata->gpio_card_detect);
748}
749
750static int __devinit jz4740_mmc_probe(struct platform_device* pdev)
751{
752    int ret;
753    struct mmc_host *mmc;
754    struct jz4740_mmc_host *host;
755    struct jz4740_mmc_platform_data *pdata;
756
757    pdata = pdev->dev.platform_data;
758
759    mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev);
760
761    if (!mmc) {
762        dev_err(&pdev->dev, "Failed to alloc mmc host structure\n");
763        return -ENOMEM;
764    }
765
766    host = mmc_priv(mmc);
767
768    host->irq = platform_get_irq(pdev, 0);
769
770    if (host->irq < 0) {
771        ret = host->irq;
772        dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
773        goto err_free_host;
774    }
775
776    host->clk = clk_get(&pdev->dev, "mmc");
777    if (!host->clk) {
778        ret = -ENOENT;
779        dev_err(&pdev->dev, "Failed to get mmc clock\n");
780        goto err_free_host;
781    }
782
783    host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
784
785    if (!host->mem) {
786        ret = -ENOENT;
787        dev_err(&pdev->dev, "Failed to get base platform memory\n");
788        goto err_clk_put;
789    }
790
791    host->mem = request_mem_region(host->mem->start, resource_size(host->mem),
792                    pdev->name);
793
794    if (!host->mem) {
795        ret = -EBUSY;
796        dev_err(&pdev->dev, "Failed to request base memory region\n");
797        goto err_clk_put;
798    }
799
800    host->base = ioremap_nocache(host->mem->start, resource_size(host->mem));
801
802    if (!host->base) {
803        ret = -EBUSY;
804        dev_err(&pdev->dev, "Failed to ioremap base memory\n");
805        goto err_release_mem_region;
806    }
807
808    if (pdata && pdata->data_1bit)
809        ret = jz_gpio_bulk_request(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
810    else
811        ret = jz_gpio_bulk_request(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
812
813    if (ret) {
814        dev_err(&pdev->dev, "Failed to request function pins: %d\n", ret);
815        goto err_iounmap;
816    }
817
818    ret = jz4740_mmc_request_gpios(pdev);
819    if (ret)
820        goto err_gpio_bulk_free;
821
822    mmc->ops = &jz4740_mmc_ops;
823    mmc->f_min = JZ_MMC_CLK_RATE / 128;
824    mmc->f_max = JZ_MMC_CLK_RATE;
825    mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
826    mmc->caps = (pdata && pdata->data_1bit) ? 0 : MMC_CAP_4_BIT_DATA;
827    mmc->caps |= MMC_CAP_SDIO_IRQ;
828    mmc->max_seg_size = 4096;
829    mmc->max_phys_segs = 128;
830
831    mmc->max_blk_size = (1 << 10) - 1;
832    mmc->max_blk_count = (1 << 15) - 1;
833    mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
834
835    host->mmc = mmc;
836    host->pdev = pdev;
837    host->pdata = pdata;
838    host->max_clock = JZ_MMC_CLK_RATE;
839    spin_lock_init(&host->lock);
840    host->irq_mask = 0xffff;
841
842    host->card_detect_irq = gpio_to_irq(pdata->gpio_card_detect);
843
844    if (host->card_detect_irq < 0) {
845        dev_warn(&pdev->dev, "Failed to get irq for card detect gpio\n");
846    } else {
847        ret = request_irq(host->card_detect_irq,
848            jz4740_mmc_card_detect_irq,
849            IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
850            "MMC card detect", host);
851
852        if (ret) {
853            dev_err(&pdev->dev, "Failed to request card detect irq");
854            goto err_free_gpios;
855        }
856    }
857
858    ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker,
859        IRQF_DISABLED, dev_name(&pdev->dev), host);
860    if (ret) {
861        dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
862        goto err_free_card_detect_irq;
863    }
864
865    jz4740_mmc_reset(host);
866    jz4740_mmc_clock_disable(host);
867    setup_timer(&host->timeout_timer, jz4740_mmc_timeout,
868            (unsigned long)host);
869
870    platform_set_drvdata(pdev, host);
871    ret = mmc_add_host(mmc);
872
873    if (ret) {
874        dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret);
875        goto err_free_irq;
876    }
877    dev_info(&pdev->dev, "JZ SD/MMC card driver registered\n");
878
879    return 0;
880
881err_free_irq:
882    free_irq(host->irq, host);
883err_free_card_detect_irq:
884    if (host->card_detect_irq >= 0)
885        free_irq(host->card_detect_irq, host);
886err_free_gpios:
887    jz4740_mmc_free_gpios(pdev);
888err_gpio_bulk_free:
889    if (pdata && pdata->data_1bit)
890        jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
891    else
892        jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
893err_iounmap:
894    iounmap(host->base);
895err_release_mem_region:
896    release_mem_region(host->mem->start, resource_size(host->mem));
897err_clk_put:
898    clk_put(host->clk);
899err_free_host:
900    platform_set_drvdata(pdev, NULL);
901    mmc_free_host(mmc);
902
903    return ret;
904}
905
906static int jz4740_mmc_remove(struct platform_device *pdev)
907{
908    struct jz4740_mmc_host *host = platform_get_drvdata(pdev);
909    struct jz4740_mmc_platform_data *pdata = host->pdata;
910
911    del_timer_sync(&host->timeout_timer);
912    jz4740_mmc_disable_irq(host, 0xff);
913    jz4740_mmc_reset(host);
914
915    mmc_remove_host(host->mmc);
916
917    free_irq(host->irq, host);
918    if (host->card_detect_irq >= 0)
919        free_irq(host->card_detect_irq, host);
920
921    jz4740_mmc_free_gpios(pdev);
922    if (pdata && pdata->data_1bit)
923        jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
924    else
925        jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
926
927    iounmap(host->base);
928    release_mem_region(host->mem->start, resource_size(host->mem));
929
930    clk_put(host->clk);
931
932    platform_set_drvdata(pdev, NULL);
933    mmc_free_host(host->mmc);
934
935    return 0;
936}
937
938#ifdef CONFIG_PM
939static int jz4740_mmc_suspend(struct device *dev)
940{
941    struct jz4740_mmc_host *host = dev_get_drvdata(dev);
942    struct jz4740_mmc_platform_data *pdata = host->pdata;
943
944    mmc_suspend_host(host->mmc, PMSG_SUSPEND);
945
946    if (pdata && pdata->data_1bit)
947        jz_gpio_bulk_suspend(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
948    else
949        jz_gpio_bulk_suspend(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
950
951    return 0;
952}
953
954static int jz4740_mmc_resume(struct device *dev)
955{
956    struct jz4740_mmc_host *host = dev_get_drvdata(dev);
957    struct jz4740_mmc_platform_data *pdata = host->pdata;
958
959    if (pdata && pdata->data_1bit)
960        jz_gpio_bulk_resume(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
961    else
962        jz_gpio_bulk_resume(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
963
964    mmc_resume_host(host->mmc);
965
966    return 0;
967}
968
969const struct dev_pm_ops jz4740_mmc_pm_ops = {
970    .suspend = jz4740_mmc_suspend,
971    .resume = jz4740_mmc_resume,
972    .poweroff = jz4740_mmc_suspend,
973    .restore = jz4740_mmc_resume,
974};
975
976#define JZ4740_MMC_PM_OPS (&jz4740_mmc_pm_ops)
977#else
978#define JZ4740_MMC_PM_OPS NULL
979#endif
980
981static struct platform_driver jz4740_mmc_driver = {
982    .probe = jz4740_mmc_probe,
983    .remove = jz4740_mmc_remove,
984    .driver = {
985        .name = "jz4740-mmc",
986        .owner = THIS_MODULE,
987        .pm = JZ4740_MMC_PM_OPS,
988    },
989};
990
991static int __init jz4740_mmc_init(void)
992{
993    return platform_driver_register(&jz4740_mmc_driver);
994}
995module_init(jz4740_mmc_init);
996
997static void __exit jz4740_mmc_exit(void)
998{
999    platform_driver_unregister(&jz4740_mmc_driver);
1000}
1001module_exit(jz4740_mmc_exit);
1002
1003MODULE_DESCRIPTION("JZ4720/JZ4740 SD/MMC controller driver");
1004MODULE_LICENSE("GPL");
1005MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
include/linux/mmc/jz4740_mmc.h
1#ifndef __LINUX_MMC_JZ4740_MMC
2#define __LINUX_MMC_JZ4740_MMC
3
4struct jz4740_mmc_platform_data {
5    int gpio_power;
6    int gpio_card_detect;
7    int gpio_read_only;
8    unsigned card_detect_active_low:1;
9    unsigned read_only_active_low:1;
10    unsigned power_active_low:1;
11
12    unsigned data_1bit:1;
13};
14
15#endif

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