Date:2009-12-01 07:54:56 (10 years 6 months ago)
Author:xiangfu
Commit:0bb57009f2787e5c7750974538304a4641899556
Message:001-core.patch

Files: arch/mips/Kconfig (4 diffs)
arch/mips/Makefile (4 diffs)
arch/mips/boot/Makefile (3 diffs)
arch/mips/include/asm/bootinfo.h (1 diff)
arch/mips/include/asm/cpu.h (3 diffs)
arch/mips/include/asm/mach-generic/irq.h (1 diff)
arch/mips/include/asm/r4kcache.h (11 diffs)
arch/mips/include/asm/suspend.h (1 diff)
arch/mips/kernel/cpu-probe.c (3 diffs)
arch/mips/mm/c-r4k.c (1 diff)
arch/mips/mm/cache.c (1 diff)
arch/mips/mm/tlbex.c (1 diff)

Change Details

arch/mips/Kconfig
158158     Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
159159     Olivetti M700-10 workstations.
160160
161config MACH_JZ
162    bool "Ingenic JZ4720/JZ4740 based machines"
163
161164config LASAT
162165    bool "LASAT Networks platforms"
163166    select CEVT_R4K
...... 
661664source "arch/mips/alchemy/Kconfig"
662665source "arch/mips/basler/excite/Kconfig"
663666source "arch/mips/jazz/Kconfig"
667source "arch/mips/jz4740/Kconfig"
664668source "arch/mips/lasat/Kconfig"
665669source "arch/mips/pmc-sierra/Kconfig"
666670source "arch/mips/sgi-ip27/Kconfig"
...... 
19111915
19121916source "kernel/time/Kconfig"
19131917
1918# the value of (max order + 1)
1919config FORCE_MAX_ZONEORDER
1920    prompt "MAX_ZONEORDER"
1921    int
1922    default "12"
1923    help
1924     The max memory that can be allocated = 4KB * 2^(CONFIG_FORCE_MAX_ZONEORDER - 1)
1925
19141926#
19151927# Timer Interrupt Frequency Configuration
19161928#
...... 
21822194
21832195endmenu
21842196
2197menu "CPU Frequency scaling"
2198
2199config CPU_FREQ_JZ
2200    tristate "CPUfreq driver for JZ CPUs"
2201    depends on JZSOC
2202    default n
2203    help
2204      This enables the CPUfreq driver for JZ CPUs.
2205
2206      If in doubt, say N.
2207
2208if (CPU_FREQ_JZ)
2209source "drivers/cpufreq/Kconfig"
2210endif
2211
2212endmenu
2213
21852214menu "Power management options"
21862215
21872216config ARCH_HIBERNATION_POSSIBLE
arch/mips/Makefile
180180load-$(CONFIG_AR7) += 0xffffffff94100000
181181
182182#
183# Commond Ingenic JZ4740 series
184#
185
186core-$(CONFIG_SOC_JZ4740) += arch/mips/jz4740/
187cflags-$(CONFIG_SOC_JZ4740) += -I$(srctree)/arch/mips/include/asm/mach-jz4740
188load-$(CONFIG_SOC_JZ4740) += 0xffffffff80010000
189
190#
183191# Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
184192#
185193core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
...... 
714722
715723all: $(all-y)
716724
725uImage: $(vmlinux-32)
726    +@$(call makeboot,$@)
727
728zImage: $(vmlinux-32)
729    +@$(call makeboot,$@)
730
717731vmlinux.bin: $(vmlinux-32)
718732    +@$(call makeboot,$@)
719733
...... 
743757
744758archclean:
745759    @$(MAKE) $(clean)=arch/mips/boot
760    @$(MAKE) $(clean)=arch/mips/boot/compressed
746761    @$(MAKE) $(clean)=arch/mips/lasat
747762
748763define archhelp
...... 
750765    echo ' vmlinux.ecoff - ECOFF boot image'
751766    echo ' vmlinux.bin - Raw binary boot image'
752767    echo ' vmlinux.srec - SREC boot image'
768    echo ' uImage - u-boot format image (arch/$(ARCH)/boot/uImage)'
769    echo ' zImage - Compressed binary image (arch/$(ARCH)/boot/compressed/zImage)'
770    echo ' vmlinux.bin - Uncompressed binary image (arch/$(ARCH)/boot/vmlinux.bin)'
753771    echo
754772    echo ' These will be default as apropriate for a configured platform.'
755773endef
arch/mips/boot/Makefile
77# Copyright (C) 2004 Maciej W. Rozycki
88#
99
10# This one must match the LOADADDR in arch/mips/Makefile!
11LOADADDR=0x80010000
12
1013#
1114# Some DECstations need all possible sections of an ECOFF executable
1215#
...... 
2528
2629VMLINUX = vmlinux
2730
28all: vmlinux.ecoff vmlinux.srec addinitrd
31all: vmlinux.ecoff vmlinux.srec addinitrd uImage zImage
2932
3033vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX)
3134    $(obj)/elf2ecoff $(VMLINUX) vmlinux.ecoff $(E2EFLAGS)
...... 
4245$(obj)/addinitrd: $(obj)/addinitrd.c
4346    $(HOSTCC) -o $@ $^
4447
48uImage: $(VMLINUX) vmlinux.bin
49    rm -f $(obj)/vmlinux.bin.gz
50    gzip -9 $(obj)/vmlinux.bin
51    mkimage -A mips -O linux -T kernel -C gzip \
52        -a $(LOADADDR) -e $(shell sh ./$(obj)/tools/entry $(NM) $(VMLINUX) ) \
53        -n 'Linux-$(KERNELRELEASE)' \
54        -d $(obj)/vmlinux.bin.gz $(obj)/uImage
55    @echo ' Kernel: arch/mips/boot/$@ is ready'
56
57zImage:
58    $(Q)$(MAKE) $(build)=$(obj)/compressed loadaddr=$(LOADADDR) $@
59    @echo ' Kernel: arch/mips/boot/compressed/$@ is ready'
60
4561clean-files += addinitrd \
4662           elf2ecoff \
4763           vmlinux.bin \
4864           vmlinux.ecoff \
49           vmlinux.srec
65           vmlinux.srec \
66           vmlinux.bin.gz \
67           uImage \
68           zImage
arch/mips/include/asm/bootinfo.h
5757#define MACH_MIKROTIK_RB532 0 /* Mikrotik RouterBoard 532 */
5858#define MACH_MIKROTIK_RB532A 1 /* Mikrotik RouterBoard 532A */
5959
60/*
61 * Valid machtype for group INGENIC
62 */
63#define MACH_INGENIC_JZ4720 0 /* JZ4730 SOC */
64#define MACH_INGENIC_JZ4740 1 /* JZ4740 SOC */
65
6066#define CL_SIZE COMMAND_LINE_SIZE
6167
6268extern char *system_type;
arch/mips/include/asm/cpu.h
3434#define PRID_COMP_LSI 0x080000
3535#define PRID_COMP_LEXRA 0x0b0000
3636#define PRID_COMP_CAVIUM 0x0d0000
37
37#define PRID_COMP_INGENIC 0xd00000
3838
3939/*
4040 * Assigned values for the product ID register. In order to detect a
...... 
127127#define PRID_IMP_CAVIUM_CN52XX 0x0700
128128
129129/*
130 * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
131 */
132
133#define PRID_IMP_JZRISC 0x0200
134
135/*
130136 * Definitions for 7:0 on legacy processors
131137 */
132138
...... 
217223    CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
218224    CPU_CAVIUM_OCTEON,
219225
226    /*
227     * Ingenic class processors
228     */
229    CPU_JZRISC, CPU_XBURST,
230
220231    CPU_LAST
221232};
222233
arch/mips/include/asm/mach-generic/irq.h
99#define __ASM_MACH_GENERIC_IRQ_H
1010
1111#ifndef NR_IRQS
12#define NR_IRQS 128
12#define NR_IRQS 256
1313#endif
1414
1515#ifdef CONFIG_I8259
arch/mips/include/asm/r4kcache.h
1717#include <asm/cpu-features.h>
1818#include <asm/mipsmtregs.h>
1919
20#ifdef CONFIG_JZRISC
21
22#define K0_TO_K1() \
23do { \
24    unsigned long __k0_addr; \
25                        \
26    __asm__ __volatile__( \
27    "la %0, 1f\n\t" \
28    "or %0, %0, %1\n\t" \
29    "jr %0\n\t" \
30    "nop\n\t" \
31    "1: nop\n" \
32    : "=&r"(__k0_addr) \
33    : "r" (0x20000000) ); \
34} while(0)
35
36#define K1_TO_K0() \
37do { \
38    unsigned long __k0_addr; \
39    __asm__ __volatile__( \
40    "nop;nop;nop;nop;nop;nop;nop\n\t" \
41    "la %0, 1f\n\t" \
42    "jr %0\n\t" \
43    "nop\n\t" \
44    "1: nop\n" \
45    : "=&r" (__k0_addr)); \
46} while (0)
47
48#define INVALIDATE_BTB() \
49do { \
50    unsigned long tmp; \
51    __asm__ __volatile__( \
52    ".set mips32\n\t" \
53    "mfc0 %0, $16, 7\n\t" \
54    "nop\n\t" \
55    "ori %0, 2\n\t" \
56    "mtc0 %0, $16, 7\n\t" \
57    "nop\n\t" \
58    : "=&r" (tmp)); \
59} while (0)
60
61#define SYNC_WB() __asm__ __volatile__ ("sync")
62
63#else /* CONFIG_JZRISC */
64
65#define K0_TO_K1() do { } while (0)
66#define K1_TO_K0() do { } while (0)
67#define INVALIDATE_BTB() do { } while (0)
68#define SYNC_WB() do { } while (0)
69
70#endif /* CONFIG_JZRISC */
71
2072/*
2173 * This macro return a properly sign-extended address suitable as base address
2274 * for indexed cache operations. Two issues here:
...... 
144196{
145197    __iflush_prologue
146198    cache_op(Index_Invalidate_I, addr);
199    INVALIDATE_BTB();
147200    __iflush_epilogue
148201}
149202
...... 
151204{
152205    __dflush_prologue
153206    cache_op(Index_Writeback_Inv_D, addr);
207    SYNC_WB();
154208    __dflush_epilogue
155209}
156210
...... 
163217{
164218    __iflush_prologue
165219    cache_op(Hit_Invalidate_I, addr);
220    INVALIDATE_BTB();
166221    __iflush_epilogue
167222}
168223
...... 
170225{
171226    __dflush_prologue
172227    cache_op(Hit_Writeback_Inv_D, addr);
228    SYNC_WB();
173229    __dflush_epilogue
174230}
175231
...... 
177233{
178234    __dflush_prologue
179235    cache_op(Hit_Invalidate_D, addr);
236    SYNC_WB();
180237    __dflush_epilogue
181238}
182239
...... 
209266static inline void protected_flush_icache_line(unsigned long addr)
210267{
211268    protected_cache_op(Hit_Invalidate_I, addr);
269    INVALIDATE_BTB();
212270}
213271
214272/*
...... 
220278static inline void protected_writeback_dcache_line(unsigned long addr)
221279{
222280    protected_cache_op(Hit_Writeback_Inv_D, addr);
281    SYNC_WB();
223282}
224283
225284static inline void protected_writeback_scache_line(unsigned long addr)
...... 
396455__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
397456__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
398457__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
458#ifndef CONFIG_JZRISC
399459__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
400460__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
461#endif
401462__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
402463__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64)
403464__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
...... 
405466__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
406467
407468__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16)
469#ifndef CONFIG_JZRISC
408470__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32)
471#endif
409472__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16)
410473__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32)
411474__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64)
412475__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128)
413476
477#ifdef CONFIG_JZRISC
478
479static inline void blast_dcache32(void)
480{
481    unsigned long start = INDEX_BASE;
482    unsigned long end = start + current_cpu_data.dcache.waysize;
483    unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
484    unsigned long ws_end = current_cpu_data.dcache.ways <<
485                           current_cpu_data.dcache.waybit;
486    unsigned long ws, addr;
487
488    for (ws = 0; ws < ws_end; ws += ws_inc)
489        for (addr = start; addr < end; addr += 0x400)
490            cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
491
492    SYNC_WB();
493}
494
495static inline void blast_dcache32_page(unsigned long page)
496{
497    unsigned long start = page;
498    unsigned long end = page + PAGE_SIZE;
499
500    do {
501        cache32_unroll32(start,Hit_Writeback_Inv_D);
502        start += 0x400;
503    } while (start < end);
504
505    SYNC_WB();
506}
507
508static inline void blast_dcache32_page_indexed(unsigned long page)
509{
510    unsigned long indexmask = current_cpu_data.dcache.waysize - 1;
511    unsigned long start = INDEX_BASE + (page & indexmask);
512    unsigned long end = start + PAGE_SIZE;
513    unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
514    unsigned long ws_end = current_cpu_data.dcache.ways <<
515                           current_cpu_data.dcache.waybit;
516    unsigned long ws, addr;
517
518    for (ws = 0; ws < ws_end; ws += ws_inc)
519        for (addr = start; addr < end; addr += 0x400)
520            cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
521
522    SYNC_WB();
523}
524
525static inline void blast_icache32(void)
526{
527    unsigned long start = INDEX_BASE;
528    unsigned long end = start + current_cpu_data.icache.waysize;
529    unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
530    unsigned long ws_end = current_cpu_data.icache.ways <<
531                           current_cpu_data.icache.waybit;
532    unsigned long ws, addr;
533
534    K0_TO_K1();
535
536    for (ws = 0; ws < ws_end; ws += ws_inc)
537        for (addr = start; addr < end; addr += 0x400)
538            cache32_unroll32(addr|ws,Index_Invalidate_I);
539
540    INVALIDATE_BTB();
541
542    K1_TO_K0();
543}
544
545static inline void blast_icache32_page(unsigned long page)
546{
547    unsigned long start = page;
548    unsigned long end = page + PAGE_SIZE;
549
550    K0_TO_K1();
551
552    do {
553        cache32_unroll32(start,Hit_Invalidate_I);
554        start += 0x400;
555    } while (start < end);
556
557    INVALIDATE_BTB();
558
559    K1_TO_K0();
560}
561
562static inline void blast_icache32_page_indexed(unsigned long page)
563{
564    unsigned long indexmask = current_cpu_data.icache.waysize - 1;
565    unsigned long start = INDEX_BASE + (page & indexmask);
566    unsigned long end = start + PAGE_SIZE;
567    unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
568    unsigned long ws_end = current_cpu_data.icache.ways <<
569                           current_cpu_data.icache.waybit;
570    unsigned long ws, addr;
571
572    K0_TO_K1();
573
574    for (ws = 0; ws < ws_end; ws += ws_inc)
575        for (addr = start; addr < end; addr += 0x400)
576            cache32_unroll32(addr|ws,Index_Invalidate_I);
577
578    INVALIDATE_BTB();
579
580    K1_TO_K0();
581}
582
583#endif /* CONFIG_JZRISC */
584
414585/* build blast_xxx_range, protected_blast_xxx_range */
415586#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
416587static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
...... 
432603    __##pfx##flush_epilogue \
433604}
434605
606#ifndef CONFIG_JZRISC
435607__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
608#endif
436609__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
610#ifndef CONFIG_JZRISC
437611__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
438612__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
613#endif
439614__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
440615/* blast_inv_dcache_range */
441616__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
442617__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
443618
619#ifdef CONFIG_JZRISC
620
621static inline void protected_blast_dcache_range(unsigned long start,
622                        unsigned long end)
623{
624    unsigned long lsize = cpu_dcache_line_size();
625    unsigned long addr = start & ~(lsize - 1);
626    unsigned long aend = (end - 1) & ~(lsize - 1);
627
628    while (1) {
629        protected_cache_op(Hit_Writeback_Inv_D, addr);
630        if (addr == aend)
631            break;
632        addr += lsize;
633    }
634    SYNC_WB();
635}
636
637static inline void protected_blast_icache_range(unsigned long start,
638                        unsigned long end)
639{
640    unsigned long lsize = cpu_icache_line_size();
641    unsigned long addr = start & ~(lsize - 1);
642    unsigned long aend = (end - 1) & ~(lsize - 1);
643
644    K0_TO_K1();
645
646    while (1) {
647        protected_cache_op(Hit_Invalidate_I, addr);
648        if (addr == aend)
649            break;
650        addr += lsize;
651    }
652    INVALIDATE_BTB();
653
654    K1_TO_K0();
655}
656
657static inline void blast_dcache_range(unsigned long start,
658                      unsigned long end)
659{
660    unsigned long lsize = cpu_dcache_line_size();
661    unsigned long addr = start & ~(lsize - 1);
662    unsigned long aend = (end - 1) & ~(lsize - 1);
663
664    while (1) {
665        cache_op(Hit_Writeback_Inv_D, addr);
666        if (addr == aend)
667            break;
668        addr += lsize;
669    }
670    SYNC_WB();
671}
672
673#endif /* CONFIG_JZRISC */
674
444675#endif /* _ASM_R4KCACHE_H */
arch/mips/include/asm/suspend.h
22#define __ASM_SUSPEND_H
33
44static inline int arch_prepare_suspend(void) { return 0; }
5#if defined(CONFIG_PM) && defined(CONFIG_JZSOC)
6extern int jz_pm_init(void);
7#endif
58
69/* References to section boundaries */
710extern const void __nosave_begin, __nosave_end;
arch/mips/kernel/cpu-probe.c
160160    case CPU_PR4450:
161161    case CPU_BCM3302:
162162    case CPU_CAVIUM_OCTEON:
163    case CPU_JZRISC:
163164        cpu_wait = r4k_wait;
164165        break;
165166
...... 
888889    }
889890}
890891
892static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
893{
894    decode_configs(c);
895    c->options &= ~MIPS_CPU_COUNTER; /* JZRISC does not implement the CP0 counter. */
896    switch (c->processor_id & 0xff00) {
897    case PRID_IMP_JZRISC:
898        c->cputype = CPU_JZRISC;
899        c->isa_level = MIPS_CPU_ISA_M32R1;
900        c->tlbsize = 32;
901        __cpu_name[cpu] = "Ingenic JZRISC";
902        break;
903    default:
904        panic("Unknown Ingenic Processor ID!");
905        break;
906    }
907}
908
891909const char *__cpu_name[NR_CPUS];
892910
893911__cpuinit void cpu_probe(void)
...... 
925943    case PRID_COMP_CAVIUM:
926944        cpu_probe_cavium(c, cpu);
927945        break;
946     case PRID_COMP_INGENIC:
947        cpu_probe_ingenic(c, cpu);
948        break;
928949    }
929950
930951    BUG_ON(!__cpu_name[cpu]);
arch/mips/mm/c-r4k.c
928928        c->dcache.waybit = 0;
929929        break;
930930
931    case CPU_JZRISC:
932        config1 = read_c0_config1();
933        config1 = (config1 >> 22) & 0x07;
934        if (config1 == 0x07)
935            config1 = 10;
936        else
937            config1 = config1 + 11;
938        config1 += 2;
939        icache_size = (1 << config1);
940        c->icache.linesz = 32;
941        c->icache.ways = 4;
942        c->icache.waybit = __ffs(icache_size / c->icache.ways);
943
944        config1 = read_c0_config1();
945        config1 = (config1 >> 13) & 0x07;
946        if (config1 == 0x07)
947            config1 = 10;
948        else
949            config1 = config1 + 11;
950        config1 += 2;
951        dcache_size = (1 << config1);
952        c->dcache.linesz = 32;
953        c->dcache.ways = 4;
954        c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
955
956        c->dcache.flags = 0;
957        c->options |= MIPS_CPU_PREFETCH;
958
959        break;
960
931961    default:
932962        if (!(config & MIPS_CONF_M))
933963            panic("Don't know how to probe P-caches on this cpu.");
arch/mips/mm/cache.c
5252void (*_dma_cache_inv)(unsigned long start, unsigned long size);
5353
5454EXPORT_SYMBOL(_dma_cache_wback_inv);
55EXPORT_SYMBOL(_dma_cache_wback);
56EXPORT_SYMBOL(_dma_cache_inv);
5557
5658#endif /* CONFIG_DMA_NONCOHERENT */
5759
arch/mips/mm/tlbex.c
385385        tlbw(p);
386386        break;
387387
388    case CPU_JZRISC:
389        tlbw(p);
390        uasm_i_nop(p);
391        break;
392
388393    default:
389394        panic("No TLB refill handler yet (CPU type: %d)",
390395              current_cpu_data.cputype);

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