Date: | 2009-12-01 07:54:56 (14 years 3 months ago) |
---|---|
Author: | xiangfu |
Commit: | 0bb57009f2787e5c7750974538304a4641899556 |
Message: | 001-core.patch |
Files: |
arch/mips/Kconfig (4 diffs) arch/mips/Makefile (4 diffs) arch/mips/boot/Makefile (3 diffs) arch/mips/include/asm/bootinfo.h (1 diff) arch/mips/include/asm/cpu.h (3 diffs) arch/mips/include/asm/mach-generic/irq.h (1 diff) arch/mips/include/asm/r4kcache.h (11 diffs) arch/mips/include/asm/suspend.h (1 diff) arch/mips/kernel/cpu-probe.c (3 diffs) arch/mips/mm/c-r4k.c (1 diff) arch/mips/mm/cache.c (1 diff) arch/mips/mm/tlbex.c (1 diff) |
Change Details
arch/mips/Kconfig | ||
---|---|---|
158 | 158 | Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and |
159 | 159 | Olivetti M700-10 workstations. |
160 | 160 | |
161 | config MACH_JZ | |
162 | bool "Ingenic JZ4720/JZ4740 based machines" | |
163 | ||
161 | 164 | config LASAT |
162 | 165 | bool "LASAT Networks platforms" |
163 | 166 | select CEVT_R4K |
... | ... | |
661 | 664 | source "arch/mips/alchemy/Kconfig" |
662 | 665 | source "arch/mips/basler/excite/Kconfig" |
663 | 666 | source "arch/mips/jazz/Kconfig" |
667 | source "arch/mips/jz4740/Kconfig" | |
664 | 668 | source "arch/mips/lasat/Kconfig" |
665 | 669 | source "arch/mips/pmc-sierra/Kconfig" |
666 | 670 | source "arch/mips/sgi-ip27/Kconfig" |
... | ... | |
1911 | 1915 | |
1912 | 1916 | source "kernel/time/Kconfig" |
1913 | 1917 | |
1918 | # the value of (max order + 1) | |
1919 | config FORCE_MAX_ZONEORDER | |
1920 | prompt "MAX_ZONEORDER" | |
1921 | int | |
1922 | default "12" | |
1923 | help | |
1924 | The max memory that can be allocated = 4KB * 2^(CONFIG_FORCE_MAX_ZONEORDER - 1) | |
1925 | ||
1914 | 1926 | # |
1915 | 1927 | # Timer Interrupt Frequency Configuration |
1916 | 1928 | # |
... | ... | |
2182 | 2194 | |
2183 | 2195 | endmenu |
2184 | 2196 | |
2197 | menu "CPU Frequency scaling" | |
2198 | ||
2199 | config CPU_FREQ_JZ | |
2200 | tristate "CPUfreq driver for JZ CPUs" | |
2201 | depends on JZSOC | |
2202 | default n | |
2203 | help | |
2204 | This enables the CPUfreq driver for JZ CPUs. | |
2205 | ||
2206 | If in doubt, say N. | |
2207 | ||
2208 | if (CPU_FREQ_JZ) | |
2209 | source "drivers/cpufreq/Kconfig" | |
2210 | endif | |
2211 | ||
2212 | endmenu | |
2213 | ||
2185 | 2214 | menu "Power management options" |
2186 | 2215 | |
2187 | 2216 | config ARCH_HIBERNATION_POSSIBLE |
arch/mips/Makefile | ||
---|---|---|
180 | 180 | load-$(CONFIG_AR7) += 0xffffffff94100000 |
181 | 181 | |
182 | 182 | # |
183 | # Commond Ingenic JZ4740 series | |
184 | # | |
185 | ||
186 | core-$(CONFIG_SOC_JZ4740) += arch/mips/jz4740/ | |
187 | cflags-$(CONFIG_SOC_JZ4740) += -I$(srctree)/arch/mips/include/asm/mach-jz4740 | |
188 | load-$(CONFIG_SOC_JZ4740) += 0xffffffff80010000 | |
189 | ||
190 | # | |
183 | 191 | # Acer PICA 61, Mips Magnum 4000 and Olivetti M700. |
184 | 192 | # |
185 | 193 | core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/ |
... | ... | |
714 | 722 | |
715 | 723 | all: $(all-y) |
716 | 724 | |
725 | uImage: $(vmlinux-32) | |
726 | +@$(call makeboot,$@) | |
727 | ||
728 | zImage: $(vmlinux-32) | |
729 | +@$(call makeboot,$@) | |
730 | ||
717 | 731 | vmlinux.bin: $(vmlinux-32) |
718 | 732 | +@$(call makeboot,$@) |
719 | 733 | |
... | ... | |
743 | 757 | |
744 | 758 | archclean: |
745 | 759 | @$(MAKE) $(clean)=arch/mips/boot |
760 | @$(MAKE) $(clean)=arch/mips/boot/compressed | |
746 | 761 | @$(MAKE) $(clean)=arch/mips/lasat |
747 | 762 | |
748 | 763 | define archhelp |
... | ... | |
750 | 765 | echo ' vmlinux.ecoff - ECOFF boot image' |
751 | 766 | echo ' vmlinux.bin - Raw binary boot image' |
752 | 767 | echo ' vmlinux.srec - SREC boot image' |
768 | echo ' uImage - u-boot format image (arch/$(ARCH)/boot/uImage)' | |
769 | echo ' zImage - Compressed binary image (arch/$(ARCH)/boot/compressed/zImage)' | |
770 | echo ' vmlinux.bin - Uncompressed binary image (arch/$(ARCH)/boot/vmlinux.bin)' | |
753 | 771 | echo |
754 | 772 | echo ' These will be default as apropriate for a configured platform.' |
755 | 773 | endef |
arch/mips/boot/Makefile | ||
---|---|---|
7 | 7 | # Copyright (C) 2004 Maciej W. Rozycki |
8 | 8 | # |
9 | 9 | |
10 | # This one must match the LOADADDR in arch/mips/Makefile! | |
11 | LOADADDR=0x80010000 | |
12 | ||
10 | 13 | # |
11 | 14 | # Some DECstations need all possible sections of an ECOFF executable |
12 | 15 | # |
... | ... | |
25 | 28 | |
26 | 29 | VMLINUX = vmlinux |
27 | 30 | |
28 | all: vmlinux.ecoff vmlinux.srec addinitrd | |
31 | all: vmlinux.ecoff vmlinux.srec addinitrd uImage zImage | |
29 | 32 | |
30 | 33 | vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX) |
31 | 34 | $(obj)/elf2ecoff $(VMLINUX) vmlinux.ecoff $(E2EFLAGS) |
... | ... | |
42 | 45 | $(obj)/addinitrd: $(obj)/addinitrd.c |
43 | 46 | $(HOSTCC) -o $@ $^ |
44 | 47 | |
48 | uImage: $(VMLINUX) vmlinux.bin | |
49 | rm -f $(obj)/vmlinux.bin.gz | |
50 | gzip -9 $(obj)/vmlinux.bin | |
51 | mkimage -A mips -O linux -T kernel -C gzip \ | |
52 | -a $(LOADADDR) -e $(shell sh ./$(obj)/tools/entry $(NM) $(VMLINUX) ) \ | |
53 | -n 'Linux-$(KERNELRELEASE)' \ | |
54 | -d $(obj)/vmlinux.bin.gz $(obj)/uImage | |
55 | @echo ' Kernel: arch/mips/boot/$@ is ready' | |
56 | ||
57 | zImage: | |
58 | $(Q)$(MAKE) $(build)=$(obj)/compressed loadaddr=$(LOADADDR) $@ | |
59 | @echo ' Kernel: arch/mips/boot/compressed/$@ is ready' | |
60 | ||
45 | 61 | clean-files += addinitrd \ |
46 | 62 | elf2ecoff \ |
47 | 63 | vmlinux.bin \ |
48 | 64 | vmlinux.ecoff \ |
49 | vmlinux.srec | |
65 | vmlinux.srec \ | |
66 | vmlinux.bin.gz \ | |
67 | uImage \ | |
68 | zImage |
arch/mips/include/asm/bootinfo.h | ||
---|---|---|
57 | 57 | #define MACH_MIKROTIK_RB532 0 /* Mikrotik RouterBoard 532 */ |
58 | 58 | #define MACH_MIKROTIK_RB532A 1 /* Mikrotik RouterBoard 532A */ |
59 | 59 | |
60 | /* | |
61 | * Valid machtype for group INGENIC | |
62 | */ | |
63 | #define MACH_INGENIC_JZ4720 0 /* JZ4730 SOC */ | |
64 | #define MACH_INGENIC_JZ4740 1 /* JZ4740 SOC */ | |
65 | ||
60 | 66 | #define CL_SIZE COMMAND_LINE_SIZE |
61 | 67 | |
62 | 68 | extern char *system_type; |
arch/mips/include/asm/cpu.h | ||
---|---|---|
34 | 34 | #define PRID_COMP_LSI 0x080000 |
35 | 35 | #define PRID_COMP_LEXRA 0x0b0000 |
36 | 36 | #define PRID_COMP_CAVIUM 0x0d0000 |
37 | ||
37 | #define PRID_COMP_INGENIC 0xd00000 | |
38 | 38 | |
39 | 39 | /* |
40 | 40 | * Assigned values for the product ID register. In order to detect a |
... | ... | |
127 | 127 | #define PRID_IMP_CAVIUM_CN52XX 0x0700 |
128 | 128 | |
129 | 129 | /* |
130 | * These are the PRID's for when 23:16 == PRID_COMP_INGENIC | |
131 | */ | |
132 | ||
133 | #define PRID_IMP_JZRISC 0x0200 | |
134 | ||
135 | /* | |
130 | 136 | * Definitions for 7:0 on legacy processors |
131 | 137 | */ |
132 | 138 | |
... | ... | |
217 | 223 | CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, |
218 | 224 | CPU_CAVIUM_OCTEON, |
219 | 225 | |
226 | /* | |
227 | * Ingenic class processors | |
228 | */ | |
229 | CPU_JZRISC, CPU_XBURST, | |
230 | ||
220 | 231 | CPU_LAST |
221 | 232 | }; |
222 | 233 |
arch/mips/include/asm/mach-generic/irq.h | ||
---|---|---|
9 | 9 | #define __ASM_MACH_GENERIC_IRQ_H |
10 | 10 | |
11 | 11 | #ifndef NR_IRQS |
12 | #define NR_IRQS 128 | |
12 | #define NR_IRQS 256 | |
13 | 13 | #endif |
14 | 14 | |
15 | 15 | #ifdef CONFIG_I8259 |
arch/mips/include/asm/r4kcache.h | ||
---|---|---|
17 | 17 | #include <asm/cpu-features.h> |
18 | 18 | #include <asm/mipsmtregs.h> |
19 | 19 | |
20 | #ifdef CONFIG_JZRISC | |
21 | ||
22 | #define K0_TO_K1() \ | |
23 | do { \ | |
24 | unsigned long __k0_addr; \ | |
25 | \ | |
26 | __asm__ __volatile__( \ | |
27 | "la %0, 1f\n\t" \ | |
28 | "or %0, %0, %1\n\t" \ | |
29 | "jr %0\n\t" \ | |
30 | "nop\n\t" \ | |
31 | "1: nop\n" \ | |
32 | : "=&r"(__k0_addr) \ | |
33 | : "r" (0x20000000) ); \ | |
34 | } while(0) | |
35 | ||
36 | #define K1_TO_K0() \ | |
37 | do { \ | |
38 | unsigned long __k0_addr; \ | |
39 | __asm__ __volatile__( \ | |
40 | "nop;nop;nop;nop;nop;nop;nop\n\t" \ | |
41 | "la %0, 1f\n\t" \ | |
42 | "jr %0\n\t" \ | |
43 | "nop\n\t" \ | |
44 | "1: nop\n" \ | |
45 | : "=&r" (__k0_addr)); \ | |
46 | } while (0) | |
47 | ||
48 | #define INVALIDATE_BTB() \ | |
49 | do { \ | |
50 | unsigned long tmp; \ | |
51 | __asm__ __volatile__( \ | |
52 | ".set mips32\n\t" \ | |
53 | "mfc0 %0, $16, 7\n\t" \ | |
54 | "nop\n\t" \ | |
55 | "ori %0, 2\n\t" \ | |
56 | "mtc0 %0, $16, 7\n\t" \ | |
57 | "nop\n\t" \ | |
58 | : "=&r" (tmp)); \ | |
59 | } while (0) | |
60 | ||
61 | #define SYNC_WB() __asm__ __volatile__ ("sync") | |
62 | ||
63 | #else /* CONFIG_JZRISC */ | |
64 | ||
65 | #define K0_TO_K1() do { } while (0) | |
66 | #define K1_TO_K0() do { } while (0) | |
67 | #define INVALIDATE_BTB() do { } while (0) | |
68 | #define SYNC_WB() do { } while (0) | |
69 | ||
70 | #endif /* CONFIG_JZRISC */ | |
71 | ||
20 | 72 | /* |
21 | 73 | * This macro return a properly sign-extended address suitable as base address |
22 | 74 | * for indexed cache operations. Two issues here: |
... | ... | |
144 | 196 | { |
145 | 197 | __iflush_prologue |
146 | 198 | cache_op(Index_Invalidate_I, addr); |
199 | INVALIDATE_BTB(); | |
147 | 200 | __iflush_epilogue |
148 | 201 | } |
149 | 202 | |
... | ... | |
151 | 204 | { |
152 | 205 | __dflush_prologue |
153 | 206 | cache_op(Index_Writeback_Inv_D, addr); |
207 | SYNC_WB(); | |
154 | 208 | __dflush_epilogue |
155 | 209 | } |
156 | 210 | |
... | ... | |
163 | 217 | { |
164 | 218 | __iflush_prologue |
165 | 219 | cache_op(Hit_Invalidate_I, addr); |
220 | INVALIDATE_BTB(); | |
166 | 221 | __iflush_epilogue |
167 | 222 | } |
168 | 223 | |
... | ... | |
170 | 225 | { |
171 | 226 | __dflush_prologue |
172 | 227 | cache_op(Hit_Writeback_Inv_D, addr); |
228 | SYNC_WB(); | |
173 | 229 | __dflush_epilogue |
174 | 230 | } |
175 | 231 | |
... | ... | |
177 | 233 | { |
178 | 234 | __dflush_prologue |
179 | 235 | cache_op(Hit_Invalidate_D, addr); |
236 | SYNC_WB(); | |
180 | 237 | __dflush_epilogue |
181 | 238 | } |
182 | 239 | |
... | ... | |
209 | 266 | static inline void protected_flush_icache_line(unsigned long addr) |
210 | 267 | { |
211 | 268 | protected_cache_op(Hit_Invalidate_I, addr); |
269 | INVALIDATE_BTB(); | |
212 | 270 | } |
213 | 271 | |
214 | 272 | /* |
... | ... | |
220 | 278 | static inline void protected_writeback_dcache_line(unsigned long addr) |
221 | 279 | { |
222 | 280 | protected_cache_op(Hit_Writeback_Inv_D, addr); |
281 | SYNC_WB(); | |
223 | 282 | } |
224 | 283 | |
225 | 284 | static inline void protected_writeback_scache_line(unsigned long addr) |
... | ... | |
396 | 455 | __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16) |
397 | 456 | __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16) |
398 | 457 | __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16) |
458 | #ifndef CONFIG_JZRISC | |
399 | 459 | __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32) |
400 | 460 | __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32) |
461 | #endif | |
401 | 462 | __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32) |
402 | 463 | __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64) |
403 | 464 | __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64) |
... | ... | |
405 | 466 | __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128) |
406 | 467 | |
407 | 468 | __BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16) |
469 | #ifndef CONFIG_JZRISC | |
408 | 470 | __BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32) |
471 | #endif | |
409 | 472 | __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16) |
410 | 473 | __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32) |
411 | 474 | __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64) |
412 | 475 | __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128) |
413 | 476 | |
477 | #ifdef CONFIG_JZRISC | |
478 | ||
479 | static inline void blast_dcache32(void) | |
480 | { | |
481 | unsigned long start = INDEX_BASE; | |
482 | unsigned long end = start + current_cpu_data.dcache.waysize; | |
483 | unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; | |
484 | unsigned long ws_end = current_cpu_data.dcache.ways << | |
485 | current_cpu_data.dcache.waybit; | |
486 | unsigned long ws, addr; | |
487 | ||
488 | for (ws = 0; ws < ws_end; ws += ws_inc) | |
489 | for (addr = start; addr < end; addr += 0x400) | |
490 | cache32_unroll32(addr|ws,Index_Writeback_Inv_D); | |
491 | ||
492 | SYNC_WB(); | |
493 | } | |
494 | ||
495 | static inline void blast_dcache32_page(unsigned long page) | |
496 | { | |
497 | unsigned long start = page; | |
498 | unsigned long end = page + PAGE_SIZE; | |
499 | ||
500 | do { | |
501 | cache32_unroll32(start,Hit_Writeback_Inv_D); | |
502 | start += 0x400; | |
503 | } while (start < end); | |
504 | ||
505 | SYNC_WB(); | |
506 | } | |
507 | ||
508 | static inline void blast_dcache32_page_indexed(unsigned long page) | |
509 | { | |
510 | unsigned long indexmask = current_cpu_data.dcache.waysize - 1; | |
511 | unsigned long start = INDEX_BASE + (page & indexmask); | |
512 | unsigned long end = start + PAGE_SIZE; | |
513 | unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; | |
514 | unsigned long ws_end = current_cpu_data.dcache.ways << | |
515 | current_cpu_data.dcache.waybit; | |
516 | unsigned long ws, addr; | |
517 | ||
518 | for (ws = 0; ws < ws_end; ws += ws_inc) | |
519 | for (addr = start; addr < end; addr += 0x400) | |
520 | cache32_unroll32(addr|ws,Index_Writeback_Inv_D); | |
521 | ||
522 | SYNC_WB(); | |
523 | } | |
524 | ||
525 | static inline void blast_icache32(void) | |
526 | { | |
527 | unsigned long start = INDEX_BASE; | |
528 | unsigned long end = start + current_cpu_data.icache.waysize; | |
529 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; | |
530 | unsigned long ws_end = current_cpu_data.icache.ways << | |
531 | current_cpu_data.icache.waybit; | |
532 | unsigned long ws, addr; | |
533 | ||
534 | K0_TO_K1(); | |
535 | ||
536 | for (ws = 0; ws < ws_end; ws += ws_inc) | |
537 | for (addr = start; addr < end; addr += 0x400) | |
538 | cache32_unroll32(addr|ws,Index_Invalidate_I); | |
539 | ||
540 | INVALIDATE_BTB(); | |
541 | ||
542 | K1_TO_K0(); | |
543 | } | |
544 | ||
545 | static inline void blast_icache32_page(unsigned long page) | |
546 | { | |
547 | unsigned long start = page; | |
548 | unsigned long end = page + PAGE_SIZE; | |
549 | ||
550 | K0_TO_K1(); | |
551 | ||
552 | do { | |
553 | cache32_unroll32(start,Hit_Invalidate_I); | |
554 | start += 0x400; | |
555 | } while (start < end); | |
556 | ||
557 | INVALIDATE_BTB(); | |
558 | ||
559 | K1_TO_K0(); | |
560 | } | |
561 | ||
562 | static inline void blast_icache32_page_indexed(unsigned long page) | |
563 | { | |
564 | unsigned long indexmask = current_cpu_data.icache.waysize - 1; | |
565 | unsigned long start = INDEX_BASE + (page & indexmask); | |
566 | unsigned long end = start + PAGE_SIZE; | |
567 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; | |
568 | unsigned long ws_end = current_cpu_data.icache.ways << | |
569 | current_cpu_data.icache.waybit; | |
570 | unsigned long ws, addr; | |
571 | ||
572 | K0_TO_K1(); | |
573 | ||
574 | for (ws = 0; ws < ws_end; ws += ws_inc) | |
575 | for (addr = start; addr < end; addr += 0x400) | |
576 | cache32_unroll32(addr|ws,Index_Invalidate_I); | |
577 | ||
578 | INVALIDATE_BTB(); | |
579 | ||
580 | K1_TO_K0(); | |
581 | } | |
582 | ||
583 | #endif /* CONFIG_JZRISC */ | |
584 | ||
414 | 585 | /* build blast_xxx_range, protected_blast_xxx_range */ |
415 | 586 | #define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \ |
416 | 587 | static inline void prot##blast_##pfx##cache##_range(unsigned long start, \ |
... | ... | |
432 | 603 | __##pfx##flush_epilogue \ |
433 | 604 | } |
434 | 605 | |
606 | #ifndef CONFIG_JZRISC | |
435 | 607 | __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_) |
608 | #endif | |
436 | 609 | __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_) |
610 | #ifndef CONFIG_JZRISC | |
437 | 611 | __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_) |
438 | 612 | __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, ) |
613 | #endif | |
439 | 614 | __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, ) |
440 | 615 | /* blast_inv_dcache_range */ |
441 | 616 | __BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, ) |
442 | 617 | __BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, ) |
443 | 618 | |
619 | #ifdef CONFIG_JZRISC | |
620 | ||
621 | static inline void protected_blast_dcache_range(unsigned long start, | |
622 | unsigned long end) | |
623 | { | |
624 | unsigned long lsize = cpu_dcache_line_size(); | |
625 | unsigned long addr = start & ~(lsize - 1); | |
626 | unsigned long aend = (end - 1) & ~(lsize - 1); | |
627 | ||
628 | while (1) { | |
629 | protected_cache_op(Hit_Writeback_Inv_D, addr); | |
630 | if (addr == aend) | |
631 | break; | |
632 | addr += lsize; | |
633 | } | |
634 | SYNC_WB(); | |
635 | } | |
636 | ||
637 | static inline void protected_blast_icache_range(unsigned long start, | |
638 | unsigned long end) | |
639 | { | |
640 | unsigned long lsize = cpu_icache_line_size(); | |
641 | unsigned long addr = start & ~(lsize - 1); | |
642 | unsigned long aend = (end - 1) & ~(lsize - 1); | |
643 | ||
644 | K0_TO_K1(); | |
645 | ||
646 | while (1) { | |
647 | protected_cache_op(Hit_Invalidate_I, addr); | |
648 | if (addr == aend) | |
649 | break; | |
650 | addr += lsize; | |
651 | } | |
652 | INVALIDATE_BTB(); | |
653 | ||
654 | K1_TO_K0(); | |
655 | } | |
656 | ||
657 | static inline void blast_dcache_range(unsigned long start, | |
658 | unsigned long end) | |
659 | { | |
660 | unsigned long lsize = cpu_dcache_line_size(); | |
661 | unsigned long addr = start & ~(lsize - 1); | |
662 | unsigned long aend = (end - 1) & ~(lsize - 1); | |
663 | ||
664 | while (1) { | |
665 | cache_op(Hit_Writeback_Inv_D, addr); | |
666 | if (addr == aend) | |
667 | break; | |
668 | addr += lsize; | |
669 | } | |
670 | SYNC_WB(); | |
671 | } | |
672 | ||
673 | #endif /* CONFIG_JZRISC */ | |
674 | ||
444 | 675 | #endif /* _ASM_R4KCACHE_H */ |
arch/mips/include/asm/suspend.h | ||
---|---|---|
2 | 2 | #define __ASM_SUSPEND_H |
3 | 3 | |
4 | 4 | static inline int arch_prepare_suspend(void) { return 0; } |
5 | #if defined(CONFIG_PM) && defined(CONFIG_JZSOC) | |
6 | extern int jz_pm_init(void); | |
7 | #endif | |
5 | 8 | |
6 | 9 | /* References to section boundaries */ |
7 | 10 | extern const void __nosave_begin, __nosave_end; |
arch/mips/kernel/cpu-probe.c | ||
---|---|---|
160 | 160 | case CPU_PR4450: |
161 | 161 | case CPU_BCM3302: |
162 | 162 | case CPU_CAVIUM_OCTEON: |
163 | case CPU_JZRISC: | |
163 | 164 | cpu_wait = r4k_wait; |
164 | 165 | break; |
165 | 166 | |
... | ... | |
888 | 889 | } |
889 | 890 | } |
890 | 891 | |
892 | static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) | |
893 | { | |
894 | decode_configs(c); | |
895 | c->options &= ~MIPS_CPU_COUNTER; /* JZRISC does not implement the CP0 counter. */ | |
896 | switch (c->processor_id & 0xff00) { | |
897 | case PRID_IMP_JZRISC: | |
898 | c->cputype = CPU_JZRISC; | |
899 | c->isa_level = MIPS_CPU_ISA_M32R1; | |
900 | c->tlbsize = 32; | |
901 | __cpu_name[cpu] = "Ingenic JZRISC"; | |
902 | break; | |
903 | default: | |
904 | panic("Unknown Ingenic Processor ID!"); | |
905 | break; | |
906 | } | |
907 | } | |
908 | ||
891 | 909 | const char *__cpu_name[NR_CPUS]; |
892 | 910 | |
893 | 911 | __cpuinit void cpu_probe(void) |
... | ... | |
925 | 943 | case PRID_COMP_CAVIUM: |
926 | 944 | cpu_probe_cavium(c, cpu); |
927 | 945 | break; |
946 | case PRID_COMP_INGENIC: | |
947 | cpu_probe_ingenic(c, cpu); | |
948 | break; | |
928 | 949 | } |
929 | 950 | |
930 | 951 | BUG_ON(!__cpu_name[cpu]); |
arch/mips/mm/c-r4k.c | ||
---|---|---|
928 | 928 | c->dcache.waybit = 0; |
929 | 929 | break; |
930 | 930 | |
931 | case CPU_JZRISC: | |
932 | config1 = read_c0_config1(); | |
933 | config1 = (config1 >> 22) & 0x07; | |
934 | if (config1 == 0x07) | |
935 | config1 = 10; | |
936 | else | |
937 | config1 = config1 + 11; | |
938 | config1 += 2; | |
939 | icache_size = (1 << config1); | |
940 | c->icache.linesz = 32; | |
941 | c->icache.ways = 4; | |
942 | c->icache.waybit = __ffs(icache_size / c->icache.ways); | |
943 | ||
944 | config1 = read_c0_config1(); | |
945 | config1 = (config1 >> 13) & 0x07; | |
946 | if (config1 == 0x07) | |
947 | config1 = 10; | |
948 | else | |
949 | config1 = config1 + 11; | |
950 | config1 += 2; | |
951 | dcache_size = (1 << config1); | |
952 | c->dcache.linesz = 32; | |
953 | c->dcache.ways = 4; | |
954 | c->dcache.waybit = __ffs(dcache_size / c->dcache.ways); | |
955 | ||
956 | c->dcache.flags = 0; | |
957 | c->options |= MIPS_CPU_PREFETCH; | |
958 | ||
959 | break; | |
960 | ||
931 | 961 | default: |
932 | 962 | if (!(config & MIPS_CONF_M)) |
933 | 963 | panic("Don't know how to probe P-caches on this cpu."); |
arch/mips/mm/cache.c | ||
---|---|---|
52 | 52 | void (*_dma_cache_inv)(unsigned long start, unsigned long size); |
53 | 53 | |
54 | 54 | EXPORT_SYMBOL(_dma_cache_wback_inv); |
55 | EXPORT_SYMBOL(_dma_cache_wback); | |
56 | EXPORT_SYMBOL(_dma_cache_inv); | |
55 | 57 | |
56 | 58 | #endif /* CONFIG_DMA_NONCOHERENT */ |
57 | 59 |
arch/mips/mm/tlbex.c | ||
---|---|---|
385 | 385 | tlbw(p); |
386 | 386 | break; |
387 | 387 | |
388 | case CPU_JZRISC: | |
389 | tlbw(p); | |
390 | uasm_i_nop(p); | |
391 | break; | |
392 | ||
388 | 393 | default: |
389 | 394 | panic("No TLB refill handler yet (CPU type: %d)", |
390 | 395 | current_cpu_data.cputype); |
Branches:
ben-wpan
ben-wpan-stefan
5396a9238205f20f811ea57898980d3ca82df0b6
jz-2.6.34
jz-2.6.34-rc5
jz-2.6.34-rc6
jz-2.6.34-rc7
jz-2.6.35
jz-2.6.36
jz-2.6.37
jz-2.6.38
jz-2.6.39
jz-3.0
jz-3.1
jz-3.11
jz-3.12
jz-3.13
jz-3.15
jz-3.16
jz-3.18-dt
jz-3.2
jz-3.3
jz-3.4
jz-3.5
jz-3.6
jz-3.6-rc2-pwm
jz-3.9
jz-3.9-clk
jz-3.9-rc8
jz47xx
jz47xx-2.6.38
master
Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9