| Date: | 2010-07-16 19:25:09 (13 years 5 months ago) |
|---|---|
| Author: | Lars C. |
| Commit: | 2d6b4fe3044f3bee94f0f3f8d9deabb15ba1d1f9 |
| Message: | fbdev: jz4740: Add special tft type lcds support. |
| Files: |
drivers/video/jz4740_fb.c (8 diffs) include/linux/jz4740_fb.h (2 diffs) |
Change Details
| drivers/video/jz4740_fb.c | ||
|---|---|---|
| 153 | 153 | JZ_GPIO_BULK_PIN(LCD_DE), |
| 154 | 154 | JZ_GPIO_BULK_PIN(LCD_PS), |
| 155 | 155 | JZ_GPIO_BULK_PIN(LCD_REV), |
| 156 | JZ_GPIO_BULK_PIN(LCD_CLS), | |
| 157 | JZ_GPIO_BULK_PIN(LCD_SPL), | |
| 156 | 158 | }; |
| 157 | 159 | |
| 158 | 160 | static const struct jz_gpio_bulk_request jz_lcd_data_pins[] = { |
| ... | ... | |
| 190 | 192 | case JZ_LCD_TYPE_8BIT_SERIAL: |
| 191 | 193 | num = 3; |
| 192 | 194 | break; |
| 195 | case JZ_LCD_TYPE_SPECIAL_TFT_1: | |
| 196 | case JZ_LCD_TYPE_SPECIAL_TFT_2: | |
| 197 | case JZ_LCD_TYPE_SPECIAL_TFT_3: | |
| 198 | num = 8; | |
| 199 | break; | |
| 193 | 200 | default: |
| 194 | 201 | num = 0; |
| 195 | 202 | break; |
| ... | ... | |
| 211 | 218 | case JZ_LCD_TYPE_8BIT_SERIAL: |
| 212 | 219 | num = 8; |
| 213 | 220 | break; |
| 221 | case JZ_LCD_TYPE_SPECIAL_TFT_1: | |
| 222 | case JZ_LCD_TYPE_SPECIAL_TFT_2: | |
| 223 | case JZ_LCD_TYPE_SPECIAL_TFT_3: | |
| 224 | if (jzfb->pdata->bpp == 18) | |
| 225 | num = 18; | |
| 226 | else | |
| 227 | num = 16; | |
| 228 | break; | |
| 214 | 229 | default: |
| 215 | 230 | num = 0; |
| 216 | 231 | break; |
| ... | ... | |
| 335 | 350 | static int jzfb_set_par(struct fb_info *info) |
| 336 | 351 | { |
| 337 | 352 | struct jzfb *jzfb = info->par; |
| 353 | struct jz4740_fb_platform_data *pdata = jzfb->pdata; | |
| 338 | 354 | struct fb_var_screeninfo *var = &info->var; |
| 339 | 355 | struct fb_videomode *mode; |
| 340 | 356 | uint16_t hds, vds; |
| ... | ... | |
| 363 | 379 | |
| 364 | 380 | ctrl = JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16; |
| 365 | 381 | |
| 366 | switch (jzfb->pdata->bpp) { | |
| 382 | switch (pdata->bpp) { | |
| 367 | 383 | case 1: |
| 368 | 384 | ctrl |= JZ_LCD_CTRL_BPP_1; |
| 369 | 385 | break; |
| ... | ... | |
| 390 | 406 | break; |
| 391 | 407 | } |
| 392 | 408 | |
| 393 | cfg = JZ_LCD_CFG_PS_DISABLE | JZ_LCD_CFG_CLS_DISABLE | | |
| 394 | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE; | |
| 409 | cfg = pdata->lcd_type & 0xf; | |
| 395 | 410 | |
| 396 | 411 | if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT)) |
| 397 | 412 | cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW; |
| ... | ... | |
| 399 | 414 | if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT)) |
| 400 | 415 | cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW; |
| 401 | 416 | |
| 402 | if (jzfb->pdata->pixclk_falling_edge) | |
| 417 | if (pdata->pixclk_falling_edge) | |
| 403 | 418 | cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE; |
| 404 | 419 | |
| 405 | if (jzfb->pdata->date_enable_active_low) | |
| 420 | if (pdata->date_enable_active_low) | |
| 406 | 421 | cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW; |
| 407 | 422 | |
| 408 | if (jzfb->pdata->lcd_type == JZ_LCD_TYPE_GENERIC_18_BIT) | |
| 423 | if (pdata->lcd_type == JZ_LCD_TYPE_GENERIC_18_BIT) | |
| 409 | 424 | cfg |= JZ_LCD_CFG_18_BIT; |
| 410 | 425 | |
| 411 | cfg |= jzfb->pdata->lcd_type & 0xf; | |
| 412 | ||
| 413 | 426 | if (mode->pixclock) { |
| 414 | 427 | rate = PICOS2KHZ(mode->pixclock) * 1000; |
| 415 | 428 | mode->refresh = rate / vt / ht; |
| 416 | 429 | } else { |
| 417 | if (jzfb->pdata->lcd_type == JZ_LCD_TYPE_8BIT_SERIAL) | |
| 430 | if (pdata->lcd_type == JZ_LCD_TYPE_8BIT_SERIAL) | |
| 418 | 431 | rate = mode->refresh * (vt + 2 * mode->xres) * ht; |
| 419 | 432 | else |
| 420 | 433 | rate = mode->refresh * vt * ht; |
| ... | ... | |
| 428 | 441 | else |
| 429 | 442 | ctrl |= JZ_LCD_CTRL_ENABLE; |
| 430 | 443 | |
| 444 | switch (pdata->lcd_type) { | |
| 445 | case JZ_LCD_TYPE_SPECIAL_TFT_1: | |
| 446 | case JZ_LCD_TYPE_SPECIAL_TFT_2: | |
| 447 | case JZ_LCD_TYPE_SPECIAL_TFT_3: | |
| 448 | writel(pdata->special_tft_config.spl, jzfb->base + JZ_REG_LCD_SPL); | |
| 449 | writel(pdata->special_tft_config.cls, jzfb->base + JZ_REG_LCD_CLS); | |
| 450 | writel(pdata->special_tft_config.ps, jzfb->base + JZ_REG_LCD_PS); | |
| 451 | writel(pdata->special_tft_config.ps, jzfb->base + JZ_REG_LCD_REV); | |
| 452 | break; | |
| 453 | default: | |
| 454 | cfg |= JZ_LCD_CFG_PS_DISABLE; | |
| 455 | cfg |= JZ_LCD_CFG_CLS_DISABLE; | |
| 456 | cfg |= JZ_LCD_CFG_SPL_DISABLE; | |
| 457 | cfg |= JZ_LCD_CFG_REV_DISABLE; | |
| 458 | break; | |
| 459 | } | |
| 460 | ||
| 431 | 461 | writel(mode->hsync_len, jzfb->base + JZ_REG_LCD_HSYNC); |
| 432 | 462 | writel(mode->vsync_len, jzfb->base + JZ_REG_LCD_VSYNC); |
| 433 | 463 | |
| include/linux/jz4740_fb.h | ||
|---|---|---|
| 32 | 32 | JZ_LCD_TYPE_8BIT_SERIAL = 12, |
| 33 | 33 | }; |
| 34 | 34 | |
| 35 | #define JZ4740_FB_SPECIAL_TFT_CONFIG(start, stop) (((start) << 16) | (stop)) | |
| 36 | ||
| 35 | 37 | /* |
| 36 | 38 | * width: width of the lcd display in mm |
| 37 | 39 | * height: height of the lcd display in mm |
| ... | ... | |
| 51 | 53 | unsigned int bpp; |
| 52 | 54 | enum jz4740_fb_lcd_type lcd_type; |
| 53 | 55 | |
| 56 | struct { | |
| 57 | uint32_t spl; | |
| 58 | uint32_t cls; | |
| 59 | uint32_t ps; | |
| 60 | uint32_t rev; | |
| 61 | } special_tft_config; | |
| 62 | ||
| 54 | 63 | unsigned pixclk_falling_edge:1; |
| 55 | 64 | unsigned date_enable_active_low:1; |
| 56 | 65 | }; |
Branches:
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ben-wpan-stefan
5396a9238205f20f811ea57898980d3ca82df0b6
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Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9
