Date:2013-05-05 18:55:04 (7 years 29 days ago)
Author:Lars C.
Commit:308eb78115de485aca7ffd594cd9b373f1b87ce3
Message:devicetree stuff

Files: arch/mips/Kconfig (1 diff)
arch/mips/jz4740/Makefile (1 diff)
arch/mips/jz4740/board-qi_lb60.c (10 diffs)
arch/mips/jz4740/clock.c (4 diffs)
arch/mips/jz4740/gpio.c (2 diffs)
arch/mips/jz4740/irq.c (3 diffs)
arch/mips/jz4740/prom.c (3 diffs)
arch/mips/jz4740/setup.c (3 diffs)
drivers/dma/dma-jz4740.c (6 diffs)
drivers/mfd/jz4740-adc.c (2 diffs)
drivers/mtd/nand/jz4740_nand.c (4 diffs)

Change Details

arch/mips/Kconfig
249249    select GENERIC_IRQ_CHIP
250250    select CPU_SUPPORTS_CPUFREQ
251251    select COMMON_CLK
252    select USE_OF
252253
253254config LANTIQ
254255    bool "Lantiq based platforms"
arch/mips/jz4740/Makefile
77obj-y += prom.o irq.o time.o reset.o setup.o \
88    gpio.o clock.o platform.o timer.o serial.o
99
10obj-y += dts/
11
1012# board specific support
1113
1214obj-$(CONFIG_JZ4740_QI_LB60) += board-qi_lb60.o
arch/mips/jz4740/board-qi_lb60.c
153153
154154
155155/* Keyboard*/
156
156#if 0
157157#define KEY_QI_QI KEY_F13
158158#define KEY_QI_UPRED KEY_RIGHTALT
159159#define KEY_QI_VOLUP KEY_VOLUMEUP
...... 
269269        .platform_data = &qi_lb60_pdata,
270270    },
271271};
272
272#endif
273273/* Display */
274274static struct fb_videomode qi_lb60_video_modes[] = {
275275    {
...... 
297297    .lcd_type = JZ_LCD_TYPE_8BIT_SERIAL,
298298    .pixclk_falling_edge = 1,
299299};
300
300#if 0
301301struct spi_gpio_platform_data spigpio_platform_data = {
302302    .sck = JZ_GPIO_PORTC(23),
303303    .mosi = JZ_GPIO_PORTC(22),
...... 
322322        .max_speed_hz = 30 * 1000,
323323    },
324324};
325#endif
325326
326327/* Battery */
327328static struct jz_battery_platform_data qi_lb60_battery_pdata = {
...... 
334335        .voltage_min_design = 3600000,
335336    },
336337};
337
338#if 0
338339/* GPIO Key: power */
339340static struct gpio_keys_button qi_lb60_gpio_keys_buttons[] = {
340341    [0] = {
...... 
358359        .platform_data = &qi_lb60_gpio_keys_data,
359360    }
360361};
361
362#endif
363#if 0
362364static struct regulator_consumer_supply qi_lb60_mmc_regulator_consumer =
363365    REGULATOR_SUPPLY("vmmc", "jz4740-mmc.0");
364366
...... 
390392        .platform_data = &qi_lb60_mmc_regulator_data,
391393    }
392394};
395#endif
393396
394397static struct jz4740_mmc_platform_data qi_lb60_mmc_pdata = {
395398    .gpio_card_detect = QI_LB60_GPIO_SD_CD,
396399    .gpio_read_only = -1,
397400};
398
399401/* OHCI */
400402static struct regulator_consumer_supply avt2_usb_regulator_consumer =
401403    REGULATOR_SUPPLY("vbus", "jz4740-ohci");
...... 
457459    },
458460};
459461
462#if 0
460463/* audio */
461464static struct platform_device qi_lb60_audio_device = {
462465    .name = "qi-lb60-audio",
463466    .id = -1,
464467};
468#endif
465469
466470static struct gpiod_lookup_table qi_lb60_audio_gpio_table = {
467471    .dev_id = "qi-lb60-audio",
...... 
473477};
474478
475479static struct platform_device *jz_platform_devices[] __initdata = {
480#if 0
476481    &jz4740_udc_device,
477482    &jz4740_udc_xceiv_device,
478483    &jz4740_mmc_device,
484#endif
479485    &jz4740_nand_device,
480    &qi_lb60_keypad,
481    &spigpio_device,
486/* &qi_lb60_keypad,*/
487/* &spigpio_device,*/
482488    &jz4740_framebuffer_device,
483    &jz4740_pcm_device,
489/* &jz4740_pcm_device,
484490    &jz4740_i2s_device,
485    &jz4740_codec_device,
486    &jz4740_rtc_device,
491    &jz4740_codec_device,*/
492/* &jz4740_rtc_device,*/
487493    &jz4740_adc_device,
488494    &jz4740_pwm_device,
489    &jz4740_dma_device,
490    &qi_lb60_gpio_keys,
495/* &jz4740_dma_device,*/
496/* &qi_lb60_gpio_keys,*/
491497    &qi_lb60_pwm_beeper,
492498    &qi_lb60_charger_device,
493    &qi_lb60_audio_device,
494    &qi_lb60_mmc_regulator_device,
499/* &qi_lb60_audio_device,*/
500/* &qi_lb60_mmc_regulator_device,*/
495501};
496502
497503static void __init board_gpio_setup(void)
...... 
514520
515521    jz4740_serial_device_register();
516522
523#if 0
517524    spi_register_board_info(qi_lb60_spi_board_info,
518525                ARRAY_SIZE(qi_lb60_spi_board_info));
519
526#endif
520527    if (is_avt2) {
521528        platform_device_register(&avt2_usb_regulator_device);
522529        platform_device_register(&jz4740_usb_ohci_device);
arch/mips/jz4740/clock.c
481481    clk = jz4740_register_gate("rtc", "RTCLK_XI", JZ_CLOCK_GATE_RTC);
482482    clk_register_clkdev(clk, "rtc", "jz4740-rtc");
483483    clk_register_clkdev(clk, "rtc", "jz4740-wdt");
484    clk_register_clkdev(clk, "rtc", "10003000.rtc");
484485
485486#if 0
486487    jz4740_register_gate("uart0", "EXCLK", JZ_CLOCK_GATE_UART0);
...... 
503504
504505    clk = jz4740_register_gate("aic", "EXCLK", JZ_CLOCK_GATE_AIC);
505506    clk_register_clkdev(clk, "aic", "jz4740-i2s");
507    clk_register_clkdev(clk, "aic", "10020000.aic");
506508
507509    clk_register_divider_table(NULL, "PERIP CLK", "PLL", 0,
508510        jz4740_clk_base + JZ_REG_CLOCK_CTRL, 21, 1, 0,
...... 
513515        JZ_REG_CLOCK_I2S, 0, 9,
514516        JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_I2S);
515517    clk_register_clkdev(clk, "i2s", "jz4740-i2s");
518    clk_register_clkdev(clk, "i2s", "10020000.aic");
516519
517520    jz4740_register_peripheral_clock("spi", "EXCLK",
518521        JZ_REG_CLOCK_SPI, 31,
...... 
533536        JZ_REG_CLOCK_MMC, 0, 5,
534537        JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_MMC);
535538    clk_register_clkdev(clk, "mmc", "jz4740-mmc.0");
539    clk_register_clkdev(clk, "mmc", "10021000.msc");
536540
537541    clk = jz4740_register_peripheral_clock("uhc", NULL, 0, 0,
538542        JZ_REG_CLOCK_UHC, 0, 4,
arch/mips/jz4740/gpio.c
2222#include <linux/delay.h>
2323#include <linux/interrupt.h>
2424#include <linux/bitops.h>
25#include <linux/of.h>
2526
2627#include <linux/debugfs.h>
2728#include <linux/seq_file.h>
...... 
458459
459460static int __init jz4740_gpio_init(void)
460461{
461    unsigned int i;
462    struct device_node *np;
463    unsigned int i = 0;
464
465    for_each_compatible_node(np, NULL, "ingenic,jz4740-gpio") {
466        jz4740_gpio_chips[i].gpio_chip.of_node = np;
467        i++;
468    }
462469
463470    for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i)
464471        jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i);
arch/mips/jz4740/irq.c
2121#include <linux/timex.h>
2222#include <linux/slab.h>
2323#include <linux/delay.h>
24#include <linux/of.h>
25#include <linux/irqdomain.h>
26#include <linux/of_irq.h>
2427
2528#include <linux/debugfs.h>
2629#include <linux/seq_file.h>
...... 
7679    .name = "JZ4740 cascade interrupt",
7780};
7881
82static struct of_device_id __initdata of_irq_ids[] = {
83    { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
84    {},
85};
86
7987void __init arch_init_irq(void)
8088{
8189    struct irq_chip_generic *gc;
8290    struct irq_chip_type *ct;
91    struct irq_domain *domain;
92    struct device_node *np;
93    int ret;
8394
95    of_irq_init(of_irq_ids);
8496    mips_cpu_irq_init();
8597
98    np = of_find_compatible_node(NULL, NULL, "ingenic,jz4740-intc");
99
86100    jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14);
87101
88102    /* Mask all irqs */
89103    writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK);
90104
91    gc = irq_alloc_generic_chip("INTC", 1, JZ4740_IRQ_BASE, jz_intc_base,
92        handle_level_irq);
105    domain = irq_domain_add_linear(np, 32, &irq_generic_chip_ops,
106    NULL);
107
108    ret = irq_alloc_domain_generic_chips(domain, 32, 1, "INTC",
109        handle_level_irq, 0, IRQ_NOPROBE | IRQ_LEVEL, 0);
110    printk("INTC: %d\n", ret);
111
112    gc = irq_get_domain_generic_chip(domain, 0);
93113
94114    gc->wake_enabled = IRQ_MSK(32);
95115
...... 
102122    ct->chip.irq_set_wake = irq_gc_set_wake;
103123    ct->chip.irq_suspend = jz4740_irq_suspend;
104124    ct->chip.irq_resume = jz4740_irq_resume;
125    gc->reg_base = jz_intc_base;
105126
106    irq_setup_generic_chip(gc, IRQ_MSK(32), 0, 0, IRQ_NOPROBE | IRQ_LEVEL);
127    irq_domain_associate_many(domain, JZ4740_IRQ_BASE, 0, 32);
107128
108129    setup_irq(2, &jz4740_cascade_action);
109130}
arch/mips/jz4740/prom.c
1717#include <linux/kernel.h>
1818#include <linux/init.h>
1919#include <linux/string.h>
20#include <linux/bootmem.h>
21#include <linux/of_platform.h>
22#include <linux/of_fdt.h>
2023
2124#include <linux/serial_reg.h>
2225
...... 
4447    *dst = 0;
4548}
4649
50void __init device_tree_init(void)
51{
52    unflatten_and_copy_device_tree();
53}
54
4755void __init prom_init(void)
4856{
4957    jz4740_init_cmdline((int)fw_arg0, (char **)fw_arg1);
...... 
6674
6775    writeb(c, UART_REG(UART_TX));
6876}
77
78static const struct of_device_id __initdata of_ids[] = {
79    { .compatible = "simple-bus", },
80    {},
81};
82
83static int __init plat_of_setup(void)
84{
85    if (!of_have_populated_dt())
86        return 0;
87    return of_platform_bus_probe(NULL, of_ids, NULL);
88}
89arch_initcall(plat_of_setup);
arch/mips/jz4740/setup.c
1717#include <linux/init.h>
1818#include <linux/io.h>
1919#include <linux/kernel.h>
20#include <linux/of_platform.h>
21#include <linux/of_fdt.h>
2022
2123#include <asm/bootinfo.h>
24#include <asm/mips-boards/generic.h>
25#include <asm/prom.h>
2226
2327#include <asm/mach-jz4740/base.h>
2428
...... 
2731
2832#define JZ4740_EMC_SDRAM_CTRL 0x80
2933
30
3134static void __init jz4740_detect_mem(void)
3235{
3336    void __iomem *jz_emc_base;
...... 
5356{
5457    jz4740_reset_init();
5558    jz4740_detect_mem();
59    __dt_setup_arch(&__dtb_start);
5660}
5761
5862const char *get_system_type(void)
drivers/dma/dma-jz4740.c
2424#include <linux/spinlock.h>
2525#include <linux/irq.h>
2626#include <linux/clk.h>
27#include <linux/of_dma.h>
2728
2829#include <asm/mach-jz4740/dma.h>
2930
...... 
125126
126127    struct jz4740_dma_desc *desc;
127128    unsigned int next_sg;
129
130    unsigned int mode;
128131};
129132
130133struct jz4740_dma_dev {
...... 
260263    cmd |= src_width << JZ_DMA_CMD_SRC_WIDTH_OFFSET;
261264    cmd |= dst_width << JZ_DMA_CMD_DST_WIDTH_OFFSET;
262265    cmd |= transfer_size << JZ_DMA_CMD_TRANSFER_SIZE_OFFSET;
263    cmd |= JZ4740_DMA_MODE_SINGLE << JZ_DMA_CMD_MODE_OFFSET;
266    cmd |= chan->mode << JZ_DMA_CMD_MODE_OFFSET;
264267    cmd |= JZ_DMA_CMD_TRANSFER_IRQ_ENABLE;
265268
266269    jz4740_dma_write(dmadev, JZ_REG_DMA_CMD(chan->id), cmd);
...... 
526529    kfree(container_of(vdesc, struct jz4740_dma_desc, vdesc));
527530}
528531
532struct jz4740_dma_filter_args {
533    struct dma_device *dev;
534    unsigned int slave_id;
535    unsigned int prio;
536    unsigned int mode;
537};
538
539static bool jz4740_of_filter(struct dma_chan *c, void *param)
540{
541    struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
542    struct jz4740_dma_filter_args *fargs = param;
543
544    if (c->device != fargs->dev)
545        return false;
546
547    if (chan->id <= 3 && fargs->prio == 1)
548        return false;
549
550    if (chan->id >= 4 && fargs->prio == 0)
551        return false;
552
553    chan->mode = fargs->mode;
554/* chan->slave_id = fargs->salve_id;*/
555
556    return true;
557}
558
559static struct dma_chan *jz4740_dma_of_xlate(struct of_phandle_args *dma_spec,
560    struct of_dma *ofdma)
561{
562    struct jz4740_dma_filter_args fargs;
563    dma_cap_mask_t cap;
564
565    if (dma_spec->args_count != 3)
566        return NULL;
567
568    fargs.dev = ofdma->of_dma_data;
569    fargs.slave_id = dma_spec->args[0];
570    fargs.prio = dma_spec->args[1];
571    fargs.mode = dma_spec->args[2];
572
573    dma_cap_zero(cap);
574    dma_cap_set(DMA_SLAVE, cap);
575
576    return dma_request_channel(cap, jz4740_of_filter, &fargs);
577
578}
579
529580static int jz4740_dma_probe(struct platform_device *pdev)
530581{
531582    struct jz4740_dmaengine_chan *chan;
...... 
577628    if (ret)
578629        return ret;
579630
631    of_dma_controller_register(pdev->dev.of_node, jz4740_dma_of_xlate,
632            &dmadev->ddev);
633
580634    irq = platform_get_irq(pdev, 0);
581635    ret = request_irq(irq, jz4740_dma_irq, 0, dev_name(&pdev->dev), dmadev);
582636    if (ret)
...... 
603657    return 0;
604658}
605659
660static const struct of_device_id jz4740_dma_of_match[] = {
661    { .compatible = "ingenic,jz4740-dmac" },
662    {},
663};
664MODULE_DEVICE_TABLE(of, jz4740_dma_of_match);
665
606666static struct platform_driver jz4740_dma_driver = {
607667    .probe = jz4740_dma_probe,
608668    .remove = jz4740_dma_remove,
609669    .driver = {
610670        .name = "jz4740-dma",
611671        .owner = THIS_MODULE,
672        .of_match_table = jz4740_dma_of_match,
612673    },
613674};
614675module_platform_driver(jz4740_dma_driver);
drivers/mfd/jz4740-adc.c
157157}
158158EXPORT_SYMBOL_GPL(jz4740_adc_set_config);
159159
160static struct resource jz4740_hwmon_resources[] = {
160static struct resource jz4740_iio_resources[] = {
161161    {
162162        .start = JZ_ADC_IRQ_ADCIN,
163163        .flags = IORESOURCE_IRQ,
164164    },
165165    {
166        .start = JZ_REG_ADC_HWMON_BASE,
167        .end = JZ_REG_ADC_HWMON_BASE + 3,
168        .flags = IORESOURCE_MEM,
169    },
170};
171
172static struct resource jz4740_battery_resources[] = {
173    {
174166        .start = JZ_ADC_IRQ_BATTERY,
175167        .flags = IORESOURCE_IRQ,
176168    },
177169    {
178170        .start = JZ_REG_ADC_BATTERY_BASE,
179        .end = JZ_REG_ADC_BATTERY_BASE + 3,
171        .end = JZ_REG_ADC_BATTERY_BASE + 7,
180172        .flags = IORESOURCE_MEM,
181173    },
182174};
...... 
184176static const struct mfd_cell jz4740_adc_cells[] = {
185177    {
186178        .id = 0,
187        .name = "jz4740-hwmon",
188        .num_resources = ARRAY_SIZE(jz4740_hwmon_resources),
189        .resources = jz4740_hwmon_resources,
190
191        .enable = jz4740_adc_cell_enable,
192        .disable = jz4740_adc_cell_disable,
193    },
194    {
195        .id = 1,
196        .name = "jz4740-battery",
197        .num_resources = ARRAY_SIZE(jz4740_battery_resources),
198        .resources = jz4740_battery_resources,
179        .name = "jz4740-iio",
180        .num_resources = ARRAY_SIZE(jz4740_iio_resources),
181        .resources = jz4740_iio_resources,
199182
200183        .enable = jz4740_adc_cell_enable,
201184        .disable = jz4740_adc_cell_disable,
drivers/mtd/nand/jz4740_nand.c
405405    return ret;
406406}
407407
408static const char *jz_nand_part_probes[] = { "ofpart", NULL };
409
408410static int jz_nand_probe(struct platform_device *pdev)
409411{
410412    int ret;
...... 
414416    struct jz_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
415417    size_t chipnr, bank_idx;
416418    uint8_t nand_maf_id = 0, nand_dev_id = 0;
419    struct mtd_part_parser_data ppdata;
417420
418421    nand = kzalloc(sizeof(*nand), GFP_KERNEL);
419422    if (!nand)
...... 
507510        goto err_unclaim_banks;
508511    }
509512
510    ret = mtd_device_parse_register(mtd, NULL, NULL,
513    ppdata.of_node = pdev->dev.of_node;
514    ret = mtd_device_parse_register(mtd, jz_nand_part_probes, &ppdata,
511515                    pdata ? pdata->partitions : NULL,
512516                    pdata ? pdata->num_partitions : 0);
513517
...... 
563567    return 0;
564568}
565569
570static const struct of_device_id jz4740_nand_of_match[] = {
571    { .compatible = "ingenic,jz4740-nand" },
572    {},
573};
574MODULE_DEVICE_TABLE(of, jz4740_nand_of_match);
575
566576static struct platform_driver jz_nand_driver = {
567577    .probe = jz_nand_probe,
568578    .remove = jz_nand_remove,
569579    .driver = {
570580        .name = "jz4740-nand",
571581        .owner = THIS_MODULE,
582        .of_match_table = jz4740_nand_of_match,
572583    },
573584};
574585

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