Date:2014-07-17 01:42:36 (6 years 22 days ago)
Author:Paul Cercueil
Commit:3d6b748613d01183f75803dfc33cf95250c6159e
Message:pinctrl: JZ4770: Added a pinctrl driver for the JZ4770 SoC

This is a squashed version of development done in the jz-3.12 branch.

Changes in 3.18 migration:
- moved into ingenic/ subdir
- renamed .enable to .set_mux
Files: drivers/pinctrl/Kconfig (1 diff)
drivers/pinctrl/Makefile (1 diff)
drivers/pinctrl/ingenic/Kconfig (1 diff)
drivers/pinctrl/ingenic/Makefile (1 diff)
drivers/pinctrl/ingenic/pinctrl-jz4770.c (1 diff)

Change Details

drivers/pinctrl/Kconfig
205205
206206source "drivers/pinctrl/berlin/Kconfig"
207207source "drivers/pinctrl/freescale/Kconfig"
208source "drivers/pinctrl/ingenic/Kconfig"
208209source "drivers/pinctrl/mvebu/Kconfig"
209210source "drivers/pinctrl/nomadik/Kconfig"
210211source "drivers/pinctrl/qcom/Kconfig"
drivers/pinctrl/Makefile
3939
4040obj-$(CONFIG_ARCH_BERLIN) += berlin/
4141obj-y += freescale/
42obj-y += ingenic/
4243obj-$(CONFIG_PLAT_ORION) += mvebu/
4344obj-y += nomadik/
4445obj-$(CONFIG_ARCH_QCOM) += qcom/
drivers/pinctrl/ingenic/Kconfig
1config PINCTRL_JZ4770
2    bool "Ingenic JZ4770 pinctrl driver"
3    select PINMUX
4    select GENERIC_PINCONF
drivers/pinctrl/ingenic/Makefile
1# Ingenic pin control drivers
2obj-$(CONFIG_PINCTRL_JZ4770) += pinctrl-jz4770.o
drivers/pinctrl/ingenic/pinctrl-jz4770.c
1/*
2 * Pinctrl driver for Ingenic JZ4770 SoC
3 *
4 * Copyright (c) 2014 Paul Cercueil <paul@crapouillou.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <asm/io.h>
17#include <linux/mm.h>
18#include <linux/module.h>
19#include <linux/pinctrl/pinctrl.h>
20#include <linux/pinctrl/pinconf.h>
21#include <linux/pinctrl/pinmux.h>
22#include <linux/pinctrl/pinconf-generic.h>
23#include <linux/platform_device.h>
24
25#define PORTS 6
26#define PINS 32
27#define PORT(x) ((x) / PINS)
28#define PORT_PIN(x) ((x) % PINS)
29
30#define GPA(x) ((x) + 32 * 0)
31#define GPB(x) ((x) + 32 * 1)
32#define GPC(x) ((x) + 32 * 2)
33#define GPD(x) ((x) + 32 * 3)
34#define GPE(x) ((x) + 32 * 4)
35#define GPF(x) ((x) + 32 * 5)
36
37#define INT_OFFSET(port) ((port) * 0x100 + 0x10)
38#define INT_SET_OFFSET(port) ((port) * 0x100 + 0x14)
39#define INT_CLR_OFFSET(port) ((port) * 0x100 + 0x18)
40
41#define MASK_OFFSET(port) ((port) * 0x100 + 0x20)
42#define MASK_SET_OFFSET(port) ((port) * 0x100 + 0x24)
43#define MASK_CLR_OFFSET(port) ((port) * 0x100 + 0x28)
44
45#define PAT1_OFFSET(port) ((port) * 0x100 + 0x30)
46#define PAT1_SET_OFFSET(port) ((port) * 0x100 + 0x34)
47#define PAT1_CLR_OFFSET(port) ((port) * 0x100 + 0x38)
48
49#define PAT0_OFFSET(port) ((port) * 0x100 + 0x40)
50#define PAT0_SET_OFFSET(port) ((port) * 0x100 + 0x44)
51#define PAT0_CLR_OFFSET(port) ((port) * 0x100 + 0x48)
52
53#define PULL_OFFSET(port) ((port) * 0x100 + 0x70)
54#define PULL_SET_OFFSET(port) ((port) * 0x100 + 0x74)
55#define PULL_CLR_OFFSET(port) ((port) * 0x100 + 0x78)
56
57struct jz_pinctrl {
58    struct device *dev;
59    struct pinctrl_dev *pctl;
60    void __iomem *base;
61    spinlock_t lock;
62};
63
64struct jz_pin_group {
65    const char *name;
66    const unsigned int *pins;
67    const u8 *sels;
68    unsigned int num_pins;
69};
70
71struct jz_pmux_func {
72    const char *name;
73    const char * const *groups;
74    unsigned int num_groups;
75};
76
77static struct pinctrl_pin_desc jz_pins[] = {
78#define JZ_PIN_DESC(_name, pin) { \
79    .number = pin, \
80    .name = _name, \
81}
82    /* Port A */
83    JZ_PIN_DESC("A00", GPA(0)),
84    JZ_PIN_DESC("A01", GPA(1)),
85    JZ_PIN_DESC("A02", GPA(2)),
86    JZ_PIN_DESC("A03", GPA(3)),
87    JZ_PIN_DESC("A04", GPA(4)),
88    JZ_PIN_DESC("A05", GPA(5)),
89    JZ_PIN_DESC("A06", GPA(6)),
90    JZ_PIN_DESC("A07", GPA(7)),
91    JZ_PIN_DESC("A08", GPA(8)),
92    JZ_PIN_DESC("A09", GPA(9)),
93    JZ_PIN_DESC("A10", GPA(10)),
94    JZ_PIN_DESC("A11", GPA(11)),
95    JZ_PIN_DESC("A12", GPA(12)),
96    JZ_PIN_DESC("A13", GPA(13)),
97    JZ_PIN_DESC("A14", GPA(14)),
98    JZ_PIN_DESC("A15", GPA(15)),
99    JZ_PIN_DESC("A16", GPA(16)),
100    JZ_PIN_DESC("A17", GPA(17)),
101    JZ_PIN_DESC("A18", GPA(18)),
102    JZ_PIN_DESC("A19", GPA(19)),
103    JZ_PIN_DESC("A20", GPA(20)),
104    JZ_PIN_DESC("A21", GPA(21)),
105    JZ_PIN_DESC("A22", GPA(22)),
106    JZ_PIN_DESC("A23", GPA(23)),
107    JZ_PIN_DESC("A24", GPA(24)),
108    JZ_PIN_DESC("A25", GPA(25)),
109    JZ_PIN_DESC("A26", GPA(26)),
110    JZ_PIN_DESC("A27", GPA(27)),
111    JZ_PIN_DESC("A28", GPA(28)),
112    JZ_PIN_DESC("A29", GPA(29)),
113    JZ_PIN_DESC("A30", GPA(30)),
114    /* A31 does not exist */
115
116    /* Port B */
117    JZ_PIN_DESC("B00", GPB(0)),
118    JZ_PIN_DESC("B01", GPB(1)),
119    JZ_PIN_DESC("B02", GPB(2)),
120    JZ_PIN_DESC("B03", GPB(3)),
121    JZ_PIN_DESC("B04", GPB(4)),
122    JZ_PIN_DESC("B05", GPB(5)),
123    JZ_PIN_DESC("B06", GPB(6)),
124    JZ_PIN_DESC("B07", GPB(7)),
125    JZ_PIN_DESC("B08", GPB(8)),
126    JZ_PIN_DESC("B09", GPB(9)),
127    JZ_PIN_DESC("B10", GPB(10)),
128    JZ_PIN_DESC("B11", GPB(11)),
129    JZ_PIN_DESC("B12", GPB(12)),
130    JZ_PIN_DESC("B13", GPB(13)),
131    JZ_PIN_DESC("B14", GPB(14)),
132    JZ_PIN_DESC("B15", GPB(15)),
133    JZ_PIN_DESC("B16", GPB(16)),
134    JZ_PIN_DESC("B17", GPB(17)),
135    JZ_PIN_DESC("B18", GPB(18)),
136    JZ_PIN_DESC("B19", GPB(19)),
137    JZ_PIN_DESC("B20", GPB(20)),
138    JZ_PIN_DESC("B21", GPB(21)),
139    JZ_PIN_DESC("B22", GPB(22)),
140    JZ_PIN_DESC("B23", GPB(23)),
141    JZ_PIN_DESC("B24", GPB(24)),
142    JZ_PIN_DESC("B25", GPB(25)),
143    JZ_PIN_DESC("B26", GPB(26)),
144    JZ_PIN_DESC("B27", GPB(27)),
145    JZ_PIN_DESC("B28", GPB(28)),
146    JZ_PIN_DESC("B29", GPB(29)),
147    JZ_PIN_DESC("B30", GPB(30)),
148    JZ_PIN_DESC("B31", GPB(31)),
149
150    /* Port C */
151    JZ_PIN_DESC("C00", GPC(0)),
152    JZ_PIN_DESC("C01", GPC(1)),
153    JZ_PIN_DESC("C02", GPC(2)),
154    JZ_PIN_DESC("C03", GPC(3)),
155    JZ_PIN_DESC("C04", GPC(4)),
156    JZ_PIN_DESC("C05", GPC(5)),
157    JZ_PIN_DESC("C06", GPC(6)),
158    JZ_PIN_DESC("C07", GPC(7)),
159    JZ_PIN_DESC("C08", GPC(8)),
160    JZ_PIN_DESC("C09", GPC(9)),
161    JZ_PIN_DESC("C10", GPC(10)),
162    JZ_PIN_DESC("C11", GPC(11)),
163    JZ_PIN_DESC("C12", GPC(12)),
164    JZ_PIN_DESC("C13", GPC(13)),
165    JZ_PIN_DESC("C14", GPC(14)),
166    JZ_PIN_DESC("C15", GPC(15)),
167    JZ_PIN_DESC("C16", GPC(16)),
168    JZ_PIN_DESC("C17", GPC(17)),
169    JZ_PIN_DESC("C18", GPC(18)),
170    JZ_PIN_DESC("C19", GPC(19)),
171    JZ_PIN_DESC("C20", GPC(20)),
172    JZ_PIN_DESC("C21", GPC(21)),
173    JZ_PIN_DESC("C22", GPC(22)),
174    JZ_PIN_DESC("C23", GPC(23)),
175    JZ_PIN_DESC("C24", GPC(24)),
176    JZ_PIN_DESC("C25", GPC(25)),
177    JZ_PIN_DESC("C26", GPC(26)),
178    JZ_PIN_DESC("C27", GPC(27)),
179    JZ_PIN_DESC("C28", GPC(28)),
180    JZ_PIN_DESC("C29", GPC(29)),
181    JZ_PIN_DESC("C30", GPC(30)),
182    JZ_PIN_DESC("C31", GPC(31)),
183
184    /* Port D */
185    JZ_PIN_DESC("D00", GPD(0)),
186    JZ_PIN_DESC("D01", GPD(1)),
187    JZ_PIN_DESC("D02", GPD(2)),
188    JZ_PIN_DESC("D03", GPD(3)),
189    JZ_PIN_DESC("D04", GPD(4)),
190    JZ_PIN_DESC("D05", GPD(5)),
191    JZ_PIN_DESC("D06", GPD(6)),
192    JZ_PIN_DESC("D07", GPD(7)),
193    JZ_PIN_DESC("D08", GPD(8)),
194    JZ_PIN_DESC("D09", GPD(9)),
195    JZ_PIN_DESC("D10", GPD(10)),
196    JZ_PIN_DESC("D11", GPD(11)),
197    JZ_PIN_DESC("D12", GPD(12)),
198    JZ_PIN_DESC("D13", GPD(13)),
199    JZ_PIN_DESC("D14", GPD(14)),
200    JZ_PIN_DESC("D15", GPD(15)),
201    JZ_PIN_DESC("D16", GPD(16)),
202    JZ_PIN_DESC("D17", GPD(17)),
203    JZ_PIN_DESC("D18", GPD(18)),
204    JZ_PIN_DESC("D19", GPD(19)),
205    JZ_PIN_DESC("D20", GPD(20)),
206    JZ_PIN_DESC("D21", GPD(21)),
207    JZ_PIN_DESC("D22", GPD(22)),
208    JZ_PIN_DESC("D23", GPD(23)),
209    JZ_PIN_DESC("D24", GPD(24)),
210    JZ_PIN_DESC("D25", GPD(25)),
211    JZ_PIN_DESC("D26", GPD(26)),
212    JZ_PIN_DESC("D27", GPD(27)),
213    JZ_PIN_DESC("D28", GPD(28)),
214    JZ_PIN_DESC("D29", GPD(29)),
215    JZ_PIN_DESC("D30", GPD(30)),
216    JZ_PIN_DESC("D31", GPD(31)),
217
218    /* Port E */
219    JZ_PIN_DESC("E00", GPE(0)),
220    JZ_PIN_DESC("E01", GPE(1)),
221    JZ_PIN_DESC("E02", GPE(2)),
222    JZ_PIN_DESC("E03", GPE(3)),
223    JZ_PIN_DESC("E04", GPE(4)),
224    JZ_PIN_DESC("E05", GPE(5)),
225    JZ_PIN_DESC("E06", GPE(6)),
226    JZ_PIN_DESC("E07", GPE(7)),
227    JZ_PIN_DESC("E08", GPE(8)),
228    JZ_PIN_DESC("E09", GPE(9)),
229    JZ_PIN_DESC("E10", GPE(10)),
230    JZ_PIN_DESC("E11", GPE(11)),
231    JZ_PIN_DESC("E12", GPE(12)),
232    JZ_PIN_DESC("E13", GPE(13)),
233    JZ_PIN_DESC("E14", GPE(14)),
234    JZ_PIN_DESC("E15", GPE(15)),
235    JZ_PIN_DESC("E16", GPE(16)),
236    JZ_PIN_DESC("E17", GPE(17)),
237    JZ_PIN_DESC("E18", GPE(18)),
238    JZ_PIN_DESC("E19", GPE(19)),
239    JZ_PIN_DESC("E20", GPE(20)),
240    JZ_PIN_DESC("E21", GPE(21)),
241    JZ_PIN_DESC("E22", GPE(22)),
242    JZ_PIN_DESC("E23", GPE(23)),
243    JZ_PIN_DESC("E24", GPE(24)),
244    JZ_PIN_DESC("E25", GPE(25)),
245    JZ_PIN_DESC("E26", GPE(26)),
246    JZ_PIN_DESC("E27", GPE(27)),
247    JZ_PIN_DESC("E28", GPE(28)),
248    JZ_PIN_DESC("E29", GPE(29)),
249    JZ_PIN_DESC("E30", GPE(30)),
250    JZ_PIN_DESC("E31", GPE(31)),
251
252    /* Port F */
253    JZ_PIN_DESC("F00", GPF(0)),
254    JZ_PIN_DESC("F01", GPF(1)),
255    JZ_PIN_DESC("F02", GPF(2)),
256    JZ_PIN_DESC("F03", GPF(3)),
257    JZ_PIN_DESC("F04", GPF(4)),
258    JZ_PIN_DESC("F05", GPF(5)),
259    JZ_PIN_DESC("F06", GPF(6)),
260    JZ_PIN_DESC("F07", GPF(7)),
261    JZ_PIN_DESC("F08", GPF(8)),
262    JZ_PIN_DESC("F09", GPF(9)),
263    JZ_PIN_DESC("F10", GPF(10)),
264    JZ_PIN_DESC("F11", GPF(11)),
265    JZ_PIN_DESC("F12", GPF(12)),
266    JZ_PIN_DESC("F13", GPF(13)),
267    JZ_PIN_DESC("F14", GPF(14)),
268    JZ_PIN_DESC("F15", GPF(15)),
269    JZ_PIN_DESC("F16", GPF(16)),
270    JZ_PIN_DESC("F17", GPF(17)),
271    JZ_PIN_DESC("F18", GPF(18)),
272    JZ_PIN_DESC("F19", GPF(19)),
273    JZ_PIN_DESC("F20", GPF(20)),
274    JZ_PIN_DESC("F21", GPF(21)),
275    JZ_PIN_DESC("F22", GPF(22)),
276#undef JZ_PIN_DESC
277};
278
279static const unsigned int jz_pulldown_pins[] = {
280    GPB(0), GPB(1), GPB(10), GPB(11),
281    GPB(16), GPB(17), GPB(18), GPB(19),
282    GPD(12), GPD(13), GPD(15), GPE(0),
283    GPE(1), GPE(7), GPE(10), GPF(4),
284    GPF(5), GPF(6), GPF(7), GPF(8),
285    GPF(9), GPF(10), GPF(11), GPF(16),
286    GPF(17), GPF(19), GPF(20), GPF(22),
287};
288
289static const unsigned int msc0_4bit_pins[] = {
290    GPA(18), GPA(19), GPA(20), GPA(21), GPA(22), GPA(23),
291};
292static const u8 msc0_4bit_sels[] = {
293    1, 1, 0, 1, 1, 1,
294};
295
296static const unsigned int msc1_4bit_pins[] = {
297    GPD(20), GPD(21), GPD(22), GPD(23), GPD(24), GPD(25),
298};
299static const u8 msc1_4bit_sels[] = {
300    0, 0, 0, 0, 0, 0,
301};
302
303static const unsigned int msc2_4bit_pins[] = {
304    GPB(20), GPB(21), GPB(28), GPB(29), GPB(30), GPB(31),
305};
306static const u8 msc2_4bit_sels[] = {
307    0, 0, 0, 0, 0, 0,
308};
309
310static const unsigned int msc_8bit_pins[] = {
311    GPE(20), GPE(21), GPE(22), GPE(23), GPE(24),
312    GPE(25), GPE(26), GPE(27), GPE(28), GPE(29),
313};
314static const u8 msc0_8bit_sels[] = {
315    0, 0, 0, 0, 0,
316    0, 0, 0, 0, 0,
317};
318static const u8 msc1_8bit_sels[] = {
319    1, 1, 1, 1, 1,
320    1, 1, 1, 1, 1,
321};
322static const u8 msc2_8bit_sels[] = {
323    2, 2, 2, 2, 2,
324    2, 2, 2, 2, 2,
325};
326#define msc0_8bit_pins msc_8bit_pins
327#define msc1_8bit_pins msc_8bit_pins
328#define msc2_8bit_pins msc_8bit_pins
329
330static const unsigned int uart0_pins[] = { GPF( 0), GPF( 1), GPF( 2), GPF( 3), };
331static const u8 uart0_sels[] = { 0, 0, 0, 0, };
332static const unsigned int uart1_pins[] = { GPD(26), GPD(27), GPD(28), GPD(29), };
333static const u8 uart1_sels[] = { 0, 0, 0, 0, };
334static const unsigned int uart2_pins[] = { GPC(28), GPC(29), GPC(30), GPC(31), };
335static const u8 uart2_sels[] = { 0, 0, 0, 0, };
336static const unsigned int uart3_pins[] = { GPD(12), GPE( 5), GPE( 8), GPE( 9), };
337static const u8 uart3_sels[] = { 0, 1, 0, 0, };
338
339static const unsigned int i2c0_pins[] = { GPD(30), GPD(31), };
340static const u8 i2c0_sels[] = { 0, 0, };
341static const unsigned int i2c1_pins[] = { GPE(30), GPE(31), };
342static const u8 i2c1_sels[] = { 0, 0, };
343static const unsigned int i2c2_pins[] = { GPF(16), GPF(17), };
344static const u8 i2c2_sels[] = { 2, 2, };
345
346static const unsigned int pwm0_pins[] = { GPE(0), };
347static const unsigned int pwm1_pins[] = { GPE(1), };
348static const unsigned int pwm2_pins[] = { GPE(2), };
349static const unsigned int pwm3_pins[] = { GPE(3), };
350static const unsigned int pwm4_pins[] = { GPE(4), };
351static const unsigned int pwm5_pins[] = { GPE(5), };
352static const unsigned int pwm6_pins[] = { GPD(10), };
353static const unsigned int pwm7_pins[] = { GPD(11), };
354static const u8 pwm_sels[] = { 0, };
355#define pwm0_sels pwm_sels
356#define pwm1_sels pwm_sels
357#define pwm2_sels pwm_sels
358#define pwm3_sels pwm_sels
359#define pwm4_sels pwm_sels
360#define pwm5_sels pwm_sels
361#define pwm6_sels pwm_sels
362#define pwm7_sels pwm_sels
363
364static const unsigned int otg_pins[] = { GPE(10), };
365static const u8 otg_sels[] = { 0, };
366
367static const unsigned int lcd_pins[] = {
368    /* PCLK, DE, HSYNC, VSYNC */
369    GPC( 8), GPC( 9), GPC(18), GPC(19),
370    /* B0..B4 */
371    GPC( 0), GPC( 1), GPC( 2), GPC( 3), GPC( 4),
372    /* G0..G5 */
373    GPC(10), GPC(11), GPC(12), GPC(13), GPC(14), GPC(15),
374    /* R0..R4 */
375    GPC(20), GPC(21), GPC(22), GPC(23), GPC(24),
376    /* 18 bpp: B5, R5 */
377    GPC( 5), GPC(25),
378    /* 24 bpp: B6/7, G6/7, R6/7 */
379    GPC( 6), GPC( 7), GPC(16), GPC(17), GPC(26), GPC(27),
380};
381static const u8 lcd_sels[ARRAY_SIZE(lcd_pins)] = { 0 };
382
383static const struct jz_pin_group jz_pin_groups[] = {
384#define JZ_GROUP(group) { \
385    .name = #group, \
386    .pins = group##_pins, \
387    .sels = group##_sels, \
388    .num_pins = ARRAY_SIZE(group##_pins), \
389}
390    JZ_GROUP(msc0_4bit),
391    JZ_GROUP(msc1_4bit),
392    JZ_GROUP(msc2_4bit),
393    JZ_GROUP(msc0_8bit),
394    JZ_GROUP(msc1_8bit),
395    JZ_GROUP(msc2_8bit),
396    JZ_GROUP(uart0),
397    JZ_GROUP(uart1),
398    JZ_GROUP(uart2),
399    JZ_GROUP(uart3),
400    JZ_GROUP(i2c0),
401    JZ_GROUP(i2c1),
402    JZ_GROUP(i2c2),
403    JZ_GROUP(pwm0),
404    JZ_GROUP(pwm1),
405    JZ_GROUP(pwm2),
406    JZ_GROUP(pwm3),
407    JZ_GROUP(pwm4),
408    JZ_GROUP(pwm5),
409    JZ_GROUP(pwm6),
410    JZ_GROUP(pwm7),
411    JZ_GROUP(otg),
412    { "lcd_rgb565", lcd_pins, lcd_sels, 4 + 16 },
413    { "lcd_rgb666", lcd_pins, lcd_sels, 4 + 18 },
414    { "lcd_rgb888", lcd_pins, lcd_sels, 4 + 24 },
415    { "no_pins", NULL, NULL, 0 },
416#undef JZ_GROUP
417};
418
419static int jz_get_groups_count(struct pinctrl_dev *pctldev)
420{
421    return ARRAY_SIZE(jz_pin_groups);
422}
423
424static const char *jz_get_group_name(struct pinctrl_dev *pctldev,
425        unsigned int group)
426{
427    return jz_pin_groups[group].name;
428}
429
430static int jz_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
431        const unsigned int **pins,
432        unsigned int *num_pins)
433{
434    *pins = jz_pin_groups[group].pins;
435    *num_pins = jz_pin_groups[group].num_pins;
436    return 0;
437}
438
439static const struct pinctrl_ops jz_pctrl_ops = {
440    .get_groups_count = jz_get_groups_count,
441    .get_group_name = jz_get_group_name,
442    .get_group_pins = jz_get_group_pins,
443};
444
445static const char * const msc0_groups[] = { "msc0_4bit", "msc0_8bit", };
446static const char * const msc1_groups[] = { "msc1_4bit", "msc1_8bit", };
447static const char * const msc2_groups[] = { "msc2_4bit", "msc2_8bit", };
448static const char * const uart0_groups[] = { "uart0", };
449static const char * const uart1_groups[] = { "uart1", };
450static const char * const uart2_groups[] = { "uart2", };
451static const char * const uart3_groups[] = { "uart3", };
452static const char * const i2c0_groups[] = { "i2c0", };
453static const char * const i2c1_groups[] = { "i2c1", };
454static const char * const i2c2_groups[] = { "i2c2", };
455static const char * const pwm0_groups[] = { "pwm0", };
456static const char * const pwm1_groups[] = { "pwm1", };
457static const char * const pwm2_groups[] = { "pwm2", };
458static const char * const pwm3_groups[] = { "pwm3", };
459static const char * const pwm4_groups[] = { "pwm4", };
460static const char * const pwm5_groups[] = { "pwm5", };
461static const char * const pwm6_groups[] = { "pwm6", };
462static const char * const pwm7_groups[] = { "pwm7", };
463static const char * const otg_groups[] = { "otg", };
464static const char * const lcd_groups[] = {
465    "lcd_rgb888", "lcd_rgb666", "lcd_rgb565", "no_pins"
466};
467
468static const struct jz_pmux_func jz_functions[] = {
469#define JZ_GROUP(group) { \
470    .name = #group, \
471    .groups = group##_groups, \
472    .num_groups = ARRAY_SIZE(group##_groups), \
473}
474    JZ_GROUP(msc0),
475    JZ_GROUP(msc1),
476    JZ_GROUP(msc2),
477    JZ_GROUP(uart0),
478    JZ_GROUP(uart1),
479    JZ_GROUP(uart2),
480    JZ_GROUP(uart3),
481    JZ_GROUP(i2c0),
482    JZ_GROUP(i2c1),
483    JZ_GROUP(i2c2),
484    JZ_GROUP(pwm0),
485    JZ_GROUP(pwm1),
486    JZ_GROUP(pwm2),
487    JZ_GROUP(pwm3),
488    JZ_GROUP(pwm4),
489    JZ_GROUP(pwm5),
490    JZ_GROUP(pwm6),
491    JZ_GROUP(pwm7),
492    JZ_GROUP(otg),
493    JZ_GROUP(lcd),
494#undef JZ_GROUP
495};
496
497int jz_get_functions_count(struct pinctrl_dev *pctldev)
498{
499    return ARRAY_SIZE(jz_functions);
500}
501
502const char *jz_get_fname(struct pinctrl_dev *pctrldev, unsigned int func)
503{
504    return jz_functions[func].name;
505}
506
507static int jz_get_groups(struct pinctrl_dev *pctrldev, unsigned int func,
508        const char * const **groups, unsigned int * const num_groups)
509{
510    *groups = jz_functions[func].groups;
511    *num_groups = jz_functions[func].num_groups;
512    return 0;
513}
514
515static void jz_set_gpio_input(struct pinctrl_dev *pctldev, unsigned int pin)
516{
517    struct jz_pinctrl *jz = pinctrl_dev_get_drvdata(pctldev);
518    const unsigned int bit = BIT(PORT_PIN(pin)), port = PORT(pin);
519    unsigned long flags;
520
521    spin_lock_irqsave(&jz->lock, flags);
522    writel(bit, jz->base + INT_CLR_OFFSET(port));
523    writel(bit, jz->base + MASK_SET_OFFSET(port));
524    writel(bit, jz->base + PAT1_SET_OFFSET(port));
525    spin_unlock_irqrestore(&jz->lock, flags);
526}
527
528static void jz_set_gpio_output(struct pinctrl_dev *pctldev, unsigned int pin)
529{
530    struct jz_pinctrl *jz = pinctrl_dev_get_drvdata(pctldev);
531    const unsigned int bit = BIT(PORT_PIN(pin)), port = PORT(pin);
532    unsigned long flags;
533
534    spin_lock_irqsave(&jz->lock, flags);
535    writel(bit, jz->base + INT_CLR_OFFSET(port));
536    writel(bit, jz->base + MASK_SET_OFFSET(port));
537    writel(bit, jz->base + PAT1_CLR_OFFSET(port));
538    spin_unlock_irqrestore(&jz->lock, flags);
539}
540
541static void jz_set_function(struct pinctrl_dev *pctldev,
542        unsigned int pin, u8 sel)
543{
544    struct jz_pinctrl *jz = pinctrl_dev_get_drvdata(pctldev);
545    const unsigned int bit = BIT(PORT_PIN(pin)), port = PORT(pin);
546    unsigned long flags;
547
548    spin_lock_irqsave(&jz->lock, flags);
549
550    writel(bit, jz->base + INT_CLR_OFFSET(port));
551    writel(bit, jz->base + MASK_CLR_OFFSET(port));
552    if (sel & BIT(0))
553        writel(bit, jz->base + PAT0_SET_OFFSET(port));
554    else
555        writel(bit, jz->base + PAT0_CLR_OFFSET(port));
556    if (sel & BIT(1))
557        writel(bit, jz->base + PAT1_SET_OFFSET(port));
558    else
559        writel(bit, jz->base + PAT1_CLR_OFFSET(port));
560
561    spin_unlock_irqrestore(&jz->lock, flags);
562}
563
564static int jz_set_mux(struct pinctrl_dev *pctrldev, unsigned func_selector,
565            unsigned group_selector)
566{
567    const struct jz_pin_group *pin_group = &jz_pin_groups[group_selector];
568    unsigned int i;
569
570    for (i = 0; i < pin_group->num_pins; i++)
571        jz_set_function(pctrldev, pin_group->pins[i],
572                      pin_group->sels[i]);
573
574    return 0;
575}
576
577static int jz_pmux_gpio_set_direction(struct pinctrl_dev *pctldev,
578        struct pinctrl_gpio_range *range,
579        unsigned int offset, bool input)
580{
581    if (input)
582        jz_set_gpio_input(pctldev, offset);
583    else
584        jz_set_gpio_output(pctldev, offset);
585    return 0;
586}
587
588static const struct pinmux_ops jz_pmux_ops = {
589    .get_functions_count = jz_get_functions_count,
590    .get_function_name = jz_get_fname,
591    .get_function_groups = jz_get_groups,
592    .set_mux = jz_set_mux,
593    .gpio_set_direction = jz_pmux_gpio_set_direction,
594};
595
596static bool jz_pin_is_pulldown(unsigned int pin)
597{
598    unsigned int i;
599    for (i = 0; i < ARRAY_SIZE(jz_pulldown_pins); i++)
600        if (jz_pulldown_pins[i] == pin)
601            return true;
602    return false;
603}
604
605static void jz_pin_disable_pullup_pulldown(struct jz_pinctrl *jz,
606        unsigned int pin)
607{
608    writel(BIT(PORT_PIN(pin)), jz->base + PULL_SET_OFFSET(PORT(pin)));
609}
610
611static void jz_pin_enable_pullup_pulldown(struct jz_pinctrl *jz,
612        unsigned int pin)
613{
614    writel(BIT(PORT_PIN(pin)), jz->base + PULL_CLR_OFFSET(PORT(pin)));
615}
616
617static bool jz_pin_is_pullup_pulldown_enabled(struct jz_pinctrl *jz,
618        unsigned int pin)
619{
620    u32 val = readl(jz->base + PULL_OFFSET(PORT(pin)));
621    return !(val & BIT(PORT_PIN(pin)));
622}
623
624static int jz_pin_config_get(struct pinctrl_dev *pctldev,
625        unsigned int pin, unsigned long *config)
626{
627    struct jz_pinctrl *jz = pinctrl_dev_get_drvdata(pctldev);
628    enum pin_config_param param = pinconf_to_config_param(*config);
629    u16 param_val = pinconf_to_config_argument(*config);
630
631    switch (param) {
632        case PIN_CONFIG_BIAS_PULL_UP:
633            if (jz_pin_is_pulldown(pin))
634                return -EINVAL;
635            param_val = jz_pin_is_pullup_pulldown_enabled(jz, pin);
636            break;
637
638        case PIN_CONFIG_BIAS_PULL_DOWN:
639            if (!jz_pin_is_pulldown(pin))
640                return -EINVAL;
641            param_val = jz_pin_is_pullup_pulldown_enabled(jz, pin);
642            break;
643
644        case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
645            param_val = jz_pin_is_pullup_pulldown_enabled(jz, pin);
646            break;
647
648        default:
649            return -ENOTSUPP;
650    };
651
652    *config = pinconf_to_config_packed(param, param_val);
653    return 0;
654}
655
656static int jz_pin_config_set(struct pinctrl_dev *pctldev,
657        unsigned int pin, unsigned long *configs,
658        unsigned int num_configs)
659{
660    struct jz_pinctrl *jz = pinctrl_dev_get_drvdata(pctldev);
661    unsigned int i;
662    enum pin_config_param param;
663    u16 param_val;
664
665    for (i = 0; i < num_configs; i++) {
666        param = pinconf_to_config_param(configs[i]);
667        param_val = pinconf_to_config_argument(configs[i]);
668
669        switch (param) {
670        case PIN_CONFIG_BIAS_PULL_UP:
671            if (jz_pin_is_pulldown(pin))
672                return -EINVAL;
673            jz_pin_enable_pullup_pulldown(jz, pin);
674            break;
675
676        case PIN_CONFIG_BIAS_PULL_DOWN:
677            if (!jz_pin_is_pulldown(pin))
678                return -EINVAL;
679            jz_pin_enable_pullup_pulldown(jz, pin);
680            break;
681
682        case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
683            jz_pin_enable_pullup_pulldown(jz, pin);
684            break;
685
686        case PIN_CONFIG_BIAS_DISABLE:
687            jz_pin_disable_pullup_pulldown(jz, pin);
688            break;
689
690        default:
691            return -ENOTSUPP;
692        }
693    }
694
695    return 0;
696}
697
698static int jz_pin_config_group_get(struct pinctrl_dev *pctldev,
699        unsigned int group, unsigned long *config)
700{
701    /* TODO */
702    return -ENOTSUPP;
703}
704
705static int jz_pin_config_group_set(struct pinctrl_dev *pctldev,
706        unsigned int group, unsigned long *configs,
707        unsigned int num_configs)
708{
709    unsigned int nb_pins;
710    const unsigned int *pins;
711    int ret = jz_get_group_pins(pctldev, group, &pins, &nb_pins);
712
713    while (!ret && nb_pins--)
714        ret = jz_pin_config_set(pctldev, pins[nb_pins],
715                configs, num_configs);
716    return ret;
717}
718
719static const struct pinconf_ops jz_pconf_ops = {
720    .is_generic = true,
721    .pin_config_get = jz_pin_config_get,
722    .pin_config_set = jz_pin_config_set,
723    .pin_config_group_get = jz_pin_config_group_get,
724    .pin_config_group_set = jz_pin_config_group_set,
725};
726
727static struct pinctrl_desc jz_desc = {
728    .name = "jz4770-pinctrl",
729    .pins = jz_pins,
730    .npins = ARRAY_SIZE(jz_pins),
731    .pctlops = &jz_pctrl_ops,
732    .pmxops = &jz_pmux_ops,
733    .confops = &jz_pconf_ops,
734    .owner = THIS_MODULE,
735};
736
737static int jz4770_pinctrl_probe(struct platform_device *pdev)
738{
739    struct jz_pinctrl *jz;
740    struct resource *res;
741
742    jz = devm_kzalloc(&pdev->dev, sizeof(*jz), GFP_KERNEL);
743    if (!jz) {
744        dev_err(&pdev->dev, "Unable to allocate memory\n");
745        return -ENOMEM;
746    }
747
748    jz->dev = &pdev->dev;
749    platform_set_drvdata(pdev, jz);
750    spin_lock_init(&jz->lock);
751
752    res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
753    jz->base = devm_ioremap_resource(&pdev->dev, res);
754    if (IS_ERR(jz->base)) {
755        dev_err(&pdev->dev, "Failed to remap registers\n");
756        return PTR_ERR(jz->base);
757    }
758
759    jz->pctl = pinctrl_register(&jz_desc, &pdev->dev, jz);
760    if (!jz->pctl) {
761        dev_err(&pdev->dev, "Failed to register pinctrl driver\n");
762        return -ENODEV;
763    }
764
765    dev_dbg(&pdev->dev, "pinctrl driver registered\n");
766    return 0;
767}
768
769static int jz4770_pinctrl_remove(struct platform_device *pdev)
770{
771    struct jz_pinctrl *jz = platform_get_drvdata(pdev);
772    pinctrl_unregister(jz->pctl);
773    return 0;
774}
775
776static struct platform_driver jz4770_pinctrl_driver = {
777    .driver = {
778        .name = "jz4770-pinctrl",
779        .owner = THIS_MODULE,
780    },
781    .probe = jz4770_pinctrl_probe,
782    .remove = jz4770_pinctrl_remove,
783};
784
785static int __init jz4770_pinctrl_drv_register(void)
786{
787    return platform_driver_register(&jz4770_pinctrl_driver);
788}
789postcore_initcall(jz4770_pinctrl_drv_register);
790
791static void __exit jz4770_pinctrl_drv_unregister(void)
792{
793    platform_driver_unregister(&jz4770_pinctrl_driver);
794}
795module_exit(jz4770_pinctrl_drv_unregister);
796
797MODULE_DESCRIPTION("Ingenic JZ4770 pin control driver");
798MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
799MODULE_ALIAS("platform:jz4770-pinctrl");
800MODULE_LICENSE("GPL v2");

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